Back surface process manufacturing method of semiconductor device and semiconductor device

Abstract

The invention provides a back process manufacturing method of a semiconductor device and the semiconductor device, and the method comprises the steps: carrying out the processing of the back of a wafer, and enabling the back of the wafer to comprise a first back structure in a pyramid shape; processing the first back surface structure to obtain a second back surface structure; wherein the processing of the first back surface structure comprises the following steps: carrying out planarization processing on the first back surface structure and / or forming a protective layer on the surface of the first back surface structure; forming a plurality of light-transmitting areas on the surface of the second back surface structure by adopting a photoetching process; and performing ion implantation in the light-transmitting region to form a doped region. The electrical characteristics of the semiconductor device are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a method for manufacturing a backside process of a semiconductor device and a semiconductor device. Background Art

[0002] As a hybrid power device, an IGBT (Insulated Gate Bipolar Transistor) has the characteristics of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure input and bipolar structure output. Therefore, it has the advantages of high input impedance of MOSFET, small driving circuit power, simple driving, fast switching speed, and small switching loss, as well as the advantages of large current density of bipolar power transistor, strong current handling ability, and low conduction saturation voltage. When an IGBT is used, it needs to be paired with a freewheeling fast recovery diode (FRD). To reduce the chip cost and improve the power cycle reliability, the reverse conducting IGBT (RCIGBT) has been widely studied and widely used in the field of white household appliances.

[0003] One of the key processes of RCIGBT is to perform local N-type ion implantation on the backside of the chip to form a specific doping structure. The conventional process is to release the stress caused by the thinning process in the wafer. After the wafer is thinned, the silicon backside will be subjected to silicon etching treatment, resulting in an uneven morphology with a "pyramid" shape on the silicon surface, and the height difference can be as high as 2 um. This rough surface will cause the following problems in the subsequent process:

[0004] After spin-coating photoresist, the thickness of the photoresist at the "pyramid" peaks is significantly thinned, making it difficult to effectively block ion implantation. During the N-type ion implantation process, ions with higher energy will penetrate the ultra-thin photoresist layer, resulting in difficult removal of the photoresist, affecting the contact between the backside metal and the backside silicon. Even the N-type ions will penetrate the photoresist blocking area and implant non-expected N-type doped ion regions in the silicon, resulting in a relatively large collector-emitter saturation voltage (Vcesat), and causing the Vcesat value distribution range to expand (disperse). This not only reduces the performance of the device but also reduces the wafer yield.

[0005] It should be noted that the information disclosed in the above background art section is only used to strengthen the understanding of the background of the present application, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] Aiming at the problems in the prior art, the purpose of the present application is to provide a method for manufacturing a backside process of a semiconductor device and a semiconductor device, enabling good ohmic contact between the backside metal and the backside silicon, reducing the Vcesat value, and making the Vcesat value converge, effectively improving the electrical characteristics of the device.

[0007] An embodiment of the present application provides a method for manufacturing a backside process of a semiconductor device, including:

[0008] Processing the backside of a wafer, wherein the backside of the wafer includes a first backside structure having a pyramid shape;

[0009] Processing the first backside structure to obtain a second backside structure; wherein, processing the first backside structure includes: performing a planarization process on the first backside structure and / or forming a protective layer on the surface of the first backside structure;

[0010] Using a lithography process to form a plurality of light-transmitting regions on the surface of the second backside structure;

[0011] Performing ion implantation in the light-transmitting regions to form doped regions.

[0012] In some embodiments, performing a planarization process on the first backside structure includes: performing a laser annealing process on the first backside structure to planarize the peaks of the pyramid shape.

[0013] In some embodiments, processing the first backside structure includes forming a protective layer on the surface of the first backside structure; using a lithography process to form a plurality of light-transmitting regions on the surface of the second backside structure, including the following steps:

[0014] Setting a photoresist on the surface of the second backside structure and performing exposure and development to form a plurality of light-transmitting regions;

[0015] Etching away the protective layer in the light-transmitting regions.

[0016] In some embodiments, before the step of performing ion implantation in the light-transmitting regions to form doped regions, the following steps are further included:

[0017] Removing the photoresist on the surface of the second backside structure.

[0018] In some embodiments, after the step of performing ion implantation in the light-transmitting regions to form doped regions, the following steps are further included:

[0019] Etching away the photoresist;

[0020] Etching away the protective layer.

[0021] In some embodiments, processing the first backside structure includes the following steps:

[0022] Performing a laser annealing process on the first backside structure to planarize the peaks of the pyramid shape;

[0023] The protective layer is formed on the surface of the first backside structure after laser annealing.

[0024] In some embodiments, the laser annealing process for the first backside structure includes one or more of the following conditions:

[0025] (1) Use a laser with a wavelength of 492 nm to 550 nm;

[0026] (2) The laser annealing energy is 1.2 J - 3 J;

[0027] (3) The scanning overlap rate in the X direction is greater than 50%;

[0028] (4) The scanning overlap rate in the Y direction is greater than 65%.

[0029] In some embodiments, the protective layer is a silicon dioxide layer; and / or the thickness of the protective layer is

[0030] In some embodiments, the ion implantation is performed on the backside of the wafer after the laser annealing step.

[0031] An embodiment of the present application also provides a semiconductor device, and the backside structure of the semiconductor device is manufactured by the above manufacturing method.

[0032] The backside process manufacturing method of the semiconductor device and the semiconductor device provided by the present application have the following advantages:

[0033] Before the lithography process, the laser annealing process is performed on the first backside structure of the wafer backside and / or a protective layer is formed on the backside, effectively reducing the adverse effects of the uneven topography of the "pyramid" shape, avoiding the problem of penetrating the photoresist during ion implantation, increasing the process window, enabling good ohmic contact between the backside metal and the backside silicon; at the same time, effectively reducing the Vcesat value and making the Vcesat value converge. Brief Description of the Drawings

[0034] The drawings here are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0035] Figure 1 is a flowchart of the backside process manufacturing method of a semiconductor device according to an embodiment of the present application;

[0036] Figures 2 - 6 is a schematic diagram of the backside process manufacturing process of an existing semiconductor device;

[0037] Figures 7 - 11 is a flowchart of a backside process manufacturing method of a semiconductor device according to the first embodiment of the present application;

[0038] Figures 12 - 16 is a flowchart of a backside process manufacturing method of a semiconductor device according to the second embodiment of the present application;

[0039] Figures 17 - 21 is a flowchart of a backside process manufacturing method of a semiconductor device according to the third embodiment of the present application;

[0040] Figure 22 is a technical effect comparison diagram of the backside process manufacturing method of the semiconductor device adopting the present application;

[0041] FIGS. 23(a)-(d) are schematic topographic views after silicon etching and annealing treatment are performed on the backside of a wafer. Detailed Embodiments

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted. The "or" or "or" in the specification may mean "and" or "or". Spatial relationship terms such as "... on" can be used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figure is flipped, an element or feature described as "... on" will be oriented as "... under" other elements or features. Thus, the exemplary term "... on" can include both the upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial description terms used herein are accordingly interpreted.

[0043] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not excluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the related listed items. Although the terms "first" or "second" etc. are used in this specification to denote certain features, they are only for the purpose of indication and do not limit the quantity and importance of the specific features.

[0044] In view of the problem in the prior art that during the backside process manufacturing, due to the relatively rough surface after the silicon etching treatment on the backside of the wafer, the "pyramid" - shaped uneven topography makes it easy for ions to penetrate the photoresist during ion implantation, thus affecting the contact between the backside metal and the backside silicon, the present application provides a method for manufacturing the backside process of a semiconductor device, aiming to reduce the influence of the "pyramid" - shaped uneven topography on the backside of the wafer on the subsequent lithography process and ion implantation process.

[0045] As Figure 1 shown, an embodiment of the present application provides a method for manufacturing the backside process of a semiconductor device, including:

[0046] S100: Process the backside of the wafer. Among them, the backside of the wafer includes a first backside structure having a pyramid shape; Provide a wafer, after forming a front - side structure on the wafer according to the conventional front - side process, perform a thinning process on the backside of the wafer to improve device performance, and perform a silicon etching process to release the stress brought by the thinning process in the wafer; The first backside structure formed here is the backside structure of the wafer with a "pyramid" - shaped uneven topography.

[0047] S200: Process the first backside structure to obtain a second backside structure; Among them, processing the first backside structure includes: performing a planarization process on the first backside structure and / or forming a protective layer on the surface of the first backside structure.

[0048] In this embodiment, planarizing the first back surface structure includes: performing laser annealing on the first back surface structure to reduce the influence of the uneven "pyramid" shape on the back surface of the wafer on subsequent lithography and ion implantation processes; optionally, performing laser annealing on the first back surface structure includes: annealing the first back surface structure with a laser having a wavelength of 492 nm to 550 nm, the laser energy being, for example, 1.2 J to 3 J, the scanning overlap rate in the X direction being greater than 50%, and the scanning overlap rate in the Y direction being greater than 65%. By using the laser to make the temperature on the back surface of the wafer higher than 1400 °C, the silicon on the back surface of the wafer is melted to flatten the "pyramid" peaks. Here, flattening the "pyramid" peaks means changing the acute angle of the "pyramid" peaks to an obtuse angle, and the obtuse angle after treatment is preferably greater than 110°, or eliminating the "pyramid". Through the planarization process, it is possible to avoid forming areas with too thin photoresist when forming the photoresist subsequently, and avoid penetrating the photoresist during ion implantation;

[0049] In this embodiment, the protective layer can be optionally a silicon dioxide protective layer, or other suitable material layers such as silicon nitride and silicon oxynitride can be selected; the protective layer can be optionally formed by SACVD (Sub-Atmospheric Chemical Vapor Deposition), or can be optionally formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable deposition methods; the thickness of the protective layer can be optionally For example etc. The thickness of the protective layer should be such that it can provide sufficient protection and not increase the difficulty of subsequent etching removal; by forming the protective layer, it is used as a barrier layer during ion implantation to absorb ion energy, which can prevent the ion implantation range from penetrating the photoresist, thereby avoiding the formation of undesired doped regions and ensuring the stability of the electrical performance and parameters of the device; and the silicon dioxide layer can enhance the stability of the photoresist, provide a flatter substrate for the photoresist, reduce the unevenness of the photoresist layer thickness caused by the uneven "pyramid" shape, and reduce the photoresist defects caused by the rough silicon surface;

[0050] S300: Form a plurality of light-transmitting regions on the surface of the second back surface structure by using a lithography process;

[0051] Among them, first, a photoresist is disposed on the surface of the second back surface structure, and then the photoresist is developed and exposed to form a plurality of light-transmitting region patterns; optionally, the photoresist is formed on the surface of the second back surface structure by spin coating;

[0052] S400: Perform ion implantation in the light-transmitting regions to form doped regions;

[0053] For example, N-type ion implantation (such as implanting N-type dopants like phosphorus (P), arsenic (As), antimony (Sb), etc.) or P-type ion implantation (such as implanting P-type dopants like boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) is performed in the light-transmitting region to form an N-type doped region or a P-type doped region. Preferably, for various ion implantation processes that need to be performed on the backside process, they are all executed after the laser annealing step. For example, when performing P-type ion implantation, such as boron, since the boron ion implantation energy is relatively low, generally less than 50 keV, the uneven topography of the "pyramid" shape also has an impact on boron ion implantation. By performing the boron ion implantation process after laser annealing treatment, the adverse effects during the boron ion implantation process can also be reduced.

[0054] By adopting the present application, after forming the first backside structure by processing the backside of the wafer through step S100, before the photolithography process in step S300, the first backside structure on the backside of the wafer is subjected to laser annealing treatment and / or a protective layer is formed on the backside through step S200, effectively reducing the adverse effects of the uneven topography of the "pyramid" shape on the backside of the wafer, avoiding the problem of penetrating the photoresist during ion implantation, increasing the process window, enabling good ohmic contact between the backside metal and the backside silicon; at the same time, effectively reducing the Vcesat value and making the Vcesat value converge. The present application solves the key performance problems by optimizing the backside process of discrete devices, providing a more reliable technical path for the manufacture of high-performance power discrete devices.

[0055] The backside process manufacturing method of the semiconductor device of the present application is not only applicable to RCIGBT (Reverse Conducting Insulated Gate Bipolar Transistor), but also applicable to devices that require photolithography processes on the backside such as RBIGBT (Reverse Blocking Insulated Gate Bipolar Transistor), CIBH FRD (Cathode-Isolated Buried Heterojunction Fast Recovery Diode), and FCE FRD (Field Charge Extraction Fast Recovery Diode), and has broad application prospects.

[0056] In this embodiment, step S200: processing the first back structure to obtain a second back structure may be that after planarizing the first back structure, the planarized structure is the second back structure; or, after forming a protective layer on the surface of the first back structure, the structure with the protective layer is the second back structure; or, after planarizing the first back structure, forming a protective layer on the surface of the planarized structure, and the structure with the protective layer is the second back structure.

[0057] In this embodiment, step S200: processing the first back structure to obtain a second back structure includes, when forming a protective layer on the surface of the first back structure, step S300: forming a plurality of light-transmitting regions on the surface of the second back structure by using a photolithography process, including the following steps:

[0058] Spin-coating a photoresist on the surface of the second back structure and performing exposure and development to form a plurality of light-transmitting regions;

[0059] Etch and remove the protective layer in the light-transmitting regions. Optionally, dry etching is used to remove the protective layer in the light-transmitting regions, and hydrofluoric acid (HF) is added for cleaning. Or, wet etching can also be used to remove the protective layer in the light-transmitting regions.

[0060] In this embodiment, in step S400, when performing ion implantation in the light-transmitting regions, the photoresist is used as a mask for ion implantation, so that only the surface of the wafer in the light-transmitting regions is implanted with ions. When the second back structure includes a protective layer, the protective layer and the photoresist can jointly serve as a mask for ion implantation, so that only the surface of the wafer in the light-transmitting regions is implanted with ions. Or, when the second back structure includes a protective layer, before the step of performing ion implantation in the light-transmitting regions to form a doped region, the photoresist on the surface of the second back structure is removed, and only the protective layer is used as a mask for ion implantation. In this case, the protective layer is made to have a relatively large thickness to play a better protective role, such as This method of removing the photoresist before ion implantation can completely avoid the penetration of the photoresist during ion implantation, which is beneficial to the complete removal of the photoresist.

[0061] In this embodiment, step S200: processing the first back structure to obtain a second back structure includes, when forming a protective layer on the surface of the first back structure, if the photoresist is not removed before ion implantation, then after step S400: performing ion implantation in the light-transmitting regions to form a doped region, the following steps are further included:

[0062] Etch and remove the photoresist; optionally, dry etching is used to remove the photoresist, or after dry etching to remove the photoresist, an EKC cleaning solution is added for cleaning;

[0063] Etch away the protective layer; optionally, wet etching is used to remove the protective layer.

[0064] An embodiment of the present application further provides a semiconductor device, and the back structure of the semiconductor device is manufactured by the above manufacturing method. The semiconductor device obtained by this method has better electrical performance compared with the semiconductor devices in the prior art, with a smaller Vcesat value and better convergence. Such semiconductor devices are, for example, RCIGBT, RBIGBT, CIBH FRD, FCEFRD, etc.

[0065] The differences in the implementation processes of the manufacturing methods in the prior art and the specific embodiments of the present application will be introduced in detail below with reference to the accompanying drawings.

[0066] Figures 2 - 6 is a schematic diagram of the manufacturing process of the backside process of an existing semiconductor device. As Figure 2 shown, first, a wafer is provided. After the conventional front process, the backside of the wafer is thinned and silicon-etched to form a first back structure 101 with an uneven morphology in the shape of a "pyramid". As Figure 3 shown, a photoresist 102 is spin-coated on the surface of the first back structure 101. As Figure 4 shown, the photoresist is exposed and developed to form a plurality of light-transmitting regions. As Figure 5 shown, ion implantation is performed in the light-transmitting regions to form a desired doping region 104, and at the same time, an undesired doping region 1041 may be formed. Among them, after ion implantation, the photoresist becomes hard, and the hardened part of the photoresist is represented by 103. As Figure 6 shown, the photoresists 102 and 103 are removed. At the peaks of the "pyramid", the photoresist is thinner, and the implanted ions penetrate the photoresist, making it difficult to remove the photoresist 103, resulting in the residue of the photoresist 103, which affects the subsequent contact between the backside metal and the backside silicon. And due to the formation of the undesired doping region 1041, the Vcesat is relatively large and discrete.

[0067] Figures 7 - 11 is a flowchart of the manufacturing method of the backside process of the semiconductor device according to the first embodiment of the present application. As Figure 7 shown, corresponding to step S100, first, a wafer is provided. After the conventional front process, the backside of the wafer is thinned and silicon-etched to form a first back structure 100 with an uneven morphology in the shape of a "pyramid". As Figure 8As shown, corresponding to step S200, annealing treatment is performed on the back surface of the wafer using a green laser with a wavelength of 492 nm to 550 nm. The annealing energy is 1.2 J to 3 J, the scanning overlap rate in the X direction is greater than 50%, and the scanning overlap rate in the Y direction is greater than 65%, so that the temperature of the back surface of the wafer is higher than 1400 °C, melting the silicon on the back surface of the wafer to flatten the "pyramid" peaks. Here, flattening the "pyramid" peaks means changing the acute angle of the "pyramid" peaks to an obtuse angle, preferably greater than 110°, to obtain the second back surface structure 110. Figures 23(a) to (d) are schematic diagrams of the morphology after silicon etching and annealing treatment on the back surface of the wafer. Among them, Figure 23(a) is a schematic diagram of the morphology after silicon etching on the back surface of the wafer, Figure 23(b) is a schematic diagram of the morphology after laser annealing with 1.3 J on the back surface of the wafer, Figure 23(c) is a schematic diagram of the morphology after laser annealing with 2.0 J on the back surface of the wafer, and Figure 23(d) is a schematic diagram of the morphology after laser annealing with 2.6 J on the back surface of the wafer. Combining Figures 23(a) to (d), it can be seen that after laser annealing, the "pyramid" peak situation on the back surface of the wafer has been significantly improved. As Figure 9 As shown, corresponding to step S300, a photoresist 200 is spin-coated on the surface of the second back surface structure 110, and multiple light-transmitting regions are formed by developing and exposing. As Figure 10 As shown, corresponding to step S400, ion implantation is performed in the light-transmitting regions to form an ion-doped region 400. The photoresist hardened due to ion implantation is denoted by 300. The ion implantation is, for example, N-type ion implantation or P-type ion implantation to form an N-type doped region or a P-type doped region. As Figure 11 As shown, the photoresist is removed by dry etching, or after dry etching to remove the photoresist, EKC cleaning is added. Since the photoresist is not penetrated by the implanted ions, the photoresist on the final back surface silicon is completely removed. Therefore, this method effectively reduces the adverse effects of the uneven topography of the "pyramid" shape, reduces the gradient change of the photoresist thickness, and avoids the problem that the photoresist is penetrated during ion implantation due to the thin photoresist thickness at the "pyramid" peaks. During ion implantation, a relatively uniform photoresist layer can more stably block ions, allowing the implantation energy to fluctuate within a larger range without penetrating the photoresist layer, thereby increasing the process window and enabling good ohmic contact between the back surface metal and the back surface silicon; at the same time, the Vcesat value is effectively reduced and the Vcesat value converges.

[0068] Figures 12 - 16 is a flowchart of the back surface process manufacturing method of the semiconductor device according to the second embodiment of the present application. As Figure 12 As shown, corresponding to step S100, first, a wafer is provided, and after the conventional front surface process, the back surface of the wafer is thinned and silicon-etched to form a first back surface structure 100 with an uneven topography in the shape of a "pyramid". As Figure 13As shown, corresponding to step S200, a silicon dioxide layer 500 is deposited on the surface of the first back structure 100 by SACVD as a protective layer to obtain a second back structure. The thickness of the silicon dioxide layer 500 is As Figure 14 shown, corresponding to step S300, a photoresist 200 is spin-coated on the surface of the second back structure and exposed and developed to form a plurality of light-transmitting regions. Then, the silicon dioxide layer in the light-transmitting regions is removed by dry etching. Optionally, hydrofluoric acid is added for cleaning. As Figure 15 shown, corresponding to step S400, ion implantation is performed with the photoresist 200 and the silicon dioxide layer 500 as masks to form a doped region 400. The photoresist hardened due to ion implantation is denoted by 300. The ion implantation is, for example, N-type ion implantation or P-type ion implantation to form an N-type doped region or a P-type doped region. As Figure 16 shown, the photoresist is removed by dry etching or the photoresist is removed by dry etching and then an EKC cleaning agent is added for cleaning, and then the silicon dioxide layer is removed by wet etching. Finally, the photoresist and the silicon dioxide layer on the back surface of the silicon are completely removed. Since during ion implantation, under the isolation of the silicon dioxide layer, the ion implantation will not penetrate the photoresist, and the silicon dioxide layer absorbs part of the ion energy. Even if the photoresist is thin, it is difficult for ions to penetrate, which broadens the allowable range of the implantation energy, reduces the dependence on the thickness of the photoresist layer at the same time, and avoids the problem that the photoresist is difficult to completely remove. Therefore, this method effectively reduces the adverse effects of the high and low step differences on the back surface of the wafer, avoids the problem of ion implantation penetrating the photoresist, increases the process window, enables good ohmic contact between the back surface metal and the back surface silicon; at the same time, effectively reduces the Vcesat value and makes the Vcesat value converge. In another alternative embodiment, in step S400, first, the photoresist 200 is etched away (such as by using a dry etching process), then ion implantation is performed with the silicon dioxide layer 500 as a mask to form a doped region 400, and then the silicon dioxide layer is removed by wet etching. This embodiment completely removes the photoresist before the ion implantation step, further ensuring that the photoresist can be completely removed. The silicon dioxide layer 500 has a larger thickness to provide better isolation protection during the ion implantation process. For example, the thickness of the silicon dioxide layer 500 is

[0069] Figures 17 - 22 is a flowchart of a back process manufacturing method for a semiconductor device according to the third embodiment of the present application. As Figure 17 shown, corresponding to step S100, first, a wafer is provided. After the conventional front process, the back surface of the wafer is thinned and silicon-etched to form a first back structure 100 with an uneven "pyramid" shape. As Figure 18As shown, corresponding to step S200, annealing treatment is performed on the back surface of the wafer using a green laser with a wavelength of 492 nm to 550 nm. The annealing energy is 1.2 J to 3 J, the scanning overlap rate in the X direction is greater than 50%, and the scanning overlap rate in the Y direction is greater than 65%, so that the temperature of the back surface of the wafer is higher than 1400 °C, melting the surface silicon on the back surface of the wafer, flattening the "pyramid" peaks, and changing the "pyramid" peak angle from an acute angle to an obtuse angle, preferably greater than 110°, to obtain the flattened structure 110. Then, silicon dioxide layer 500 is deposited on the surface of the flattened structure 110 by SACVD as a protective layer to obtain the second back surface structure. The thickness of the silicon dioxide layer 500 is As Figure 19 shown, corresponding to step S300, photoresist 200 is spin-coated on the surface of the second back surface structure and exposed and developed to form a plurality of light-transmitting regions. Then, the silicon dioxide layer in the light-transmitting regions is removed by dry etching. Optionally, hydrofluoric acid cleaning is added. As Figure 20 shown, corresponding to step S400, ion implantation is performed with photoresist 200 and silicon dioxide layer 500 as masks to form the doped region 400. The photoresist hardened due to ion implantation is denoted by 300. The ion implantation is, for example, N-type ion implantation or P-type ion implantation to form an N-type doped region or a P-type doped region. As Figure 21As shown, the photoresist is removed by dry etching or the photoresist is removed by dry etching and then an EKC cleaning agent is added for cleaning, and then the silicon dioxide layer is removed by wet etching. Finally, the photoresist and the silicon dioxide layer on the back surface of the silicon are completely removed. Since the surface of the first back structure is planarized, the subsequent formed dioxide layer and photoresist layer will not have regions with too thin thickness. During ion implantation, under the isolation of the silicon dioxide layer, the silicon dioxide layer absorbs part of the ion energy. Even if the photoresist is thin, it is difficult for ions to penetrate, broadening the allowable range of implantation energy, reducing the dependence on the thickness of the photoresist layer, and there is no region with too thin thickness in the photoresist layer, so ions will not penetrate the photoresist during ion implantation, avoiding the problem that the photoresist is difficult to completely remove. This embodiment combines the processes of laser annealing planarization treatment and the protection provided by the silicon dioxide layer. The planarized surface reduces the thickness non-uniformity of the silicon dioxide layer and the photoresist, and the silicon dioxide layer can provide further protection. Even in the case of higher implantation energy or thinner photoresist, it can still effectively block ion penetration, significantly improving the process robustness. Therefore, this method effectively reduces the adverse effects of the "pyramid" peaks on the back of the wafer, avoids the problem of ion penetration through the photoresist during ion implantation, increases the process window, enabling good ohmic contact between the back metal and the back silicon; at the same time, it effectively reduces the Vcesat value and makes the Vcesat value converge. In another alternative embodiment, in step S400, first, the photoresist 200 is etched away (such as using a dry etching process), then ion implantation is performed with the silicon dioxide layer 500 as a mask to form a doped region 400, and then the silicon dioxide layer is removed by wet etching. In this embodiment, the photoresist is completely removed before the ion implantation step, further ensuring that the photoresist can be completely removed. The silicon dioxide layer 500 has a relatively large thickness to provide better isolation protection during ion implantation. For example, the thickness of the silicon dioxide layer 500 is

[0070] Figure 22 shows a comparison diagram of Vcesat of an RCIGBT device after annealing treatment (such as laser annealing) before the ion implantation step and Vcesat of a semiconductor device without annealing treatment before the ion implantation step. From Figure 22 it can be seen that by using laser annealing treatment before the ion implantation step, the Vcesat value is generally low and has good convergence, while for the device without annealing treatment before the ion implantation step, the Vcesat value is generally high and has a wide distribution range (discrete). For the back of the RCIGBT device, there is not only local N-type ion implantation but also all or part of P-type ion implantation, such as boron. Since the boron ion implantation energy is relatively low, generally less than 50 keV, the uneven "pyramid" shape also has an impact on boron ion implantation. It is preferably to perform the boron ion implantation process after the laser annealing treatment.

[0071] In summary, the backside process manufacturing method of the semiconductor device provided by the present application and the semiconductor device have the following advantages:

[0072] Before the lithography process, laser annealing treatment is performed on the first backside structure of the wafer backside and / or a protective layer is formed on the backside, effectively reducing the adverse effects of the uneven topography of the "pyramid" shape and avoiding the problem of photoresist penetration during ion implantation. Through the dual optimization of surface planarization and / or dielectric layer protection, the sensitivity of the process to the silicon surface roughness, photoresist thickness, and ion implantation energy is significantly reduced, expanding the allowable fluctuation range of key process parameters (such as implantation energy, photoresist thickness, cleaning time, etc.), thereby increasing the process window and enabling good ohmic contact between the backside metal and the backside silicon; at the same time, the Vcesat value is effectively reduced and the Vcesat value converges. Using this method is conducive to achieving a higher production yield, obtaining semiconductor devices with more stable electrical properties, and making the process control more flexible during the manufacturing process.

[0073] The above content is a further detailed description of the present application in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present application is only limited to these descriptions. For those of ordinary skill in the technical field to which the present application belongs, without departing from the concept of the present application, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present application.

Claims

1. A method for manufacturing a backside process of a semiconductor device, characterized in that, Comprising: Processing the back surface of the wafer, wherein the back surface of the wafer includes a first back structure having a pyramid shape; Processing the first back structure to obtain a second back structure; wherein, processing the first back structure includes: planarizing the first back structure and / or forming a protective layer on the surface of the first back structure; Using a lithography process to form a plurality of light-transmitting regions on the surface of the second back structure; Performing ion implantation on the light-transmitting regions to form doped regions.

2. The method for manufacturing a backside process of a semiconductor device according to claim 1, wherein Planarizing the first back structure includes: performing laser annealing on the first back structure to planarize the peaks of the pyramid shape.

3. The method for manufacturing a backside process of a semiconductor device according to claim 1, wherein Processing the first back structure includes forming a protective layer on the surface of the first back structure; using a lithography process to form a plurality of light-transmitting regions on the surface of the second back structure, including the following steps: Setting a photoresist on the surface of the second back structure and performing exposure and development to form a plurality of light-transmitting regions; Etching away the protective layer in the light-transmitting regions.

4. The method for manufacturing a backside process of a semiconductor device according to claim 3, wherein, Before the step of performing ion implantation on the light-transmitting regions to form doped regions, the following steps are further included: Removing the photoresist on the surface of the second back structure.

5. The method for manufacturing the backside process of the semiconductor device according to claim 3, characterized in that, After the step of performing ion implantation on the light-transmitting regions to form doped regions, the following steps are further included: Etching away the photoresist; Etching away the protective layer.

6. The method for manufacturing the backside process of a semiconductor device according to claim 1, characterized in that, Processing the first back structure includes the following steps: Performing laser annealing on the first back structure to planarize the peaks of the pyramid shape; Forming the protective layer on the surface of the first back structure after laser annealing.

7. The method for manufacturing the backside process of a semiconductor device according to claim 2 or 6, characterized in that, Performing laser annealing on the first back structure includes one or more of the following conditions: (1) Using a laser with a wavelength of 492 nm to 550 nm; (2) The laser annealing energy is 1.2 J - 3 J; (3) The scanning overlap rate in the X direction is greater than 50%; (4) The scanning overlap rate in the Y direction is greater than 65%.

8. The method for manufacturing a backside process of a semiconductor device according to claim 1, characterized in that, The protective layer is a silicon dioxide layer; and / or the thickness of the protective layer is 9. The method for manufacturing a backside process of a semiconductor device according to claim 2 or 6, characterized in that, Performing the ion implantation on the back surface of the wafer after the laser annealing step.

10. A semiconductor device, characterized in that, The back structure of the semiconductor device is manufactured by the method according to any one of claims 1 to 9.

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