A low residual voltage ESD device and its preparation method

Abstract

The present invention discloses a low residual voltage ESD device and a method for manufacturing the same. The method comprises: providing a P-type substrate, exposing an N-type implantation region and a P-type implantation region through a mask layer; simultaneously implanting inert ions into the N-type implantation region and the P-type implantation region to form an amorphous structure layer; implanting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region; performing multiple annealing treatments on the P-type substrate and forming a passivation layer on the surface of the P-type substrate; etching the passivation layer to form contact holes to expose the surfaces of the N-type implantation region and the P-type implantation region, and growing an electrode layer in the contact holes to obtain a low residual voltage ESD device. The present invention forms an ultra-shallow junction through the amorphous structure layer and low-energy ion implantation, which can significantly reduce the on-resistance of the ESD device and reduce the voltage clamping residual voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a low residual voltage ESD device and a preparation method thereof. Background Art

[0002] As semiconductor process nodes move below 7nm, the core voltage of the chip drops to 1V or even below 0.8V, but the clamping residual voltage of traditional ESD devices (such as diodes and SCRs) is usually higher than 5V.

[0003] In advanced processes, the gate oxide layer is only a few angstroms thick, and the breakdown voltage may be less than 2V. The residual voltage of traditional ESD devices (5V) far exceeds this threshold, rendering their protection ineffective. For example, in 7nm FinFET manufacturing, the NMOS gate oxide breakdown voltage is approximately 1.8V. If the residual voltage of the ESD device is 5V, the electrostatic shock will directly penetrate the gate oxide, causing permanent damage.

[0004] Therefore, the existing technology still has the problem that when ESD devices are used in circuits and are subjected to a large current shock, they cannot quickly discharge the large current, causing device damage and rendering protection ineffective. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the present invention aims to provide a low residual voltage ESD device and a method for preparing the same, in order to solve the above-mentioned problems described in the background art.

[0006] One aspect of the present invention is to provide a method for preparing a low residual voltage ESD device, the method comprising:

[0007] Providing a P-type substrate;

[0008] Coating photoresist on the surface of the P-type substrate, exposing and developing, to obtain a mask layer, exposing the N-type injection region and the P-type injection region isolated from each other;

[0009] Simultaneously injecting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer;

[0010] Implanting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, and removing the mask layer;

[0011] Performing multiple annealing processes on the P-type substrate and forming a passivation layer on the surface of the P-type substrate;

[0012] The passivation layer is etched to form a hole to obtain a contact hole to expose the surface of the N-type injection region and the P-type injection region, and an electrode layer is grown in the contact hole to obtain a low residual voltage ESD device.

[0013] According to one aspect of the above technology, the step of simultaneously implanting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer includes:

[0014] Simultaneously implanting silicon ions into the N-type implant region and the P-type implant region of the P-type substrate to form an amorphous structure layer;

[0015] The silicon ion implantation energy into the N-type implantation area and the P-type implantation area is 16keV-24keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

[0016] According to one aspect of the above technology, phosphorus ions are implanted into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region. The implantation energy of the phosphorus ions is 3keV-4keV, and the implantation dose is 1×10 15 cm -2 -3×10 15 cm -2 ;

[0017] In the step of implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, the implantation energy of the boron ions is 1keV-4keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

[0018] According to one aspect of the above technology, the step of performing multiple annealing treatments on the P-type substrate and forming a passivation layer on the surface of the P-type substrate includes:

[0019] Performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment is completed;

[0020] In a hydrogen atmosphere, a third annealing treatment is performed on the P-type substrate according to preset third process parameters, and a passivation layer is formed on the surface of the P-type substrate.

[0021] According to one aspect of the above technology, the steps of performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment is completed, include:

[0022] In a nitrogen atmosphere, performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment is completed;

[0023] Among them, the first annealing temperature in the first process parameter is 550° C.-630° C., and the first annealing time is 25s-40s. The second annealing temperature in the second process parameter is 960° C.-1080° C., and the second annealing time is 1s-3s.

[0024] According to one aspect of the above technology, in a hydrogen atmosphere, the P-type substrate is subjected to a third annealing treatment according to preset third process parameters, and in the step of forming a passivation layer on the surface of the P-type substrate, in the third process parameters, the third annealing temperature is 370°C-420°C, and the third annealing time is 12min-15min.

[0025] According to one aspect of the above technology, the passivation layer is an overlapping structure of Si3N4 / SiO2 with a thickness of 60nm-80nm.

[0026] According to one aspect of the above technology, the passivation layer is etched to form a contact hole to expose the surface of the N-type implantation region and the P-type implantation region, and an electrode layer is grown in the contact hole to obtain a low residual voltage ESD device, including the following steps:

[0027] Etching the passivation layer to open windows to obtain an N-pole contact hole and a P-pole contact hole to expose the surfaces of the N-type implantation region and the P-type implantation region respectively;

[0028] Depositing VO2 material on the surfaces of the N-type injection region and the P-type injection region in the N-pole contact hole and the P-pole contact hole at the same time, and etching to form an electrode interdigital structure;

[0029] A Pt material is sputtered on the electrode interdigital structure, and a thermal-sensitive electrode layer with a curved structure is formed by photolithography to obtain a low residual voltage ESD device.

[0030] Another aspect of the present invention is to provide a low residual voltage ESD device, which is prepared by the preparation method described in the above technical solution.

[0031] Compared with the prior art, the low residual voltage ESD device and the preparation method thereof shown in the present invention have the following beneficial effects:

[0032] The present invention forms an amorphous structure layer by injecting inert ions into the N-type injection area and the P-type injection area of the P-type substrate, then performs phosphorus ion implantation into the N-type injection area to form an N-type trigger area on the surface of the amorphous structure layer in the N-type injection area, and performs boron ion implantation into the P-type injection area to form a P-type anode area on the surface of the amorphous structure layer in the P-type injection area. An ultra-shallow junction is formed by the amorphous structure layer and the low-energy ion implantation, which can significantly reduce the on-resistance of the ESD device and reduce the voltage clamping residual voltage. Moreover, the ultra-shallow junction cooperates with the low-resistance electrode layer to enable the ESD device to quickly discharge a large current under a nanosecond ESD pulse, thereby better protecting the circuit devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0034] Figure 1 Schematic diagram of a process for preparing a low residual voltage ESD device according to an embodiment of the present invention;

[0035] Figure 2 A schematic structural diagram of a low residual voltage ESD device manufacturing process according to an embodiment of the present invention;

[0036] Component symbol description in the attached figure:

[0037] P-type substrate 10, mask layer 20, N-type implantation region 30, N-region amorphous structure layer 31, N-type trigger region 32, P-type implantation region 40, P-region amorphous structure layer 41, P-type anode region 42, passivation layer 50, N-region contact hole 51, P-region contact hole 52, electrode layer 60, N-region electrode 61, and P-region electrode 62. DETAILED DESCRIPTION

[0038] To make the objectives, features, and advantages of the present invention more readily apparent, the following detailed description of specific embodiments of the present invention is provided in conjunction with the accompanying drawings. The accompanying drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0039] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] Example 1

[0042] See also Figure 1 and Figure 2 The first embodiment of the present invention provides a method for preparing a low residual voltage ESD device, which is used to manufacture a low residual voltage ESD device. It should be noted that in this embodiment, the ESD device is an SCR type device. The preparation method includes steps S10 to S60:

[0043] Step S10: providing a P-type substrate.

[0044] In this embodiment, the P-type substrate 10 is made of a wide bandgap material (such as SiC, GaN) or a low-resistivity silicon-based material (such as SOI) to reduce the on-resistance of the device, thereby reducing the residual voltage of the device.

[0045] Preferably, in this embodiment, the P-type substrate 10 is made of SiC material.

[0046] In step S20 , photoresist is coated on the surface of the P-type substrate, and the photoresist is exposed and developed to obtain a mask layer, thereby exposing the N-type implantation region and the P-type implantation region that are isolated from each other.

[0047] In this embodiment, before coating the surface of the P-type substrate 10 with photoresist, the P-type substrate 10 needs to be immersed and rinsed with deionized water and then dried, thereby improving the cleanliness of the P-type substrate 10 .

[0048] Furthermore, photoresist is coated on the surface of the P-type substrate 10 in the epitaxial growth direction, specifically by spin coating the photoresist, and then exposed and developed to obtain a mask layer 20 attached to the surface of the P-type substrate 10, and expose the N-type injection area 30 and the P-type injection area 40 separated from each other in the P-type substrate 10.

[0049] There may be multiple N-type implant regions 30 and multiple P-type implant regions 40 .

[0050] In step S30 , inert ions are simultaneously implanted into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer.

[0051] In this embodiment, the step of simultaneously implanting inert ions into the N-type implantation region 30 and the P-type implantation region 40 of the P-type substrate 10 to form an amorphous structure layer includes:

[0052] Simultaneously implanting silicon ions into the N-type implant region 30 and the P-type implant region 40 of the P-type substrate 10 to form an amorphous structure layer;

[0053] The silicon ion implantation energy into the N-type implantation region 30 and the P-type implantation region 40 is 16keV-24keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

[0054] Specifically, silicon ions are implanted into the N-type implant region 30 and the P-type implant region 40 using silicon ions as dopants to obtain an N-region amorphous structure layer 31 located at the bottom of the N-type implant region 30 and a P-region amorphous structure layer 41 located at the bottom of the P-type implant region 40. The implantation energy is 10keV-30keV, preferably 16keV-24keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 , preferably 5×10 14 cm -2 , to destroy the surface lattice to form an amorphous structure layer, thereby inhibiting the channel penetration of subsequent doped ions, ensuring shallow junction uniformity, and a junction depth of less than 50nm.

[0055] Step S40, injecting phosphorus ions into the N-type injection area to form an N-type trigger area on the surface of the amorphous structure layer in the N-type injection area, and injecting boron ions into the P-type injection area to form a P-type anode area on the surface of the amorphous structure layer in the P-type injection area, and removing the mask layer.

[0056] In this embodiment, phosphorus ions are implanted into the N-type implantation region 30 to form an N-type trigger region 32 on the surface of the amorphous structure layer in the N-type implantation region 30. The implantation energy of the phosphorus ions is 3keV-4keV, and the implantation dose is 1×10 15 cm -2 -3×10 15 cm -2 .

[0057] In addition, in the step of injecting boron ions into the P-type injection region 40 to form a P-type anode region 42 on the surface of the amorphous structure layer in the P-type injection region 40, the injection energy of the boron ions is 1keV-4keV, and the injection dose is 4×10 14 cm -2-6×10 14 cm -2 .

[0058] Specifically, in this embodiment, the penetration depth of low-energy ions is controlled by setting an extremely low energy for ion implantation. For example, the implantation energy of phosphorus ions is 3keV-4keV, preferably 4keV, and the implantation energy of boron ions is 1keV-4keV, preferably 2keV.

[0059] In addition, the implantation dose needs to be adjusted according to the target doping concentration. The implantation dose of phosphorus ions and boron ions is usually 1×10 14 cm -2 -1×10 16 cm -2 Specifically, the phosphorus ion implantation dose is 1×10 15 cm -2 -3×10 15 cm -2 , preferably 2×10 15 cm -2 , and the implantation dose of boron ions is 4×10 14 cm -2 -6×10 14 cm -2 , preferably 5×10 14 cm -2 .

[0060] Similarly, to avoid channeling during low-energy ion implantation, the wafer, ie, the P-type substrate 10 , needs to be tilted at a certain angle, such as 10°-30°, to deviate from the main crystal orientation for ion implantation.

[0061] Step S50 , performing multiple annealing processes on the P-type substrate, and forming a passivation layer on the surface of the P-type substrate.

[0062] By performing inert ion implantation on the N-type implantation region 30 and the P-type implantation region 40 of the P-type substrate 10, the surface lattice is destroyed to form an amorphous structure layer. The amorphous structure layer suppresses the channel penetration of subsequent doped ions, ensuring that the shallow junction has good uniformity. Then, phosphorus ion implantation and boron ion implantation are performed on the N-type implantation region 30 and the P-type implantation region 40 of the P-type substrate 10, respectively, to form an N-type trigger region 32 on the surface of the amorphous structure layer in the N-type implantation region 30, and a P-type anode region 42 on the surface of the amorphous structure layer in the P-type implantation region 40.

[0063] In this embodiment, after the N-type trigger region 32 and the P-type anode region 42 are formed, the P-type substrate 10 as a whole is subjected to multiple annealing processes, such as low-temperature annealing and high-temperature annealing. Specifically, low-temperature annealing is used to repair lattice damage caused by ion implantation, and high-temperature annealing is used to quickly activate dopants and suppress impurity diffusion.

[0064] After low-temperature annealing and high-temperature annealing, another annealing treatment will be performed. The annealing temperature is lower than that of the low-temperature annealing process to passivate interface dangling bonds and residual defects, achieve defect passivation, thereby reducing junction leakage current and improving device reliability.

[0065] Step S60 , etching the passivation layer to form a hole to expose the surface of the N-type implantation region and the P-type implantation region, and growing an electrode layer in the contact hole to obtain a low residual voltage ESD device.

[0066] In this embodiment, after the passivation layer 50 is produced on the surface of the P-type substrate 10, since the passivation layer 50 covers the entire surface of the P-type substrate 10, including the surfaces of the N-type injection region 30 and the P-type injection region 40, in order to achieve electrical connection between the device and the circuit board, the passivation layer 50 needs to be etched to obtain contact holes, that is, electrode connection holes, including N-region contact holes 51 and P-region contact holes 52 that expose the N-type injection region 30 and the P-type injection region 40. Then, an ALD process is used to produce a metal structure electrode layer 60 in the contact hole, including an N-region electrode 61 and a P-region electrode 62, such as a Ti / AlCu electrode with a relatively low resistivity, to finally obtain the overall structure of the low residual voltage ESD device.

[0067] Compared with the prior art, the method for preparing a low residual voltage ESD device shown in this embodiment has the following beneficial effects:

[0068] In this embodiment, inert ions are injected into the N-type injection region 30 and the P-type injection region 40 of the P-type substrate 10 to form an amorphous structure layer, and then phosphorus ions are implanted into the N-type injection region 30 to form an N-type trigger region 32 on the surface of the amorphous structure layer in the N-type injection region 30, and boron ions are implanted into the P-type injection region 40 to form a P-type anode region 42 on the surface of the amorphous structure layer in the P-type injection region 40. An ultra-shallow junction is formed by the amorphous structure layer and the low-energy ion implantation, which can significantly reduce the on-resistance of the ESD device and reduce the voltage clamping residual voltage. Moreover, the ultra-shallow junction cooperates with the low-resistance electrode layer 60 to enable the ESD device to quickly discharge a large current under a nanosecond ESD pulse, thereby better protecting the circuit devices.

[0069] Example 2

[0070] Please refer to Figure 2The second embodiment of the present invention also provides a method for preparing a low residual voltage ESD device. The preparation method shown in this embodiment is basically the same as the preparation method shown in the first embodiment, except that:

[0071] In this embodiment, the steps of performing multiple annealing treatments on the P-type substrate 10 and forming a passivation layer 50 on the surface of the P-type substrate 10 include:

[0072] Performing a first annealing treatment on the P-type substrate 10 according to a preset first process parameter, and performing a second annealing treatment according to a preset second process parameter after the first annealing treatment is completed;

[0073] In a hydrogen atmosphere, a third annealing treatment is performed on the P-type substrate 10 according to preset third process parameters, and a passivation layer 50 is formed on the surface of the P-type substrate 10 .

[0074] Furthermore, the steps of performing a first annealing treatment on the P-type substrate 10 according to a preset first process parameter, and performing a second annealing treatment according to a preset second process parameter after the first annealing treatment is completed include:

[0075] In a nitrogen atmosphere, performing a first annealing treatment on the P-type substrate 10 according to a preset first process parameter, and performing a second annealing treatment according to a preset second process parameter after the first annealing treatment is completed;

[0076] Among them, the first annealing temperature in the first process parameter is 550° C.-630° C., and the first annealing time is 25s-40s. The second annealing temperature in the second process parameter is 960° C.-1080° C., and the second annealing time is 1s-3s.

[0077] Furthermore, in a hydrogen atmosphere, the P-type substrate 10 is subjected to a third annealing treatment according to preset third process parameters, and in the step of forming a passivation layer 50 on the surface of the P-type substrate 10, in the third process parameters, the third annealing temperature is 370°C-420°C, and the third annealing time is 12min-15min.

[0078] In addition, the passivation layer 50 is an overlapping structure of Si3N4 / SiO2, and has a thickness of 60nm-80nm.

[0079] Specifically, in this embodiment, a two-step annealing process of rapid thermal annealing is included, including the above-mentioned first annealing treatment and the second annealing treatment. During the first annealing treatment, it is required to be carried out in an N2 atmosphere, the first annealing temperature is 550℃-630℃, preferably 590℃, and the first annealing time is 25s-40s, preferably 35s, so that the lattice damage between the P-type substrate 10 and the N-type trigger region 32 and the P-type anode region 42 is repaired through the first annealing treatment.

[0080] During the second annealing process, it is also carried out in an N2 atmosphere. The second annealing temperature is 960°C-1080°C, preferably 1020°C, and the second annealing time is 1s-3s. Usually, a 1s spike annealing process is used to activate the dopants in the N-type trigger region 32 and the P-type anode region 42 and inhibit the diffusion of dopants.

[0081] During the third annealing process, it is required to be carried out in an H2 atmosphere, the third annealing temperature is 370℃-420℃, preferably 400℃, and the third annealing time is 12min-15min, preferably 13min, so as to passivate the interface dangling bonds between the P-type substrate 10 and the N-type trigger region 32 and the P-type anode region 42, thereby reducing leakage current.

[0082] Compared with the first embodiment, the preparation method shown in this embodiment has the following beneficial effects:

[0083] In this embodiment, a two-step thermal annealing process is adopted, including low-temperature repair and high-temperature activation, which effectively repairs ion implantation damage and reduces the defect density in the junction area. Hydrogen annealing further passivates the interface dangling bonds and reduces carrier traps. The amorphization treatment and hydrogen passivation of the aforementioned inert ion implantation reduce lattice defects, avoid permanent damage after ESD pulse impact, and thus effectively improve the service life of the ESD device.

[0084] Example 3

[0085] The third embodiment of the present invention also provides a method for preparing a low residual voltage ESD device. The preparation method shown in this embodiment is basically similar to the preparation method shown in the first embodiment, except that:

[0086] In this embodiment, the passivation layer 50 is etched to form a contact hole to expose the surface of the N-type implantation region 30 and the P-type implantation region 40, and an electrode layer 60 is grown in the contact hole to obtain a low residual voltage ESD device, including the following steps:

[0087] The passivation layer 50 is etched to form an N-pole contact hole and a P-pole contact hole to expose the surfaces of the N-type implantation region 30 and the P-type implantation region 40 respectively;

[0088] Depositing VO2 material on the surfaces of the N-type injection region 30 and the P-type injection region 40 in the N-pole contact hole and the P-pole contact hole at the same time, and etching to form an electrode interdigital structure;

[0089] Pt material is sputtered on the electrode interdigital structure, and a thermal-sensitive electrode layer 60 with a curved structure is formed by photolithography to obtain a low residual voltage ESD device.

[0090] Specifically, in this embodiment, after the N-type trigger region 32 and the P-type anode region 42 are fabricated, annealed, and the passivation layer 50 is fabricated, the passivation layer 50 is photolithographically opened to obtain an N-type contact hole and a P-type contact hole, exposing the surfaces of the N-type injection region 30 and the P-type injection region 40, respectively. VO2 (vanadium dioxide) material is then deposited by magnetron sputtering or atomic layer deposition, specifically in the form of a thin film with a thickness of typically 20 nm to 40 nm. The VO2 thin film is then dry-etched to form an electrode interdigital structure, thereby connecting the cathode of the N-type trigger region 32 and the anode of the P-type anode region 42 through the electrode interdigital structure. Finally, Pt material or Pt / TiN material is sputtered on the VO2 thin film region, i.e., on the electrode interdigital structure, as a heating electrode, and the Joule effect is used to locally increase the temperature to trigger the phase change of the VO2 material.

[0091] It should be noted that under normal conditions, VO2 material is in an insulating state with a resistance >10 3 Ω·cm, the ESD current is mainly discharged through the SCR (i.e., the main body of the SCR-type ESD device). When an ESD pulse impact occurs, the SCR is turned on to generate heat and actively heats the thermistor electrode layer 60, causing the temperature of the VO2 material to exceed the phase transition point and gradually transform into a metallic state, forming a low-resistance bypass, further reducing the voltage clamping residual voltage. After the ESD pulse impact ends, the temperature drops and the VO2 material returns to an insulating state, avoiding permanent damage caused by local melting, and ultimately preventing the residual leakage current path.

[0092] Comparative Example 1

[0093] The first comparative example also provides a method for preparing a low residual voltage ESD device, which is an improved traditional SCR process. The preparation method includes:

[0094] 1. Substrate preparation:

[0095] Provides a low-resistivity SOI silicon-based substrate with a resistivity of 0.1Ω·cm.

[0096] 2. Injection process:

[0097] Direct photolithography to define N / P regions without inert ion pre-implantation;

[0098] The implantation energy of phosphorus ions is 6 keV and the implantation dose is 2×10 15 cm -2 ;

[0099] The boron ion implantation energy is 3 keV and the implantation dose is 5×10 14 cm -2 .

[0100] 3. Annealing

[0101] In N2 atmosphere, a two-step annealing process was adopted, with the first annealing at 600℃ / 30s and the second annealing at 1000℃ / 2s, without hydrogen.

[0102] 4. Passivation layer preparation

[0103] A Si3N4 / SiO2 passivation layer is produced.

[0104] 5. Electrode production

[0105] The same Ti / AlCu electrode as in the embodiment of the present invention was produced.

[0106] Based on the above preparation method, a low residual voltage ESD device was prepared, and its performance was compared with the low residual voltage ESD devices shown in the first and second embodiments of the present invention. The comparison results are shown in Table 1:

[0107] Table 1

[0108]

[0109] As shown in Table 1, by combining optimization of ultra-shallow junctions (<35nm) and low-resistance electrodes, the present invention reduces residual voltage to below 2V (compared to 5V+ in conventional processes), a reduction of over 60%. When only the substrate and electrodes are improved (Comparative Example 1), the residual voltage drops to only 5.2V. This demonstrates that the amorphous structure layer plus three-step annealing in this embodiment of the present invention effectively reduces residual voltage, thereby enhancing protection.

[0110] Comparative Example 2

[0111] The second comparative example also provides a method for preparing a low residual voltage ESD device. Compared with the first embodiment, the difference between the method and the first embodiment is that:

[0112] The inert ion implantation is omitted, and the rest is completely consistent with the first embodiment.

[0113] Based on the above preparation method, a low residual voltage ESD device was prepared, and its performance was compared with the low residual voltage ESD device shown in the first embodiment of the present invention. The comparison results are shown in Table 2:

[0114] Table 2

[0115]

[0116] According to Table 2, if the amorphous structure layer is omitted (Comparative Example 2), even if the same annealing and electrode process as the first embodiment of the present invention are adopted, the residual voltage still reaches 4.5V and the on-resistance reaches 0.7Ω, which is still significantly lower than that of the first embodiment of the present invention.

[0117] Table 3 is a comparison table of key parameters of Examples 1 and 2 of the present invention and Comparative Examples 1 and 2:

[0118] Table 3

[0119]

[0120] As can be seen from Table 3, the low residual voltage ESD device prepared by the preparation method shown in the embodiment of the present invention can significantly reduce the on-resistance of the ESD device and reduce the voltage clamping residual voltage through the design of ultra-shallow junction and low-resistance electrode. In addition, through the cooperation of ultra-shallow junction and low-resistance electrode layer, the ESD device can quickly discharge large current, thereby better protecting circuit devices.

[0121] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0122] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for preparing a low residual voltage ESD device, characterized in that: The preparation method comprises: Providing a P-type substrate; Coating photoresist on the surface of the P-type substrate, exposing and developing, to obtain a mask layer, exposing the N-type injection region and the P-type injection region isolated from each other; Simultaneously injecting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer; Implanting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, and removing the mask layer; Performing multiple annealing processes on the P-type substrate and forming a passivation layer on the surface of the P-type substrate; The passivation layer is etched to form a contact hole to expose the surface of the N-type implantation region and the P-type implantation region, and an electrode layer is grown in the contact hole to obtain a low residual voltage ESD device; The step of simultaneously injecting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer includes: Simultaneously implanting silicon ions into the N-type implant region and the P-type implant region of the P-type substrate to form an amorphous structure layer; The silicon ion implantation energy into the N-type implantation area and the P-type implantation area is 16keV-24keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 ; Wherein, in the step of injecting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, the phosphorus ion implantation energy is 3keV-4keV, and the implantation dose is 1×10 15 cm -2 -3×10 15 cm -2 ; In the step of implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, the implantation energy of the boron ions is 1keV-4keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

2. The method for preparing a low residual voltage ESD device according to claim 1, wherein: The step of performing multiple annealing treatments on the P-type substrate and forming a passivation layer on the surface of the P-type substrate includes: Performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment is completed; In a hydrogen atmosphere, a third annealing treatment is performed on the P-type substrate according to preset third process parameters, and a passivation layer is formed on the surface of the P-type substrate.

3. The method for preparing a low residual voltage ESD device according to claim 2, wherein: The steps of performing a first annealing treatment on the P-type substrate according to a preset first process parameter, and performing a second annealing treatment according to a preset second process parameter after the first annealing treatment is completed, include: In a nitrogen atmosphere, performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment is completed; Among them, the first annealing temperature in the first process parameter is 550° C.-630° C., and the first annealing time is 25s-40s. The second annealing temperature in the second process parameter is 960° C.-1080° C., and the second annealing time is 1s-3s.

4. The method for preparing a low residual voltage ESD device according to claim 2, wherein: In a hydrogen atmosphere, the P-type substrate is subjected to a third annealing treatment according to preset third process parameters, and in the step of forming a passivation layer on the surface of the P-type substrate, in the third process parameters, the third annealing temperature is 370°C-420°C, and the third annealing time is 12min-15min.

5. The method for preparing a low residual voltage ESD device according to claim 4, wherein: The passivation layer is an overlapping structure of Si3N4 / SiO2 and has a thickness of 60nm-80nm.

6. The method for preparing a low residual voltage ESD device according to any one of claims 1 to 5, characterized in that: The passivation layer is etched to form a contact hole to expose the surface of the N-type injection region and the P-type injection region, and an electrode layer is grown in the contact hole to obtain a low residual voltage ESD device, including: Etching the passivation layer to open windows to obtain an N-pole contact hole and a P-pole contact hole to expose the surfaces of the N-type implantation region and the P-type implantation region respectively; Depositing VO2 material on the surfaces of the N-type injection region and the P-type injection region in the N-pole contact hole and the P-pole contact hole at the same time, and etching to form an electrode interdigital structure; A Pt material is sputtered on the electrode interdigital structure, and a thermal-sensitive electrode layer with a curved structure is formed by photolithography to obtain a low residual voltage ESD device.

7. A low residual voltage ESD device, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 6.

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