Asymmetric high-reliability trench gate silicon carbide VDMOS and its preparation method

Abstract

The present invention provides an asymmetric high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, comprising: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, performing epitaxial growth on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to form a shunt region and a P-type well region; reforming the barrier layer, etching, and depositing metal to form a Schottky metal layer; reforming the barrier layer, etching, and ion implanting to form a P-type base region, a P-type source region, and an N-type source region; reforming the barrier layer, etching, and depositing metal to form a source metal layer; reforming the barrier layer, etching, and depositing to form an insulating dielectric layer; reforming the barrier layer, etching, and depositing metal to form a gate metal layer, removing the barrier layer, and completing the preparation. The asymmetric trench gate structure is adopted, and the post-conduction characteristics of the device are ensured on one side, and the freewheeling characteristics of the device body diode are ensured on one side, thereby improving the reliability of the device.

Description

Technical Field

[0001] The invention relates to an asymmetric high-reliability trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Due to their wide bandgap characteristics, silicon carbide VDMOS devices naturally have the characteristics of low gate charge and high switching speed compared to Si VDMOS devices. However, due to the material bandgap width and the immature insulation dielectric preparation process, the gate reliability of the devices has not been fully resolved. At the same time, because the device current density is greater than that of Si, the body diode is prone to continuous current burnout, which requires improving the body diode continuous current capability of the device to enhance the device reliability. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an asymmetric high-reliability trench gate silicon carbide VDMOS and a preparation method thereof. The asymmetric trench gate structure is adopted to ensure the post-conduction characteristics of the device on one side and the freewheeling characteristics of the device body diode on one side, thereby improving the reliability of the device.

[0004] In a first aspect, the present invention provides a method for preparing an asymmetric high-reliability trench-gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a shunt region;

[0007] Step 3: removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region;

[0008] Step 4: remove the barrier layer in step 3, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer and the P-type well region, deposit metal, and form a Schottky metal layer;

[0009] Step 5: remove the barrier layer of step 4, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type base region;

[0010] Step 6: remove the barrier layer in step 5, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type source region;

[0011] Step 7: remove the barrier layer in step 6, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region;

[0012] Step 8: remove the barrier layer in step 7, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the P-type source region, deposit metal to form a source metal layer;

[0013] Step 9: removing the barrier layer of step 8, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer, the shunt region, and the P-type well region to form a first groove, and depositing an insulating dielectric layer;

[0014] Step 10: remove the barrier layer of step 9, re-form the barrier layer, etch the barrier layer to form a through hole, etch the insulating dielectric layer to form a groove, deposit metal to form a gate metal layer, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides an asymmetric high-reliability trench gate silicon carbide VDMOS, which is prepared by the method for preparing an asymmetric high-reliability trench gate silicon carbide VDMOS according to the first aspect.

[0016] The advantages of the present invention are:

[0017] First, the present invention constructs an asymmetric high-reliability trench gate structure, which embodies asymmetry and reliability from two aspects: the protection of the insulating dielectric layer by the P-type well region and the construction of the Schottky parasitic body diode;

[0018] Second, the asymmetric P-type well region constructed by the present invention, and the space charge region formed by the P-type well region, the drift layer, and the shunt region under reverse withstand voltage conditions, can effectively suppress the electric field concentration caused at the corner of the device gate, thereby improving the gate reliability of the device;

[0019] Third, the N-type source region and the P-type source region of the present invention are not symmetrically distributed on the left and right sides of the gate. This is because the Schottky metal layer constructed on one side of the P-type well region that semi-encloses the device gate is in direct contact with the N-type source region, which can increase the low-resistance contact area between the Schottky metal layer and the source metal layer, thereby improving the current capability of the Schottky diode;

[0020] 4. The asymmetric P-type well region of the present invention increases the pn junction contact area of ​​the parasitic pn junction body diode of the device, which can simultaneously increase the freewheeling capability of the pn junction body diode. The structural optimization of the two body diodes can improve the freewheeling capability of the device when it is turned off, thereby improving the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] Figure 1 This is a schematic diagram of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention.

[0023] Figure 2This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 1 .

[0024] Figure 3 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 2 .

[0025] Figure 4 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 3 .

[0026] Figure 5 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 4 .

[0027] Figure 6 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 5 .

[0028] Figure 7 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 6 .

[0029] Figure 8 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 7 .

[0030] Figure 9 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 8 .

[0031] Figure 10 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 9 .

[0032] Figure 11 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 10 .

[0033] Figure 12 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 10 one.

[0034] Figure 13 This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 10 two.

[0035] Figure 14This is a cross-sectional view of the process of an asymmetric high-reliability trench gate silicon carbide VDMOS of the present invention. Figure 10 three. DETAILED DESCRIPTION

[0036] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0038] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0039] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0040] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] like Figures 1 to 14 As shown, the embodiment of the present application provides a method for preparing an asymmetric high-reliability trench gate silicon carbide VDMOS, comprising the following steps:

[0042] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110, and epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102;

[0043] Step 2: forming a barrier layer 100 on the drift layer 102, etching the barrier layer 100 to form a through hole, and implanting ions to form a shunt region 1032;

[0044] Step 3: removing the barrier layer 100 in step 2, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type well region 103;

[0045] Step 4: remove the barrier layer 100 in step 3, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, etch the drift layer 102 and the P-type well region 103, and deposit metal to form a Schottky metal layer 106;

[0046] Step 5: removing the barrier layer 100 in step 4, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type base region 1033;

[0047] Step 6: removing the barrier layer 100 in step 5, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type source region 104;

[0048] Step 7: removing the barrier layer 100 in step 6, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form an N-type source region 105;

[0049] Step 8: remove the barrier layer 100 in step 7, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the drift layer 102 to the upper side of the P-type source region 104, and deposit metal to form a source metal layer;

[0050] Step 9: remove the barrier layer 100 in step 8, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the drift layer 102, the shunt region 1032 and the P-type well region 103 to form a first groove 1031, and deposit to form an insulating dielectric layer 107;

[0051] Step 10: remove the barrier layer 100 of step 9, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the insulating dielectric layer 107 to form a groove 1071, deposit metal to form a gate metal layer 108, remove the barrier layer 100, and complete the preparation.

[0052] In this embodiment, preferably, the drift layer 102 is provided with a second groove (not shown in the figure), and the lower portion of the Schottky metal layer 106 is provided in the second groove.

[0053] In this embodiment, preferably, the lower side surface of the gate metal layer 108 is lower than the lower side surface of the P-type base region 1033 .

[0054] In this embodiment, preferably, the doping concentration of the shunt region 1032 is greater than the doping concentration of the P-type base region 1033 , and the doping concentration of the P-type well region 103 is greater than the doping concentration of the P-type base region 1033 .

[0055] In this embodiment, preferably, the doping concentration of the shunt region 1032 is greater than the doping concentration of the drift layer 102 , and the doping concentration of the P-type well region 103 is greater than the doping concentration of the drift layer 102 .

[0056] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0057] silicon carbide substrate 101,

[0058] a drift layer 102 , wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101 ;

[0059] A P-type well region 103, wherein the lower side of the P-type well region 103 is connected to the upper side of the drift layer 102; a first groove 1031, a shunt region 1032, and a P-type base region 1033 are provided in the P-type well region 103, wherein the lower side of the shunt region 1032 is connected to the upper side of the drift layer 102, the shunt region 1032 is located at the lower left corner of the first groove 1031, and the lower side of the P-type base region 1033 is connected to the shunt region 1032 and is located on the left side of the first groove 1031;

[0060] A P-type source region 104 , wherein the lower side of the P-type source region 104 is connected to the upper side of the P-type well region 103 ;

[0061] An N-type source region 105 , wherein the lower side of the N-type source region 105 is connected to the P-type well region 103 and the P-type base region 1033 , and the N-type source region 105 is connected to the P-type source region 104 ;

[0062] a Schottky metal layer 106 , wherein a lower side of the Schottky metal layer 106 is connected to the drift layer 102 , and one side of the Schottky metal layer 106 is connected to one side of the P-type well region 103 and one side of the N-type source region 105 ;

[0063] an insulating dielectric layer 107, wherein a lower portion of the insulating dielectric layer 107 is disposed within the first groove 1031, and an outer side surface of the insulating dielectric layer 107 is respectively connected to the P-type source region 104, the N-type source region 105, the P-type well region 103, the P-type base region 1033, and the shunt region 1032; and a trench 1071 is defined within the insulating dielectric layer 107;

[0064] a gate metal layer 108 , wherein the gate metal layer 108 is disposed in the trench 1071 ;

[0065] A source metal layer 109 , the source metal layer being connected to the P-type source region 104 , the N-type source region 105 and the Schottky metal layer 106 ;

[0066] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .

[0067] In another embodiment of the present invention, the silicon carbide substrate 101, the drift layer 102 and the shunt region 1032 are all N-type, and the doping concentration of the silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the drift layer 102 is 6-10e15cm -3 , the doping concentration of the shunt region 1032 is 6-10e16cm -3 The doping concentration of the P-type well region 103 is 1-5e17cm -3 , the doping concentration of the P-type base region 1033 is 1-5e16cm -3 The doping concentration of the P-type source region 104 is 1-5e19cm -3 , the doping concentration of the N-type source region 105 is 2-8e18cm -3 , the material of the insulating dielectric layer 107 may be silicon dioxide;

[0068] The doping concentration of the silicon carbide substrate 101 is designed to ensure a low-resistance ohmic contact with the drain metal layer 110, thereby reducing the overall on-resistance of the device. The doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and on-resistance of the device. The doping concentration of the P-type well region 103 is designed to protect the gate and source of the device, shield the gate-drain capacitance, reduce the Maitreya capacitance, and improve the switching speed of the device.

[0069] The doping concentration of the shunt region 1032 is designed to: firstly, reduce the device's body resistance and thus reduce the device's conduction loss; secondly, to divert electrons from one side when the device is turned on, thereby increasing the device's effective freewheeling area, reducing the on-resistance, and avoiding heat concentration;

[0070] The Schottky metal layer 106 is used to construct a parasitic Schottky diode inside the device, thereby reducing the freewheeling loss of the device's body diode; the doping concentration of the P-type source region 104 is used to reduce the loss of the device's parasitic pn junction body diode; the doping concentration of the N-type source region 105 and the P-type source region 104 is designed to reduce the contact resistance of the device, thereby reducing the on-resistance of the device; the doping concentration of the N-type base region is designed to reduce the gate charge on the basis of ensuring the device's turn-off characteristics, thereby reducing the device's driving loss;

[0071] The thickness of the silicon carbide substrate 101 of the device is 1 μm, and the thickness of the drift layer 102 is 50-100 μm. The thickness can be adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The maximum thickness of the P-type well region 103 located on one side of the P-type base region 1033 is 1.2 μm, and the maximum width is 900 nm; the width of the P-type source region 104 located on one side of the P-type base region 1033 is 600 μm, and the thickness is 300 nm; the N-type source region 104 located on one side of the P-type base region 1033 is 600 μm, and the thickness is 300 nm. The thickness of the P-type source region 105 is 300nm and the width is 600nm; this is to construct a Schottky diode. The width of the Schottky metal layer 106 is 300nm, which is designed for the current capability of the device. The thickness of the Schottky metal layer 106 is 1.5μm, and its lower side is 300nm lower than the lower side of the P-type well region 103. This is to increase the Schottky junction contact area of ​​the Schottky diode and improve the current capability of the Schottky diode; the P-type base region 1033 The width of the shunt region 1032 is 300nm and the thickness is 300nm, which is to ensure the gate control capability of the device. The maximum width of the shunt region 1032 is 900nm and the maximum thickness is 600nm, which is to ensure that its bottom is flush with the bottom of the P-type well region 103 to ensure the structural integrity of the device. The width of the P-type well region 103 on one side of the Schottky metal layer 106 is 1.5μm, which is to ensure half-wrapping of the device gate. The width of the insulating dielectric layer 107 is 1.2μm, the bottom thickness of the insulating dielectric layer 107 is 100nm, and the thickness on both sides is 50nm, which ensures the voltage resistance of the insulating dielectric at the bottom of the device and improves reliability. The thickness of the insulating dielectric on the left and right sides of the device is 50nm to ensure the gate control capability of the device. The width of the device gate metal layer 108 is 1.1μm and the thickness is 1.1μm, which is to ensure that the lower side of the gate metal layer 108 is lower than the lower side of the P-type base region 1033 to ensure the gate control capability of the device.

[0072] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing an asymmetric high-reliability trench-gate silicon carbide VDMOS, characterized by: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a shunt region; Step 3: Ion implantation to form a P-type well region; Step 4: etching the drift layer and the P-type well region, depositing metal to form a Schottky metal layer; Step 5: Ion implantation to form a P-type base region; Step 6: Ion implantation to form a P-type source region; Step 7: Ion implantation to form an N-type source region; Step 8: Etching the drift layer to the upper side of the P-type source region, depositing metal to form a source metal layer; Step 9: etching the drift layer, the shunt region, and the P-type well region to form a first groove, and depositing an insulating dielectric layer; Step 10: Etching the insulating dielectric layer to form a groove, depositing metal to form a gate metal layer, removing the barrier layer, and completing the preparation; Before ion implantation in steps 3, 5-7, and before etching in steps 4, 8-10, the barrier layer of the previous step must be removed, a new barrier layer must be formed, and the barrier layer must be etched to form a through hole; The shunt region is located at the lower left corner of the first groove, and the lower side surface of the P-type base region is connected to the shunt region and is located on the left side of the first groove; The lower side of the P-type source region is connected to the upper side of the P-type well region; The lower side of the N-type source region is connected to the P-type well region and the P-type base region respectively, and the N-type source region is connected to the P-type source region; The lower side of the Schottky metal layer is connected to the drift layer, and one side of the Schottky metal layer is connected to one side of the P-type well region and one side of the N-type source region; The outer side surfaces of the insulating dielectric layer are respectively connected to the P-type source region, the N-type source region, the P-type well region, the P-type base region and the shunt region.

2. The method for preparing an asymmetric high-reliability trench-gate silicon carbide VDMOS according to claim 1, wherein: The drift layer is provided with a second groove, and the lower portion of the Schottky metal layer is provided in the second groove.

3. The method for preparing an asymmetric high-reliability trench-gate silicon carbide VDMOS according to claim 1, wherein: The lower side of the gate metal layer is lower than the lower side of the P-type base region.

4. The method for preparing an asymmetric high-reliability trench-gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the shunt region is greater than the doping concentration of the P-type base region, and the doping concentration of the P-type well region is greater than the doping concentration of the P-type base region.

5. The method for preparing an asymmetric high-reliability trench-gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the shunt region is greater than the doping concentration of the drift layer, and the doping concentration of the P-type well region is greater than the doping concentration of the drift layer.

6. An asymmetric high-reliability trench-gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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