Enhanced GaN HEMT device and preparation method thereof

Abstract

The invention provides an enhanced GaN HEMT (High Electron Mobility Transistor) device and a preparation method thereof. The device comprises a substrate; the epitaxial structure is epitaxially grown on the substrate; the secondary epitaxial layer is epitaxially grown on the epitaxial structure; the dielectric layer is arranged on the secondary epitaxial layer; communicated groove regions are arranged in the p-GaN layer, the dielectric layer and the secondary epitaxial layer, and the p-GaN layer epitaxially grows in the groove regions from the upper surface of the epitaxial structure; the grid electrode is arranged on the p-GaN layer; and the source electrode and the drain electrode are respectively arranged at two sides of the epitaxial structure, the secondary epitaxial layer and the dielectric layer. The device has a better high-frequency dynamic characteristic; the stability and the consistency of the grid threshold voltage are improved; the crack generation risk of the epitaxial wafer is low, and the MBE-grown p-GaN does not need to be subjected to subsequent activation treatment; the gate reliability is improved, and the stability of the device is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to an enhancement-mode GaN HEMT device and a preparation method thereof. Background Art

[0002] Due to its high critical breakdown electric field and relatively large carrier mobility, gallium nitride (GaN) material is very suitable for manufacturing high-efficiency power switching devices compared with traditional silicon (Si) materials. However, there are some technical problems to be solved urgently in conventional gallium nitride high electron mobility transistors (GaN HEMTs): First of all, conventional AlGaN / GaN HEMT devices are depletion-mode devices. Even when no bias voltage is applied in their channels, there is still a high concentration of two-dimensional electron gas (2DEG). This means that when no voltage is applied between the gate and the source, the HEMT is in the on state, and it only turns off when a negative voltage is applied to the gate. This characteristic makes the device prone to mis-conduction when the gate signal is lost, resulting in a short circuit in the circuit, which greatly limits its direct application in the circuit.

[0003] Secondly, in order to meet the requirements of circuit reliability and safety, normally-off (enhancement-mode) GaN HEMTs have become more conventional and mainstream device types. At present, there are mainly two solutions for enhancement-mode HEMTs: p-GaN gate and recessed gate. However, both of these solutions have their own defects: Commercially available p-GaN HEMTs generally have problems such as relatively large specific on-resistance and dynamic resistance degradation at high frequencies, seriously affecting the efficiency and performance of the devices; while recessed-gate enhancement-mode GaN HEMTs have problems with the reliability of the gate dielectric, and the recessed-gate etching process inevitably introduces interface defects, further affecting the stability and reliability of the devices.

[0004] In view of the above technical problems, the present invention proposes a new enhancement-mode GaN HEMT device and a preparation method thereof, which are expected to significantly reduce the specific on-resistance, improve the gate stability and the dynamic performance of the device, thereby overcoming the deficiencies of the existing technology. Summary of the Invention

[0005] Based on the above description, the present invention provides an enhancement-mode GaN HEMT device and a preparation method thereof to solve the problems of large specific on-resistance, dynamic resistance degradation at high frequencies, poor gate dielectric reliability, and interface defects introduced by the recessed-gate etching process in existing enhancement-mode GaN HEMTs, which limit their performance and application.

[0006] The technical solutions of the present invention to solve the above technical problems are as follows: In the first aspect, the present invention provides an enhancement-mode GaN HEMT device, including: A substrate; An epitaxial structure, which is epitaxially grown on the substrate; A secondary epitaxial layer, which is epitaxially grown on the epitaxial structure; A dielectric layer, which is disposed on the secondary epitaxial layer; A p-GaN layer. There is a connected trench region in the dielectric layer and the secondary epitaxial layer, and the p-GaN layer is epitaxially grown from the upper surface of the epitaxial structure in the trench region; A gate, which is disposed on the p-GaN layer; A source electrode and a drain electrode, which are respectively disposed on both sides of the epitaxial structure, the secondary epitaxial layer and the dielectric layer.

[0007] On the basis of the above technical solutions, the present invention can also be improved as follows.

[0008] Further, the epitaxial structure includes a nucleation layer, a buffer layer, a channel layer, an insertion layer and a thin barrier layer arranged in sequence from bottom to top.

[0009] Further, the channel layer is an i-GaN layer; The insertion layer is an AlN layer; The thin barrier layer is an AlGaN layer.

[0010] Further, the thickness of the channel layer is 50 - 800 nm, the thickness of the insertion layer is 0 - 5 nm, and the thickness of the thin barrier layer is 1 - 20 nm.

[0011] Further, the substrate is a p-type conductive silicon wafer or a top silicon conductive SOI wafer.

[0012] Further, the secondary epitaxial layer is an AlGaN layer with a thickness of 1 - 30 nm.

[0013] Further, a cap layer is provided on the top of the secondary epitaxial layer; The cap layer is a GaN or SiN layer with a thickness of 1 - 10 nm.

[0014] Further, the thickness of the p-GaN layer is 50 - 200 nm.

[0015] In a second aspect, the present invention also provides a preparation method for manufacturing the enhanced GaN HEMT device as described in the first aspect, including the following steps: S1: Epitaxially grow an epitaxial structure on the substrate to form a GaN epitaxial wafer with a thin barrier; S2: Use photolithography and dielectric etching processes to define the groove pattern in the gate region and complete the gate pattern coverage; S3: Perform secondary epitaxy of the barrier layer in the channel region to form a secondary epitaxial layer; S4: Grow a masking dielectric on the secondary epitaxial layer; S5: Open a pattern in the gate region; S6: Epitaxially grow a p-GaN layer in the opened region using low-temperature MBE technology; S7: Remove polycrystalline GaN in the non-gate region; S8: After the horizontal GaN HEMT process is taped out, deposit metal on the p-GaN layer to fabricate the gate, and deposit metal on both sides of the structure to fabricate the source and drain, respectively, thus obtaining the device.

[0016] Based on the above technical solutions, the present invention can also be improved as follows.

[0017] Further, step S1 specifically includes: Use metal-organic chemical vapor deposition technology to sequentially grow a starting layer, a buffer layer, a channel layer, an AlN insertion layer, and a barrier layer from bottom to top on the substrate to obtain the GaN epitaxial wafer with a thin barrier.

[0018] The enhanced GaN HEMT device, device structure, and preparation method provided by the present invention have the following beneficial effects compared with the prior art: 1. The barrier heterostructure is realized by two epitaxies. The specific on-resistance limit of the device decreases, and more devices can be fabricated from the same-sized epitaxial wafer, which is beneficial to reducing the cost of a single device; the distance between the channel electrons and the surface of the barrier layer is farther, and there is no etching damage on the surface of the barrier layer above the channel layer, so the device has better high-frequency dynamic characteristics.

[0019] 2. The gate recess structure is realized by two epitaxies. The formation of the recess in the gate region does not require the III-nitride etching process, and the stability and consistency of the gate threshold voltage are improved.

[0020] 3. The enhanced GaN HEMT power device is realized by secondary epitaxy of the p-GaN layer. The temperature of the low-temperature MBE secondary epitaxy of p-GaN is low, the degradation of the already grown HEMT two-dimensional electron gas is small, the risk of cracks in the epitaxial wafer is low, and the p-GaN grown by MBE does not require subsequent activation treatment.

[0021] 4. The pattern opening in the gate region is realized by dielectric etching. On this basis, the enhancement type is realized by secondary epitaxy of p-GaN. The etching surface can be repaired before the secondary epitaxy, and no gate dielectric needs to be introduced in this scheme, so the reliability of the gate is improved, and the stability of the device is further enhanced. Description of the Drawings

[0022] Figure 1Schematic diagram of the structure of the enhanced GaN HEMT device provided in Embodiment 1 of the present invention; Figure 2 Schematic diagram of the preparation process of the enhanced GaN HEMT device provided in Embodiment 2 of the present invention; In the drawings, the list of components represented by each reference numeral is as follows: 1. Substrate; 2. Epitaxial structure; 201. Insertion layer; 202. Thin barrier layer; 3. Secondary epitaxial layer; 4. Dielectric layer; 5. p-GaN layer; 6. Gate; 7. Source; 8. Drain. Detailed implementation manners

[0023] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0024] Now two prior arts are provided to facilitate the understanding of the technical problems to be solved by the present application: Prior art one: The method adopted is to add a p-GaN layer between the gate metal and the AlGaN layer, which will raise the conduction band in the gate region above the Fermi level and make the device enter the enhancement mode. The threshold voltage (Vt) is usually in the range of 1 to 2 V.

[0025] Its existing defects are: 1. The 2DEG charge density in the E-mode device usually needs to be reduced to reach a certain Vth, resulting in a larger 2DEG sheet resistance, generally greater than 550 Ω / sq.

[0026] 2. To reduce the 2DEG charge density, the thickness of the AlGaN barrier layer is thinned (such as 10 - 20 nm). The 2DEG is closer to the surface interface, and the dynamic characteristics are easily affected by the surface interface defects, resulting in poor dynamic performance.

[0027] 3. It is necessary to etch away the p-GaN, which will inevitably cause etching loss to the AlGaN barrier layer, and the defect states lead to worse dynamic performance.

[0028] Prior art two: The two-step method, that is, the method of regrowing the barrier layer, is used to implement the recessed gate enhancement scheme. The advantage is that the two-dimensional electron device has a small sheet resistance and the dynamic performance is expected to be suppressed.

[0029] Its existing defects are as follows: This solution is essentially a MISFET solution. To achieve good gate control, the gate dielectric layer needs to be made relatively thin, and there are significant problems with the reliability of the gate dielectric. At the same time, due to the large interface defects between GaN and the dielectric layer, mass production of current recessed E-mode devices has not been achieved yet.

[0030] The following further describes in detail the implementation manners of the present invention in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0031] Embodiment 1 As Figure 1 shown, this embodiment provides an enhancement-mode GaN HEMT device, including: a substrate 1, an epitaxial structure 2, a secondary epitaxial layer 3, a dielectric layer 4, a p-GaN layer 5, a gate 6, a source 7, and a drain 8.

[0032] The epitaxial structure 2 is epitaxially grown on the substrate 1.

[0033] Among them, the epitaxial structure 2 includes a nucleation layer, a buffer layer, a channel layer, an insertion layer 201, and a thin barrier layer 202 arranged in sequence from bottom to top.

[0034] Preferably, the channel layer is an i-GaN layer; The insertion layer 201 is an AlN layer; The thin barrier layer 202 is an AlGaN layer.

[0035] Correspondingly, the thickness of the channel layer is 50 - 800 nm, the thickness of the insertion layer is 0 - 5 nm, and the thickness of the thin barrier layer is 1 - 20 nm.

[0036] In an alternative embodiment, the substrate 1 is a p-type conductive silicon wafer or a top-silicon conductive SOI wafer.

[0037] The secondary epitaxial layer 3 is epitaxially grown on the epitaxial structure 2.

[0038] Preferably, the secondary epitaxial layer 3 is an AlGaN layer with a thickness of 1 - 30 nm.

[0039] In an alternative embodiment, a cap layer is provided on the top of the secondary epitaxial layer 3; the cap layer is a GaN or SiN layer with a thickness of 1 - 10 nm.

[0040] The above specific thickness dimensions can be correspondingly set according to actual needs. In this embodiment, no specific limitations are made.

[0041] The dielectric layer 4 is disposed on the secondary epitaxial layer 3.

[0042] The trench regions are provided in the dielectric layer 4 and the secondary epitaxial layer 3, and the p-GaN layer 5 is epitaxially grown on the upper surface of the epitaxial structure 2 in the trench regions.

[0043] Preferably, the thickness of the p-GaN layer 5 is 50 - 200 nm.

[0044] The gate 6 is provided on the p-GaN layer 5.

[0045] The source 7 and the drain 8 are respectively provided on both sides of the epitaxial structure 2, the secondary epitaxial layer 3 and the dielectric layer 4.

[0046] Embodiment 2 For the purpose of facilitating the understanding of the enhancement-mode GaN HEMT device provided in Embodiment 1, as Figure 2 shown, this embodiment correspondingly provides its manufacturing method, including the following steps: Step S1: Epitaxially grow an epitaxial structure on a substrate to form a GaN epitaxial wafer with a thin barrier.

[0047] Specifically, this step includes: using metalorganic chemical vapor deposition technology to grow an initial layer, a buffer layer, a channel layer, an AlN insertion layer, and a barrier layer on the substrate from bottom to top in sequence to obtain a GaN epitaxial wafer with a thin barrier.

[0048] Among them, the substrate is a p-type conductive silicon wafer or a top silicon conductive SOI wafer.

[0049] The epitaxial layer includes a nucleation layer, a buffer layer, a channel layer, an insertion layer, and a thin barrier layer. Among them, the channel layer is i-GaN with a thickness of 50 - 800 nm, the insertion layer is AlN with a thickness of 0 - 5 nm, and the thin barrier layer is AlGaN with a thickness of 1 - 20 nm.

[0050] The GaN epitaxial wafer has a thin barrier layer of AlGaN, and the 2DEG of the epitaxial wafer has a significantly higher sheet resistance.

[0051] Step S2: Use photolithography and dielectric etching processes to define the groove pattern in the gate region and complete the gate pattern coverage.

[0052] Specifically, use the PECVD (plasma enhanced chemical vapor deposition) method to prepare the gate region mask dielectric, continue to use the photolithography process to define the gate region of the dielectric, and use the dielectric etching process to define the gate region dielectric hard mask coverage pattern.

[0053] Among them, using the photolithography process to define the gate region of the dielectric includes that the photoresist undergoes spin coating, exposure, and development to define the hard mask pattern, and the hard mask dielectric covers the gate region.

[0054] After that, photoresist residues and etch by-products are removed. Specifically, a combination of wet and dry processes is used to remove photoresist residues and etch by-products, ensuring the regrowth interface.

[0055] Step S3: Using the epitaxial process, perform secondary epitaxy of the barrier layer in the channel region to form a secondary epitaxial layer, achieving thickening of the barrier layer.

[0056] Specifically, use the MOCVD process to complete secondary epitaxial growth of the barrier layer in the epitaxial channel region and the subsequent cap layer. The thickness of the regrown barrier layer AlGaN is 1 - 30 nm, and the cap layer can be GaN or SiN with a thickness of 1 - 10 nm.

[0057] Step S4: Grow a mask dielectric on the secondary epitaxial layer.

[0058] Specifically, use methods such as ALD, PECVD, and LPCVD to grow the mask dielectric across the whole wafer. Preferably, use ALD and PECVD methods to prepare a low-loss etching dielectric mask, and the mask dielectric can be selectively used as a passivation dielectric film.

[0059] Step S5: Use the dielectric etching process to open a pattern in the gate region.

[0060] After that, remove photoresist residues and etch by-products, and perform sufficient interface treatment.

[0061] Step S6: Use the low-temperature MBE (low-temperature molecular beam epitaxy) technique to epitaxially grow a p-GaN layer in the opened region; achieve complete depletion of the 2DEG (two-dimensional electron gas) in the gate region.

[0062] Among them, the MBE regrowth temperature is 600 - 900 °C, and the thickness of the p-GaN layer is about 50 - 200 nm.

[0063] In practice, cross-sectional SEM / TEM can characterize the trapezoidal groove gate structure filled with p-GaN. There is a certain overlap between the second hard mask dielectric etching opening and the expected groove, and there is a certain overlap feature when p-GaN fills through the AlGaN barrier layer.

[0064] In addition, SIMS can characterize the p-GaN filling the groove, which has a Mg / H element ratio much larger than that of conventional process epitaxy. The Mg / H ratio of p-GaN in the MOCVD process is about 3.5, and the Mg / H ratio of p-GaN in the MBE process is greater than 10. And in the MOCVD process, Mg easily diffuses to the barrier layer at high temperatures, and there is an obvious overlap between the Mg performance analysis line and the Al performance analysis line characterized by SIMS testing.

[0065] Step S7: Selectively remove polycrystalline GaN in the non-gate region using wet etching.

[0066] It should be noted that if it is already considered to retain the mask dielectric as the passivation layer, the excess polycrystalline GaN is removed selectively by wet etching, either completely or partially.

[0067] Step S8: On the basis of the structural wafer obtained in the previous process, after the horizontal GaN HEMT process is used for wafer processing, a metal is deposited on the p-GaN layer to fabricate the gate, and metals are deposited on both sides of the structure to fabricate the source and drain, thus obtaining the device.

[0068] The above preparation method is based on a GaN epitaxial wafer with an extremely thin barrier, and uses the method of multiple (three times) epitaxy to realize an enhancement-mode high-voltage power device with a lower specific on-resistance and better dynamic stability.

[0069] In an alternative embodiment, the two-epitaxy technology can also be used for implementation. Specifically: The construction of the gate groove is realized by using a GaN low-loss etching route, which can simplify the process steps (simplify step S3 in the above steps - the secondary epitaxial layer), and the obtained structural wafer is used for selective area epitaxy of the p-GaN layer to realize a stable enhancement-mode GaN HEMT.

[0070] In summary, the enhancement-mode GaN HEMT devices and the corresponding preparation methods provided in the above Embodiment 1 and Embodiment 2 both have the following technical effects: First, the barrier heterostructure is realized by using two epitaxies. The specific on-resistance limit of the device decreases, and more devices can be fabricated with the same-size epitaxial wafers, which is beneficial to reducing the cost of a single device; the distance between the channel electrons and the surface of the barrier layer is farther, and there is no etching damage on the surface of the barrier layer above the channel layer, so the device has better high-frequency dynamic characteristics.

[0071] Second, the gate groove structure is realized by using two epitaxies. The formation of the groove in the gate region does not require the III-nitride etching process, and the stability and consistency of the gate threshold voltage are improved.

[0072] Third, the enhancement-mode GaN HEMT power device is realized by using the secondary epitaxial p-GaN layer. The temperature of the low-temperature MBE secondary epitaxial p-GaN is low, the degradation of the already grown HEMT two-dimensional electron gas is small, the risk of cracks in the epitaxial wafer is low, and the p-GaN grown by MBE does not require subsequent activation treatment.

[0073] Fourth, the opening of the gate region pattern is realized by using dielectric etching. On this basis, the enhancement mode is realized by using the secondary epitaxial p-GaN. The repair of the etched surface can be realized before the secondary epitaxy, and the gate dielectric does not need to be introduced in this scheme, so the gate reliability is improved, and the device stability is further improved.

[0074] In the description of this specification, the description with reference to terms such as "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An enhanced GaN HEMT device, characterized in that, Comprising: A substrate; An epitaxial structure, which is epitaxially grown on the substrate; A secondary epitaxial layer, which is epitaxially grown on the epitaxial structure; A dielectric layer, which is disposed on the secondary epitaxial layer; A p-GaN layer, a connected trench region is provided in the dielectric layer and the secondary epitaxial layer, and the p-GaN layer is epitaxially grown from the upper surface of the epitaxial structure in the trench region; A gate, which is disposed on the p-GaN layer; A source electrode and a drain electrode, the source electrode and the drain electrode are respectively disposed on both sides of the epitaxial structure, the secondary epitaxial layer and the dielectric layer.

2. The enhanced GaN HEMT device according to claim 1, wherein The epitaxial structure includes a nucleation layer, a buffer layer, a channel layer, an insertion layer, and a thin barrier layer arranged in sequence from bottom to top.

3. The enhanced GaN HEMT device according to claim 2, wherein The channel layer is an i-GaN layer; The insertion layer is an AlN layer; The thin barrier layer is an AlGaN layer.

4. The enhanced GaN HEMT device according to claim 2 or 3, characterized in that, The thickness of the channel layer is 50 - 800 nm, the thickness of the insertion layer is 0 - 5 nm, and the thickness of the thin barrier layer is 1 - 20 nm.

5. The enhanced GaN HEMT device according to claim 1, wherein The substrate is a p-type conductive silicon wafer or a top silicon conductive SOI wafer.

6. The enhanced GaN HEMT device according to claim 1, wherein The secondary epitaxial layer is an AlGaN layer with a thickness of 1 - 30 nm.

7. The enhanced GaN HEMT device according to claim 6, characterized in that, A cap layer is provided on the top of the secondary epitaxial layer; The cap layer is a GaN or SiN layer with a thickness of 1 - 10 nm.

8. The enhanced GaN HEMT device according to claim 1, characterized in that, The thickness of the p-GaN layer is 50 - 200 nm.

9. A manufacturing method for preparing the enhanced GaN HEMT device as described in any one of claims 1 to 8, characterized in that, Including the following steps: S1: Epitaxially grow an epitaxial structure on the substrate to form a GaN epitaxial wafer with a thin barrier; S2: Use photolithography and dielectric etching processes to define the groove pattern in the gate region and complete the gate pattern coverage; S3: Perform secondary epitaxy of the barrier layer in the channel region to form a secondary epitaxial layer; S4: Grow a masking dielectric on the secondary epitaxial layer; S5: Open the pattern in the gate region; S6: Use low-temperature MBE technology to epitaxially grow a p-GaN layer in the opened region; S7: Remove the polycrystalline GaN in the non-gate region; S8: After the horizontal GaN HEMT process is taped out, deposit metal on the p-GaN layer to make the gate, and deposit metal on both sides of the structure to make the source electrode and the drain electrode respectively, thus obtaining.

10. The preparation method according to claim 9, characterized in that, Step S1 specifically includes: Use metal organic chemical vapor deposition technology to grow an initial layer, a buffer layer, a channel layer, an AlN insertion layer, and a barrier layer on the substrate in sequence from bottom to top to obtain the GaN epitaxial wafer with a thin barrier.

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