High-speed switch double-groove SiC MOSFET device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a high-speed switch double-groove SiC MOSFET device, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, and is characterized in that the semiconductor epitaxial layer comprises an N substrate layer, an N-type drift layer, a heavily doped P region, an N well layer and a P well layer; the grid electrode is made of a polycrystalline silicon material, a rectangular groove is etched in the upper surface of the grid electrode, and grid electrode metal is deposited in the rectangular groove; a gate medium is deposited on the surfaces of the gate and the gate metal, and the gate medium comprises an upper layer medium and a covering medium. The gate metal is deposited in the gate, and the metal resistance is far smaller than the polycrystalline resistance, so that the metal is used as a gate charge transfer channel, the charge transfer efficiency can be greatly improved, the switching time of the device is greatly shortened, only one-step etching process needs to be added after the gate polycrystal is manufactured, and the manufacturing cost is reduced due to the side wall effect. A U-shaped groove can be automatically formed, and then metal deposition and etching are carried out.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-speed switching double-slot SiC MOSFET device and a preparation method thereof. Background Art

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles, photovoltaic inverters, charging piles, etc. In order to meet the development needs of high energy efficiency, high power density, and small and lightweight power electronic systems, SiC power devices are developing in the direction of high voltage, high power, high frequency and low loss.

[0003] The speed of device switching is mainly determined by the gate resistance, gate-source capacitance and gate-drain capacitance. The gate-drain capacitance mainly depends on the area of ​​the gate-drain opposite the device, which is difficult to change and the effect of change is minimal. The gate-source capacitance mainly depends on the area of ​​the gate-source opposite and the thickness of the dielectric layer. For silicon carbide MOSFET devices, after adjusting these two factors, the basic parameters will be fixed to form the optimal solution, thereby fixing the gate-source capacitance.

[0004] The existing patent discloses a dual-trench silicon carbide MOSFET device with low on-resistance and small gate charge and a preparation method (publication number: CN107658340A). The gate resistance of this patent mainly depends on the square resistance of polysilicon, as well as factors such as gate length and gate width, because the square resistance of polycrystalline is determined by the process capability of each manufacturer. In addition, this patent shortens the gate width by distributing multiple gate-buses in order to transport the charge to various parts of the gate faster, thereby increasing the device gate reaction speed and device switching speed. However, the gate square resistance of polysilicon has its material limit when the thickness is certain, and a large number of densely arranged gate-buses will lead to a waste of the source area of ​​the device, reduce the current density of the device, and offset the structural superiority brought by the device cell design. Summary of the invention

[0005] The main technical problem solved by the present invention is to provide a high-speed switching double-trench SiC MOSFET device and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a high-speed switching double-trench SiC MOSFET device includes a drain, a semiconductor epitaxial layer, a source and a gate, wherein the semiconductor epitaxial layer includes an N substrate layer, an N-type drift layer, a heavily doped P region, an N well layer and a P well layer;

[0007] The gate is made of polysilicon, a rectangular groove is etched on the upper surface of the gate, and gate metal is deposited inside the rectangular groove;

[0008] A gate dielectric is deposited on the surface of the gate and the gate metal, and the gate dielectric includes an upper dielectric and a covering dielectric.

[0009] A method for fabricating a high-speed switching dual-groove SiC MOSFET device includes the following steps:

[0010] S1. Substrate preparation, cutting, and cleaning of the substrate;

[0011] S2. Growth of the substrate layer and the drift layer;

[0012] S3. Formation of the gate structure;

[0013] S4. Doping and formation of the heavily doped P region, N well layer, and P well layer;

[0014] S5. Formation of the dual-groove structure and the rectangular groove, and deposition of the gate metal;

[0015] S6. Device testing and debugging.

[0016] Furthermore, in step S, the drift layer is grown by further growing a layer of SiC crystal on the substrate layer through chemical vapor deposition, and the growth of the drift layer is carried out at a temperature ranging from °C to °C.

[0017] Furthermore, in step S, a photosensitive material is coated on the SiO2 layer, and after exposure and development, the outline of the gate is left. Then, polysilicon is deposited in the exposed gate area by evaporation and sputtering to form the gate of the SiC MOSFET device.

[0018] Furthermore, in step S, boron atoms with different concentrations are implanted into the N-type substrate by ion implantation to form the P well layer and the heavily doped P region.

[0019] Furthermore, in step S, the polysilicon of the gate is etched to form a rectangular groove, and after using the gate metal, the gate metal is sealed in the gate U-groove by using the gate dielectric.

[0020] Furthermore, in step S, by testing the on-resistance difference, threshold voltage difference, breakdown voltage difference, and switching speed difference between the SiC MOSFET devices filled with gate metal and those without gate metal, it is determined whether the gate metal filled in the SiC MOSFET device is qualified. Then, there is:

[0021]

[0022] Wherein, C represents the qualification coefficient of the gate metal filled in the SiC MOSFET device, r represents the difference in on-resistance between the device filled with gate metal and the device without gate metal filled, u represents the difference in threshold voltage between the device filled with gate metal and the device without gate metal filled, and t represents the difference in switching speed between the device filled with gate metal and the device without gate metal filled.

[0023] Furthermore, when C≥63%, it indicates that the gate metal filled in the SiC MOSFET device is qualified and can be used for packaging production;

[0024] When C<63%, it indicates that the gate metal filled in the SiC MOSFET device is unqualified and cannot be used for packaging production.

[0025] Beneficial effects:

[0026] 1. In the present invention, a gate metal is deposited inside the gate. Since the metal resistance is much smaller than the polycrystalline resistance, using metal as the gate charge transfer channel can greatly improve the charge transfer efficiency and significantly shorten the device switching time.

[0027] 2. The present invention has a charge transfer efficiency much higher than that of existing devices. There is no need to use a large number of dense gate-buses in the device source region, so the utilization rate of the device source region can be improved, enabling the device to have a higher current density, making the device with the same resistance have a smaller area, and improving the device yield.

[0028] 3. The present invention only needs to add an etching process after the gate polycrystal is fabricated. Due to the sidewall effect, the U-groove can be automatically formed, and then metal deposition and etching can be carried out.

[0029] 4. The present invention determines whether the gate metal filled in the device is qualified by the differences in on-resistance, threshold voltage, breakdown voltage, and switching speed between the device filled with gate metal and the device without gate metal filled. This method can quickly judge whether the design scheme of the device is qualified. Description of the drawings

[0030] Figure 1 is a structural schematic diagram of the present invention;

[0031] Figure 2 is the present invention Figure 1 enlarged view of area A in.

[0032] In the figure: 1. Drain; 2. N substrate layer; 3. N-type drift layer; 4. Heavily doped P region; 5. Source; 6. Gate dielectric; 7. N-well layer; 8. Gate; 9. P-well layer; 10. Gate metal; 601. Upper dielectric; 602. Covering dielectric. Detailed implementation manners

[0033] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Embodiment 1

[0035] As Figure 1-2 shown, according to one aspect of the present invention, a high-speed switching double-groove SiC MOSFET device is provided, including a drain 1, a semiconductor epitaxial layer, a source 5, and a gate 8. The semiconductor epitaxial layer includes an N substrate layer 2, an N-type drift layer 3, a heavily doped P region 4, an N well layer 7, and a P well layer 9; the gate 8 is made of polysilicon material, and a rectangular groove is etched on the upper surface of the gate 8, and a gate metal 10 is deposited inside the rectangular groove; a gate dielectric 6 is deposited on the surfaces of the gate 8 and the gate metal 10, and the gate dielectric 6 includes an upper dielectric 601 and a covering dielectric 602. By depositing the gate metal 10 inside the gate 8 (as Figure 2 shown), and since the metal resistance is much smaller than the polycrystalline resistance, using metal as the gate charge transfer channel can greatly improve the charge transfer efficiency and significantly shorten the device switching time. And it also makes the device have a much higher charge transfer efficiency than existing devices, eliminating the need to use a large number of dense gate-buses in the device source region, thus improving the utilization rate of the device source region, enabling the device to have a higher current density, making the same-resistance device have a smaller area, and increasing the device yield.

[0036] Embodiment 2

[0037] A method for manufacturing a high-speed switching double-groove SiC MOSFET device includes the following steps:

[0038] Step 1: Substrate preparation, cutting, and cleaning of the substrate;

[0039] Step 2: Growth of the substrate layer and the drift layer: The growth of the drift layer is to further grow a layer of SiC crystal on the substrate layer through chemical vapor deposition, and the growth of the drift layer is carried out at a temperature of 1800 °C to 2000 °C.

[0040] Step 3: Formation of the gate structure: A photosensitive material is coated on the SiO2 layer, and after exposure and development, the outline of the gate is left, and then polysilicon is deposited in the exposed gate area by evaporation and sputtering to form the gate 8 of the SiC MOSFET device.

[0041] Step 4: Doping and formation of the heavily doped P region 4, the N well layer 7, and the P well layer 9: Different concentrations of boron atoms are implanted into the N-type substrate by ion implantation to form the P well layer 9 and the heavily doped P region 4.

[0042] Step 5. Formation of the double-groove structure and rectangular groove, and deposition of the gate metal 10: The polysilicon of the gate 8 is etched to form a rectangular groove. After using the gate metal, the gate dielectric 6 is used to seal the gate metal 10 in the gate U-groove. Only one additional etching process needs to be added after the gate polysilicon is fabricated. Due to the sidewall effect, the U-groove can be automatically formed, and then metal deposition and etching can be carried out.

[0043] Step 6. Device testing and debugging.

[0044] Example 3

[0045] By testing the differences in on-resistance, threshold voltage, breakdown voltage, and switching speed between the SiC MOSFET devices filled with the gate metal 10 and those without the gate metal 10, it is determined whether the filled gate metal 10 of the SiC MOSFET device is qualified. Then, there is:

[0046]

[0047] In the formula, C represents the qualification coefficient of the filled gate metal 10 of the SiC MOSFET device, r represents the difference in on-resistance between the device filled with the gate metal 10 and the device without the gate metal 10, u represents the difference in threshold voltage between the device filled with the gate metal 10 and the device without the gate metal 10, and t represents the difference in switching speed between the device filled with the gate metal 10 and the device without the gate metal 10.

[0048] When C ≥ 63%, it indicates that the filled gate metal 10 of the SiC MOSFET device is qualified and can be used for packaging production.

[0049] When C < 63%, it indicates that the filled gate metal 10 of the SiC MOSFET device is unqualified and cannot be used for packaging production.

[0050] Among them, any device X is subjected to a qualification test. The difference in on-resistance between the device filled with the gate metal 10 and the device without the gate metal 10 is taken as r = 8 (unit: mΩ, on-resistance difference = on-resistance of the device without the gate metal 10 - on-resistance of the device filled with the gate metal 10).

[0051] The difference in threshold voltage between the device filled with the gate metal 10 and the device without the gate metal 10 is taken as u = 0.4 (unit: V, threshold voltage difference = threshold voltage of the device without the gate metal 10 - threshold voltage of the device filled with the gate metal 10).

[0052] The difference in switching speed between the device filled with the gate metal 10 and the device without the gate metal 10 is taken as t = 22 (unit: ns, switching speed difference = switching speed of the device without the gate metal 10 - switching speed of the device filled with the gate metal 10). Then, there is:

[0053]

[0054] As can be known from the above calculations, the gate metal 10 filled in the SiC MOSFET device X is qualified and can be used for packaging production.

[0055] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent of the present invention shall be subject to the appended claims.

Claims

1. A high-speed switching dual-groove SiC MOSFET device, comprising a drain (1), a semiconductor epitaxial layer, a source (5) and a gate (8), characterized in that: The semiconductor epitaxial layer includes an N-type substrate layer (2), an N-type drift layer (3), a heavily doped P region (4), an N well layer (7), and a P well layer (9); The gate (8) is made of polysilicon. A rectangular groove is etched on the upper surface of the gate (8), and gate metal (10) is deposited inside the rectangular groove; A gate dielectric (6) is deposited on the surfaces of the gate (8) and the gate metal (10). The gate dielectric (6) includes an upper dielectric layer (601) and a covering dielectric layer (602).

2. A method for manufacturing a high-speed switching dual-groove SiC MOSFET device according to claim 1, characterized in that, It includes the following steps: S1. Substrate preparation, cutting, and cleaning of the substrate; S2. Growth of the substrate layer and the drift layer; S3. Formation of the gate structure; S4. Doping and formation of the heavily doped P region (4), the N well layer (7), and the P well layer (9); S5. Formation of the double-groove structure and the rectangular groove, and deposition of the gate metal (10); S6. Device testing and debugging.

3. The manufacturing method of the high-speed switching double-groove SiC MOSFET device according to claim 2, wherein: In the step S2, the growth of the drift layer is to further grow a layer of SiC crystal on the substrate layer by chemical vapor deposition, and the growth of the drift layer is carried out at a temperature of 1800 °C to 2000 °C.

4. The manufacturing method of the high-speed switching dual-groove SiC MOSFET device according to claim 2, wherein: In the step S3, a photosensitive material is coated on the SiO2 layer. After exposure and development, the outline of the gate is left. Then, polysilicon is deposited in the exposed gate area by evaporation and sputtering to form the gate (8) of the SiC MOSFET device.

5. The manufacturing method of the high-speed switching dual-groove SiC MOSFET device according to claim 2, characterized in that: In the step S4, boron atoms with different concentrations are implanted into the N-type substrate by ion implantation to form the P well layer (9) and the heavily doped P region (4).

6. The manufacturing method of the high-speed switching dual-groove SiC MOSFET device according to claim 2, characterized in that: In the step S5, the polysilicon of the gate (8) is etched to form a rectangular groove. After using the gate metal, the gate dielectric (6) is used to seal the gate metal (10) in the gate U-groove.

7. The manufacturing method of the high-speed switching double-groove SiC MOSFET device according to claim 1, characterized in that: In the step S6, by testing the on-resistance difference, threshold voltage difference, breakdown voltage difference, and switching speed difference between the SiC MOSFET devices filled with the gate metal (10) and those not filled with the gate metal (10) of the same kind, it is determined whether the gate metal (10) filled in the SiC MOSFET device is qualified. Then, there is: In the formula, C represents the qualification coefficient of the gate metal (10) filled in the SiC MOSFET device, r represents the on-resistance difference between the device filled with the gate metal (10) and the device not filled with the gate metal (10), u represents the threshold voltage difference between the device filled with the gate metal (10) and the device not filled with the gate metal (10), and t represents the switching speed difference between the device filled with the gate metal (10) and the device not filled with the gate metal (10).

8. The manufacturing method of the high-speed switching dual-groove SiC MOSFET device according to claim 7, characterized in that: When C ≥ 63%, it indicates that the gate metal (10) filled in the SiC MOSFET device is qualified and can be used for packaging production; When C < 63%, it indicates that the gate metal (10) filled in the SiC MOSFET device is unqualified and cannot be used for packaging production.

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