Silicon carbide field effect transistor

Abstract

The invention relates to a silicon carbide field effect transistor. In a general aspect, a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) may include: a substrate of a first conductivity type; a drift region of a first conductive type, wherein the drift region of the first conductive type is arranged on the substrate; a diffusion layer of a first conductivity type, the diffusion layer of the first conductivity type being disposed in the drift region; a body region of a second conductivity type, the body region of the second conductivity type being disposed in the diffusion layer; and a source region of a first conductivity type, the source region of the first conductivity type being disposed in the body region. The SiC MOSFET can further comprise a gate structure. The gate structure comprises a gate oxide layer, a gate electrode layer and a gate electrode layer, the aluminum nitride layer is arranged on the grid electrode oxide layer; and a gallium nitride layer of a second conductivity type, the gallium nitride layer being disposed on the aluminum nitride layer.

Description

[0001] This application is a divisional application of a Chinese patent application with the application number 202010831043.X and the invention title "Silicon Carbide Field Effect Transistor", which was filed on August 18, 2020. Technical Field

[0002] This specification relates to silicon carbide (SiC) semiconductor devices including field effect transistors (FETs) having an embedded channel. Background Art

[0003] In power field effect transistors (FETs), using silicon carbide (SiC) as a semiconductor material can reduce static and dynamic power losses. Such FETs can be used in various power applications such as electric motor drive control, in which it is desirable that these FETs be normally off at zero bias (e.g., on the gate or control terminal). In current embodiments, a metal oxide semiconductor FET (MOSFET) design is typically used to implement a normally-off power SiC FET. However, SiC MOSFETs have reliability issues (e.g., due to overstress of the gate oxide) and issues related to implementation in motor drive control applications (e.g., low short-circuit survival time). In addition, due to the low inversion layer carrier mobility (e.g., bulk mobility), a high specific on-resistance (R spon ) results, so current implementations of SiC MOSFETs can also be expensive. This high R is addressed by increasing the device size (e.g., increasing the channel width) to achieve a lower channel resistance and desired current rating for such SiC MOSFETs. spon SiC junction FETs (JFETs) are not susceptible to the reliability issues of SiC MOSFETs and can have a much higher bulk carrier mobility (e.g., a lower R spon ). However, the normally-off operation of current SiC JFETs can be problematic. In addition, current SiC JFET embodiments can have a low threshold voltage and low on-state current, making them unsuitable for power device applications such as motor drive control. Summary of the Invention

[0004] In general aspects, a silicon carbide (SiC) field effect transistor (FET) may include: a substrate of a first conductivity type; an n-type drift region disposed on the substrate; an n-type diffusion layer disposed in the drift region; a p-type body region disposed in the diffusion layer; and an n-type source region disposed in the body region. The SiC FET may further include: an n-type spacer layer disposed on the source region, the body region, and the diffusion layer; and an n-type lateral channel region disposed in the spacer layer. The SiC FET may further include a gate structure, the gate structure including: an aluminum nitride (AlN) layer disposed on the lateral channel region; and a p-type aluminum gallium nitride (AlGaN) layer disposed on the AlN layer.

[0005] In another general aspect, a silicon carbide (SiC) field effect transistor (FET) may include: an n-type substrate of a first conductivity type; an n-type drift region disposed on the substrate; an n-type diffusion layer disposed in the drift region; a p-type body region disposed in the diffusion layer; and an n-type source region disposed in the body region. The SiC FET may further include: an n-type spacer layer disposed on the source region, the body region, and the diffusion layer; and an n-type lateral channel region disposed in the spacer layer. The SiC FET may further include a gate structure, the gate structure including: an aluminum nitride (AlN) layer disposed on the lateral channel region; a p-type aluminum gallium nitride (AlGaN) layer disposed on the AlN layer; a p-type gallium nitride (GaN) layer disposed on the AlGaN layer; and a metal gate electrode disposed on the GaN layer, the metal gate electrode defining an ohmic contact with the GaN layer.

[0006] In another general aspect, a silicon carbide (SiC) field effect transistor (FET) may include: an n-type substrate of a first conductivity type; an n-type drift region disposed on the substrate; an n-type diffusion layer disposed in the drift region; a p-type body region disposed in the diffusion layer; and an n-type source region disposed in the body region. The SiC FET may further include: an n-type spacer layer disposed on the source region, the body region, and the diffusion layer; and an n-type lateral channel region disposed in the spacer layer. The SiC FET may further include a gate structure, the gate structure including: an aluminum nitride (AlN) layer disposed on the lateral channel region; a p-type aluminum gallium nitride (AlGaN) layer disposed on the AlN layer; and an n-type gallium nitride (GaN) layer disposed on the AlGaN layer. The GaN layer may define a tunneling contact with the AlGaN layer. The gate structure may further include a metal gate electrode disposed on the GaN layer. The metal gate electrode may define an ohmic contact with the GaN layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1Is a schematic diagram showing a side cross-sectional view of a silicon carbide (SiC) field effect transistor (FET) according to an embodiment.

[0008] Figure 2 Is a schematic diagram showing the electron concentration contour lines of a conducting state SiC FET according to an embodiment.

[0009] Figure 3 Is a schematic diagram showing the conduction band of a conducting state of a SiC FET according to an embodiment.

[0010] Figure 4A Is a schematic diagram showing the simulated output conduction state characteristics of a SiC FET according to an embodiment.

[0011] Figure 4B Is a schematic diagram showing the simulated voltage blocking characteristics of a SiC FET according to an embodiment.

[0012] Figure 5 Is a schematic diagram showing the simulated gate current characteristics of a SiC FET device according to an embodiment.

[0013] Figure 6 Is a schematic diagram showing the correlation between the conduction band edges of intrinsic SiC and aluminum gallium nitride (AlGaN) and the fraction of aluminum nitride (AlN) in AlGaN according to an embodiment.

[0014] Figure 7 Is a schematic diagram showing the simulated band diagram of a forward-biased p-type gallium nitride (GaN) gate according to an embodiment.

[0015] Figure 8 Is a schematic diagram showing the conduction band of an n-type SiC–AlN–p-type GaN heterostructure under positive gate bias according to an embodiment.

[0016] Figures 9A to 9K Is a schematic diagram showing a side cross-sectional view of the manufacturing process of a SiC field effect transistor (FET) according to an embodiment.

[0017] Figure 10 Shows the structure of a gate stack having a tunnel GaN diode according to an embodiment.

[0018] Figure 11 Shows the manufacturing stages of a SiC FET according to an embodiment.

[0019] Figure 12 Is a schematic diagram schematically showing a plan view of a SiC FET.

[0020] Figure 13 Is a graph showing the interface state density of various materials with SiC.

[0021] Figure 14 is a schematic diagram schematically showing a side cross-sectional view of a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment.

[0022] In the drawings, which are not necessarily to scale, like reference symbols may indicate like and / or similar components (elements, structures, etc.) in different views. The drawings generally illustrate, by way of example and not limitation, various embodiments discussed in the present disclosure. Reference symbols shown in one drawing may not be repeated for the same and / or similar elements in related views. Reference symbols repeated in multiple figures may not be specifically discussed for each of these figures, but rather are provided for context between related views. Additionally, not all like elements in the drawings are specifically referenced with reference symbols when showing multiple instances of the element. Detailed Description

[0023] The present disclosure relates to silicon carbide (SiC) field effect transistors FETs (e.g., JFETs, junction gate FETs, gated JFETs, etc.) that overcome at least some of the drawbacks of the current devices described above. In some embodiments, the SiC FETs described herein can be used in high power applications, such as applications having a desired blocking voltage of 600 volts (V) or higher (e.g., under reverse bias conditions of the rectifier diode of the FET). Such SiC power FETs can also have a low on-state specific resistance (R spon ), so as to allow a high operating current of a power device with a sufficiently small area to have high cost performance compared to current devices.

[0024] In some embodiments, the FETs described herein can have electrical performance parameters that are close to the theoretical performance with respect to the blocking voltage and on-state resistance, for example. For example, the R spon theoretical value limit of a vertical non-injection power device (e.g., such as the SiC FET described herein) can be determined based on the resistance of the drift region of the power device. For example, for a non-punch-through power device, R spon can be given by Equation 1 below:

[0025] R spon = 4BV 2 / (ε * mu * E c 3 ) – Equation 1,

[0026] where BV is the breakdown voltage, ε is the absolute dielectric constant of the semiconductor material (e.g., SiC) in which the device is formed, mu is the bulk carrier mobility (e.g., electrons for an n-type device), and E c is the critical electric field of avalanche breakdown of the semiconductor material. In some embodiments, a high power switch can be defined as having a specific resistance Rspon a device (e.g., a gate-controlled JFET) having a specific resistance that does not exceed 10 times the theoretical value of R given by Equation 1 above. For the purposes of this disclosure, R spon can be defined as the differential resistance of the on-state FET multiplied by the active area of the FET device (e.g., in square centimeters), where the active area can be determined by multiplying the active area of a unit cell of the FET device by the number of unit cells included in the switching device. spon

[0027] In some embodiments (such as those described herein), a vertical SiC FET (e.g., a vertical gate-controlled JFET) can include an n-type (e.g., top-side) source region, an n-type (e.g., back-side) drain region, and an n-type vertical drift region. The SiC FET of such a device (e.g., a unit cell as Figure 1 shown) can also include a shielded p-body, a passive vertical n-type JFET channel (e.g., a diffused region or layer), and a gate-controlled lateral built-in channel on top of the shielded p-body and the vertical JFET channel. The lateral channel can be configured to provide a gate-controlled electrical connection between the (top-side) source region and the passive vertical JFET channel (diffusion layer). In some embodiments, the lateral built-in channel can have a channel depth on the order of nanometers (nm), e.g., a channel depth of 100 nm or less (e.g., 20 nm or less).

[0028] Such a lateral channel can be controlled by a gate structure including a p-type (magnesium-doped) aluminum gallium nitride (AlGaN) alloy layer, where the AlGaN layer of the gate structure is separated (spaced) from the built-in channel by a thin aluminum nitride (AlN) buffer layer or interface layer. Under zero-bias gate conditions, the lateral channel can be configured such that the built-in potential through the p-type AlGaN gate is pinched off (e.g., non-conductive). In the case where a positive bias is applied to the gate, the lateral channel can be configured to become open (e.g., conductive), thereby providing a continuous electron flow path from the source region to the drain region (e.g., through the lateral channel, diffusion layer, and drift region). In the embodiments described herein, using a p-type AlGaN gate can provide a high threshold voltage (e.g., greater than 1 V, greater than 2 V, etc.), while the AlN buffer layer can provide a low interface trap density at the interface between the AlN layer and the SiC of the lateral channel and at the interface between the AlN layer and the AlGaN gate layer.

[0029] Figure 1 is a schematic diagram schematically showing a side cross-sectional view of a silicon carbide (SiC) FET 100. For example, Figure 1 shows a cross-sectional view of an exemplary embodiment of a unit cell of a SiC FET. The unit cell of the FET 100 (such as Figure 1 shown) can be the same as other instances of the unit cell (e.g., asFigure 12 are combined to form a gate-controlled SiC JFET, which can be used in power applications (such as motor control drivers, industrial controls, etc.).

[0030] As Figure 1 shown, the FET 100 includes an n-type (heavily doped) substrate 101 and an n-type epitaxial drift region 102. The FET 100 also includes an n-type diffusion layer 103 in an upper portion of the drift region 102. In some embodiments, the diffusion layer 103 may have a doping concentration higher than that of the drift region 102. Ion implantation and / or ion diffusion can be used to form the diffusion layer.

[0031] Figure 1 The FET 100 also includes a p-body region 120 and a source region 110 disposed in the diffusion layer 130. The portion of the n-type diffusion layer 103 disposed between the two p-body regions 120 may also be referred to as a vertical JFET region (vertical JFET channel, etc.). The p-body region 120 and the source region 110 can be formed by corresponding ion implantation operations.

[0032] As Figure 1 shown, the FET 100 also includes an n-type spacer layer 104 that can be formed using SiC regrowth. An n-type (heavily doped) lateral (built-in) channel region 105 can be formed in an upper portion of the spacer layer 104 using ion implantation. In this exemplary embodiment, a composite gate structure is disposed on top of the lateral channel region 105. In some embodiments (such as in the FET 100), the composite gate structure may include a thin AlN buffer (interface) layer 131, where the thickness of the AlN layer 131 can range from a few monolayers to dozens of nanometers (e.g., 1 nm to 30 nm).

[0033] In the FET 100, the composite gate structure further includes a p-type (heavily doped) aluminum gallium nitride AlGaN layer 132 disposed on the AlN layer 131, where the AlGaN layer 132 defines a heterojunction (PN junction) with the n-type lateral channel region 105. In some embodiments, such as in the FET 100, the composite gate structure may further include a p-type (heavily doped) gallium nitride GaN layer 133 disposed on the AlGaN layer 132 and a gate metal layer 135 disposed on the GaN layer 133 and defining an ohmic contact to the GaN layer. Since GaN has a lower bandgap than the AlGaN alloy, thus using as Figure 1The illustrated GaN layer 133 can reduce the contact resistance between the gate metal layer 135 and the underlying element of the composite gate structure (e.g., compared to an ohmic contact formed to the p-type AlGaN layer 132). As further discussed below, the mole fraction X of AlN in the AlGaN layer 132 can be greater than or equal to eighteen percent (e.g., to achieve a conduction band alignment for effective operation of the FET 100).

[0034] As Figure 1 shown, the FET 100 also includes an ohmic contact 145 to the drain region of the FET 100, where the substrate 101 serves as the drain region of the FET 100. The FET 100 also includes an ohmic contact 141 to the source region 110, where the ohmic contact 141 can also short the p-body region 120 to the corresponding source region 110.

[0035] The ohmic contact 141 formed to the p-body 120 can include forming a p+ sub-contact region 121, where the sub-contact region 121 has a p-type doping concentration higher than that of the p-body 120 to reduce the contact resistance of the ohmic contact 141.

[0036] The FET 100 also includes a source pad metal 148, which can provide an electrical connection to the p-body 120 (through the ohmic contact 141 and the sub-contact region 121) and the source region 110 for operating the FET 100. The pad metal 148 (in combination with the ohmic contact 141) can be referred to as a source metal structure. As Figure 1 shown, the source pad metal 148 is separated (electrically isolated) from the composite gate structure (e.g., gate stack) by an interlayer dielectric 139. In this embodiment, a backside metal layer 146 is disposed on the ohmic (drain) contact 145. In some embodiments, the backside metal layer 146 can facilitate mounting a semiconductor die including the FET 100 into a semiconductor device package and / or into a semiconductor power module (e.g., a multi-chip module). In some embodiments, such a power module can include a power sub-circuit (e.g., a half-bridge or full-bridge circuit topology) that is assembled with high-power SiC FETs (such as those described herein). Of course, such a power module can also have a topology different from the bridge configuration and can also include, for example, a semiconductor-based drive circuit.

[0037] Various details and variations of the SiC FET (such as SiC FET 100) are shown in the accompanying drawings and described below. However, in brief, such a SiC FET (referenced as FET 100) can be configured such that under zero gate bias conditions (e.g., zero bias applied to the composite gate structure via the gate metal layer 135), the lateral channel region 105 can be (fully) depleted (pinched off) by the built-in potential of the heterojunction defined by the p-type AlGaN layer 132 and the n-type lateral channel region 105. Thus, under such zero bias conditions, for a given embodiment, FET 100 can remain in the off state (e.g., not conduct from the source region 110 to the drain) until the full blocking voltage rating is reached.

[0038] In addition, in the case where a positive bias (e.g., greater than 1V) is applied to the gate metal layer 135 (and the p-type GaN layer 133), an accumulation of free electrons can occur in the lateral channel region 105, thereby providing a path for electrons to flow from the source region 110 to the drain (e.g., the substrate 101), where the path for electron flow is through the ohmic contact 141, the lateral channel region 105, the vertical channel (diffusion layer) 103, and the drift region 102.

[0039] In an exemplary embodiment of the SiC 100, the drift region 102 can have a depth (thickness from the diffusion layer 103 to the substrate 101) of approximately 9.5 micrometers (μm) along Figure 1 the line T in. The drift region 102 can have a doping concentration of 1x10 16 cm -3 . For example, a 30 - keV arsenic (As) implant can be used to form the lateral channel region 105 at a depth of 18 nm (along the line T) with a dose of 6x10 12 cm -2 . Along Figure 1 the line W in, the width (e.g., device pitch) of the unit cell of the FET 100 can be 5 μm. In some embodiments of the SiC FET 100, R spon can be less than or equal to 2 milliohms (mOhm) per square centimeter (mOhm·cm 2 ), which can be approximately two times lower than the R spon of a SiC MOSFET with a similar blocking voltage rating.

[0040] As described above, the spacer layer 104 can be a regenerated SiC layer. In some embodiments, the spacer layer 104 (including the lateral channel region 105) can have a thickness between 60 nm and 300 nm along Figure 1 the line T in. The preferred thickness of the spacer layer is approximately between 100 nm and 200 nm. The AlGaN layer 132 of the composite gate structure can have a value greater than or equal to 1x1018 cm -3 The magnesium doping concentration of -3 can provide a high transconductance for the composite gate structure. Additionally, the AlGaN layer 132 can have an AlN mole fraction X between 15% and 70% AlN , and X AlN can be a constant value over the thickness of the AlGaN layer 132. In some embodiments, the lateral channel region 105 can have a depth less than or equal to 20 nm along the line T1 in Figure 1 . The GaN layer 133 can have a magnesium doping concentration greater than or equal to 10 19 cm -3 , or in some embodiments, higher than 10 20 cm -3 .

[0041] Figure 2 FIG. 200 is a schematic diagram showing the electron concentration contour lines of a conducting state SiC FET according to an embodiment. For example, FIG. 200 is a grayscale image showing the simulated electron concentration in an embodiment of the SiC FET 100. Figure 2 The darker tones in Figure 2 represent higher electron concentrations, as indicated by the legend included in Figure 2 . The simulation in represents a SiC FET device (e.g., a portion of the SiC FET 100) with a 2.7 V gate bias and a 0 V drain bias (e.g., operating in saturation mode). Figure 2 The reference numerals in the 100 series in Figure 1 correspond to those in Figure 2 . That is, in

[0042] Figure 2 , the diffusion layer 103, the spacer layer 104, the lateral channel region 105, the source region 110, the p-body region 120, and the AlGaN layer 132 are specifically pointed out. AlN The schematic diagram 200 shown in shows the formation of an undepleted lateral channel in the lateral channel region 105 due to the effect of the 2.7 V gate bias on the p-type AlGaN layer 132 of the composite gate structure of the FET 100. This is performed for an embodiment of the SiC FET 100 with a 30% AlN mole fraction X Figure 2 . The line A-A in Figure 3 indicates the position of the cross-section that shows the conduction band and is discussed below.

[0043] Figure 3 FIG. Figure 2Schematic diagram 300 of the characteristics of the conduction band of the SiC FET shown. That is, schematic diagram 300 shows, for a conducting (on state, etc.) SiC FET (e.g., operating in saturation mode), for a cross-section along Figure 2 the line A-A shown, the electron potential at the edge of the conduction band and the corresponding Fermi level.

[0044] Figure 3 The band diagram 300 shown shows the electron conduction band E Figure 2 as a function of the distance from the SiC-AlGaN210 interface (e.g., the interface with the AlGaN layer 132 and the lateral channel region 105) along the line A-A in C . In the example as described above, the AlN mole fraction (X AlN ) in the AlGaN layer 132 is 0.3. As pointed out above, Figure 3 the conduction band diagram 300 shown is for a cross-section (along line A-A) of the SiC FET Figure 2 , which is taken at a lateral distance of 100 nm from the right-hand edge of the source region 110 (e.g., along the line D in Figure 2 ). In the schematic diagram 300 of Figure 3 , the band diagram is plotted such that x = 0 (e.g., on the x-axis of schematic diagram 300) corresponds to the interface 210 between p-AlGaN and n-type SiC. In Figure 3 , negative distance numbers correspond to positions in the p-AlGaN that enter the composite gate structure from the interface 210 along the line A-A in Figure 2 . In addition, Figure 3 positive distance numbers in Figure 3 correspond to distances along the line A-A from the interface 210 into the lateral channel region 105, the spacer layer 104, and the p-body region 120. That is, with further reference to Figure 3 , the conduction band profile plotted in Figure 2 corresponds to a cross-section (along line A-A) above the p-AlGaN layer 132, the lateral channel region 105, the spacer layer 104, and the p-body 120 of an embodiment of the SiC FET device 100 as shown in

[0045] As Figure 3 shown, within the channel region 105 (e.g., at a distance of approximately 20 nm from the interface 210), the energy of the conduction band Ec is close to the Fermi level E F , which indicates a high electron concentration in the lateral channel region 105. Also as Figure 3As shown, a discontinuity ΔEc of the conduction band Ec occurs at the interface 210 between the AlGaN layer 132 and the SiC of the lateral channel region 105. In some embodiments, as further discussed below, the position of this discontinuity ΔEc can play an important role in controlling the leakage current of a composite gate structure of a SiC FET (such as those SiC FETs described herein).

[0046] Figure 4A FIG. 400 is a schematic diagram showing the simulated output on-state characteristics of a SiC FET according to an embodiment, and Figure 4B FIG. 450 is a schematic diagram showing the simulated voltage blocking characteristics of a SiC FET according to an embodiment. Figure 4A and Figure 4B the simulation results shown in Figure 1 are for an embodiment of the SiC FET 100, where the AlN mole fraction of the p-type AlGaN layer 132 is thirty percent, and the threshold voltage Vt of the SiC FET is greater than 1V.

[0047] Figure 4A FIG. 400 shows the output characteristics of an exemplary SiC FET, where the drain current is plotted as a function of the gate bias (VG) at a constant drain bias (VD) of 1V (dashed line), and the drain current is plotted as a function of VD at a constant VG = 2.3V (solid line). According to Figure 4A the results shown in 2 it can be determined that the simulated SiC FET device (e.g., SiC FET 100) has an R spon of 1.8 mOhm cm Figure 4B As shown, the simulated SiC FET also has a blocking voltage (holding voltage, off-state voltage, etc.) sufficient to reach a 1200V rating with sufficient margin, and also exhibits a low (tens of nanoamperes) reverse (leakage) current at a temperature of 175 degrees Celsius.

[0048] Figures 5 to 8 FIG. shows various simulation results of a SiC FET embodiment, including the characteristics and comparison of different composite gate structures. As discussed below, Figures 5 to 8 the simulation results shown in Figure 5FIG. 500 is a schematic diagram showing the simulated gate current characteristics of two SiC FET devices, one SiC FET device having a p-type AlGaN gate layer for forming a heterojunction with an n-type lateral channel layer and the other SiC FET device having a p-type GaN gate layer for forming a heterojunction with an n-type lateral channel layer. Figure 5 Comparison of Figure 5 shows that the gate leakage current of SiC FET devices (such as those described herein) can depend on the exact structure of the composite gate structure (e.g., p-type gate stack).

[0049] Reference Figure 5 , since the bandgap of AlGaN increases as the percentage of AlN in the AlGaN alloy increases, the gate current of the heterojunction formed using p-type AlGaN can improve the gate leakage current in SiC FET compared to forming a heterojunction using p-type GaN. For example, a p-type gate layer with a higher molar fraction percentage of AlN (X AlN ) will have a higher contact potential with SiC and thus lower leakage than p-type GaN, such as Figure 5 shown. In this example, Figure 5 the simulation results compare a p-type AlGaN layer 132 with 30% molar fraction of AlN to p-GaN that replaces the AlGaN layer 132 in FET 100. As Figure 5 shown, for gate current turn-on, the p-AlGaN layer with X AlN = 0.3 has a higher gate voltage than the p-GaN layer. In this example, the simulated SiC FET device has an active area of 0.057 cm -2 and a unit cell width of 5 μm.

[0050] Figure 6 FIG. 600 is a schematic diagram showing the correlation of the conduction band edges of intrinsic SiC and AlGaN with the molar fraction of AlN in AlGaN according to an embodiment. As Figure 6 shown, the conduction band alignment of AlGaN (e.g., aligned to SiC) can be achieved by adjusting the molar fraction of AlN in the AlGaN layer 132 of, for example, FET 100. Specifically, Figure 6 schematic diagram 600 of AlN shows the alignment of the conduction band relative to the vacuum energy level EvaC as a function of the molar fraction of AlN X AlN . As shown in schematic diagram 600, the conduction band edge of AlGaN remains below the conduction band edge of SiC until the X AlNFor <0.18, the heterojunction of p-type AlGaN and SiC has type-II properties. For example, the conduction band position decreases as the bandgap energy increases. Such a heterojunction is not an effective injector like a type-I heterojunction because an increase in the bandgap of a type-I heterojunction is also accompanied by an increase in E C as well. As Figure 6 shown, such type-I behavior can be achieved when the X AlN mole fraction is greater than 18%.

[0051] Compared with the conduction band diagram of the p-type AlGaN heterojunction gate structure shown in Figure 3 , Figure 7 Figure 700 showing the band diagram near the forward-biased p-type GaN heterojunction gate structure simulated for a gate voltage VG = 2.7V is shown. As Figure 7 shown, the potential well 710 generated by the type-II heterojunction between p-type GaN and SiC may cause an excessive forward gate current, especially when the interface between SiC (e.g., the lateral channel region 105) and the p-type GaN layer has a high interface state density. Then, this undesired excessive current may flow to the SiC-GaN interface due to electron tunneling, as shown in the schematic diagram 700 shown in Figure 7 .

[0052] In addition, as can be seen from Figure 7 (and Figure 8 ), the type-II heterojunction between p-type GaN and SiC (e.g., the lateral channel region 105) has a conduction band discontinuity that is opposite in sign to the bandgap discontinuity at the interface between GaN and SiC. Such a conduction band discontinuity is not desired in SiC FETs, where a low forward current is expected in forward bias. As described herein, this drawback can be overcome using p-type AlGaN.

[0053] Furthermore, the defect density (D it ) at the interface between SiC (the lateral channel region 105) and the gate structure (regardless of whether p-type GaN or p-type AlGaN is used to form the heterojunction) may also contribute to the gate leakage current in SiC FET implementations. Even for an AlN mole fraction in AlGaN greater than 0.18, the conduction band discontinuity of AlGaN (as shown in Figure 6 ) becomes positive, but it is advantageous to have at least a few pure AlN monolayers at the interface with SiC (e.g., the interface between the AlGaN layer 132 and the lateral channel region 105) due to the better interface matching of AlN with SiC, resulting in a lower interface state density.

[0054] For example, referring again to Figure 1Compared with directly placing the AlGaN layer 132 on SiC, placing the AlN layer 131 between the SiC (lateral channel region 105) and the AlGaN layer 132 (or GaN layer) can reduce D it For example, several monolayers of 30 nm AlN (such as those above relative to Figure 1 discussed) can achieve less than 1x10 11 cm -2 eV -1 D it Although a few monolayers of AlN layer 131 may not block the gate current, its presence at the interface between AlGaN layer 132 and lateral channel region 105 (e.g., in the embodiment of FET 100) will reduce the interface state density D at the heterojunction between the n-type SiC of lateral channel region 105 and the AlGaN layer 132 of the composite gate structure. it , and thus reduce gate leakage current.

[0055] Figure 8 800 is a schematic diagram showing the conduction band of a SiC JFET having an n-type SiC-AlN-p-type GaN heterostructure at a positive gate bias of 2.7 V, according to an embodiment. Figure 7 Compared to the schematic diagram 700 in FIG. 8 , the schematic diagram 800 is shown for a heterojunction formed using p-type GaN, but shows the beneficial effect of the AlN layer as an interface layer between SiC and the composite gate structure (for example, for a heterojunction formed using GaN or AlGaN). That is, Figure 8 The conduction band diagram 800 shows the simulation results of a forward biased p-type GaN layer with n-type SiC (eg, lateral channel region 104) and an AlN interfacial layer with a thickness of 2 nm. Figure 8 Schematic diagram 800 and Figure 7 As shown in the comparison of schematic diagram 700 (e.g., corresponding to a p-type GaN-n-type SiC heterojunction with no AlN interface layer), it can be seen that the 2nm AlN layer significantly suppresses both interface traps and tunneling. Similar beneficial effects are achieved for AlN interface layers between AlGaN and SiC, such as in the FETs described herein.

[0056] Although the interface state density at the interface of AlN and GaN or AlGaN can be low as discussed above, when a thin (eg, 1 nm to 30 nm) AlN layer is used to implement the interface layer 131, such as Figure 1 As shown, an excessively thick AlN layer for the interface layer 131 may result in the formation of a dense dislocation network and thus a corresponding increase in the density of interface traps (eg, D itIncreasing). According to a particular embodiment (e.g., semiconductor process), the thickness of the AlN interface layer 131 can vary between approximately 10 nm and 40 nm. In other embodiments, the AlN interface layer can have a thickness less than 10 nm or greater than 40 nm.

[0057] Figures 9A to 9K is a schematic side cross-sectional view showing a semiconductor device manufacturing process for producing a SiC FET according to an embodiment. In some embodiments, the process shown in Figures 9A to 9K or a similar process can be used to produce the SiC FETs described herein, such as, for example, Figure 1 the FET 100 and / or Figure 14 the MOSFET 1400. In other embodiments, other process flows can be used to produce the FETs described herein.

[0058] Figures 9A to 9K The process (the "process") as shown in Figure 9A includes depositing an epitaxial layer (e.g., an epitaxial layer of a lightly doped n-type SiC carbide material) to form a drift region layer 902 on a substrate 901. In some embodiments, the substrate 901 can be a heavily doped hexagonal n-type SiC, such as 4H polytype modified SiC. For example, the doping concentration and thickness of the drift region layer 902 can be selected based on the desired operating voltage (e.g., blocking voltage, rated voltage, etc.) of the corresponding FET produced by this process. For example, in some embodiments, for an FET with a 1200V operating (blocking) voltage, the doping (donor doping) concentration of the drift region layer can be in the range of approximately 8x10 15 cm -3 to 1.3x10 16 cm -3 and the thickness can be in the range of approximately 8 microns to 12 microns.

[0059] Also as shown in Figure 9AAs shown, the upper portion of the epitaxial layer including the drift region layer 902 may have a relatively high donor (doping) concentration to form (define, etc.) an n-type diffusion layer 903 (e.g., a vertical JFET channel region). The doping of the diffusion layer 903 may be in the range of about 1.5 times to 5 times the doping concentration of the drift region layer 902, where the selected doping concentration of the diffusion layer 903 may depend on the desired width of the vertical JFET channel. In some embodiments, the additional (increased) n-type doping in the diffusion region 903 (compared to the drift region layer 902) may be achieved by increasing the flow rate of the n-type dopant during the corresponding epitaxial deposition process. In some embodiments, the additional (increased) n-type doping in the diffusion region 903 (compared to the drift region layer 902) may be achieved by blanket injecting donor atoms such as nitrogen, phosphorus, arsenic, or antimony into the upper portion of the epitaxial layer including the drift region layer 902.

[0060] Note that the exemplary numbers for the thickness and doping concentration of the drift region layer 902 given above are exemplary values for an FET device (e.g., FET 100) with a blocking voltage of 1200V. In some embodiments, if an FET device with a lower or higher blocking voltage is to be produced, the values of the drift region doping concentration and thickness may be adjusted to support (block) the associated peak electric field in the off state of the FET device (e.g., within the limit of the dielectric strength of 4H silicon carbide).

[0061] As Figure 9B shown, the process may include forming and patterning an implantation mask 920m. As Figure 9C shown, the implantation mask 920m may be used as an implantation blocking mask for forming (defining, etc.) a p-type body region 920. In some embodiments, the implantation mask 920m may be formed of silicon dioxide, and after the implantation mask 920m is formed, acceptor ions may be implanted to form the p-type body region 920.

[0062] See Figure 9D , after the p-type body region 920 is formed, the mask 920m may be removed. Then, a new implantation mask (not shown) may be formed and used to define an n-type source region 910. That is, as Figure 9D shown, donor ions may be implanted to form the source region 910, where an implantation mask may be used to define the location for forming the source region 910 (e.g., by blocking donor implantation at locations where the source region 910 is not desired). In some embodiments, the acceptor doping concentration in the p-type body region 920 may be 10 18 cm -3 or higher, and the donor doping concentration in the source region 910 may be 5x10 18 cm -3or higher. When forming (defining, implanting, etc.) the source region 910 and the body region 920, thermionic implantation at a substrate temperature between 200°C and 600°C can be used, which can help prevent unwanted amorphization of the SiC crystal.

[0063] See Figure 9E , for example, the implantation mask used to define the source region 910 can be removed by etching, and an epitaxial SiC regrowth can be used to form the n-type spacer 904. In some embodiments (such as an exemplary 1200V-rated FET), the spacer 904 can have a thickness between approximately 80 nm and 300 nm. Then, a thermal Al ion implantation with a doping concentration of 2x10 19 cm -3 or higher can be used to form the sub-contact p-type region 921. As Figure 9F shown, blanket donor implantation can be performed to define the lateral channel region 905 in the upper portion of the spacer 904, such as having the characteristics of the lateral channel region described herein.

[0064] As Figure 9G shown, then the n-type source sub-contact region 911 and the p-type body sub-contact region 921 (e.g., using one or more implantation masks) can be implanted (defined, formed, etc.). Although not shown in Figures 9A to 9K , when forming the sub-contact regions 911 and / or 921, implantation can also be performed on the junction termination regions around the perimeter of the corresponding FET device.

[0065] In Figures 9A to 9K 's process, after forming the sub-contact regions 911 and 921, an implant anneal can be performed at a temperature between approximately 1500°C and 1900°C to activate the implanted dopants (e.g., in the lateral channel 105, source region 910, body region 920, sub-contact regions 911 and 921, and / or the termination region). In some embodiments, a carbon coating on the top side of the SiC wafer can be used to perform this annealing process, which can avoid roughening of the upper surface of the SiC during annealing.

[0066] After removing the associated carbon layer of the implant activation annealing process, a sacrificial oxidation of the SiC can be performed, which can include forming at least a few nanometers of sacrificial silicon dioxide. Then the sacrificial silicon dioxide can be removed (which can reduce multiple surface defects caused by previous processing operations), and a gate stack including an AlN layer, an AlGaN layer, and a GaN layer can be deposited. In Figure 9H , the AlN, AlGaN, and GaN gate stack is shown as a single composite gate stack 931 / 933. In some embodiments, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and / or plasma-enhanced CVD can be used to deposit Figure 9HLayers of the composite gate stack 931 / 933 shown. In some embodiments, magnesium dopants may be provided during the formation of the composite gate stack, for example to ensure p-type conductivity of the AlGaN and GaN layers. In some embodiments, the doping concentration of the AlGaN layer and the GaN layer of the composite gate stack 931 / 933 may be 1x10 19 cm -3 or higher. Then, annealing may be performed, for example, in nitrogen or in a nitrogen-oxygen mixture, in order to activate the Mg dopants in the composite gate 931 / 933.

[0067] As Figure 9H and Figure 9I further shown, a gate metal layer 935 may be deposited onto and patterned over the composite gate stack 931 / 933. In some embodiments, the gate metal layer 935 may include titanium nitride (TiN) or tantalum nitride (TaN).

[0068] Also as Figure 9I shown, the composite gate stack 931 / 933 and the gate metal layer 935 may then be etched (e.g., dry etched) to define the Figure 9I gate stack structure shown, and also to expose the SiC surface (e.g., for forming contacts with the source region 910 and the body region 920).

[0069] As Figure 9J shown, an interlayer dielectric 939 may then be deposited over and patterned over the gate stack. In some embodiments, the interlayer dielectric 939 may include silicon nitride, silicon dioxide, or a stack of silicon nitride and silicon dioxide. As Figure 9J further shown, a metal 941m (e.g., nickel) that may be used to form an ohmic contact with the SiC may then be deposited and patterned. Additionally, as Figure 9J shown, a metal layer 945m (e.g., nickel) may also be deposited onto the backside of the associated SiC wafer, where the metal layer 945m may be used to define (form, create, etc.) a backside ohmic contact. Then, annealing may be performed to form a silicide (e.g., nickel silicide from the metal layers 941m and 945m and the SiC), and to create (define, etc.) the ohmic contacts 941 and 945, as Figure 9K shown. In this example, the resulting nickel silicide may penetrate into the silicon carbide during annealing (e.g., the silicide reaction). In some embodiments, the formation of nickel silicide may allow the omission of the formation of the sub-contact regions 911 and 921. For example, in certain embodiments, since during silicide formation, the reacting nickel (with the SiC) may penetrate through the entire depth of the underlying channel region 905 and the spacer 904, the formation of the sub-contact regions 911 and 921 for defining the ohmic contacts may be eliminated.

[0070] Although not shown in Figure 9K In an exemplary process, the top-side pad metal can then be deposited and patterned, and the back-side metal can also be deposited, such as in the Figure 1 FET 100 shown. In some embodiments, such top-side metal can include aluminum, and the back-side metal can include a stack of titanium, nickel, and silver, although other metals can also be used. After forming the top-side pad metal, a passivation dielectric can be formed in the peripheral region of the FET 900, such as silicon nitride, silicon dioxide, and / or polyimide. The gate pad region (which is not shown in Figure 1 and Figures 9A to 9K ) can be formed simultaneously with the source pad (such as the source pad metal 148 shown in Figure 1 ).

[0071] In some embodiments, the gate contact (e.g., between the gate metal layer 935 and the gate stack 931 / 933) can be formed without using an annealing process, which can reduce gate leakage under forward gate bias conditions. In this example, the top-side contact to silicon carbide can also be formed without annealing and formed as a deposited-state ohmic contact using the sub-contact regions 911 and 921. In this exemplary embodiment, the respective doping concentrations of the sub-contact regions 911 and 921 can be increased to a value higher than 1x10 20 cm -3 to facilitate a contact having deposited-state ohmic contact characteristics.

[0072] Figure 10 FIG. shows a gate structure stack 1000 of a SiC JFET according to an embodiment, where the gate structure stack 1000 includes a GaN tunnel diode. In some embodiments, the gate structure stack of Figure 1 can be implemented in the SiC FET 100 of Figure 10 , for example, instead of the gate structure stack discussed above with respect to Figure 1 . In Figure 10 , for illustrative purposes, only a portion of the lateral channel region 1005 of the underlying SiC FET structure is shown. The gate structure stack 1000 includes an AlN interface layer 1031, a p-type AlGaN layer 1032, a p-type GaN layer 1033, and an n-type GaN layer 1034 disposed on the lateral channel region 1005. The GaN layers 1033 and 1034 are heavily doped with acceptor ions and donor ions, respectively, such that a tunnel diode is defined between the layers 1033 and 1034.

[0073] In this exemplary embodiment, gate leakage can be controlled by controlling the respective doping concentrations of the p-type GaN layer 1033 and the n-type GaN layer 1034. The gate structure stack 1000 further includes a gate metal layer 1035 disposed on the n-type GaN layer 1034. In some embodiments, the p-type GaN layer 1033 can be omitted, and the n-type GaN layer 1034 can be directly disposed on the p-type AlGaN layer 1032. However, in some embodiments, using the n-type GaN layer 1034 can improve the quality (e.g., reduce the resistance) of the ohmic contact between the gate metal layer 1035 and the composite gate structure (such as the ohmic contact between the gate metal layer and the p-type GaN layer).

[0074] Figure 11 shows an SiC FET 1100 that is structurally similar to the Figure 1 SiC FET 100, where the composite gate structure stack is disposed (e.g., using selective deposition) in a well 1139 defined in an SiO2 mask 1138. For example, the SiC FET 1100 includes a substrate 1101 of a first conductivity type, a drift region 1102 of the first conductivity type, a diffused layer 1103 of the first conductivity type, a body region 1120 of a second conductivity type, a source region 1110 of the first conductivity type, a spacer layer 1104 of the first conductivity type, and a lateral channel region 1105 of the first conductivity type.

[0075] Also as Figure 11 shown, the composite gate structure stack of the SiC FET 1100 (similar to the Figure 1 composite gate structure stack of the FET 110 in Figure 11 ) can be disposed within a well 1139 defined in the SiO2 mask 1138. For example, the gate structure stack of the SiC FET 1100 includes an AlN interface layer 1131, a p-type AlGaN layer 1132, and a p-type GaN layer 1133 disposed on the lateral channel region 1105. Although not specifically shown in

[0076] Figure 12 is a schematic diagram schematically showing a plan view of the SiC FET 1200. As Figure 12As shown, the FET 1200 may include an active region that includes a one-dimensional array of linear unit cells 1260. In some embodiments, the unit cell 1260 of the SiC FET 1200 may have Figure 1 the structure of the SiC FET 100, and / or may include, relative to, for example Figure 10 and Figure 11 the features of the SiC FETs described. That is, in some embodiments, the unit cell 1260 may include and / or incorporate certain features of the various SiC FETs described herein.

[0077] Figure 12 The SiC FET 1200 may further include a terminal region 1271 disposed around the active region of the SiC FET 1200. Different methods (structures) for junction termination may be included in the terminal region 1271, where the particular terminal structure used will depend on the embodiment of the unit cell 1260 of the SiC FET 1200. In the SiC FET 1200, the terminal region 1271 should have, for example, the same or a higher breakdown voltage than the active region of the unit cell 1260 array.

[0078] Figure 13 is a graph 1300 showing the interface state density of various interface layer materials with SiC. As can be seen from Figure 13 among the materials shown in the graph 1300, AlN has the lowest D among those materials it and, in some cases, it is at least an order of magnitude smaller than other potential interface layer materials.

[0079] Figure 14 is a schematic diagram schematically showing a side cross-sectional view of a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) 1400 according to an embodiment. For example, Figure 14 shows a cross-sectional view of an exemplary embodiment of a unit cell of the SiC MOSFET 1400. Similar to Figure 1 the FET 100, the unit cell of the MOSFET 1400 (such as Figure 14 shown) may be combined with other instances of the unit cell (e.g., in an arrangement similar to that Figure 12 shown) to form a SiC MOSFET that can be used in power applications such as motor control drives, industrial control, etc.

[0080] In a MOSFET 1400, the work function of p-GaN with respect to SiC can be utilized to produce a SiC MOSFET with improved performance. For example, due to a low threshold voltage of only a few volts, current high-performance power SiC MOSFETs may have significant performance issues. Additionally, at elevated temperatures, such as after a long negative bias at the gate, an undesired high leakage current may be observed during the off-state of current SiC MOSFETs. This bias tends to cause positive charges to be trapped next to the SiC-to-oxide interface, resulting in off-state leakage. These issues present performance and reliability problems for current SiC MOSFETs.

[0081] In contrast, due to a reduction in the inversion layer mobility, power SiC MOSFETs with a higher threshold voltage tend to have an increased channel resistance. Although the exact physical mechanism by which the mobility decreases with an increasing threshold voltage has not been fully understood, it has been well established that, for example, the inversion layer mobility in a SiC MOSFET is independent of the work function of the gate. Thus, implementing a gate having a gate electrode (gate stack) formed using (including) p-type GaN instead of conventional polysilicon may form a MOSFET gate having a higher work function with respect to n-type SiC and overcoming at least some of the drawbacks of current SiC MOSFET implementations.

[0082] As Figure 14 shown, the MOSFET 1400 may include a substrate 1401, a drift region 1402, a diffusion layer 1403, a p-body 1420, and an n-source 1410. The MOSFET 1400 may also include a p+ sub-contact layer 1421. The MOSFET 1400 also includes a gate oxide 1406. The gate oxide 1406 may have a thickness between approximately 25 nm and 100 nm, and in some embodiments, may have a nitrided interface with the SiC. Such a nitrided interface can be formed by annealing an oxidized SiC surface in an environment containing nitric oxide (NO) or nitrous oxide (N2O) at a temperature between approximately 1100°C and 1400°C. Nitridation can reduce the interface state density in the gate oxide 1406 next to the SiC surface (at the interface with the SiC surface).

[0083] The MOSFET 1400 also includes an ALD-deposited intermediate layer of AlN and a gate of p-GaN, which can be crystalline or microcrystalline. The MOSFET 1400 may also include an ohmic drain contact 1445, a drain metal 1446, an ohmic contact 1441 to the source (e.g., n-type) region 1410 and the body (e.g., p-type) region 1420, a gate metal 1435, an interlayer dielectric 1439, and a source pad metal 1448. At zero gate bias, the MOSFET 1400 is in the off state, and this can block approximately the same voltage as the FET 100, as described herein, provided that the doping concentration and thickness of the drift region 1402 are similar to those described for the drift region 102 of the FET 100. A positive gate bias will cause an inversion electron channel at the interface of the SiC and the oxide 1406, and thus turn on (switch on) the MOSFET 1400. Thus, the high work function of p-GaN with respect to SiC can increase the threshold voltage of the MOSFET 1400 without significantly affecting the on-state resistance of the MOSFET 1400.

[0084] It should also be understood that for the purposes of this disclosure, when an element such as a layer, region, or substrate is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on the other element, connected to the other element, or coupled to the other element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, no intermediate element or layer is present. Although the terms directly on..., directly connected to..., or directly coupled to... may not be used throughout the detailed description, elements shown as being directly on an element, directly connected, or directly coupled can be referred to in such a manner. The claims of this application may be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0085] As used in this specification, unless specifically stated otherwise in context, the singular forms may include the plural forms. Except for the orientations shown in the drawings, the spatial relative terms (e.g., above, on, over, below, under, beneath, etc.) are intended to cover different orientations of the device during use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, the term adjacent may include laterally adjacent or horizontally adjacent.

[0086] Some embodiments may be implemented using a variety of semiconductor processing and / or packaging techniques. Some embodiments may be implemented using a variety of types of semiconductor processing techniques associated with a semiconductor substrate, which includes but is not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and the like.

[0087] Although certain features of the described embodiments have been illustrated as described herein, many modifications, alternative forms, variations, and equivalents will now occur to those skilled in the art. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the specific embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail may be made. Except for mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub - combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), comprising: An SiC substrate of a first conductivity type; A drift region of a first conductivity type, the drift region of the first conductivity type being disposed on the SiC substrate; A diffused layer of a first conductivity type, the diffused layer of the first conductivity type being disposed in the drift region; A body region of a second conductivity type, the body region of the second conductivity type being disposed in the diffused layer; A source region of a first conductivity type, the source region of the first conductivity type being disposed in the body region; And A gate structure, the gate structure comprising: A gate oxide layer; An aluminum nitride (AlN) layer, the AlN layer being disposed on the gate oxide layer; and A gallium nitride (GaN) layer of a second conductivity type, the GaN layer being disposed on the AlN layer.

2. The SiC MOSFET according to claim 1, wherein the thickness of the drift region is about 9.5 micrometers.

3. The SiC MOSFET according to claim 1, wherein the doping concentration of the drift region is 1×10 16 cm -3 .

4. The SiC MOSFET according to claim 1, wherein the drift region is an epitaxial SiC drift region.

5. The SiC MOSFET according to claim 1, wherein the gate oxide layer has a thickness between 25 nanometers (nm) and 100 nanometers.

6. The SiC MOSFET according to claim 1, further comprising: An ohmic drain contact, the ohmic drain contact being disposed on the SiC substrate; An interlayer dielectric, the interlayer dielectric being disposed on the gate structure; A source metal structure, the source metal structure comprising: An ohmic contact layer, the ohmic contact layer defining: An ohmic contact to the body region; and An ohmic contact to the source region; and A metal layer, the metal layer being disposed on the ohmic contact, a portion of the source region, and the interlayer dielectric, and the gate structure being electrically isolated from the metal layer by the interlayer dielectric.

7. The SiC MOSFET according to claim 6, wherein the ohmic contact to the body region comprises a sub-contact region of a second conductivity type disposed in the body region, the sub-contact region having a doping concentration higher than that of the body region.

8. The SiC MOSFET according to claim 7, wherein the ohmic contact layer contacts the sub-contact region and the source region.

9. The SiC MOSFET according to claim 6, further comprising a drain metal layer, the drain metal layer being disposed on the ohmic drain contact.

10. The SiC MOSFET according to claim 1, further comprising a nitrided interface located between the gate oxide layer and the diffused layer and between the gate oxide layer and the source region.

11. The SiC MOSFET according to claim 1, wherein the GaN layer is crystalline or microcrystalline.

12. The SiC MOSFET according to claim 1, wherein the AlN layer is deposited by atomic layer deposition.

13. A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), comprising: An n-type SiC substrate; An n-type drift region, which is disposed on the n-type SiC substrate; An n-type diffusion layer, which is disposed in the drift region; A p-type body region, which is disposed in the diffusion layer; An n-type source region, which is disposed in the body region; And A gate structure, which includes: A gate oxide layer; An aluminum nitride AlN layer, which is disposed on the gate oxide layer; and A p-type gallium nitride GaN layer, which is disposed on the AlN layer.

14. The SiC MOSFET according to claim 13, further including a nitrided interface, which is located between the gate oxide layer and the n-type diffusion layer and between the gate oxide layer and the n-type source region.

15. The SiC MOSFET according to claim 13, wherein the thickness of the n-type drift region is about 9.5 micrometers.

16. The SiC MOSFET tube according to claim 13, wherein the doping concentration of the n-type drift region is 1×10 16 cm -3 .

17. The SiC MOSFET according to claim 13, wherein the gate oxide layer has a thickness between 25 nanometers (nm) and 100 nm.

18. The SiC MOSFET according to claim 13, further including: An ohmic drain contact, which is disposed on the n-type SiC substrate; An interlayer dielectric, which is disposed on the gate structure; A source metal structure, which includes: An ohmic contact layer, which defines: An ohmic contact to the p-type body region; and An ohmic contact to the n-type source region; and A metal layer, which is disposed on the ohmic contact, a part of the n-type source region, and the interlayer dielectric, and the gate structure is electrically isolated from the metal layer through the interlayer dielectric.

19. The SiC MOSFET according to claim 18, wherein the ohmic contact to the body region includes a p-type sub-contact region, which is disposed in the p-type body region and has a doping concentration higher than that of the p-type body region.

20. The SiC MOSFET according to claim 19, wherein the ohmic contact layer contacts the p-type sub-contact region and the n-type source region.

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