Array substrate, preparation method and display device

Abstract

The invention discloses an array substrate, a preparation method and a display device, and relates to the technical field of display, the array substrate comprises a driving wiring structure arranged on the periphery of a display area of the array substrate and located in a non-display area of the array substrate, the driving wiring structure comprises a grounding wire and a common electrode wire, the grounding wire and the common electrode wire are different metal layers and are overlapped in the thickness direction of the array substrate to form a target coupling capacitor, so that the capacitance sum on the common electrode wire is increased, the proportion of the coupling capacitor between the data line and the common electrode wire on the capacitance sum is reduced, and the array substrate is improved. And furthermore, the coupling capacitance change voltage difference of the common electrode voltage is reduced, and the potential fluctuation of the common electrode caused by the coupling capacitance is reduced, so that the existing horizontal crosstalk and signal delay phenomena are reduced to a certain extent.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate, a preparation method, and a display device. Background Art

[0002] With the popularization of liquid crystal display panels, the coupling capacitance problem between data lines and common electrode traces has become a key factor restricting display quality. In the FFS (Fringe Field Switching) mode, the common electrode traces are designed with a whole-surface indium tin oxide thin film and are arranged on the same layer as the data lines in the array substrate, resulting in a significant increase in the capacitance coupling between the two. When the data line voltage switches with high-frequency images, the capacitance coupling will cause fluctuations in the common electrode potential, resulting in abnormal display conditions such as horizontal crosstalk and signal delay. Summary of the Invention

[0003] The main purpose of this application is to provide an array substrate, a preparation method, and a display device, aiming to solve the technical problem that the coupling capacitance between the data line and the common electrode trace causes fluctuations in the common electrode potential, resulting in horizontal crosstalk and signal delay.

[0004] To achieve the above purpose, this application proposes an array substrate, in which a driving wiring structure is arranged around the display area of the array substrate and is located in the non-display area of the array substrate;

[0005] The driving wiring structure includes a ground trace and a common electrode trace;

[0006] The ground trace and the common electrode trace are respectively different metal layers, and they overlap in the thickness direction of the array substrate to form a target coupling capacitance.

[0007] In one embodiment, the ground trace and the common electrode trace are respectively connected to a flexible electronic component on the terminal side of the display area;

[0008] The ground trace and the common electrode trace form a target coupling capacitance on the opposite side of the terminal side of the display area.

[0009] In one embodiment, the ground trace and the common electrode trace arranged on the opposite side of the terminal side of the display area are in a parallel structure.

[0010] In one embodiment, the ground trace and the common electrode trace arranged on the opposite side of the terminal side of the display area are in a grid structure.

[0011] In one embodiment, the ground signal on the ground trace and the common electrode signal on the common electrode trace are both DC signals.

[0012] In addition, to achieve the above purpose, this application also proposes a preparation method for an array substrate, and the preparation method for the array substrate includes:

[0013] Provide a glass substrate;

[0014] Form a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate in sequence;

[0015] Wherein, the first metal layer and the second metal layer form a first target coupling capacitor.

[0016] In one embodiment, the step of forming a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate in sequence further includes:

[0017] Etch the first metal layer to form a ground trace;

[0018] Etch the second metal layer to form a common electrode trace;

[0019] Form a planarization layer between the first protective layer and the second protective layer;

[0020] Wherein, the ground trace and the common electrode trace form a first target coupling capacitor.

[0021] In one embodiment, the step of forming a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate in sequence further includes:

[0022] Etch the first metal layer to form a first common electrode trace;

[0023] Etch the second metal layer to form a ground trace;

[0024] Form an indium tin oxide layer on the second protective layer;

[0025] Etch the indium tin oxide layer to form a second common electrode trace;

[0026] Wherein, the first common electrode trace and the ground trace form a first target coupling capacitor, and the ground trace and the second common electrode trace form a second target coupling capacitor.

[0027] In one embodiment, the step of forming a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate in sequence further includes:

[0028] Form a planarization layer between the first protective layer and the second protective layer.

[0029] In addition, to achieve the above object, the present application further provides a display device, which includes the array substrate as described above.

[0030] One or more technical solutions proposed by the present application have at least the following technical effects:

[0031] An array substrate is proposed, in which a driving wiring structure is arranged around the display area of the array substrate and located in the non-display area of the array substrate; the driving wiring structure includes a grounding trace and a common electrode trace, the grounding trace and the common electrode trace are respectively different metal layers, and they overlap in the light-emitting direction to form a target coupling capacitor.

[0032] That is, in this application, a grounding trace is added around the display area together with the common electrode trace, and it is set that the grounding trace and the common electrode trace are respectively formed by different metal layers, so that the two can overlap in the thickness direction of the array substrate to form a target coupling capacitor, thereby increasing the sum of capacitances on the common electrode trace, reducing the proportion of the coupling capacitance between the data line and the common electrode trace in the sum of capacitances, and further reducing the differential voltage change of the coupling capacitance of the common electrode voltage, reducing the potential fluctuation of the common electrode caused by the coupling capacitance, and thus reducing the existing horizontal crosstalk and signal delay phenomena to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0034] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0035] Figure 1 It is a schematic structural diagram of the driving wiring structure of this application in the array substrate;

[0036] Figure 2 It is a schematic structural diagram of a conventional driving wiring structure in the array substrate;

[0037] Figure 3 It is a schematic diagram of the overlapping setting method when the grounding trace and the common electrode trace are in a parallel structure;

[0038] Figure 4 It is a schematic diagram of the overlapping setting method when the grounding trace and the common electrode trace are in a grid structure;

[0039] Figure 5 It is a schematic cross-sectional diagram of the array substrate formed by the first manufacturing method of this application;

[0040] Figure 6 It is a schematic cross-sectional diagram of the array substrate formed by the second manufacturing method of this application;

[0041] Figure 7This is a schematic cross-sectional view of another array substrate formed based on the second preparation method of the present application.

[0042] Explanation of the reference numerals in the attached drawings:

[0043] 101, display area; 102, non-display area; 103, ground trace; 104, common electrode trace; 104(1), first common electrode trace; 104(2), second common electrode trace; 105, gate driver; 106, flexible electronic component; 107, out-of-plane trace.

[0044] 301, glass substrate; 302, gate insulating layer; 303, first protective layer; 304, planarization layer; 305, second protective layer; 306, sealant; 307, protective coating; 308, black matrix; 309, another glass substrate.

[0045] The realization of the purpose, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0046] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0047] In order to better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings in the specification and specific implementation manners.

[0048] The main solution of the embodiment of the present application is: an array substrate is proposed, and a driving wiring structure is arranged around the display area of the array substrate and is located in the non-display area of the array substrate; the driving wiring structure includes a ground trace and a common electrode trace, and the ground trace and the common electrode trace are respectively different metal layers, and overlap in the light-emitting direction to form a target coupling capacitor.

[0049] With the popularization of liquid crystal display panels, the coupling capacitance problem between the data line and the common electrode trace has become a key factor restricting the display quality. In the FFS mode, the common electrode trace adopts a whole-surface indium tin oxide thin film design and is arranged in the same layer as the data line in the array substrate, resulting in a significant increase in the coupling capacitance between the two. When the data line voltage switches with the high-frequency picture, the coupling capacitance will cause the potential fluctuation of the common electrode, resulting in abnormal display conditions such as horizontal crosstalk and signal delay in the display.

[0050] The present application provides a solution. By adding a ground trace that is located in the periphery of the display area and is on the same layer as the common electrode trace, and setting that the ground trace and the common electrode trace are formed by different metal layers respectively, so that the two can overlap in the thickness direction of the array substrate to form a target coupling capacitor, thereby increasing the sum of capacitances on the common electrode trace, reducing the proportion of the coupling capacitance between the data line and the common electrode trace in the sum of capacitances, and further reducing the differential voltage change of the coupling capacitance of the common electrode voltage, and reducing the potential fluctuation of the common electrode caused by the coupling capacitance, so as to reduce the existing horizontal crosstalk and signal delay phenomena to a certain extent.

[0051] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device, a display device, etc. that can implement the above functions. Hereinafter, the display device will be taken as an example to illustrate this embodiment and the following embodiments.

[0052] Based on this, an embodiment of the present application provides an array substrate. Refer to Figure 1 , Figure 1 which is a schematic structural diagram of the array substrate of the present application.

[0053] The included driving wiring structure is arranged around the display area 101 of the array substrate and is located in the non-display area 102 of the array substrate. The driving wiring structure includes a ground trace 103 and a common electrode trace 104. The ground trace 103 and the common electrode trace 104 are different metal layers respectively, and overlap in the thickness direction of the array substrate to form a target coupling capacitor.

[0054] First, taking the working mode of a TFT LCD (Thin-Film Transistor Liquid Crystal Display) as an example, the problems existing in a conventional array substrate will be described. In the horizontal direction, pixels in the same row are written with a switching signal by the same scanning line at the same time. Therefore, the crosstalk phenomenon in the horizontal direction is related to the response duration of the signal. When the voltage input on the data line of the TFT substrate changes continuously with the display screen, the voltage change on the data line will be capacitively coupled through the data line and the common electrode trace on the TFT substrate, thereby affecting the potential of the common electrode trace. At this time, the common electrode trace is in a transient delay state due to the capacitive coupling effect of the data line and its own resistance. The response duration corresponding to this delay state is shown in Formula ①:

[0055] T(delay) = R × C ———— Formula ①

[0056] Among them, T(delay) represents the response duration, R represents the resistance value of the common electrode trace itself, and C represents the coupling capacitance value corresponding to the capacitive coupling effect. It can be seen that the larger the coupling capacitance value, the longer the corresponding response duration.

[0057] Meanwhile, if the coupling capacitance value and the resistance value of itself are too large, the influence on the common electrode trace will be too great. At this time, the common electrode voltage on the common electrode trace will deviate from its set potential, manifested as a poor display phenomenon of horizontal crosstalk in the display screen. Especially for the display device in the FFS mode mentioned in the background technology, because its common electrode trace is usually a whole surface of indium tin oxide transparent electrode and is arranged on the substrate together with the data line, the capacitive coupling between the common electrode trace and the data line in this mode will be significantly greater than that in other display modes, and the corresponding poor display condition will be more obvious.

[0058] As Figure 2 shown is a schematic diagram of the peripheral wiring of the common electrode trace on the display panel corresponding to the conventional FFS mode. Its display area (i.e., 201 in 2) is a whole surface of indium tin oxide, which is connected to the peripheral metal common electrode trace (i.e., Figure 2 204 in Figure 2 ) through vias. The connection of the common electrode trace to the outside of the plane is only through a flexible electronic component (i.e., Figure 2 206 in Figure 2 ) on the terminal side to connect to the off-plane trace (i.e., Figure 2 207 in

[0059] To solve the above problems, this embodiment proposes to improve the driving wiring structure on the periphery of the display area 101, that is, on the non-display area 102 of the array substrate, so as to avoid changing the in-plane traces. Specifically, as shown in Figure 1 , a grounding trace 103 is arranged on the periphery of the display area 101. The grounding trace 103 and the originally provided common electrode trace 104 are formed by different metal layers. Therefore, the structure between the two is set to overlap along the light-emitting direction of the display panel to form a new capacitor, that is, the target coupling capacitor. Since a part of the target coupling capacitor is composed of the common electrode trace 104, it can increase the capacitance sum of the common electrode trace 104. The explanation is as follows according to formula ②:

[0060] ΔV = ΔV data变化 × C dc / C total ———— Equation ②

[0061] Among them, ΔV represents the capacitance coupling change voltage difference of the voltage of the common electrode trace 104, and ΔV data变化 represents the data line voltage change value, and C dc represents the capacitance coupling value between the data line and the common electrode trace 104, and C total represents the sum of the capacitances on the common electrode trace 104.

[0062] In this embodiment, C total = C dc + C gc + C t , among which, C gc represents the capacitance value between the scan line and the common electrode trace 104, and C t represents the capacitance value of the target coupling capacitor newly added in this embodiment.

[0063] It can be seen that under the same data line voltage change value, the larger the sum of the capacitances on the common electrode trace 104, the smaller the capacitance coupling change voltage difference of the voltage of the corresponding common electrode trace 104, the smaller the fluctuation of the common electrode potential, that is, the smaller the capacitance coupling effect of the data line on the common electrode trace 104. Furthermore, to a certain extent, it can reduce the existing horizontal crosstalk and signal delay phenomena, and effectively slow down the poor display condition caused by the capacitance coupling between the data line and the common electrode trace 104 without changing the in-plane traces and causing other display problems.

[0064] Still based on Figure 1 shown, it should be noted that the ground trace 103 and the common electrode trace 104 are respectively connected to the flexible electronic component on the terminal side of the display area 101 (that is Figure 1 106 in), and the ground trace 103 and the common electrode trace 104 form a target coupling capacitor on the opposite side of the terminal side of the display area 101. It can be seen that the wiring of the common electrode trace 104 in this embodiment is the same as that of the conventional common electrode trace 104 Figure 2 shown, both are arranged around the display area 101 and connected to the flexible electronic component on the terminal side of the display area 101, and are connected to the out-of-plane trace through the flexible electronic component (that is Figure 1 107 in). The newly added ground trace 103 is a metal layer connected to the two flexible electronic components at the left and right ends of the terminal side respectively, and the target coupling capacitor formed by it and the common electrode trace 104 is arranged on the opposite side of the terminal side of the display area 101.

[0065] The reason for setting the grounding trace 103 and the common electrode trace 104 to form a target coupling capacitor on the side opposite to the terminal side of the display area 101 is that the terminal side is usually a dense area for signal input and output. For example, for data signals, if the target coupling capacitor is formed on the terminal side, it may cross the data line due to space congestion, increasing the coupling risk. Therefore, in this embodiment, by forming the target coupling capacitor on the side opposite to the terminal side, the sensitive DC signal and the high-frequency / AC signal can be effectively isolated, further reducing the horizontal crosstalk and signal delay phenomena.

[0066] If the target coupling capacitor is formed on both sides of the non-display area 102, the maximization of the target coupling capacitor cannot be achieved because the gate drivers 105 are respectively arranged on both sides of the non-display area 102. Therefore, there is obviously no extra space on both sides of the non-display area 102 for arranging the target coupling capacitor. Therefore, in order to ensure the maximization of the overlapping area between the grounding trace 103 and the common electrode trace 104, a larger capacitor is formed, thereby maximizing the capacitance sum of the common electrode trace 104, minimizing the proportion of the coupling capacitor between the data line and the common electrode trace 104 in the capacitance sum, and further maximizing the reduction of the common electrode potential fluctuation caused by the coupling capacitor. In this embodiment, by using the space on the side opposite to the terminal side, the setting of the target coupling capacitor is realized, achieving the maximization setting of the target coupling capacitor without increasing the space of the non-display area 102.

[0067] In a feasible implementation manner, the grounding trace 103 and the common electrode trace 104 arranged on the side opposite to the terminal side of the display area 101 are in a parallel structure. It should be noted that the parallel structure here refers to the overlapping setting method. As Figure 3 shown, the overlapping setting method can directly set the two metal layers forming the grounding trace 103 and the common electrode trace 104 in parallel.

[0068] In another feasible implementation manner, the grounding trace 103 and the common electrode trace 104 arranged on the side opposite to the terminal side of the display area 101 are in a grid structure. The grid structure at this time also refers to the overlapping setting method. As can be seen from the top view of the two metal layers shown in Figure 4 , the overlapping setting method is to set the two metal layers forming the grounding trace 103 and the common electrode trace 104 in parallel, and then hollow out at multiple identical positions corresponding to the two metal layers to form a grid structure. The purpose is to ensure the light transmittance of the area coated with the sealant when the sealant needs to be coated at the position where the target coupling capacitor is formed, ensure the curing effect of the sealant, and at the same time avoid the abnormal structure situation where the insulating layer provided on the array substrate cracks due to the steep transition area caused by the edge alignment phenomenon of the two metal layers.

[0069] In addition, the ground signal on the ground trace 103 and the common electrode signal on the common electrode trace 104 are both DC signals. Since DC signals have the characteristic of stable voltage and can reduce the dynamic energy loss and switching operations in the circuit, setting both the ground signal and the common electrode signal as DC signals can avoid the increase in power consumption of the display device panel.

[0070] The present application also provides a method for manufacturing an array substrate, and the method for manufacturing the array substrate includes steps S10 to S20:

[0071] Step S10: Provide a glass substrate.

[0072] Step S20: Sequentially form a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate. Among them, the first metal layer and the second metal layer form a first target coupling capacitor.

[0073] Specifically, according to the actual manufacturing situation, the present embodiment proposes the following three manufacturing methods. It should be noted that the following Figures 5 to 7 The cross-sectional view of the array substrate shown is a partial cross-sectional schematic view at A-A' in FIG. 1.

[0074] Refer to Figure 5 As shown, the first manufacturing method included in step S20 includes steps S31 to S33:

[0075] Step S31: Etch the first metal layer to form a ground trace.

[0076] Step S32: Etch the second metal layer to form a common electrode trace.

[0077] Step S33: Form a planarization layer between the first protective layer and the second protective layer. Among them, the ground trace and the common electrode trace form a first target coupling capacitor.

[0078] Refer to Figure 5As shown, on one side of the glass substrate 301, a first metal layer is deposited by depositing a first metal material, and after etching the first metal layer, a ground trace 103 is formed. Then, on the basis of the formed ground trace 103, a dielectric layer is deposited by depositing a dielectric material, and the dielectric layer is etched to form a gate insulating layer 503, and the gate insulating layer 302 wraps the ground trace 103 formed in the previous step. Then, on the basis of the formed gate insulating layer 302, after depositing a second metal layer by depositing a second metal material and etching the second metal layer to form a common electrode trace 104, a first protective material is deposited on the formed common electrode trace 104 and etched to form a first protective layer 303 that wraps and protects the gate insulating layer 302 and the common electrode trace 104. It should be noted that at this time, a planarization material can be coated on the first protective layer 303 to form a planarization layer 304. Finally, after depositing a second protective material on the planarization layer 304 and etching to obtain a second protective layer 305, according to Figure 5 As can be seen, at this time, a sealant 306 is coated on the second protective layer 305, and the sealant 306 is attached to the black matrix 308 on the side coated with the protective coating 307, and the side of the black matrix 308 not coated with the protective coating 307 is attached to another glass substrate 309 to form an array substrate.

[0079] According to Figure 5 As shown, the ground trace 103, the gate insulating layer 303, and the common electrode trace 104 therein form a first target coupling capacitor. Further, if in the preparation process, the first metal layer deposited by depositing the first metal material is first etched to form the common electrode trace 104, then the second metal layer deposited in the subsequent steps needs to be etched to form the ground trace 103, as long as it is ensured that the deposited metal layer can be etched to obtain the ground trace 103 and the common electrode trace 104 respectively and form a first target coupling capacitor with the gate insulating layer 303, and there is no restriction on the vertical overlapping order between the ground trace 103 and the common electrode trace 104.

[0080] Referring to Figure 6 As shown, the second preparation method included in step S20 includes steps S41 to S44:

[0081] Step S41, etching the first metal layer to form a first common electrode trace.

[0082] Step S42, etching the second metal layer to form a ground trace.

[0083] Step S43, forming an indium tin oxide layer on the second protective layer.

[0084] Step S44: Etch the indium tin oxide layer to form a second common electrode trace. Among them, the first common electrode trace and the ground trace form a first target coupling capacitor, and the ground trace and the second common electrode trace form a second target coupling capacitor.

[0085] Referring to Figure 6 As shown, on one side of the glass substrate 301, after depositing the first metal material to obtain the first metal layer, the first metal layer is etched to form the first common electrode trace 104(1). Then, on the basis of the formed first common electrode trace 104(1), a dielectric material is deposited and etched to form the gate insulating layer 302, and the gate insulating layer 302 wraps the first common electrode trace 104(1) formed in the previous step. Then, on the basis of the formed gate insulating layer 302, after depositing the second metal material to obtain the second metal layer, the second metal layer is etched to form the ground trace 103. On the formed ground trace 103, a first protective material is deposited and etched to form the first protective layer 303 that wraps and protects the gate insulating layer 302 and the ground trace 103. A second protective material is deposited on the first protective layer 303 and etched to obtain the second protective layer 305. Finally, an indium tin oxide layer is deposited on the second protective layer 305, and the indium tin oxide layer is etched to form the second common electrode trace 104(2). According to Figure 6 It can be known that at this time, a sealing glue 306 will be coated on the second common electrode trace 104(2) and a part of the second protective layer 305. The sealing glue 306 is attached to the black matrix 308 with a protective coating 307 on one side, and the side of the black matrix 308 without the protective coating 307 is attached to another glass substrate 309 to form an array substrate.

[0086] It can be known that in this embodiment, there are two target coupling capacitors, that is, the first common electrode trace 104(1), the gate insulating layer 302, and the ground trace 103 form a first target coupling capacitor, and the ground trace 103, the first protective layer 303, the second protective layer 305, and the second common electrode trace 104(2) form a second target coupling capacitor. It can achieve further increasing the capacitance of the target coupling capacitor under the same planar area, that is, further expanding the sum of the capacitances on the common electrode trace 104, reducing the capacitance coupling change voltage difference of the common electrode trace 104 voltage, and slowing down the existing horizontal crosstalk and signal delay phenomena.

[0087] It should be noted that if during the preparation process, the first metal layer obtained by depositing the first metal material is first etched to form the ground trace 103, then in the subsequent steps, the second metal layer obtained by depositing the second metal material needs to be etched to form the common electrode trace 104, and the indium tin oxide needs to be etched to form another ground trace 103 to ensure that the up-and-down overlapping structure of the ground trace 103 - common electrode trace 104 can be obtained.

[0088] In addition, referring to Figure 7 as shown in Figure 7 the preparation steps shown in Figure 6 are the same as those shown in Figure 7 . The difference is that after forming the first protective layer 303 by depositing the first protective material, at this time, a planarization material is coated on the first protective layer 303 to form a planarization layer 304, and then a second protective material is deposited on the planarization layer 304 to obtain a second protective layer 305. Finally, an indium tin oxide layer is deposited on the second protective layer 305, and after etching it, a second common electrode trace 104(2) is formed. The second target coupling capacitor is formed by the ground trace 103, the first protective layer 303, the planarization layer 304, the second protective layer 305, and the second common electrode trace 104(2). Through Figure 7 The planarization layer 304 provided in Figure 6 can fill the uneven structures existing therein, ensuring the uniformity and performance stability of the array substrate. And Figure 6 the reason for not setting the planarization layer 304 is to reduce the thickness of the array substrate.

[0089] So far, the array substrate obtained based on any of the above-described preparation methods can reduce the capacitive coupling effect of the data signal on the data line on the common electrode signal on the common electrode trace 104 without increasing the power consumption of the display panel, reduce the fluctuation of the common electrode potential, and further improve the horizontal crosstalk and signal delay phenomena existing in the display panel.

[0090] It should be noted that the preparation process involved in this embodiment is implemented based on an 8-mask process.

[0091] This application also provides a display device, and this display device includes the array substrate described above.

[0092] The above are only partial embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structural transformation made under the technical concept of this application by using the content of the specification and drawings of this application, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of this application.

Claims

1. An array substrate, characterized in that, The driving wiring structure is disposed around the display area of the array substrate and is located in the non-display area of the array substrate; The driving wiring structure includes a ground trace and a common electrode trace; The ground trace and the common electrode trace are respectively different metal layers, and overlap in the thickness direction of the array substrate to form a target coupling capacitor.

2. The array substrate according to claim 1, wherein The ground trace and the common electrode trace are respectively connected to a flexible electronic component on the terminal side of the display area; The ground trace and the common electrode trace form the target coupling capacitor on the opposite side of the terminal side of the display area.

3. The array substrate according to claim 2, wherein The ground trace and the common electrode trace disposed on the opposite side of the terminal side of the display area are in a parallel structure.

4. The array substrate according to claim 2, wherein The ground trace and the common electrode trace disposed on the opposite side of the terminal side of the display area are in a grid structure.

5. The array substrate according to claim 2, wherein The ground signal on the ground trace and the common electrode signal on the common electrode trace are both DC signals.

6. A method for preparing an array substrate, characterized in that, The method for manufacturing the array substrate includes: Providing a glass substrate; Successively forming a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate; Wherein, the first metal layer and the second metal layer form a first target coupling capacitor.

7. The method for preparing an array substrate according to claim 6, wherein, The step of successively forming a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate further includes: Etching the first metal layer to form a ground trace; Etching the second metal layer to form a common electrode trace; Forming a planarization layer between the first protective layer and the second protective layer; Wherein, the ground trace and the common electrode trace form a first target coupling capacitor.

8. The method for preparing an array substrate according to claim 6, wherein, The step of successively forming a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate further includes: Etching the first metal layer to form a first common electrode trace; Etching the second metal layer to form a ground trace; Forming an indium tin oxide layer on the second protective layer; Etching the indium tin oxide layer to form a second common electrode trace; Wherein, the first common electrode trace and the ground trace form a first target coupling capacitor, and the ground trace and the second common electrode trace form a second target coupling capacitor.

9. The manufacturing method of the array substrate according to claim 8, wherein, The step of successively forming a first metal layer, a gate insulating layer, a second metal layer, a first protective layer, and a second protective layer on the glass substrate further includes: Forming a planarization layer between the first protective layer and the second protective layer.

10. A display device, characterized in that, The display device includes the array substrate according to any one of claims 1 to 4.

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