Three-dimensional integrated photoelectric conversion chip based on through silicon vias and preparation method of three-dimensional integrated photoelectric conversion chip

Abstract

The invention provides a through-silicon-via-based three-dimensional integrated photoelectric conversion chip and a preparation method thereof. The through-silicon-via-based three-dimensional integrated photoelectric conversion chip comprises an electric chip layer; a second rewiring layer, a silicon through hole switching layer, a first rewiring layer and an optical chip layer are sequentially stacked on one side of the electric chip layer along the first direction; wherein the electric chip layer is bonded with the second rewiring layer through a second salient point, and the first rewiring layer is bonded with the optical chip layer through a first salient point; the electric chip layer comprises a low-noise amplifier chip, and the optical chip layer comprises a photoelectric detector chip; the photoelectric detector chip and the low-noise amplifier chip are connected through the first rewiring layer, the second rewiring layer and the through silicon via switching layer to form a photoelectric conversion channel, and the photoelectric conversion channel is used for converting an optical signal received by the photoelectric detector chip into a radio-frequency signal and outputting the radio-frequency signal through the low-noise amplifier chip.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technologies, and particularly to a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias and a preparation method thereof. Background Art

[0002] As Moore's Law approaches the physical limit, traditional planar integrated circuits face challenges such as increasing interconnect delay, rising power consumption, and insufficient bandwidth density. Especially in the fields of optical communication, high-performance computing, and artificial intelligence, the bandwidth and energy consumption problems of electrical interconnections are becoming increasingly prominent, and optoelectronic integration has become a breakthrough direction. The development of silicon photonics has laid the foundation for the compatibility between optoelectronic devices and CMOS processes. Three-dimensional integration technology can achieve heterogeneous integration of optoelectronic devices and electronic devices through vertical stacking and TSV (through-silicon via) interconnection, shortening the interconnect distance and improving system performance. As the core of three-dimensional integration, TSV technology realizes high-density interconnection of multi-layer chips through vertical conductive channels penetrating the silicon substrate, and its process includes key steps such as deep silicon etching, insulating layer deposition, and copper filling.

[0003] However, in the existing insulating layer process of TSV technology, there are problems such as poor process compatibility, low step coverage, large parasitic capacitance, and the commonly used barrier layer preparation process being expensive and time-consuming atomic layer deposition. In addition, although applying TSV to optoelectronic conversion chips can directly transmit the electrical signals generated by photodetectors to the lower-layer processing circuit, improving signal integrity and transmission rate, the packaging size of electrical chips is relatively large, and the biasing circuit of photodetectors will make the packaging more cumbersome. Summary of the Invention

[0004] In view of the above deficiencies, a first aspect of the present invention provides a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias, including: an electrical chip layer; a second redistribution layer, a through-silicon via transition layer, a first redistribution layer, and an optical chip layer are sequentially stacked on one side of the electrical chip layer along a first direction; wherein, the electrical chip layer and the second redistribution layer are bonded by second bumps, and the first redistribution layer and the optical chip layer are bonded by first bumps; the electrical chip layer includes a low-noise amplifier chip, and the optical chip layer includes a photodetector chip; the first redistribution layer, the second redistribution layer, and the through-silicon via transition layer connect the photodetector chip and the low-noise amplifier chip to form an optoelectronic conversion channel, and the optoelectronic conversion channel is used to convert the optical signal received by the photodetector chip into a radio frequency signal and output it through the low-noise amplifier chip.

[0005] In the above solution, the first redistribution layer includes a redistribution body of the optical chip layer, a bias circuit of the photodetector chip, and a DC-blocking capacitor of the low-noise amplifier chip; among them, the bias circuit of the photodetector chip includes: a first resistor, a second resistor, a first capacitor, and a second capacitor, and the DC-blocking capacitor of the low-noise amplifier chip includes a first DC-blocking capacitor and a second DC-blocking capacitor; a first end of the first resistor is connected to the positive electrode of the photodetector chip, and a second end of the first resistor is respectively connected to a second end of the first capacitor and a second end of the second capacitor; a first end of the second resistor is respectively connected to the negative electrode of the photodetector chip and a first end of the first capacitor, and a second end of the second resistor is connected to a first end of the second capacitor.

[0006] In the above solution, the through-silicon via transfer layer sequentially includes a second silicon dioxide layer insulation layer, a silicon substrate, and a first silicon dioxide layer insulation layer in the direction from the electrical chip layer to the optical chip layer; among them, a plurality of through-silicon vias are provided in the silicon substrate.

[0007] In the above solution, the side wall of the through-silicon via includes: a polyimide insulation layer and a titanium nitride barrier layer, and the inside of the through-silicon via is filled with electroplated copper.

[0008] The second aspect of the present invention provides a method for manufacturing a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias, including: S1, providing a silicon substrate, and etching one side of the silicon substrate along a first direction to form a plurality of through-silicon vias; S2, based on the plurality of through-silicon vias, manufacturing a through-silicon via transfer layer including the silicon substrate; S3, sputtering a metal seed layer on one side of the through-silicon via transfer layer along the first direction to form a first redistribution layer; S4, bonding the DC-blocking capacitor of the low-noise amplifier chip, the photodetector chip, and the bias circuit of the photodetector chip to the first redistribution layer; S5, sputtering a metal seed layer on the other side of the silicon substrate along the first direction to form a second redistribution layer; S6, bonding the low-noise amplifier chip to the second redistribution layer; S7, respectively forming a photolithography circuit on the first redistribution layer and the second redistribution layer, and combining and connecting the photodetector chip and the low-noise amplifier chip through the through-silicon via transfer layer to form an optoelectronic conversion channel.

[0009] In the above solution, S2 includes: sequentially depositing a polyimide insulation layer and a titanium nitride barrier layer on the side wall of each through-silicon via of the silicon substrate, and filling electroplated copper in each through-silicon via.

[0010] In the above solution, S3 includes: performing a surface planarization treatment on the surface of the through-silicon via transfer layer, and depositing a first silicon dioxide layer insulation layer on one side of the silicon substrate along the first direction; sputtering a metal seed layer on the first silicon dioxide layer insulation layer; photolithographically forming a wiring layer pattern on the metal seed layer, and coating a photoresist as an insulation layer to form a first redistribution layer.

[0011] In the above solution, S4 includes: lithographically electroplating gold-tin on the first redistribution layer to form a first bump; bonding the DC-blocking capacitor of the low-noise amplifier chip, the photodetector chip, and the bias circuit of the photodetector chip to the first bump.

[0012] In the above solution, S5 includes: polishing and thinning the other side of the silicon substrate along the first direction to expose the copper pillar of the through-silicon via; depositing a second silicon dioxide insulating layer on the side surface of the silicon substrate where the copper pillar is exposed, and performing a polishing process to make the silicon dioxide insulating layer flush with the copper pillar; sputtering a metal seed layer on the second silicon dioxide insulating layer to form a second redistribution layer.

[0013] In the above solution, S6 further includes: lithographically electroplating gold-tin on the second redistribution layer to form a second bump; bonding the low-noise amplifier chip to the second bump.

[0014] The technical solution of the invention embodiment has at least the following beneficial effects:

[0015] Using the vacuum-assisted spin coating technology to deposit polyimide can improve the step coverage rate and enhance the electrical performance and thermo-mechanical reliability of the TSV.

[0016] Using the dual-catalyzed electroless plating process to prepare the barrier layer, the process equipment is simple, the cost is low, the coating thickness is uniform, and the porosity is low.

[0017] Integrating the bias circuit and the photodetector on the same layer by using the size difference of the optoelectronic chips can effectively utilize the packaging space and improve the chip integration degree. Brief Description of the Drawings

[0018] Figure 1 Schematically shows an overall cross-sectional view of a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to an embodiment of the present invention;

[0019] Figure 2 Schematically shows a diagram of the first redistribution layer according to an embodiment of the present invention;

[0020] Figure 3 Schematically shows a flowchart of a preparation method of a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to an embodiment of the present invention;

[0021] Figure 4 Schematically shows one of the cross-sectional views of a three-dimensional integrated optoelectronic conversion chip of a GaAs-based pin-type photodetector chip and a GaAs-based low-noise amplifier chip according to an embodiment of the present invention;

[0022] Figure 5 Schematically shows another cross-sectional view of a three-dimensional integrated optoelectronic conversion chip of a GaAs-based pin-type photodetector chip and a GaAs-based low-noise amplifier chip according to an embodiment of the present invention;

[0023] Figure 6 Schematically shows a third cross-sectional view of a three-dimensional integrated optoelectronic conversion chip of a GaAs-based pin photodetector chip and a GaAs-based low-noise amplifier chip according to an embodiment of the present invention;

[0024] Figure 7 Schematically shows a fourth cross-sectional view of a three-dimensional integrated optoelectronic conversion chip of a GaAs-based pin photodetector chip and a GaAs-based low-noise amplifier chip according to an embodiment of the present invention;

[0025] Figure 8 Schematically shows a fifth cross-sectional view of a three-dimensional integrated optoelectronic conversion chip of a GaAs-based pin photodetector chip and a GaAs-based low-noise amplifier chip according to an embodiment of the present invention.

[0026] [Description of reference numerals]

[0027] 1 - Electrical chip layer; 2 - Second redistribution layer; 3 - Through-silicon via transfer layer; 4 - First redistribution layer; 5 - Optical chip layer; 6 - Second bump; 7 - First bump; 301 - Silicon substrate; 302 - First silicon dioxide layer insulating layer; 303 - Polyimide insulating layer; 304 - Titanium nitride barrier layer; 305 - Through-silicon via; 308 - Bonding layer; 309 - Second silicon dioxide layer insulating layer; 312 - Low-noise amplifier chip; 313 - Photodetector chip; 314 - First DC-blocking capacitor; 315 - Second DC-blocking capacitor; 316 - First resistor; 317 - Second resistor; 318 - First capacitor; 319 - Second capacitor. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0029] Figure 1 Schematically shows an overall cross-sectional view of a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to an embodiment of the present invention.

[0030] As Figure 1 shown, a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias includes: an electrical chip layer 1; a second redistribution layer 2, a through-silicon via transfer layer 3, a first redistribution layer 4, and an optical chip layer 5 are sequentially stacked on one side of the electrical chip layer 1 along the first direction X1; wherein, the electrical chip layer 1 and the second redistribution layer 2 are bonded together through a second bump 6, and the first redistribution layer 4 and the optical chip layer 5 are bonded together through a first bump 7.

[0031] Specifically, the electrical chip layer 1 includes a low-noise amplifier chip 312, and the optical chip layer 5 includes a photodetector chip 313; the first redistribution layer 4, the second redistribution layer 2, and the through-silicon via interposer layer 3 connect the photodetector chip 313 and the low-noise amplifier chip 312 to form an optoelectronic conversion channel, which is used to convert the optical signal received by the photodetector chip 313 into a radio frequency signal and output it through the low-noise amplifier chip 312.

[0032] Optionally, the type of the photodetector chip can be any one of p-i-n type, Schottky type, metal-semiconductor-metal type, and avalanche type.

[0033] Optionally, the type of the low-noise amplifier chip can be any one of gallium arsenide type, silicon-based type, gallium nitride type, and high electron mobility transistor type.

[0034] As Figure 1 shown, the through-silicon via interposer layer 3 sequentially includes a second silicon dioxide layer insulating layer 309, a silicon substrate 301, and a first silicon dioxide layer insulating layer 302 in the direction from the electrical chip layer 1 to the optical chip layer 5; wherein, a plurality of through-silicon vias 305 are provided in the silicon substrate 301. Here, the direction from the electrical chip layer 1 to the optical chip layer 5 is parallel to the first direction X1.

[0035] As Figure 1 shown, the side wall of the through-silicon via 305 includes a polyimide insulating layer 303 and a titanium nitride barrier layer 304, and the inside of the through-silicon via 305 is filled with electroplated copper.

[0036] As Figure 1 shown, the DC-blocking capacitor of the low-noise amplifier chip 312, the photodetector chip 313, and the bias circuit of the photodetector chip 313 are all bonded to the first bump 7. Among them, the first bump 7 is formed by photolithography and electroplating of gold-tin on the first redistribution layer.

[0037] Furthermore, the low-noise amplifier chip 312 is bonded to the second bump 6. Among them, the second bump 6 is formed by photolithography and electroplating of gold-tin on the second redistribution layer.

[0038] Figure 2 Schematically shows a diagram of the first redistribution layer according to an embodiment of the present invention.

[0039] In an embodiment of the present invention, the first redistribution layer 4 includes a re-routing body of the optical chip layer, a bias circuit of the photodetector chip 313, and a DC-blocking capacitor of the low-noise amplifier chip 312. Among them, the bias circuit of the photodetector chip 313 includes: a first resistor 316, a second resistor 317, a first capacitor 318, and a second capacitor 319, and the DC-blocking capacitor of the low-noise amplifier chip 312 includes a first DC-blocking capacitor 314 and a second DC-blocking capacitor 315.

[0040] As Figure 2 shown, the first end of the first resistor 316 is connected to the positive electrode of the photodetector chip 313, and the second end of the first resistor 316 is respectively connected to the second end of the first capacitor 318 and the second end of the second capacitor 319; the first end of the second resistor 317 is respectively connected to the negative electrode of the photodetector chip 313 and the first end of the first capacitor 318, and the second end of the second resistor 317 is connected to the first end of the second capacitor 319.

[0041] Through the embodiments of the present invention, the three-dimensional integrated optoelectronic conversion chip based on through-silicon vias adopts broadband optoelectronic conversion technology, and connects the photodetector chip 313 and the low-noise amplifier chip 312 through the first redistribution layer 4, the second redistribution layer 2 and the through-silicon via transfer layer 3 to form an optoelectronic conversion channel. This optoelectronic conversion channel converts the optical signal received by the photodetector chip 313 into a radio frequency signal and outputs it through the low-noise amplifier chip 312. This optoelectronic conversion chip has the advantages of high integration, excellent preparation process, and good signal integrity.

[0042] Figure 3 Schematically shows a flowchart of a method for preparing a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to an embodiment of the present invention.

[0043] As Figure 3 shown, the method for preparing the above-mentioned three-dimensional integrated optoelectronic conversion chip based on through-silicon vias specifically includes operations S1 to S7.

[0044] S1. Provide a silicon substrate 301, and perform etching on one side of the silicon substrate 301 along the first direction to form a plurality of through-silicon vias 305.

[0045] S2. Based on the plurality of through-silicon vias 305, prepare a through-silicon via transfer layer 3 including the silicon substrate 301.

[0046] Specifically, prepare a silicon substrate, which can be rectangular or circular. For example, prepare a wafer material, cut the selected wafer into square pieces, and thin the wafer to the required thickness. Then deposit a layer of silicon dioxide mask layer, clean it with standard RCA and dry it with nitrogen, and then perform photolithography to define the positions of the through-silicon vias, and sequentially complete the processes of spin coating, pre-baking, exposure, development and post-baking.

[0047] Further, using silicon dioxide as a mask on the silicon substrate, realize the etching of the through-silicon via array through photolithography, dry etching or wet etching, then remove the etching mask layer, and clean the vias through RCA standard cleaning or Ar gas cleaning.

[0048] In an embodiment of the present invention, S2 includes: sequentially depositing a polyimide insulating layer 303 and a titanium nitride barrier layer 304 on the sidewalls of each through-silicon via 305 of the silicon substrate 301, and filling each through-silicon via 305 with electroplated copper.

[0049] Exemplarily, a thin polyimide insulating layer is formed in the through-hole by vacuum-assisted spin coating or plasma-enhanced chemical vapor deposition, and then a thin titanium nitride barrier layer is grown by dual-catalyzed electroless plating or metal-organic chemical vapor deposition.

[0050] Exemplarily, for conductive material filling in the through-hole, a uniform metal seed layer is grown on the sidewalls of the hole by physical vapor deposition or chemical vapor deposition, and then the hole core is filled by a bottom-up copper electroplating technique, and the electroplated copper forms a copper pillar in the through-silicon via 305.

[0051] S3, sputter a metal seed layer on one side of the through-silicon via interposer 3 along the first direction to form a first redistribution layer 4.

[0052] In an embodiment of the present invention, S3 includes: planarizing the surface of the through-silicon via interposer 3, and depositing a first silicon dioxide layer insulating layer 302 on one side of the silicon substrate 301 along the first direction X1; sputtering a metal seed layer on the first silicon dioxide layer insulating layer 302; lithographically forming a wiring layer pattern on the metal seed layer, and coating a photoresist as an insulating layer to form a first redistribution layer 4.

[0053] Specifically, planarize the surface of the through-silicon via interposer 3, sequentially remove the electroplated copper residue layer, the barrier layer, the polymer insulating dielectric layer, and the silicon dioxide mask to expose the silicon substrate, and here the silicon substrate can also be exposed by chemical mechanical polishing. Then clean the surface of the through-silicon via interposer and dry it with nitrogen.

[0054] Further, as Figure 1 shown, use the PECVD process to deposit a first silicon dioxide layer insulating layer 302 on one side of the silicon substrate 301 along the first direction X1, and then perform patterning and etch contact holes above the copper pillars using the photoresist as a mask layer.

[0055] Further, sputter a metal seed layer on the first silicon dioxide layer insulating layer 302, and lithographically form a first redistribution layer pattern on the metal seed layer. Among them, the metal seed layer can be made of metal materials such as Ti, Cu, or Al.

[0056] Further, coat a photoresist on the metal seed layer as an insulating layer, and repeat the steps of sputtering the metal seed layer, lithographically patterning the redistribution layer, and electroplating for thickening, so as to form a first redistribution layer.

[0057] S4. Bond the DC-blocking capacitor of the low-noise amplifier chip 312, the photodetector chip 313, and the bias circuit of the photodetector chip 313 to the first redistribution layer 4.

[0058] In an embodiment of the present invention, S4 includes: lithographically electroplating AuSn on the first redistribution layer 4 to form a first bump 7; bonding the DC-blocking capacitor of the low-noise amplifier chip 312, the photodetector chip 313, and the bias circuit of the photodetector chip 313 to the first bump 7.

[0059] Specifically, lithographically electroplate AuSn on the first redistribution layer to form a solder bump, that is, the first bump 7. Then, the DC-blocking capacitor of the pre-fabricated low-noise amplifier chip 312, the photodetector chip 313, and the bias circuit of the photodetector chip 313 can be directly bonded to the first bump 7. It should be noted that here, the first redistribution layer can be temporarily bonded to the glass wafer by spin-coating a temporary bonding adhesive on one side along the first direction X1, and then debonded by a laser lift-off process. Subsequently, the DC-blocking capacitor of the pre-fabricated low-noise amplifier chip 312, the photodetector chip 313, and the bias circuit of the photodetector chip 313 are bonded to the first bump 7.

[0060] S5. Sputter a metal seed layer on the other side of the silicon substrate 301 along the first direction to form a second redistribution layer 2.

[0061] In an embodiment of the present invention, S5 includes: polishing and thinning the other side of the silicon substrate 301 along the first direction X1 to expose the copper pillar of the silicon through hole 305; depositing a second silicon dioxide layer insulating layer 309 on the surface of the side of the silicon substrate 301 where the copper pillar is exposed, and performing a polishing process to make the silicon dioxide insulating layer flush with the copper pillar; sputtering a metal seed layer on the second silicon dioxide layer insulating layer 309 to form a second redistribution layer 2.

[0062] Specifically, the other side of the silicon substrate along the first direction X1 can be thinned by methods such as mechanical grinding, CMP, and dry etching to reduce the other side of the silicon substrate along the first direction X1 to expose the root of the copper pillar.

[0063] Further, deposit a second silicon dioxide layer insulating layer 309 on the surface of the side of the silicon substrate 301 where the copper pillar is exposed by PECVD process, then polish to make the copper pillar flush with the silicon dioxide insulating layer, and clean the plane with deionized water.

[0064] Further, sputter a metal seed layer on the second silicon dioxide layer insulating layer 309, and lithographically form a second redistribution layer pattern on the metal seed layer. Among them, the metal seed layer can be made of metal materials such as Ti, Cu, or Al.

[0065] Further, a photoresist is coated on the metal seed layer as an insulating layer, and the steps of sputtering the metal seed layer, lithographing the pattern of the rewiring layer, and electroplating for thickening are repeated to form the second rewiring layer.

[0066] S6. Bond the low-noise amplifier chip 312 to the second rewiring layer 2.

[0067] Specifically, a second bump 6 is formed by lithographic electroplating of gold-tin on the second rewiring layer 2; the low-noise amplifier chip 312 is bonded to the second bump 6.

[0068] It should be noted that, in the embodiments of the present invention, the bonding may include various bonding types such as thermocompression bonding, direct bonding, adhesive bonding, and wire bonding.

[0069] S7. Form lithographic circuits on the first rewiring layer 4 and the second rewiring layer 2 respectively, and connect the photodetector chip 313 and the low-noise amplifier chip 312 through the silicon through-hole transfer layer 3 to form a photoelectric conversion channel.

[0070] Specifically, lithographic circuits are formed on the above-mentioned first rewiring layer 4 and the second rewiring layer 2 respectively, so that the photodetector chip 313 and the low-noise amplifier chip 312 are connected through the first rewiring layer 4, the second rewiring layer 2, and the silicon through-hole transfer layer 3 to form a photoelectric conversion channel, thereby realizing the fabrication of a three-dimensional integrated photoelectric conversion chip based on silicon through-holes.

[0071] According to the above preparation method of the three-dimensional integrated photoelectric conversion chip based on silicon through-holes, embodiments of the present invention also provide a fabrication method of a three-dimensional integrated photoelectric conversion chip of a GaAs-based pin-type photodetector chip and a GaAs-based low-noise amplifier chip. The following is a detailed description.

[0072] Figure 4 One of the cross-sectional views of a three-dimensional integrated photoelectric conversion chip of a GaAs-based pin-type photodetector chip and a GaAs-based low-noise amplifier chip according to an embodiment of the present invention is schematically shown.

[0073] Exemplarily, a wafer is selected and cut into 4-inch square pieces, and the wafer silicon substrate 301 is thinned to 200 μm, and then a silicon dioxide mask layer is deposited. As Figure 4 shown, the lithographic alignment marks are made, and then the positions of the silicon through-holes are defined by lithography. The processes of spin coating, pre-baking, exposure, development, and post-baking are completed in sequence. Then, deep reactive ion etching is performed on the wafer to form cylindrical silicon through-holes 305 with a diameter of 50 μm and a depth of 200 μm. Then, the etching mask layer is removed, and the through-holes are cleaned by RCA standard cleaning or Ar gas cleaning.

[0074] Please continue to refer to Figure 4, inside the through-hole, a 0.8-μm-thick polyimide insulating layer 303 is grown by vacuum-assisted spin coating technology. Then, a 0.1-μm-thick titanium nitride barrier layer 304 is grown by dual-catalyzed electroless plating. Subsequently, conductive material is filled. An even copper seed layer is grown on the sidewalls of the hole by electroless plating, and then the hole core is filled with through-silicon via 305 by electroplating copper to form a copper pillar. Thereafter, an annealing process is carried out, with an annealing temperature of 300 °C and a duration of 30 minutes.

[0075] Furthermore, the wafer surface is planarized by chemical mechanical polishing to sequentially remove the copper electroplating residual layer, the barrier layer, and the polymer insulating dielectric layer, and then it is cleaned and dried with nitrogen. Thereafter, a 2-μm-thick first silicon dioxide insulating layer 302 is deposited on one side of the wafer along the first direction X1 by PECVD process, and contact holes are etched directly above the copper pillars.

[0076] Figure 5 Schematically shows a second cross-sectional view of the GaAs-based pin-type photodetector chip and the GaAs-based low-noise amplifier chip three-dimensional integrated optoelectronic conversion chip according to an embodiment of the present invention.

[0077] As Figure 5 shown, photolithography is performed, a Ti seed layer is sputtered on the wafer surface, and a first redistribution layer pattern is formed in the Ti seed layer. The first redistribution layer is electroplated to increase its thickness, de-glued, and etched, where the thickness of the first redistribution layer 4 is 2 μm. Subsequently, it is cleaned and dried with nitrogen. Thereafter, bump photolithography is performed on the first redistribution layer 4, and a 1.6-μm-thick Au layer and a 1.7-μm-thick Sn layer are deposited on the seed layer by evaporation and then peeled off to form the first bump 7.

[0078] Figure 6 Schematically shows a third cross-sectional view of the GaAs-based pin-type photodetector chip and the GaAs-based low-noise amplifier chip three-dimensional integrated optoelectronic conversion chip according to an embodiment of the present invention.

[0079] As Figure 6 shown, the wafer is temporarily bonded to the glass wafer on one side along the first direction X1 on the bonding instrument by applying a bonding layer 308, and the other side of the wafer along the first direction X1 is thinned to 200 μm by chemical mechanical polishing to expose the copper pillars of the through-silicon via 305. Thereafter, the silicon wafer is dry-etched by 3 μm to expose the copper pillars by 3 μm.

[0080] Figure 7 Schematically shows a fourth cross-sectional view of the GaAs-based pin-type photodetector chip and the GaAs-based low-noise amplifier chip three-dimensional integrated optoelectronic conversion chip according to an embodiment of the present invention.

[0081] As Figure 7As shown, a second silicon dioxide insulating layer 309 with a thickness of 2 μm is deposited on the exposed side surface of the copper pillar on the silicon substrate 301. Chemical mechanical polishing is performed to make the copper pillar flush with the silicon dioxide insulating layer, and the plane is cleaned with deionized water. Then, a Ti seed layer is sputtered on the second silicon dioxide insulating layer 309, and a second redistribution layer pattern is formed by photolithography on the Ti seed layer. Electroplating thickening, degluing, and etching are performed on the second redistribution layer, where the thickness of the second redistribution layer 2 is 2 μm.

[0082] Furthermore, it is cleaned and dried with nitrogen. Then, photolithography is performed on the second redistribution layer 2, and a 1.6-μm-thick Au layer and a 1.7-μm-thick Sn layer are deposited by evaporation on the seed layer and then lifted off to obtain the second bump 6.

[0083] Figure 8 FIG. 5 schematically shows a cross-sectional view of a GaAs-based pin-type photodetector chip and a GaAs-based low-noise amplifier chip three-dimensional integrated optoelectronic conversion chip according to an embodiment of the present invention.

[0084] As Figure 8 shown, it is debonded by a laser lift-off process, and the residual glue is cleaned with a solvent. A low-noise amplifier chip 312 with a size of 3.36 mm × 1.50 mm is fabricated by GaAs PHEMT process. Then, the pre-fabricated photodetector chip 313 is bonded to the first redistribution layer 4 and the low-noise amplifier chip 312 is bonded to the second redistribution layer 2 by thermocompression bonding. After that, the first DC-blocking capacitor 314, the second DC-blocking capacitor 315, the first resistor 316, the second resistor 317, the first capacitor 318, and the second capacitor 319 are soldered on the first redistribution layer 4.

[0085] Those skilled in the art can understand that although the present invention has been shown and described with reference to specific exemplary embodiments of the present invention, those skilled in the art should understand that various changes in form and details can be made to the present invention without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents. Therefore, the scope of the present invention should not be limited to the above embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

[0086] The above specific embodiments have further detailed the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-dimensional integrated optoelectronic conversion chip based on through-silicon vias, characterized in that, Comprising: An electrical chip layer (1); A second redistribution layer (2), a through-silicon via interposer layer (3), a first redistribution layer (4) and an optical chip layer (5) are sequentially stacked on one side of the electrical chip layer (1) along a first direction; Wherein, the electrical chip layer (1) and the second redistribution layer (2) are bonded by second bumps (6), and the first redistribution layer (4) and the optical chip layer (5) are bonded by first bumps (7); The electrical chip layer (1) includes a low-noise amplifier chip (312), and the optical chip layer (5) includes a photodetector chip (313); The first redistribution layer (4), the second redistribution layer (2) and the through-silicon via interposer layer (3) connect the photodetector chip (313) and the low-noise amplifier chip (312) to form an optoelectronic conversion channel, and the optoelectronic conversion channel is used to convert the optical signal received by the photodetector chip (313) into a radio frequency signal and output it through the low-noise amplifier chip (312).

2. The three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 1, wherein The first redistribution layer (4) includes a re-routing body for the optical chip layer, a bias circuit for the photodetector chip (313) and a DC-blocking capacitor for the low-noise amplifier chip (312); Wherein, the bias circuit of the photodetector chip (313) includes: a first resistor (316), a second resistor (317), a first capacitor (318) and a second capacitor (319), and the DC-blocking capacitors of the low-noise amplifier chip (312) include a first DC-blocking capacitor (314) and a second DC-blocking capacitor (315); The first end of the first resistor (316) is connected to the positive electrode of the photodetector chip (313), and the second end of the first resistor (316) is respectively connected to the second end of the first capacitor (318) and the second end of the second capacitor (319); The first end of the second resistor (317) is respectively connected to the negative electrode of the photodetector chip (313) and the first end of the first capacitor (318), and the second end of the second resistor (317) is connected to the first end of the second capacitor (319).

3. The three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 1, characterized in that, The through-silicon via interposer layer (3) sequentially includes a second silicon dioxide layer insulating layer (309), a silicon substrate (301) and a first silicon dioxide layer insulating layer (302) in the direction from the electrical chip layer (1) to the optical chip layer (5); Wherein, a plurality of through-silicon vias (305) are provided in the silicon substrate (301).

4. The three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 3, characterized in that, The side walls of the through-silicon vias (305) include a polyimide insulating layer (303) and a titanium nitride barrier layer (304), and the interiors of the through-silicon vias (305) are filled with electroplated copper.

5. A method for preparing a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias, characterized in that, Comprising: S1, providing a silicon substrate (301), and etching on one side of the silicon substrate (301) along a first direction to form a plurality of through-silicon vias (305); S2, preparing a through-silicon via interposer layer (3) including the silicon substrate (301) based on the plurality of through-silicon vias (305); S3, sputtering a metal seed layer on one side of the through-silicon via interposer layer (3) along a first direction to form a first redistribution layer (4); S4. Bond the DC-blocking capacitor of the low-noise amplifier chip (312), the photodetector chip (313), and the bias circuit of the photodetector chip (313) to the first redistribution layer (4). S5. Sputter a metal seed layer on the other side of the silicon substrate (301) along the first direction to form a second redistribution layer (2). S6. Bond the low-noise amplifier chip (312) to the second redistribution layer (2). S7. Form a lithography circuit on the first redistribution layer (4) and the second redistribution layer (2) respectively, and combine and connect the photodetector chip (313) and the low-noise amplifier chip (312) through the silicon via transfer layer (3) to form a photoelectric conversion channel.

6. The method for preparing a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 5, wherein S2 includes: Deposit a polyimide insulating layer (303) and a titanium nitride barrier layer (304) on the sidewalls of each silicon via (305) of the silicon substrate (301) in sequence, and fill each silicon via (305) with electroplated copper.

7. The preparation method of the three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 5, wherein, S3 includes: Perform a planarization treatment on the surface of the silicon via transfer layer (3), and deposit a first silicon dioxide layer insulating layer (302) on one side of the silicon substrate (301) along the first direction. Sputter a metal seed layer on the first silicon dioxide layer insulating layer (302). Lithographically form a wiring layer pattern on the metal seed layer, and coat a photoresist as an insulating layer to form a first redistribution layer (4).

8. The manufacturing method of the three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 7, characterized in that, S4 includes: Lithographically electroplate gold-tin on the first redistribution layer (4) to form a first bump (7). Bond the DC-blocking capacitor of the low-noise amplifier chip (312), the photodetector chip (313), and the bias circuit of the photodetector chip (313) to the first bump (7).

9. The method for preparing a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 5, characterized in that, S5 includes: Perform a polishing and thinning treatment on the other side of the silicon substrate (301) along the first direction to expose the copper pillars of the silicon vias (305). Deposit a second silicon dioxide layer insulating layer (309) on the exposed side surface of the copper pillars of the silicon substrate (301), and perform a polishing treatment to make the silicon dioxide insulating layer flush with the copper pillars. Sputter a metal seed layer on the second silicon dioxide layer insulating layer (309) to form a second redistribution layer (2).

10. The method for preparing a three-dimensional integrated optoelectronic conversion chip based on through-silicon vias according to claim 9, wherein S6 further includes: Lithographically electroplate gold-tin on the second redistribution layer (2) to form a second bump (6). Bond the low-noise amplifier chip (312) to the second bump (6).

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