Method for applying stable strain to semiconductor material and product

Abstract

The invention provides a method for applying stable strain to a semiconductor material and a product. The method mainly comprises the following steps that S1, a semiconductor material donor and a negative thermal expansion substrate are obtained, and the negative thermal expansion substrate has the property of positive thermal expansion or low thermal expansion in a first temperature interval and a third temperature interval and has the property of negative thermal expansion in a second temperature interval between the first temperature interval and the third temperature interval; s2, bonding the semiconductor material donor to the negative thermal expansion substrate at a first temperature in a first temperature interval; s3, stripping the first semiconductor layer on the semiconductor material donor from the semiconductor material donor at a second temperature in the first temperature interval; and S4, enabling the product subjected to the step S3 to work at the temperature of a third temperature interval. According to the method for applying the stable strain to the semiconductor material, the strain stability of the semiconductor material can be kept at the working temperature, and the strain control cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor materials and device processes. Specifically, it relates to a method for applying stable strain to a semiconductor material and related semiconductor products. Background Art

[0002] Applying strain to a semiconductor material can change the unit cell parameters of its lattice, and thus can regulate the optical and electrical properties of the semiconductor. The national invention patent application with the application number CN202510412013.8 provides a technical solution for applying strain to a semiconductor material by bonding the semiconductor material to a negative thermal expansion substrate. However, as Figure 1 shown, due to the large difference in the thermal expansion coefficients between the semiconductor material and the negative thermal expansion substrate, when the working temperature of the semiconductor material or the device prepared therefrom fluctuates, the stress on the semiconductor material changes greatly, and the performance of the material or device will fluctuate greatly. In order to avoid the influence caused by such temperature fluctuations, it is necessary to precisely control the working temperature of the material or device, which will increase the additional usage cost. Reducing the influence of temperature fluctuations on the performance of the material or device, that is, improving the temperature stability of the material or device performance, is very important. Summary of the Invention

[0003] The main object of the present invention is to provide a method for applying stable strain to a semiconductor material, and at the same time provide a semiconductor product with large strain based on this method.

[0004] The first aspect of the present invention provides a method for applying stable strain to a semiconductor material, the method comprising the following steps:

[0005] Step S1, obtaining a semiconductor material donor and a negative thermal expansion substrate, the negative thermal expansion substrate having the property of positive thermal expansion or low thermal expansion in the first temperature range and the third temperature range, and having the property of negative thermal expansion in the second temperature range between the first temperature range and the third temperature range;

[0006] Step S2, bonding the semiconductor material donor to the negative thermal expansion substrate at a first temperature within the first temperature range;

[0007] Step S3, peeling a first semiconductor layer on the semiconductor material donor from the semiconductor material donor at a second temperature within the first temperature range;

[0008] Step S4, operating the product completed in step S3 at a temperature within the third temperature range.

[0009] Optionally, as a possible implementation, in the step S1, the negative thermal expansion substrate may be composed of a negative thermal expansion material, or may be prepared by mixing multiple negative thermal expansion materials, or may be a composite material of negative thermal expansion and other substances.

[0010] Optionally, as a possible implementation, in the step S1, the negative thermal expansion substrate preferably contains a compound or alloy having a magnetic phase change.

[0011] Optionally, as a possible implementation, in the step S1, the negative thermal expansion substrate contains (Zr,Nb)Fe2, (Hf,Nb)Fe2, (Hf,Ta)Fe 2+x , (Hf,Ti)Fe2, Tb(Co,Fe)2, La(Fe,Co,Si) 13 , Mn3(Cu,A)N (A = Co, Ni, Zn, Ga, Ge, Rh, Pd, Ag, In, Sn or Sb), (Ga,Mn)N y Mn3(0 < y < 1), CrAs, intermetallic compounds based on MnCoGe, intermetallic compounds based on MnNiGe, or one or more of them.

[0012] Optionally, as a possible implementation, the semiconductor material donor may be an elemental semiconductor, such as Si, Ge; or a semiconductor alloy, such as Si x Ge y , Ge x Sn y , Si x Ge y Sn z ; or a compound semiconductor, such as GaAs, InP.

[0013] Optionally, as a possible implementation, the semiconductor material donor may be a semiconductor wafer or an epitaxial wafer.

[0014] Optionally, as a possible implementation, the semiconductor material donor may be a substrate material, and in some scenarios, it may also be an epitaxial wafer with a device structure.

[0015] Optionally, as a possible implementation, preferably, the negative thermal expansion substrate has a thermal expansion coefficient close to that of the semiconductor material donor in the first temperature range, and the difference between the two is not higher than 10 ppm K -1 . In one case, the second temperature may be the same as the first temperature. It should be understood that the selection of the second temperature should be based on the fact that the thermal stress between the semiconductor material donor and the negative thermal expansion substrate during the peeling process is within the range that both materials can withstand.

[0016] Optionally, as a possible implementation, in step S2, any one of the bonding methods such as glass fusion bonding, dielectric layer bonding, surface activation bonding, and anodic bonding can be used for the bonding.

[0017] Optionally, as a possible implementation, in order to enhance the bonding strength, a bonding enhancement layer can also be provided on the negative thermal expansion substrate, and then the bonding process is carried out.

[0018] Optionally, as a possible implementation, in step S3, the peeling of the first semiconductor layer on the semiconductor material donor at the second temperature in the first temperature range can be achieved by injecting light ions into the semiconductor material donor, and then, during or after bonding, making the injected ions aggregate to generate bubbles and cure and crosslink at the second temperature, so that the first semiconductor layer on the side of the semiconductor material donor bonded to the negative thermal expansion substrate is peeled off from the semiconductor material donor.

[0019] The light ions are usually H or He; the injection dose of the ions is between 1×10 16 cm -2 and 2×10 17 cm -2 .

[0020] Optionally, as a possible implementation, in step S3, the peeling of the first semiconductor layer on the semiconductor material donor at the second temperature in the first temperature range can be achieved by using a laser that can be transmitted by the original substrate of the epitaxial wafer and absorbed by the epitaxial layer to separate the epitaxial layer from its original substrate at the second temperature after bonding, where the semiconductor material donor is an epitaxial wafer and the epitaxial layer of the epitaxial wafer is the first semiconductor layer of the present invention.

[0021] Optionally, as a possible implementation, in step S3, the peeling of the first semiconductor layer on the semiconductor material donor at the second temperature in the first temperature range can be achieved by using thinning and / or polishing and combining dry etching and / or wet etching to complete the removal of the epitaxial substrate after bonding, where the semiconductor material donor is an epitaxial wafer and the epitaxial layer of the epitaxial wafer is the first semiconductor layer of the present invention.

[0022] Optionally, as a possible implementation, in step S3, the second temperature in the first temperature range strips the first semiconductor layer on the semiconductor material donor from the semiconductor material donor. More specifically, the semiconductor material donor may be an epitaxial wafer obtained by using the van der Waals epitaxy method, and the epitaxial layer of the epitaxial wafer is the first semiconductor layer of the present invention. After the bonding is completed, the epitaxial layer is stripped from its original substrate by mechanical stripping at the second temperature.

[0023] Optionally, as a possible implementation, the method for applying stable strain to a semiconductor material according to the present invention may further include removing a portion of the first semiconductor layer that is not the target semiconductor material layer after step S3; the removing of the portion of the first semiconductor layer that is not the target semiconductor material layer can be accomplished by dry etching or wet etching.

[0024] Optionally, as a possible implementation, the method for applying stable strain to a semiconductor material according to the present invention may further include a repair step for the target semiconductor material layer after step S3; the repair step can be accomplished by thermal annealing or laser annealing at a specific temperature.

[0025] The second aspect of the present invention provides a semiconductor product with strain, which includes a negative thermal expansion substrate, a semiconductor material layer, and a bonding layer. The semiconductor product is obtained by implementing the method for applying stable strain to a semiconductor material provided in the first aspect.

[0026] Compared with the prior art, the beneficial effects of the present invention are: it can maintain the stability of the semiconductor material strain at the working temperature, and while adjusting the optical and electrical properties of the semiconductor material, it reduces the control cost of its optoelectronic properties. Description of the Drawings

[0027] Figure 1 It is a schematic diagram of the temperature instability of the negative thermal expansion substrate applying strain to the semiconductor material;

[0028] Figure 2 It is a schematic diagram of the principle of applying stable strain to the semiconductor material of the present invention;

[0029] Figure 3 It is a process flow chart of the method for applying stable strain to the semiconductor material of the present invention;

[0030] Figure 4 It is a process schematic diagram of an embodiment of the present invention;

[0031] Figure 5 It is a graph of the relative length change of the negative thermal expansion substrate and the semiconductor material used in the embodiment of the present invention versus temperature;

[0032] Figure 6 It is the product structure diagram obtained by implementing the method described in the present invention. Detailed implementation manners

[0033] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further describes the present invention in detail with reference to specific embodiments and the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0034] In the present invention, the endpoints and any values within the invented ranges are not limited to the exact ranges or values. These ranges or values should be understood to include values close to these ranges or values. For numerical ranges, between the endpoint values of each range, between the endpoint values of each range and individual point values, and between individual point values, they can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically invented in the present invention.

[0035] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0036] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0037] Similarly, in order to streamline the present invention and help understand one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure or description thereof. The description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0038] The descriptions such as "first", "second", etc. used herein are only for distinguishing the specified features and should not be understood as specific limitations on the specific features.

[0039] Strain can change the unit cell parameters of a crystal. Especially for semiconductors, the application of strain can regulate the optical and electrical properties of the semiconductor. Using the difference in the thermal expansion coefficients of materials to apply strain to semiconductor materials is a scheme for realizing the regulation of the optoelectronic properties of semiconductor materials. For example, since the thermal expansion coefficient of Ge is higher than that of Si, Ge on Si (GOS) obtained by epitaxially growing Ge on Si can obtain a tensile strain of about 0.2% in the epitaxial Ge layer under high-temperature annealing. This tensile strain can improve the absorption efficiency of Ge in the C-band and L-band. Based on the GOS platform, high-performance optoelectronic sensors that can be used in the communication band can be prepared at low cost using standard CMOS processes. In addition, the national invention patent application with the application number CN202510412013.8 provides a technical solution for applying strain to a semiconductor material by bonding the semiconductor material to a negative thermal expansion substrate. The strain ε introduced in this technical solution can be evaluated by the following formula:

[0040]

[0041] In the above formula, α semi refers to the thermal expansion coefficient of the semiconductor material, and α NTE is the thermal expansion coefficient of the negative thermal expansion substrate, T bonding is the temperature at which the bonding process is completed, T application is the temperature at which the device or equipment made of the semiconductor product operates, and δ is the influence of some relaxation mechanisms of the strain on the strain; and respectively represent the in-plane length change rates of the negative thermal expansion substrate and the semiconductor material when changing temperature from the temperature at which the bonding process is completed to the application temperature. When ε is positive, it means that the semiconductor material layer on the negative thermal expansion substrate is applied with tensile strain; when ε is negative, it means that the semiconductor material layer on the negative thermal expansion substrate is applied with compressive strain.

[0042] However, as Figure 1 shown, due to the large difference in the thermal expansion coefficients between the semiconductor substrate and the negative thermal expansion material, when the operating temperature of the material or device obtained based on this technical solution fluctuates, the strain applied to the material will change greatly, and thus the performance of the material or device will fluctuate greatly. In order to avoid the influence caused by such temperature fluctuations, it is necessary to precisely control the operating temperature of the material or device, which will increase additional usage costs. Reducing the influence of temperature fluctuations on the performance of the material or device, that is, improving the temperature stability of the performance of the material or device, is very important.

[0043] To solve the above technical problems, the first aspect of the present invention provides a method for applying stable strain to a semiconductor material, as Figure 2As shown, this method bonds a semiconductor material to a negative thermal expansion substrate with specific negative thermal expansion properties to apply stable strain to the semiconductor material. In this method, the negative thermal expansion substrate has positive thermal expansion or low thermal expansion properties in the first temperature range and the third temperature range, and has negative thermal expansion properties in the second temperature range between the first temperature range and the third temperature range. The so-called low thermal expansion means that the thermal expansion coefficient of the material is lower than 5 ppm K -1 , and more preferably, lower than 2 ppm K -1 . This method bonds a semiconductor material donor to the negative thermal expansion substrate at a first temperature in the first temperature range, so as to realize a semiconductor product with strain in the entire semiconductor material layer at a third temperature in the third temperature range. The third temperature is the operating temperature of the device or equipment made based on this semiconductor product, usually room temperature, or a lower temperature. It can be understood that when the third temperature is lower than the first temperature, when the product temperature decreases from the first temperature to the third temperature, the negative thermal expansion substrate expands in volume, and then stretches the semiconductor material layer, which can apply tensile strain to the semiconductor material layer. In some cases, the third temperature is higher than the first temperature, that is, bonding is completed at a lower temperature, and the device or equipment made of this semiconductor product operates at a higher temperature. At this time, compressive strain can be introduced into the semiconductor material layer.

[0044] As Figure 3 shown, the method for applying stable strain to a semiconductor material according to the present invention includes the following steps:

[0045] Step S1, obtain a semiconductor material donor and a negative thermal expansion substrate. The negative thermal expansion substrate has positive thermal expansion or low thermal expansion properties in the first temperature range and the third temperature range, and has negative thermal expansion properties in the second temperature range between the first temperature range and the third temperature range.

[0046] The so-called negative thermal expansion substrate refers to a substrate material with the property of contracting when heated and expanding when cooled in the plane, that is, negative thermal expansion; the negative thermal expansion substrate can have uniaxial negative thermal expansion properties, that is, it can realize uniaxial strain on the material bonded to it, or it can be a substrate with biaxial negative thermal expansion properties, that is, it can realize biaxial strain on the material bonded to it; the negative thermal expansion substrate can have isotropic negative thermal expansion properties or anisotropic negative thermal expansion properties. The negative thermal expansion substrate can be composed of a single negative thermal expansion material, or can be made by mixing multiple negative thermal expansion materials, or can be a composite material of negative thermal expansion and other substances, such as adding a strength enhancer to the negative thermal expansion material. The negative thermal expansion substrate preferably includes a compound or alloy having a magnetic phase change, such as including (Zr,Nb)Fe2, (Hf,Nb)Fe2, (Hf,Ta)Fe 2+x, (Hf,Ti)Fe2, Tb(Co,Fe)2, La(Fe,Co,Si) 13 , Mn3(Cu,A)N (A = Co, Ni, Zn, Ga, Ge, Rh, Pd, Ag, In, Sn or Sb), (Ga,Mn)N y One or more of Mn3(0 < y < 1), CrAs, intermetallic compounds based on MnCoGe, and intermetallic compounds based on MnNiGe.

[0047] The semiconductor material donor can be an elemental semiconductor, such as Si, Ge; or a semiconductor alloy, such as Si x Ge y , Ge x Sn y , Si x Ge y Sn z ; or a compound semiconductor, such as GaAs, InP. The semiconductor material donor can be a semiconductor wafer or an epitaxial wafer; in addition, the semiconductor material donor can be a substrate material, and in some scenarios, it can also be an epitaxial wafer with a device structure, etc.

[0048] Step S2, bond the semiconductor material donor to the negative thermal expansion substrate at a first temperature within the first temperature range. The bonding can be any bonding method as long as its bonding strength can ensure that the bonded wafer will not fail at the third temperature in the third temperature range, i.e., the working temperature. The bonding can use any one of glass fusion bonding, dielectric layer bonding, surface activation bonding, and anodic bonding. To enhance the bonding strength, a bonding enhancement layer can also be provided on the negative thermal expansion substrate, and then the bonding process is carried out.

[0049] Step S3, peel the first semiconductor layer on the semiconductor material donor from the semiconductor material donor at a second temperature within the first temperature range. Both the first temperature and the second temperature are within the first temperature range. Preferably, the negative thermal expansion substrate has a thermal expansion coefficient close to that of the semiconductor material donor within the first temperature range, and the difference between the two is not higher than 10 ppm K -1 . In one case, the second temperature can be the same as the first temperature. It should be understood that the selection of the second temperature should be based on the fact that the thermal stress between the semiconductor material donor and the negative thermal expansion substrate during the peeling process is within the range that both materials can withstand.

[0050] In an embodiment of the present invention, the second temperature in the first temperature range strips the first semiconductor layer on the semiconductor material donor from the semiconductor material. This can be achieved by injecting light ions into the semiconductor material donor before the bonding process. Then, during or after the bonding, the injected ions are aggregated at the second temperature to generate bubbles and cure and crosslink, so that the first semiconductor layer on the side of the semiconductor material donor bonded to the negative thermal expansion substrate is stripped from the semiconductor material donor. The light ions are usually H or He, and H or He is injected into a certain depth of the semiconductor material donor by ion implantation. The certain depth means that the injected H or He ions aggregate at the second temperature to generate bubbles and cure and crosslink, causing the first semiconductor layer to be stripped from the semiconductor material donor. The injection dose of the ions is between 1×10 16 cm -2 and 2×10 17 cm -2 .

[0051] In an embodiment of the present invention, the second temperature in the first temperature range strips the first semiconductor layer on the semiconductor material donor from the semiconductor material donor. This can be achieved by using a semiconductor material donor as an epitaxial wafer, where the epitaxial layer of the epitaxial wafer is the first semiconductor layer of the present invention. After the bonding is completed, at the second temperature, a laser that can be transmitted by the original substrate of the epitaxial wafer and absorbed by the epitaxial layer is used to separate the epitaxial layer from its original substrate.

[0052] In an embodiment of the present invention, the second temperature in the first temperature range strips the first semiconductor layer on the semiconductor material donor from the semiconductor material donor. This can be achieved by using a semiconductor material donor as an epitaxial wafer, where the epitaxial layer of the epitaxial wafer is the first semiconductor layer of the present invention. After the bonding is completed, at the second temperature, the removal of the epitaxial substrate is completed by thinning and / or polishing and combining dry etching and / or wet etching.

[0053] In an embodiment of the present invention, the second temperature in the first temperature range strips the first semiconductor layer on the semiconductor material donor from the semiconductor material donor. More specifically, this can be achieved by using a semiconductor material donor as an epitaxial wafer obtained by the van der Waals epitaxy method, where the epitaxial layer of the epitaxial wafer is the first semiconductor layer of the present invention. After the bonding is completed, at the second temperature, the epitaxial layer is stripped from its original substrate by mechanical peeling.

[0054] Step S4: Operate the product that has completed step S3 at a temperature in the third temperature range.

[0055] In addition, the method according to the present invention may further include removing a portion of the first semiconductor layer that is not the target semiconductor material layer after step S3; the removing of the portion of the first semiconductor layer that is not the target semiconductor material layer may be accomplished by dry etching or wet etching.

[0056] In addition, the method according to the present invention may further include a repairing step for the target semiconductor material layer after step S3; the repairing step may be accomplished by thermal annealing or laser annealing at a specific temperature. Laser annealing is performed at a specific temperature to ensure that the laser annealing step does not relax the strain introduced to the target semiconductor material layer by the method according to the present invention.

[0057] To better illustrate the method for applying stable strain to a semiconductor material according to the present invention, the following will be introduced in combination with specific embodiments. The following embodiments are only for facilitating the understanding of the method for applying stable strain to a semiconductor material according to the present invention, and should not be construed as the method for applying stable strain to a semiconductor material according to the present invention being only applicable to the following embodiments.

[0058] Embodiment 1

[0059] Ge has good absorption performance for electromagnetic waves in the communication band and is an important platform for manufacturing detectors in the communication band. Applying tensile strain to Ge can improve its detection performance in the C band and longer bands. Currently, the main solution for applying tensile strain to Ge lies in the doping of Sn. However, the solid solubility of Sn in Ge is very low, and the saturated solid solubility in the equilibrium state is less than 0.3%, and the strain introduced by it in Ge is very limited. The embodiment of the present invention discloses a method for obtaining large-sized Ge with stable tensile strain, as Figure 4 shown.

[0060] First, a negative thermal expansion substrate 401 and a Ge wafer 402 are obtained. In this embodiment, the negative thermal expansion substrate 401 is made of LaFe 10.7 Co 0.8 Si 1.5 formed.

[0061] 300-nm SiO2 layers 403 and 404 are respectively disposed on the negative thermal expansion substrate 401 and the Ge wafer 402.

[0062] H ion implantation is performed on the side of the Ge wafer 402 provided with the SiO2 layer 404. The H ion implantation energy is 180 KeV, and the implantation dose is 6×10 16 cm -2 , and the implanted H ions are mainly concentrated at 405 about 1 μm deep from the surface of the Ge wafer.

[0063] Perform CMP polishing on the SiO2 layer 403 and the SiO2 layer 404 to make the surface roughness RMS lower than 0.5 nm.

[0064] Use surface activated bonding to pre-bond the polished SiO2 layer 403 and the SiO2 layer 404 together at room temperature to obtain the bonding layer 406.

[0065] Then complete the bonding by maintaining at a pressure of 2000 N at 300 °C for 3 hours. At the same time, the H ions implanted in the Ge wafer will form bubbles and cure and crosslink under this condition, causing the Ge layer 407 with a thickness of about 1 μm in contact with the bonding layer 406 on the Ge wafer to peel off from the Ge wafer to obtain the bonded wafer 408.

[0066] In addition, in order to repair the damage to the Ge layer 407 caused by ion implantation, pulsed laser annealing, flash lamp annealing or furnace annealing can be used to anneal and repair the Ge layer 407.

[0067] Based on Figure 5 It is known that when the bonded wafer 408 is cooled to below 230 K, a tensile strain of about 0.4% can be obtained on the Ge layer 407, which is equivalent to the tensile strain introduced by 4% Sn doping. And below 230 K, the difference in the coefficient of thermal expansion between the Ge layer 407 and the negative thermal expansion substrate 401 is small, and the change in the working temperature has little effect on the magnitude of the strain in Ge.

[0068] It should be noted again that the semiconductor material donor is not limited to the form disclosed in the above embodiments, and can also be an epitaxial wafer with a device structure, etc. In addition, the negative thermal expansion substrate is not limited to the substrate made of LaFe 10.7 Co 0.8 Si 1.5 prepared substrate, and can also be made of other negative thermal expansion materials, or made of a composite of a negative thermal expansion material and other materials.

[0069] The second aspect of the present invention provides a semiconductor product with stable strain. As Figure 6 shown, it includes a negative thermal expansion substrate 601, a semiconductor material layer 602 and a bonding layer 603. The semiconductor product is prepared by implementing the method for applying stable strain to the semiconductor material provided in the first aspect.

[0070] The above specific embodiments have further detailed the purpose, technical solution and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for applying a stable strain to a semiconductor material, the method comprising the following steps: Step S1, obtaining a semiconductor material donor and a negative thermal expansion substrate, the negative thermal expansion substrate having the property of positive thermal expansion or low thermal expansion in a first temperature range and a third temperature range, and having the property of negative thermal expansion in a second temperature range between the first temperature range and the third temperature range; Step S2, bonding the semiconductor material donor to the negative thermal expansion substrate at a first temperature within the first temperature range; Step S3, peeling a first semiconductor layer on the semiconductor material donor from the semiconductor material donor at a second temperature within the first temperature range; Step S4, operating the product completed in Step S3 at a temperature within the third temperature range.

2. The method for applying a stable strain to a semiconductor material according to claim 1, characterized in that, The negative thermal expansion substrate may be composed of a negative thermal expansion material, or may be prepared by mixing multiple negative thermal expansion materials, or may be a composite material of negative thermal expansion and other substances.

3. The method for applying a stable strain to a semiconductor material according to claim 1, characterized in that, The negative thermal expansion substrate preferably includes a compound or alloy having a magnetic phase change.

4. The method for applying a stable strain to a semiconductor material according to claim 1, characterized in that, The semiconductor material donor may be a semiconductor wafer or an epitaxial wafer.

5. The method for applying a stable strain to a semiconductor material according to claim 1, characterized in that, In the first temperature range, the negative thermal expansion substrate has a thermal expansion coefficient close to that of the semiconductor material donor, and the difference between the two is not higher than 10 ppmK -1 ; in one case, the second temperature may be the same as the first temperature. It should be understood that the second temperature should be selected such that the thermal stress between the semiconductor material donor and the negative thermal expansion substrate during the peeling process is within the range that both materials can withstand.

6. The method for applying a stable strain to a semiconductor material according to claim 1, characterized in that, The bonding may use any one of the bonding methods such as glass fusion bonding, dielectric layer bonding, surface activation bonding, and anodic bonding.

7. The method for applying a stable strain to a semiconductor material according to claim 1, characterized in that, In order to enhance the bonding strength, a bonding enhancement layer may be provided on the negative thermal expansion substrate, and then the bonding process is carried out.

8. The method for applying a stable strain to a semiconductor material according to claim 1, characterized in that, The peeling of the first semiconductor layer on the semiconductor material donor from the semiconductor material at the second temperature within the first temperature range may be that light ions are implanted into the semiconductor material donor, and then during or after bonding, the implanted ions are aggregated at the second temperature to generate bubbles and cure and crosslink, so that the first semiconductor layer on the side of the semiconductor material donor bonded to the negative thermal expansion substrate is peeled from the semiconductor material donor.

9. The method for applying a stable strain to a semiconductor material according to claim 1, wherein The peeling of the first semiconductor layer on the semiconductor material donor from the semiconductor material donor at the second temperature within the first temperature range may be that the semiconductor material donor is an epitaxial wafer, the epitaxial layer of the epitaxial wafer is the first semiconductor layer described in the present invention, and after bonding is completed, the removal of the epitaxial substrate is completed at the second temperature using thinning and / or polishing and combined with dry etching and / or wet etching.

10. A semiconductor product having a stable strain, which includes a negative thermal expansion substrate, a semiconductor material layer, and a bonding layer, and the semiconductor product is prepared by implementing the method according to any one of claims 1-9.

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