Display substrate, display device and crack detection method

Abstract

The embodiment of the invention provides a display substrate, a display device and a crack detection method. The display substrate comprises a display area and a frame area located around the display area, the frame area comprises a detection unit and at least one first anti-static unit, the detection unit at least comprises a first detection line and a second detection line, and the second detection line is located on the side, away from the display area, of the first detection line. The first detection line and the second detection line are electrically connected through at least one connecting structure, at least one of the at least one connecting structure is of a nonlinear structure, the first detection line at least partially surrounds the display area, the second detection line at least partially surrounds the display area, and the detection unit is configured to detect whether the display substrate has cracks or not. The first anti-static unit is electrically connected with at least one of the first detection line and the second detection line, and the detection unit is connected with the first anti-static unit, so that the risk of electrostatic injury in the detection unit can be reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and in particular, to a display substrate, a display device, and a crack testing method. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technologies, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFTs) have become the mainstream products in the current display field.

[0003] Currently, there is a technical problem that the crack detection line of the display substrate is prone to electrostatic damage. Summary of the Invention

[0004] The problem to be solved by the embodiments of the present disclosure is to provide a display substrate, a display device, and a crack detection method to solve the technical problem that the crack detection line of the existing display substrate is prone to electrostatic damage.

[0005] To solve the above technical problem, in a first aspect, embodiments of the present disclosure provide a display substrate, including:

[0006] A substrate, where the substrate includes a display area and a border area located around the display area;

[0007] A detection unit, located in the border area, where the detection unit at least includes a first detection line and a second detection line, the second detection line is located on a side of the first detection line away from the display area, the first detection line and the second detection line are electrically connected through at least one connection structure, at least one of the at least one connection structure is a non-linear structure, the first detection line at least partially surrounds the display area, the second detection line at least partially surrounds the display area, and the detection unit is configured to detect whether the display substrate has cracks;

[0008] At least one first anti-static unit, located in the border area, and the at least one first anti-static unit is electrically connected to at least one of the first detection line and the second detection line.

[0009] In an exemplary embodiment, in the direction from the display area towards the border area, the width dimension of the second detection line is greater than the width dimension of the first detection line.

[0010] In an exemplary embodiment, in the direction from the display area towards the border area, the width dimension of the second detection line is greater than or equal to 15 micrometers, and the width dimension of the first detection line is less than 15 micrometers.

[0011] In an exemplary embodiment, in a second direction, the border area includes a first border area and a second border area located on both sides of the display area; in a first direction, the border area includes a third border area and a fourth border area located on both sides of the display area; in the plane of the substrate, the first direction intersects the second direction.

[0012] At least part of the structures of the first detection line and the second detection line extend along the third border area, the second border area, and the fourth border area, and surround the display area. The first detection line and the second detection line merge into one detection line in the first border area.

[0013] In an exemplary embodiment, the at least one first anti-static unit is located in the first border area and is electrically connected to the first detection line and the second detection line through the one detection line.

[0014] In an exemplary embodiment, the border area further includes a first corner area and a second corner area. The first border area is connected to the third border area through the first corner area, and the first border area is connected to the fourth border area through the second corner area.

[0015] The number of the at least one first anti-static unit is two. The two first anti-static units are respectively located in the first corner area and the second corner area and are electrically connected to the first detection line and the second detection line through the one detection line.

[0016] In an exemplary embodiment, the at least one connection structure includes a first connection structure, a second connection structure, and a third connection structure. The first connection structure is located in the second border area, the second connection structure is located in the third border area, and the third connection structure is located in the fourth border area.

[0017] In an exemplary embodiment, the first connection structure is located in the middle of the second border area, the second connection structure is located in the middle of the third border area, and the third connection structure is located in the middle of the fourth border area.

[0018] In an exemplary embodiment, at least one of the first connection structure, the second connection structure, and the third connection structure is a broken line or a curved line structure.

[0019] In an exemplary embodiment, the path length of the second connection structure is less than the path lengths of the first connection structure and the third connection structure.

[0020] In an exemplary embodiment, the path length of the first connection structure is 5 cm to 15 cm, the path length of the second connection structure is 50 μm to 150 μm, and the path length of the third connection structure is 5 cm to 15 cm.

[0021] In an exemplary embodiment, the first detection line and the second detection line are bent in the first corner region and the second corner region, and chamfers are provided at the bending positions.

[0022] In an exemplary embodiment, the display area further includes a plurality of sub-pixels, at least one of the plurality of sub-pixels includes a pixel driving circuit, the pixel driving circuit includes a plurality of transistors and at least one capacitor, and the plurality of transistors includes at least one first type of transistor;

[0023] In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate on one side of the substrate, and a second electrode plate on a side of the first electrode plate away from the substrate; the first type of transistor includes: an active layer, a control electrode, a first electrode, and a second electrode, the active layer of the first type of transistor is located between the first electrode plate and the substrate, the control electrode of the first type of transistor is arranged on the same layer as the first electrode plate, and the first electrode and the second electrode are located on a side of the second electrode plate away from the substrate;

[0024] At least part of the structures of the first detection line and the second detection line is arranged on the same layer as at least one of the first electrode plate and the second electrode plate, and the at least one connection structure is arranged on the same layer as the first detection line and the second detection line.

[0025] In an exemplary embodiment, the plurality of transistors further includes at least one second type of transistor, the second type of transistor includes: an active layer, a control electrode, a first electrode, and a second electrode, in a direction perpendicular to the plane of the substrate, the active layer of the second type of transistor is located on a side of the second electrode plate away from the substrate, the control electrode of the second type of transistor is located on a side of the active layer of the second type of transistor away from the substrate, and the first electrode and the second electrode of the second type of transistor, and the first electrode and the second electrode of the first type of transistor are located on a side of the control electrode of the second type of transistor away from the substrate;

[0026] At least part of the structures of the first detection line and the second detection line are provided in the same layer as at least one of the first electrode plate, the second electrode plate, and the control electrode of the second type of transistor.

[0027] In an exemplary embodiment, the display substrate may further include at least one jumper wire, and the at least one jumper wire includes at least one first jumper wire and at least one second jumper wire. The first jumper wire is electrically connected to the first detection line, and the second jumper wire is electrically connected to the second detection line;

[0028] The first jumper wire and the second jumper wire are provided in the same layer as the first pole and the second pole, or the first jumper wire and the second jumper wire are located on a side of the first pole and the second pole away from the substrate.

[0029] In an exemplary embodiment, one first jumper wire and one second jumper wire are respectively provided in the third border area and the fourth border area. The two first jumper wires located in the third border area and the fourth border area are symmetric with respect to the first midline, and the two second jumper wires located in the third border area and the fourth border area are symmetric with respect to the first midline. The first midline is the midline of the display substrate extending along the second direction.

[0030] In an exemplary embodiment, the border area further includes a low-voltage power line, a first corner area, and a second corner area. At least part of the structure of the low-voltage power line is located in the first corner area and the second corner area. The first border area is connected to the third border area through the first corner area, and the first border area is connected to the fourth border area through the second corner area; the one detection line, the low-voltage power line are provided in the same layer as the first pole and the second pole, or the one detection line, the low-voltage power line are located on a side of the first pole and the second pole away from the substrate;

[0031] The number of the at least one first anti-static unit is two, and the two first anti-static units are respectively located in the first corner area and the second corner area. The first anti-static unit includes a plurality of anti-static capacitors connected in parallel, and the plurality of anti-static capacitors include a first electrode plate and a second electrode plate;

[0032] In the same first anti-static unit: the first electrode plates of the plurality of anti-static capacitors are electrically connected to the one detection line, the second electrode plates of the plurality of anti-static capacitors are electrically connected to the low-voltage power line, the first electrode plates of the anti-static capacitors are provided in the same layer as the active layer of the first type of transistor, and the second electrode plates of the anti-static capacitors are provided in the same layer as the control electrode of the first type of transistor.

[0033] In an exemplary embodiment, within the same anti-static unit: the second electrodes of the plurality of anti-static capacitors are in a closed annular structure, and the first electrodes of the plurality of anti-static capacitors are a plurality of independent block structures. In the closed annular structure, the width of the overlapping region with the plurality of independent block structures is greater than the width of the non-overlapping region with the plurality of independent block structures.

[0034] In an exemplary embodiment, the first border region includes a first voltage signal line and a second voltage signal line. The one detection line, the first voltage signal line, and the second voltage signal line are disposed on the same layer as the first electrode and the second electrode, or the one detection line, the first voltage signal line, and the second voltage signal line are located on the side of the first electrode and the second electrode away from the substrate.

[0035] The number of the at least one first anti-static unit is two. The two first anti-static units are located in the first border region. And in the first direction, one of the first anti-static units is located on the side of the first border region close to the third border region, and the other first anti-static unit is located on the side of the first border region close to the fourth border region.

[0036] In a second aspect, the present disclosure also provides a display device including the display substrate according to any one of the above embodiments.

[0037] In a third aspect, an embodiment of the present disclosure also provides a crack detection method for detecting cracks in a display substrate. The display substrate includes a display region and a border region around the display region. The border region includes a detection unit. The detection unit at least includes a first detection line and a second detection line. The second detection line is located on the side of the first detection line away from the display region. The first detection line and the second detection line are electrically connected through at least one connection structure. At least one of the at least one connection structure is a non-linear structure. The first detection line at least partially surrounds the display region. The second detection line at least partially surrounds the display region. The detection unit is configured to detect whether cracks occur in the display substrate. The crack detection method includes:

[0038] Testing the resistance of the detection unit and determining whether cracks occur in the display substrate according to the tested resistance.

[0039] In an exemplary embodiment, in a second direction, the border area includes a first border area and a second border area located on both sides of the display area. In a first direction, the border area includes a third border area and a fourth border area located on both sides of the display area. In the plane of the substrate, the first direction intersects the second direction; at least part of the structures of the first detection line and the second detection line extend along the third border area, the second border area, and the fourth border area and surround the display area. The first detection line and the second detection line merge into one detection line in the first border area. The one detection line includes a first end point and a second end point. The first end point is the connection node of the first detection line and the second detection line with the one detection line located in the third border area, and the second end point is the connection node of the first detection line and the second detection line with the one detection line located in the fourth border area;

[0040] The at least one connection structure includes a first connection structure, a second connection structure, and a third connection structure. The first connection structure is located in the second border area, the second connection structure is located in the third border area, and the third connection structure is located in the fourth border area;

[0041] Testing the resistance of the test detection unit includes: testing the resistance between the first end point and the second end point.

[0042] In an exemplary embodiment, the first connection structure is located in the middle of the second border area, the second connection structure is located in the middle of the third border area, the third connection structure is located in the middle of the fourth border area. The detection unit includes a first area, a second area, a third area, and a fourth area. The first area is located between the first connection structure and the second connection structure, the second area is located between the first connection structure and the third connection structure, the third area is located between the second connection structure and the first border area, and the fourth area is located between the third connection structure and the first border area;

[0043] The method further includes: determining the position of the crack on the display substrate according to the tested resistance; the crack position includes at least one of the first area, the second area, the third area, and the fourth area.

[0044] In an exemplary embodiment, the border area further includes at least one first anti-static unit, and the at least one first anti-static unit is electrically connected to at least one of the first detection line and the second detection line.

[0045] The display substrate, display device, and crack detection method provided by the embodiments of the present disclosure. The display substrate includes a display area and a border area located around the display area. The border area includes a detection unit and at least one first anti-static unit. The detection unit includes at least a first detection line and a second detection line. The second detection line is located on the side of the first detection line away from the display area. The first detection line and the second detection line are electrically connected through at least one connection structure. At least one of the at least one connection structure is a non-linear structure. The first detection line at least partially surrounds the display area, and the second detection line at least partially surrounds the display area. The detection unit is configured to detect whether a crack appears on the display substrate. The first anti-static unit is electrically connected to at least one of the first detection line and the second detection line. In the technical solution provided by the embodiments of the present disclosure, the detection unit is connected to the first anti-static unit, which can reduce the risk of electrostatic injury in the detection unit. At least one of the at least one connection structure being a non-linear structure can preliminarily detect the position where a crack appears on the display substrate.

[0046] Other aspects will be apparent after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the content of the present disclosure schematically.

[0048] Figure 1 Shown is a schematic structural diagram of a display device;

[0049] Figure 2a Shown is a schematic structural diagram of a display substrate;

[0050] Figure 2b Shown is a schematic structural diagram of a display substrate;

[0051] Figure 3 Shown is a schematic diagram of the first border area of a display substrate;

[0052] Figure 4 Described is a schematic structural diagram of a display substrate;

[0053] Figure 5a Described as Figure 2a and Figure 2b a schematic cross-sectional structure diagram along the a0-a0 position in

[0054] Figure 5b Described as Figure 2a and Figure 2b a schematic cross-sectional structure diagram along the a0-a0 position in

[0055] Figure 6 Schematic diagram of the structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0056] Figure 7 Schematic diagram of the structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0057] Figure 8a For Figure 6 And Figure 7 Enlarged schematic diagram of the structure at position U2 in

[0058] Figure 8b For Figure 8a Enlarged schematic diagram of the position at U1 in

[0059] Figure 9a For Figure 6 And Figure 7 Enlarged schematic diagram of the structure at position U3 in

[0060] Figure 9b For Figure 6 And Figure 7 Enlarged schematic diagram of the structure at position U4 in

[0061] Figure 9c For Figure 6 And Figure 7 Enlarged schematic diagram of the structure at position U5 in

[0062] Figure 9d For Figure 6 And Figure 7 Enlarged schematic diagram of the structure at position U3 in

[0063] Figure 9e For Figure 6 And Figure 7 Enlarged schematic diagram of the structure at position U4 in

[0064] Figure 9f For Figure 6 And Figure 7 Enlarged schematic diagram of the structure at position U5 in

[0065] Figure 10a Schematic diagram of a transfer structure of a detection unit provided by an exemplary embodiment of the present disclosure;

[0066] Figure 10b Schematic diagram of a transfer structure of a detection unit provided by an exemplary embodiment of the present disclosure;

[0067] Figure 11a Schematic diagram of the structure of a first anti-static unit provided by an exemplary embodiment of the present disclosure;

[0068] Figure 11b For Figure 11aSchematic diagram of an equivalent circuit of a first anti-static unit;

[0069] Figure 11c Schematic diagram of the structure of a semiconductor layer of a first anti-static unit provided by an exemplary embodiment of the present disclosure;

[0070] Figure 11d Schematic diagram of a first anti-static unit after forming a first gate metal layer provided by an exemplary embodiment of the present disclosure;

[0071] Figure 11e Schematic diagram of a first anti-static unit after forming a second gate metal layer provided by an exemplary embodiment of the present disclosure;

[0072] Figure 11f Schematic diagram of a first anti-static unit after forming a connection via provided by an exemplary embodiment of the present disclosure;

[0073] Figure 11g Schematic diagram of a first anti-static unit after forming a first source / drain metal layer provided by an exemplary embodiment of the present disclosure;

[0074] Figure 11h Schematic diagram of a first source / drain metal layer of a first anti-static unit provided by an exemplary embodiment of the present disclosure;

[0075] Figure 11i Schematic diagram of the structure of a first anti-static unit provided by an exemplary embodiment of the present disclosure;

[0076] Figure 12a Schematic diagram of the structure of a first anti-static unit provided by an exemplary embodiment of the present disclosure;

[0077] Figure 12b For Figure 12a Schematic diagram of an equivalent circuit of a first anti-static unit;

[0078] Figure 12c Schematic diagram of the structure of a semiconductor layer of a first anti-static unit provided by an exemplary embodiment of the present disclosure;

[0079] Figure 12d Schematic diagram of a first anti-static unit after forming a first gate metal layer provided by an exemplary embodiment of the present disclosure;

[0080] Figure 12e Schematic diagram of a first anti-static unit after forming a connection via provided by an exemplary embodiment of the present disclosure;

[0081] Figure 12f Schematic diagram of a first anti-static unit after forming a first source / drain metal layer provided by an exemplary embodiment of the present disclosure;

[0082] Figure 12g Schematic diagram of the first source-drain metal layer of a first anti-static unit provided by an exemplary embodiment of the present disclosure;

[0083] Figure 13 Shown is a schematic diagram of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0084] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0085] It can be understood that the accompanying drawings in the embodiments of the present disclosure are only used to schematically show the connection relationships between various components. The sizes of the various components in the drawings are not drawn to scale, and their relative positional relationships do not necessarily exactly correspond to the actual positions.

[0086] In the present disclosure, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection", "fixation" and the like shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0087] In the present disclosure, "electrical connection" includes the situation where components are connected together through components having a certain electrical effect. There are no particular limitations on the "components having a certain electrical effect" as long as they can transfer electrical signals between the constituent elements that can be connected. Examples of the "components having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having various functions.

[0088] In the present disclosure, "film" and "layer" can be interchanged. For example, sometimes the "conductive layer" can be changed to the "conductive film". Similarly, sometimes the "insulating film" can be changed to the "insulating layer".

[0089] The "lithography process" referred to in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist. Deposition can be carried out using any one or more selected from sputtering, evaporation plating, and chemical vapor deposition. Coating can be carried out using any one or more selected from spraying and spin coating. Etching can be carried out using any one or more selected from dry etching and wet etching. A "thin film" refers to a thin film made of a certain material on a substrate (which can be called a substrate board) using a deposition or coating process. If this "thin film" does not require a lithography process during the entire manufacturing process, this "thin film" can also be called a "layer". When this "thin film" still requires a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process contains at least one "pattern".

[0090] In the present disclosure, "electrical connection" includes cases where components are connected together through an element having a certain electrical effect. There are no particular limitations on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. The "element having a certain electrical effect" can be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, an inductor, or a capacitor.

[0091] Figure 1The following is a schematic structural diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is respectively connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is respectively connected to a plurality of data signal lines (D1 to Dn). The scan signal driving circuit is respectively connected to a plurality of scan signal lines (G1 to Gm). The light emission signal driving circuit is respectively connected to a plurality of light emission signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The pixel driving circuit may be respectively connected to the scan signal line, the light emission signal line, and the data signal line (which may be referred to as the data line). In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data signal driving circuit may sample the gray value using a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driving circuit may generate scan signals to be provided to the scan signal lines G1, G2, G3,..., and Gm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driving circuit may sequentially provide scan signals having conductive level pulses to the scan signal lines G1 to Gm. For example, the scan signal driving circuit may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where m may be a natural number. The light emission signal driving circuit may generate emission signals to be provided to the light emission signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emission signal driving circuit may sequentially provide emission signals having cut-off level pulses to the light emission signal lines E1 to Eo. For example, the light emission driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where o may be a natural number.

[0092] Figure 2aThe following is a schematic structural diagram of a display panel. As Figure 2a shown, the display panel may include a display area AA and a border area BB located around the display area AA. In some examples, the border area BB may include: a first border area (lower border) B1 and a second border area (upper border) B2 that are oppositely arranged in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 that are oppositely arranged in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a plurality of regularly arranged sub-pixels Pxij, a plurality of gate control signal lines SL, and a plurality of data lines DL. The plurality of gate control signal lines SL may extend along the first direction X, and the plurality of data lines DL may extend along the second direction Y. The orthographic projections of the plurality of gate control signal lines SL and the plurality of data lines DL on the substrate may cross to form a plurality of sub-pixel areas, and one sub-pixel Pxij may be disposed in each sub-pixel area. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels Pxij, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels Pxij. The plurality of gate control signal lines SL may be electrically connected to the plurality of sub-pixels Pxij, and the plurality of gate control signal lines SL may be configured to provide gate control signals to the plurality of sub-pixels Pxij. In some examples, the gate control signal may include a scan signal and a light emission control signal, or may include a scan signal, or may include a scan signal, a reset control signal, and a light emission control signal. The sub-pixel Pxij may include a pixel driving circuit and a light emitting device. The first border area B1 may include a bonding circuit for connecting signal lines to an external driving device. The third border B3 and the fourth border B4 may include a gate driving circuit and a second power supply line VSS for transmitting voltage signals to the plurality of sub-pixels.

[0093] Figure 3The figure shows a schematic plan view of the first border region B1. In a plane parallel to the display substrate, the first border region B1 may include a first fan-out region 11, a bending region 12, a second fan-out region 13, an anti-static region 15, a third fan-out region 16, and a bonding region 14, which are arranged in sequence along the direction away from the display region AA. Among them, the bonding region 14 may include a driving chip region 141 and a bonding electrode region 142, which are arranged in sequence along the direction of the second fan-out region 13 away from the bending region 12. The first fan-out region 11 may include data fan-out lines, a first power supply line, and a second power supply line VSS. The data fan-out lines are located in the middle of the first fan-out region 11 and include a plurality of data connection lines. The plurality of data connection lines are configured to connect the data lines in the display region AA in a fan-out routing manner. The first power supply line is configured to connect the high-voltage power supply line (VDD) in the display region AA, and the second power supply line is the low-voltage power supply line (VSS) located in the third border region B3 and the fourth border region B4. The bending region 12 may include a composite insulating layer provided with grooves and is configured to bend the bonding region 14 to the back of the display region AA (such as Figure 4As shown, the bending region 12 is provided with data connection lines. One end of the data connection lines in the bending region 12 is connected to the data connection lines in the first fan-out region 11, and the other end is connected to the data connection lines in the second fan-out region 13. The second fan-out region 13 includes multiple data connection lines led out in a fan-out routing manner. The anti-static region 15 is provided with multiple anti-static circuits 40, and the multiple anti-static circuits 40 are connected to the multiple data connection lines in the second fan-out region 13. The third fan-out region 16 includes multiple data output lines led out in a fan-out routing manner, and the multiple data output lines are connected to the multiple anti-static circuits 40 in the anti-static region 15. The driving chip region 141 can be provided with an integrated circuit (IC) 20, configured to be connected to the multiple data output lines in the third fan-out region 16. The driving chip region 141 can be provided with multiple driving pads and multiple input pads. Multiple input ports of the integrated circuit 20 can be electrically connected to the multiple input pads, and multiple output ports of the integrated circuit can be connected to the multiple driving pads. The input pads are used for inputting signals, and after being signal-converted by the integrated circuit 20, the signals are output to the driving pads. The driving pads transfer signals (such as data signals) to the corresponding data lines DL through the corresponding data output lines and corresponding data connection lines. The bonding electrode region 142 includes multiple bonding pads, configured to be bonded and connected to a flexible printed circuit (FPC) 30. The bonding pads can also be electrically connected to the corresponding input pads through multiple signal leads. Signals from the FPC can be transmitted to the integrated circuit 20 through the input pads. In an exemplary embodiment, the integrated circuit 20 can be bonded and connected in the driving chip region 141, and the flexible circuit board 30 can be bonded and connected in the bonding electrode region 142. In an exemplary embodiment, the integrated circuit 20 (which can be referred to as a data driving circuit) can generate driving signals required for driving sub-pixels and can provide the driving signals to the sub-pixels Pxij located in the display area AA. For example, the driving signals can be data signals for controlling the light-emitting brightness of the sub-pixels. In an exemplary embodiment, the bonding electrode region 142 can be provided with bonding pads (PADs) including multiple pins, and the flexible printed circuit 30 can be bonded and connected to the pads.

[0094] In an exemplary embodiment, as Figure 4 shown, the bending region 12 can invert the surface of the bonding region 14, that is, the surface of the bonding region 14 facing upward can be converted to face downward through the bending of the bending region 12. In an exemplary embodiment, when the bending region 12 is bent, the bonding region 14 can overlap with the display area AA in the thickness direction of the display panel.

[0095] In an exemplary embodiment, as Figure 2b shown, it is a schematic structural diagram of another display panel.Figure 2b The difference from Figure 2a is that Figure 2b there is no bending area 12 provided in Figure 2b , and the binding area 14 cannot be bent to the back of the display area AA. Other structures are the same as those of Figure 2a and Figure 2b . In an exemplary embodiment, the integrated circuit 20 in

[0096] is bound to the first border area B1; the integrated circuit 20 can also be bound to the flexible circuit board 30, which can reduce the size of the first border area B1. This structure can be called a chip on film (COF).

[0097] Figure 5a is Figure 2a and Figure 2b a schematic cross-sectional view taken along the a0-a0 position of the sub-pixel Pxij in the display area AA of the display substrate shown in Figure 5a . In Figure 5a , the structure of a sub-pixel in the display area is taken as an example for illustration. In this example, it is assumed that the types of multiple transistors in the pixel circuit are the same. For example, multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors or all be oxide thin-film transistors. As shown in Figure 5b , multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors. In other examples, multiple transistors in the pixel circuit can be low-temperature polysilicon thin-film transistors and oxide thin-film transistors, as shown in

[0098] In some examples, such as Figure 5aAs shown in the figure, in the Z direction perpendicular to the plane where the display substrate is located, the display area of the display substrate may include: a substrate 100, and a circuit structure layer 200, a light-emitting structure layer 300, a packaging structure layer 400, a touch control structure layer 500, and a color filter layer 600 that are sequentially disposed on the substrate 100. Among them, the display structure layer may at least include the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may at least include: pixel circuits of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light-emitting structure layer 300 may at least include: light-emitting elements of a plurality of sub-pixels.

[0099] In some examples, Figure 5aTaking an example where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 200 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer, a passivation layer 204 and a first planarization layer 205 may be disposed between the first source-drain metal layer and the second source-drain metal layer, a second planarization layer 206 may be disposed between the second source-drain metal layer and the third source-drain metal layer, and a third planarization layer 207 may be disposed on the side of the third source-drain metal layer away from the substrate 100. Among them, the first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, and the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited thereto. In some other examples, a buffer layer 1501 may further be disposed on the side of the semiconductor layer close to the substrate. The buffer layer 1501 can prevent harmful substances in the substrate from invading the interior of the display substrate, and can also increase the adhesion of the film layers in the display substrate to the substrate. In some other examples, a bottom shielding metal layer (BSM, Bottom Shielding Metal) may be disposed on the side of the buffer layer 1501 close to the substrate. The bottom shielding metal layer BSM may be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid the influence of external light on the performance of the thin-film transistor. In some other examples, the passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first planarization layer may be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0100] In some examples, such as Figure 5aAs shown, the semiconductor layer of the display region may at least include: the active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may at least include: the gate 213 of the thin film transistor 21, and the first electrode plate 221 of the capacitor 22. The orthogonal projection of the gate 213 of the thin film transistor 21 on the substrate 100 may cover the orthogonal projection of the channel region 2100 of the active layer 210 on the substrate 100. The second gate metal layer may at least include: the second electrode plate 222 of the capacitor 22. The orthogonal projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may at least include: the source 211 and the drain 212 of the thin film transistor 21. The interlayer insulating layer 203 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display region. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 in the first pixel via may be removed to expose at least a part of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 in the second pixel via may be removed to expose at least a part of the surface of the second region 2102 of the active layer 210. The source 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may at least include: a first transfer electrode 231. The first transfer electrode 231 may be electrically connected to the drain 212 of the thin film transistor 21 of the pixel circuit through a third pixel via opened in the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may at least include: a second transfer electrode 232. The second transfer electrode 232 may be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer through a fourth pixel via opened in the second planarization layer 206. The second transfer electrode 232 may be electrically connected to the first electrode 301 (for example, the anode) of the light-emitting element through a fifth pixel via opened in the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the first transfer electrode 231 and the second transfer electrode 232.

[0101] In some examples, the gate lines of the display area may be located in the first gate metal layer or the second gate metal layer, for example. The data lines of the display area may be located in the second source-drain metal layer or the third source-drain metal layer, for example. The high-potential power supply line (the first power supply line) of the display area may be located in at least one of the second source-drain metal layer and the third source-drain metal layer. This embodiment is not limited thereto. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging a large number of traces in a single source-drain metal layer, thus facilitating the realization of a narrow border structure.

[0102] In some examples, as Figure 5a shown, the light-emitting structure layer 300 may include: a pixel definition layer 304 and a plurality of light-emitting elements. For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. The first electrode 301 may be disposed on the third planar layer 207 and is electrically connected to the second transfer electrode 232 through a fifth pixel via formed in the third planar layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer 207. The pixel definition layer 304 may be provided with a plurality of pixel openings, and at least a part of the surface of a corresponding first electrode 301 may be exposed through one pixel opening. At least a part of the organic light-emitting layer 302 may be disposed in one pixel opening and is connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may further be disposed on the side of the pixel definition layer 304 away from the substrate 100. The isolation pillar layer may include a plurality of isolation pillars (PS).

[0103] In some examples, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole block layer (HBL, Hole Block Layer), an electron block layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be utilized to emit light according to the required gray level.

[0104] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by a single process (a single evaporation process or a single inkjet printing process), and isolation may be achieved through the surface step difference of the formed film layer or through surface treatment and other means. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or may be formed by an inkjet process.

[0105] In some examples, as Figure 5a shown, in a direction perpendicular to the substrate, the encapsulation structure layer 400 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. Among them, the first encapsulation layer 401 and the third encapsulation layer 403 may adopt inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 402 may adopt an organic material. For example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or may be a polymer resin, etc. to planarize the surface of the display substrate, and can relieve the stress between the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that invade the interior. However, this embodiment is not limited thereto. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0106] In some examples, the touch structure layer in the display area may include: a plurality of first touch electrodes, a plurality of first connection portions, a plurality of second touch electrodes, and a plurality of second connection portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connection portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connection portions.

[0107] In some examples, as Figure 5aAs shown, in the direction perpendicular to the substrate, the touch structure layer 500 of the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, which are sequentially arranged. Among them, the touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, for example, they may be SiNx layers. The first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connection parts. The first touch electrodes and the first connection parts may be an integrated structure connected to each other. The second touch conductive layer 512 may include a plurality of second connection parts. The second connection parts may be connected to adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited thereto. In some other examples, the first touch conductive layer may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connection parts, and the second touch electrodes and the second connection parts may be an integrated structure connected to each other; the second touch conductive layer may include a plurality of first connection parts, and the first connection parts may be connected to adjacent first touch electrodes through vias formed in the touch interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Or, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited thereto.

[0108] In some examples, the first touch electrodes and the second touch electrodes may have a rhombus shape, for example, they may be a regular rhombus, or a horizontally long rhombus, or a vertically long rhombus. In some other examples, the first touch electrodes and the second touch electrodes may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The embodiments of the present disclosure do not limit this here.

[0109] In some examples, the first touch electrodes and the second touch electrodes may be in the form of transparent conductive electrodes. In some other examples, the first touch electrodes and the second touch electrodes may be in the form of a metal grid. The metal grid may be formed by interweaving multiple metal wires. The metal grid may include a plurality of grid patterns, and the grid patterns may be polygons formed by multiple metal wires. The first touch electrodes and the second touch electrodes in the form of a metal grid have advantages such as low resistance, small thickness, and fast response speed.

[0110] In some examples, such as Figure 5aAs shown, in the direction perpendicular to the substrate, the color filter layer (Colorfilter On Encapsulation, COE) 600 may include: an insulating layer 601, a color film layer, and an overcoat (OC) film 602, which are sequentially arranged. The color film layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610. The color filter units 611 may be, for example, red filter units, green filter units, or blue filter units.

[0111] In some examples, as Figure 5b shown, for Figure 2a and Figure 2b shown is a cross-sectional schematic diagram taken along the a0-a0 position of the sub-pixel Pxij in the display area AA of the display substrate. In the direction Z perpendicular to the display panel, the display area of the display substrate may include: a substrate 100 and a circuit structure layer 200, a light-emitting structure layer 300, a packaging structure layer 400, and a touch control structure layer 500, which are sequentially arranged on the substrate 100. Among them, the display structure layer may at least include the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may at least include: pixel circuits of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light-emitting structure layer 300 may at least include: light-emitting elements of a plurality of sub-pixels.

[0112] In some examples, Figure 5b takes one example where each sub-pixel includes a first transistor 21, a second transistor 23, and a capacitor 22 for illustration. The transistor types of the first transistor 21 and the second transistor 23 may be different. Among them, the first transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second transistor 23 may be an oxide thin-film transistor.

[0113] In some examples, the circuit structure layer 200 of the display region may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 100. The multiple display region metal layers of the display structure layer in this example may include: the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source / drain metal layer, and the second source / drain metal layer. A first gate insulation (GI) layer 201 may be disposed between the first semiconductor layer and the first gate metal layer, and a second gate insulation layer 202 may be disposed between the first gate metal layer and the second gate metal layer; a first interlayer dielectric (ILD) layer 103 and a first buffer layer 104 may be disposed between the second gate metal layer and the second semiconductor layer, and the first buffer layer 104 may be located on the side of the first interlayer dielectric layer 103 away from the substrate 100; a third gate insulation layer 105 may be disposed between the second semiconductor layer and the third gate metal layer; a second interlayer dielectric layer 106 may be disposed between the third gate metal layer and the first source / drain metal layer; a passivation (PVX) layer 204 and a first planarization (PLN) layer 205 may be disposed between the first source / drain metal layer and the second source / drain metal layer, and the first planarization layer 205 may be located on the side of the passivation layer 204 away from the substrate 100; a second planarization layer 206 may be disposed on the side of the second source / drain metal layer away from the substrate 100. Among them, the first gate insulation layer 201, the second gate insulation layer 202, the first interlayer dielectric layer 103, the first buffer layer 104, the third gate insulation layer 105, the second interlayer dielectric layer 106, and the passivation layer 204 may be inorganic insulation layers, and the first planarization layer 205 and the second planarization layer 206 may be organic insulation layers. However, this embodiment is not limited thereto. In some other examples, a buffer layer 1501 may further be disposed on the side of the first semiconductor layer close to the substrate, and the buffer layer 1501 may prevent harmful substances in the substrate from invading the interior of the display panel and may also increase the adhesion of the film layers in the display panel to the substrate. In some other examples, a bottom shielding metal layer (BSM) may further be disposed on the side of the buffer layer 1501 close to the substrate, and the bottom shielding metal layer BSM may be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid the influence of external light on the performance of the transistor. In some other examples, the passivation layer may be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer may be disposed between the first source / drain metal layer and the second source / drain metal layer. In some other examples, the first buffer layer may be omitted between the second gate metal layer and the second semiconductor layer, and only the first interlayer dielectric layer 103 may be disposed.

[0114] In some examples, such as Figure 5bAs shown, the first semiconductor layer of the display region may at least include: the first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may at least include: the first gate 213 of the first transistor 21 and the first electrode plate 221 of the capacitor 22. The orthographic projection of the first gate 213 of the first transistor 21 on the substrate 100 may cover the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 100. The second gate metal layer may at least include: the second electrode plate 222 of the capacitor 22 and the third gate 234 of the second transistor 23. The orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 100 may at least partially overlap. For example, the two may coincide. The second semiconductor layer may at least include: the second active layer 230 of the second transistor 23. The third gate metal layer may at least include: the second gate 233 of the second transistor 23. The orthographic projection of the second gate 233 of the second transistor 23 on the substrate 100 and the orthographic projection of the second active layer 230 on the substrate 100 may partially overlap. The orthographic projection of the third gate 234 of the second transistor 23 on the substrate 100 and the orthographic projection of the second active layer 230 on the substrate 100 may partially overlap. The third gate 234 may be the bottom gate of the second transistor 23, and the second gate 233 may be the top gate of the second transistor 23.

[0115] In some examples, such as Figure 5bAs shown, the first source-drain metal layer may at least include: the first source 211 and the first drain 212 of the first transistor 21, the second source 235 and the second drain 236 of the second transistor 23. The second interlayer insulating layer 106 may be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via may be removed to expose at least a part of the surface of the first region 2101 of the first active layer 210; the second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via may be removed to expose at least a part of the surface of the second region 2102 of the first active layer 210. The second interlayer insulating layer 106 and the third gate insulating layer 105 within the third pixel via and the fourth pixel via may be removed to expose at least a part of the surfaces at both ends of the second active layer 230. The first source 211 of the first transistor 21 may be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 may be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 235 of the second transistor 23 may be electrically connected to one end of the second active layer 230 through the third pixel via, and the second drain 236 of the second transistor 23 may be electrically connected to the other end of the second active layer 230 through the fourth pixel via. The second source-drain metal layer may at least include: a first transfer electrode 231. The first transfer electrode 231 may be electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through a fifth pixel via formed in the passivation layer 204 and the first planarization layer 205. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the first transfer electrode 231.

[0116] In some examples, the gate lines in the display area may be located, for example, in the first gate metal layer and the third gate metal layer, the data lines in the display area may be located, for example, in the second source-drain metal layer, and the high-potential power supply line (the first power supply line) in the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited thereto.

[0117] In some examples, such as Figure 5bAs shown, the light-emitting structure layer 300 may include: a pixel definition layer 304 and a plurality of light-emitting elements. For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. The first electrode 301 may be disposed on the second planar layer 206 and electrically connected to the first transfer electrode 231 through a sixth pixel via formed in the second planar layer 206. The pixel definition layer 304 is disposed on the first electrode 301 and the second planar layer 206. The pixel definition layer 304 may be provided with a plurality of pixel openings, and at least a part of the surface of a corresponding first electrode 301 may be exposed through one pixel opening. At least a part of the organic light-emitting layer 302 may be disposed in one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 may emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303.

[0118] In some examples, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more of a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole block layer (HBL, Hole Block Layer), an electron block layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material may be used to emit light according to the required gray scale.

[0119] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by one process (one evaporation process or one inkjet printing process), and isolation may be achieved by means of surface steps formed on the film layer or surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or by an inkjet process.

[0120] In some examples, as Figure 5b shown, the encapsulation structure layer 400 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. Among them, the first encapsulation layer 401 and the third encapsulation layer 403 may adopt inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 402 may adopt an organic material. For example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to planarize the surface of the display panel, and can relieve the stress between the first encapsulation layer 401 and the third encapsulation layer 403, and may also include a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that invade the interior. However, this embodiment is not limited thereto. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0121] In some examples, the touch structure layer in the display area may include: a plurality of first touch electrodes, a plurality of first connection parts, a plurality of second touch electrodes, and a plurality of second connection parts. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected by the first connection parts. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected by the second connection parts.

[0122] In some examples, as Figure 5bAs shown, in a direction perpendicular to the display panel, the touch structure layer 500 of the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulation layer (TLD) 502, a second touch conductive layer 512, and a protective layer 503, which are sequentially arranged. Among them, the touch buffer layer 501 and the touch interlayer insulation layer 502 may be inorganic insulation layers, and the protective layer 503 may be an organic insulation layer. The first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connection parts. The first touch electrodes and the first connection parts may be an integrated structure connected to each other. The second touch conductive layer 512 may include a plurality of second connection parts. The second connection parts may be connected to adjacent second touch electrodes through vias formed in the touch interlayer insulation layer. However, this embodiment is not limited thereto. In some other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connection parts, and the second touch electrodes and the second connection parts may be an integrated structure connected to each other; the second touch conductive layer may include a plurality of first connection parts, and the first connection parts may be connected to adjacent first touch electrodes through vias formed in the touch interlayer insulation layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Or, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited thereto.

[0123] In some examples, the first touch electrodes and the second touch electrodes may have a rhombus shape, for example, a regular rhombus, or a horizontally long rhombus, or a vertically long rhombus. In some other examples, the first touch electrodes and the second touch electrodes may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and the embodiments of the present disclosure do not limit this here.

[0124] In some examples, the first touch electrodes and the second touch electrodes may be in the form of transparent conductive electrodes. In some other examples, the first touch electrodes and the second touch electrodes may be in the form of a metal mesh, and the metal mesh may be formed by intertwining a plurality of metal wires. The metal mesh may include a plurality of mesh patterns, and the mesh patterns may be polygons formed by a plurality of metal wires. The first touch electrodes and the second touch electrodes in the form of a metal mesh have advantages such as low resistance, small thickness, and fast response speed.

[0125] In an exemplary embodiment, at least one sub-pixel Pxij may include a pixel circuit (which may be referred to as a pixel driving circuit) and a light-emitting element. In the same sub-pixel Pxij, the light-emitting element is electrically connected to the pixel circuit and is configured to emit light under the drive of the pixel circuit.

[0126] In an exemplary embodiment, Figure 2aThe difference from Figure 2b is that Figure 2b there is no bending area 12 set in Figure 2a , and the binding area 14 cannot be bent to the back of the display area AA. The other structures are the same as Figure 3 . In the structure shown in

[0127] , the driving chip area 141 is set to be bound and connected to the integrated circuit. This structure can be called a COP (Chip on Panel) structure. The integrated circuit can be a driver integrated circuit (abbreviated as DIC), and the binding electrode area 142 can be called a flexible circuit board binding area (which can be abbreviated as the FPC area). The driving integrated circuit (DIC) can also be bound to the flexible circuit board, which can reduce the size of the first border area B1. This structure can be called a chip on flex (COF).

[0128] Embodiments of the present disclosure provide a display substrate, which may include:

[0129] a substrate, the substrate includes a display area and a border area around the display area;

[0130] a detection unit, located in the border area, the detection unit at least includes a first detection line and a second detection line, the second detection line is located on a side of the first detection line away from the display area, the first detection line and the second detection line are electrically connected through at least one connection structure, at least one of the at least one connection structure is a non-linear structure, the first detection line at least partially surrounds the display area, the second detection line at least partially surrounds the display area, and the detection unit is configured to detect whether a crack appears on the display substrate;

[0131] at least one first anti-static unit, located in the border area, the at least one first anti-static unit is electrically connected to at least one of the first detection line and the second detection line.

[0132] In the display substrate provided by the embodiments of the present disclosure, it includes a display area and a border area located around the display area. The border area includes a detection unit and at least one first anti-static unit. The detection unit at least includes a first detection line and a second detection line. The second detection line is located on the side of the first detection line away from the display area. The first detection line and the second detection line are electrically connected through at least one connection structure. At least one of the at least one connection structure is a non-linear structure. The first detection line at least partially surrounds the display area, and the second detection line at least partially surrounds the display area. The detection unit is configured to detect whether there is a crack in the display substrate. The first anti-static unit is electrically connected to at least one of the first detection line and the second detection line. In the technical solution provided by the embodiments of the present disclosure, the detection unit is connected to the first anti-static unit, which can reduce the risk of electrostatic injury in the detection unit. At least one of the at least one connection structure being a non-linear structure can initially detect the location where the display substrate has a crack.

[0133] As Figure 6 and Figure 7 shown, the display substrate provided by the embodiments of the present disclosure may include:

[0134] A substrate, which includes a display area AA and a border area BB located around the display area AA;

[0135] A detection unit PCD, located in the border area BB. The detection unit PCD at least includes a first detection line L1 and a second detection line L2. The second detection line L2 may be located on the side of the first detection line L1 away from the display area AA. The first detection line L1 and the second detection line L2 are electrically connected through at least one connection structure CL. At least one of the at least one connection structure CL is a non-linear structure. The first detection line L1 at least partially surrounds the display area AA, and the second detection line L2 at least partially surrounds the display area AA. The detection unit PCD is configured to detect whether there is a crack in the display substrate;

[0136] At least one first anti-static unit ESD1, located in the border area BB. The at least one first anti-static unit ESD1 is electrically connected to at least one of the first detection line L1 and the second detection line L2.

[0137] In an exemplary embodiment, the detection unit PCD is a crack detection unit (the full English name is Panel Crack detector, abbreviated as PCD), which is used to detect whether there is a crack in the display substrate.

[0138] In an exemplary embodiment, when a crack appears in the display substrate, the second detection line L2 usually cracks or breaks. The first detection line L1 and the second detection line L2 are connected by at least one connection structure CL2, and at least one of the at least one connection structure CL is a non-linear structure. The connection structure CL can serve as a bridge resistor to divide the detection unit PCD into at least two regions. When the second detection line L2 breaks in different regions, the resistance of the detection unit PCD will be different, and it is possible to determine which region has a crack by testing the resistance of the detection unit PCD.

[0139] In an exemplary embodiment, as Figure 8a and Figure 8b shown, Figure 8a is Figure 6 and Figure 7 the enlarged schematic structural diagram of the detection unit PCD at the U2 position in Figure 8b is Figure 8a the enlarged schematic structural diagram of the U1 position in . In the direction from the display area AA to the border area BB, the width dimension D12 of the second detection line L2 is greater than the width dimension D11 of the first detection line L1.

[0140] In an exemplary embodiment, as Figure 8a and Figure 8b shown, in the direction from the display area AA to the border area, the width dimension D12 of the second detection line L2 is greater than or equal to 15 micrometers, and the width dimension D11 of the first detection line L1 is less than 15 micrometers. For example, in the direction from the display area AA to the border area BB, the width dimension D12 of the second detection line L2 is greater than or equal to 20 micrometers, and the width dimension D11 of the first detection line L1 is less than or equal to 10 micrometers.

[0141] In an exemplary embodiment, the width dimension D12 of the second detection line L2 is set relatively large, which can reduce the impedance of the second detection line L2, increase the current transmission ability, and reduce the risk of electrostatic burn.

[0142] In an exemplary embodiment, as Figure 6 and Figure 7 shown, in the second direction Y, the border area BB may include a first border area B1 and a second border area B2 on both sides of the display area AA. In the first direction X, the border area BB may include a third border area B3 and a fourth border area B4 on both sides of the display area AA. In the plane of the substrate, the first direction X intersects with the second direction Y;

[0143] At least part of the structures of the first detection line L1 and the second detection line L2 can extend along the third border area B3, the second border area B2, and the fourth border area B4 and surround the display area AA. The first detection line L1 and the second detection line L2 merge into one detection line L0 in the first border area B1.

[0144] In an exemplary embodiment, as Figure 6 shown, at least one first anti-static unit ESD1 can be located in the first border area B1 and is electrically connected to the first detection line L1 and the second detection line L2 through a detection line L0.

[0145] In an exemplary embodiment, as Figure 7 shown, the border area BB can further include a first corner area C1 and a second corner area C2. The first border area B1 is connected to the third border area B3 through the first corner area C1, and the first border area B1 is connected to the fourth border area B4 through the second corner area C2;

[0146] The number of at least one first anti-static unit ESD1 is two. The two first anti-static units ESD1 are respectively located in the first corner area C1 and the second corner area C2 and are electrically connected to the first detection line L1 and the second detection line L2 through a detection line L0.

[0147] In an exemplary embodiment, as Figures 9a to 9f shown, Figure 9a and Figure 9d are partial enlarged schematic diagrams of the detection unit PCD at the U3 position in Figure 7 and Figure 9b and Figure 9e are partial enlarged schematic diagrams of the detection unit PCD at the U4 position in Figure 7 and Figure 9c and Figure 9f are partial enlarged schematic diagrams of the detection unit PCD at the U5 position in Figure 7 . The first detection line L1 and the second detection line L2 can be electrically connected through at least one connection structure CL.

[0148] In an exemplary embodiment, as Figures 9a to 9f shown, at least one connection structure CL can include a first connection structure CL1, a second connection structure CL2, and a third connection structure CL3. The first connection structure CL1 can be located in the second border area B2, the second connection structure CL2 can be located in the third border area B3, and the third connection structure CL3 can be located in the fourth border area B4.

[0149] In an exemplary embodiment, the first connection structure CL1 may be located in the middle of the second border region B2, the second connection structure CL2 may be located in the middle of the third border region B3, and the third connection structure CL3 may be located in the middle of the fourth border region B4.

[0150] In an exemplary embodiment, as Figures 9a to 9f shown, at least one of the first connection structure CL1, the second connection structure CL2, and the third connection structure CL3 is a broken line or a curve structure. As Figures 9a to 9c shown, the first connection structure CL1, the second connection structure CL2, and the third connection structure CL3 are broken line structures. As Figures 9d to 9f shown, the first connection structure CL1, the second connection structure CL2, and the third connection structure CL3 are curve structures.

[0151] In an exemplary embodiment, as Figures 9a to 9f shown, the path length of the second connection structure CL2 is less than the path lengths of the first connection structure CL1 and the third connection structure CL3.

[0152] In an exemplary embodiment, the path length of the first connection structure CL1 may be 5 cm to 15 cm, the path length of the second connection structure CL2 may be 50 μm to 150 μm, and the path length of the third connection structure CL3 may be 5 cm to 15 cm. For example, the path length of the first connection structure CL1 may be 10 cm, the path length of the second connection structure CL2 may be 100 μm, and the path length of the third connection structure CL3 may be 10 cm. The first connection structure CL1, the second connection structure CL2, and the third connection structure CL3 may serve as bridge resistors. By setting the path lengths of the first connection structure CL1, the second connection structure CL2, and the third connection structure CL3 to be not completely the same, the position where the detection unit PCD has a crack (i.e., a break) can be preliminarily determined by testing the resistance of the detection unit PCD, so that the position where the display substrate has a crack can be determined.

[0153] In an exemplary embodiment, as Figures 9a to 9f shown, a blocking structure Dam may be provided in the border region BB. In the direction from the display region AA to the border region BB, the blocking structure Dam may be located between the first detection line L1 and the second detection line L2. The blocking structure Dam is disposed around the display region AA and is used to block the crack from extending to the display region AA. The blocking structure Dam is disconnected at the position of the connection structure CL. The blocking structure Dam may be a double-layer structure located in the first gate metal layer and the second gate metal layer.

[0154] In an exemplary embodiment, as Figure 8a and Figure 8bAs shown, the first detection line L1 and the second detection line L2 are bent in the first corner region C1 and the second corner region C2, and a chamfer F1 is provided at the bending position, which can weaken the static electricity at the corner positions of the first detection line L1 and the second detection line L2.

[0155] In an exemplary embodiment, as Figure 5a , Figure 5b , Figure 6 , Figure 7 shown, the display area AA may further include a plurality of sub-pixels Pxij, and at least one of the plurality of sub-pixels Pxij may include a pixel driving circuit. The pixel driving circuit includes a plurality of transistors and at least one capacitor. The plurality of transistors include at least one first type of transistor;

[0156] In a direction perpendicular to the plane of the substrate, the capacitor may include: a first electrode plate on one side of the substrate, and a second electrode plate on a side of the first electrode plate away from the substrate; the first type of transistor includes: an active layer, a control electrode, a first electrode, and a second electrode. The active layer of the first type of transistor is located between the first electrode plate and the substrate, the control electrode of the first type of transistor is provided on the same layer as the first electrode plate, and the first electrode and the second electrode are located on a side of the second electrode plate away from the substrate;

[0157] At least part of the structures of the first detection line L1 and the second detection line L2 are provided on the same layer as at least one of the first electrode plate and the second electrode plate, and at least one connection structure CL is provided on the same layer as the first detection line L1 and the second detection line L2. That is, at least part of the structures of the first detection line L1 and the second detection line L2 are located in at least one of the film layers such as Figure 5a shown, the first gate metal layer and the second gate metal layer.

[0158] In an exemplary embodiment, as Figure 5b shown, the plurality of transistors may further include at least one second type of transistor. The second type of transistor includes: an active layer, a control electrode, a first electrode, and a second electrode. In a direction perpendicular to the plane of the substrate, the active layer of the second type of transistor is located on a side of the second electrode plate away from the substrate, the control electrode of the second type of transistor is located on a side of the active layer of the second type of transistor away from the substrate, and the first electrode and the second electrode of the second type of transistor, and the first electrode and the second electrode of the first type of transistor are located on a side of the control electrode of the second type of transistor away from the substrate;

[0159] At least part of the structures of the first detection line L1 and the second detection line L2 are provided on the same layer as at least one of the first electrode plate, the second electrode plate, and the control electrode of the second type of transistor. That is, at least part of the structures of the first detection line L1 and the second detection line L2 may be located in at least one of the film layers such as Figure 5b shown, the first gate metal layer, the second gate metal layer, and the third gate metal layer.

[0160] In an exemplary embodiment, at least a partial region of the first detection line L1 and the second detection line L2 may be arranged to be in the same layer as at least two of the first electrode plate, the second electrode plate, and the control electrode of the second type of transistor. The multi-layer structure can reduce impedance and increase the electrostatic transmission ability of the first detection line L1 and the second detection line L2.

[0161] In an exemplary embodiment, the first type of transistor may be a P-type transistor, and the second type of transistor may be an N-type transistor. Figure 5a and Figure 5b in which the first transistor 21 is the first type of transistor, Figure 5b and the second transistor 23 is the second type of transistor.

[0162] In an exemplary embodiment, as Figure 10a and Figure 10b shown, the display substrate may further include at least one transfer line ZD. The at least one transfer line ZD may include at least one first transfer line ZD1 and at least one second transfer line ZD2. The first transfer line ZD1 is electrically connected to the first detection line L1, and the second transfer line ZD2 is electrically connected to the second detection line L2;

[0163] The first transfer line ZD1 and the second transfer line ZD2 may be arranged in the same layer as the first and second electrodes of the transistor, or the first transfer line ZD1 and the second transfer line ZD2 may be located on a side of the first and second electrodes of the transistor away from the substrate. The first transfer line ZD1 and the second transfer line ZD2 may be located in at least one of the film layers such as the first source-drain metal layer and the second source-drain metal layer as shown in Figure 5a and Figure 5b shown.

[0164] In an exemplary embodiment, arranging the first transfer line ZD1 and the second transfer line ZD2 can reduce the impedance of the first detection line L1 and the second detection line L2, increase the electrostatic transmission ability of the first detection line L1 and the second detection line L2, and reduce the risk of electrostatic burn of the first detection line L1 and the second detection line L2. Figure 10a As shown, the first detection line L1 and the second detection line L2 may be located in the first gate metal layer, Figure 10b As shown, the first detection line L1 and the second detection line L2 may be located in the second gate metal layer, and the first transfer line ZD1 and the second transfer line ZD2 may be located in the first source-drain metal layer. The first transfer line ZD1 may be electrically connected to the first detection line L1 through a first transfer via Vm1, and the second transfer line ZD2 may be electrically connected to the second detection line L2 through a second transfer via Vm2. In an exemplary embodiment, the first detection line L1 and the second detection line L2 may be a double-layer structure located in the first gate metal layer and the second gate metal layer, which can reduce resistance and enhance the electrostatic discharge ability.

[0165] In an exemplary embodiment, as shown in 6, Figure 7 , Figure 10a and Figure 10b shown, a first jumper wire ZD1 and a second jumper wire ZD2 are respectively arranged in the third border area B3 and the fourth border area B4. The two first jumper wires ZD1 located in the third border area B3 and the fourth border area B4 are symmetric with respect to the first median line Q1-Q1. The two second jumper wires ZD2 located in the third border area B3 and the fourth border area B4 are symmetric with respect to the first median line Q1-Q1, which can improve the accuracy of detecting the crack position. The first median line Q1-Q1 is the median line of the display substrate extending along the second direction Y.

[0166] In an exemplary embodiment, as shown in Figure 11a and Figure 11b shown, the border area BB may further include a low-voltage power supply line VSS (i.e., the second power supply line VSS), a first corner area C1 and a second corner area C2. At least part of the structure of the low-voltage power supply line VSS is located in the first corner area C1 and the second corner area C2. The first border area B1 is connected to the third border area B3 through the first corner area C1, and the first border area B1 is connected to the fourth border area B4 through the second corner area C2; the one detection line L0 and the low-voltage power supply line VSS may be arranged on the same layer as the first and second poles of the transistor, or the one detection line L0 and the low-voltage power supply line VSS may be located on the side of the first and second poles of the transistor away from the substrate; for example, the one detection line L0 and the low-voltage power supply line VSS may be located in at least one of the first source-drain metal layer and the second source-drain metal layer as shown in Figure 5a and Figure 5b shown.

[0167] The number of at least one first electrostatic protection unit ESD1 may be two. The two first electrostatic protection units ESD1 are respectively located in the first corner area C1 and the second corner area C2. The first electrostatic protection unit ESD1 includes a plurality of electrostatic protection capacitors CS connected in parallel. The plurality of electrostatic protection capacitors CS may include a first electrode plate CS1 and a second electrode plate CS2;

[0168] In the same first electrostatic protection unit ESD1: the first electrode plates CS1 of the plurality of electrostatic protection capacitors CS are electrically connected to the one detection line L0, the second electrode plates CS2 of the plurality of electrostatic protection capacitors CS are electrically connected to the low-voltage power supply line VSS, the first electrode plates CS1 of the electrostatic protection capacitors CS are arranged on the same layer as the active layer of the first type of transistor, the second electrode plates CS2 of the electrostatic protection capacitors CS are arranged on the same layer as the control pole of the first type of transistor, and the one detection line L0 can release static electricity into the electrostatic protection capacitors CS and the low-voltage power supply line VSS.

[0169] In an exemplary embodiment, as shown inFigure 11a and Figure 11h As shown in Figure 11d , in the same first anti-static unit: the second plates CS2 of multiple anti-static capacitors CS can be a closed annular structure, and the first plates CS1 of multiple anti-static capacitors CS can be multiple independent block structures. For example Figure 11d As shown in Figure 11d , in the closed annular structure, the width W1 of the overlapping region U6 with multiple independent block structures is greater than the width W2 of the region not overlapping with multiple independent block structures, which can increase the capacitance of the anti-static capacitor CS and reduce the risk of the anti-static capacitor CS being damaged by static electricity.

[0170] In an exemplary embodiment, as Figure 12a and Figure 12g As shown in Figure 5a , the first border region B1 may include a first voltage signal line VGH and a second voltage signal line VGL. The one detection line L0, the first voltage signal line VGH, and the second voltage signal line VGL may be disposed on the same layer as the first and second poles of the transistor, or the one detection line L0, the first voltage signal line VGH, and the second voltage signal line VGL are located on the side of the first and second poles of the transistor away from the substrate. For example, the one detection line L0, the first voltage signal line VGH, and the second voltage signal line VGL may be located in at least one of the first source-drain metal layer and the second source-drain metal layer as shown in Figure 5b . Figure 5a and Figure 5b As shown in Figure 5b .

[0171] The number of at least one first anti-static unit ESD1 may be two. The two first anti-static units ESD1 are located in the first border region B1. And in the first direction X, one of the first anti-static units ESD1 may be located on the side of the first border region B1 close to the third border region B3, and the other first anti-static unit ESD1 may be located on the side of the first border region B1 close to the fourth border region B4. The one detection line L0 may be configured to release static electricity to the first voltage signal line VGH or the second voltage signal line VGL under the control of the first anti-static unit ESD1.

[0172] In an exemplary embodiment, as Figure 6 and Figure 7 As shown in Figure 7 , the border region BB may further include a third corner region C3 and a fourth corner region C4. The third border region B3 may be connected to the second border region B2 through the third corner region C3, and the fourth border region B4 may be connected to the second border region B2 through the fourth corner region C4.

[0173] In an exemplary embodiment, Figure 11a is a structural diagram of a first anti-static unit, Figure 11aThe first anti-static unit shown can be located in the first corner region C1 and the second corner region C2 ( Figure 11a The position shown is in the first corner region C1. The first anti-static unit in the second corner region C2 can be symmetric with respect to the first center line Q1-Q1 to the first anti-static unit in the first corner region C1). The number of the first anti-static units can exceed two and is not limited to being arranged in the first corner region C1 and the second corner region C2. For example, it can also be arranged in at least one position among the first border region B1, the second border region B2, the third border region B3, the fourth border region B4, the third corner region C3, and the fourth corner region C4. Figure 12a The anti-static unit shown can be arranged in the first border region B1, but is not limited to being arranged in the first border region B1. For example, it can also be arranged in at least one position among the first corner region C1, the second corner region C2, the second border region B2, the third border region B3, the fourth border region B4, the third corner region C3, and the fourth corner region C4.

[0174] As Figures 12a to 12g shown, Figure 12a Shown is a schematic plan view of the first electrostatic discharge unit. Figure 12b Shown is a schematic circuit principle diagram of the first electrostatic discharge unit. Figure 12c Shown is the semiconductor layer of the first electrostatic discharge unit. Figure 12d Shown is a schematic diagram after the first electrostatic discharge unit forms the first gate metal layer. Figure 12e Shown is a schematic diagram after forming the connection vias. Figure 12f Shown is a schematic diagram after forming the source-drain metal layer. Figure 12g Shown is a schematic diagram of the source-drain metal layer. As Figure 12a shown, the first electrostatic discharge unit ESD1 can include the first transistor T1 to the twelfth transistor T12, and the first resistor R1 to the twelfth resistor R12. Among them, the first poles of the first transistor T1 to the twelfth transistor T12 are electrically connected to the detection line L0. The second poles of the first transistor T1, the second transistor T2, and the seventh transistor T7 to the tenth transistor T10 are electrically connected to the first voltage signal line VGH. The second poles of the third transistor T3 to the sixth transistor T6, the eleventh transistor T11, and the twelfth transistor T12 are electrically connected to the second voltage signal line VGL.

[0175] As Figure 12cAs shown, the semiconductor layer may include the active layers of the first resistor R1 to the twelfth resistor R12, and the first transistor T1 to the twelfth transistor T12. In the first direction X, the first resistor R1, the third resistor R3, the fifth resistor R5, the seventh resistor R7, the ninth resistor R9, and the eleventh resistor R11 may be located on one side of the first transistor T1 to the twelfth transistor T12, and the second resistor R2, the fourth resistor R4, the sixth resistor R6, the eighth resistor R8, the tenth resistor R10, and the twelfth resistor R12 may be located on the other side of the first transistor T1 to the twelfth transistor T2. The first resistor R1, the third resistor R3, the fifth resistor R5, the seventh resistor R7, the ninth resistor R9, and the eleventh resistor R11 may be arranged in sequence along the second direction Y, and the second resistor R2, the fourth resistor R4, the sixth resistor R6, the eighth resistor R8, the tenth resistor R10, and the twelfth resistor R12 may be arranged in sequence along the second direction Y. The active layer AT1 of the first transistor T1, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, the active layer AT7 of the seventh transistor T7, the active layer AT9 of the ninth transistor T9, and the active layer AT11 of the eleventh transistor T11 may be arranged in sequence along the second direction. The active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, the active layer AT6 of the sixth transistor T6, the active layer AT8 of the eighth transistor T8, the active layer AT10 of the tenth transistor T10, and the active layer AT12 of the twelfth transistor T12 may be arranged in sequence along the second direction. In the first direction X, the first resistor R1 to the twelfth resistor R12 are located on both sides of the active layers of the first transistor T1 to the twelfth transistor T2.

[0176] As Figure 12d shown, the first gate metal layer may include the gate electrodes (Tg1 to Tg12) of the first transistor T1 to the twelfth transistor T12 extending along the first direction X, the first structure VGH1 of the first voltage signal line, the second structure VGH2 of the first voltage signal line, the first structure VGL1 of the second voltage signal line, and the second structure VGL2 of the second voltage signal line. The gate electrode Tg1 of the first transistor T1 is connected to the gate electrode Tg2 of the second transistor T2, the gate electrode Tg3 of the third transistor T3 is connected to the gate electrode Tg4 of the fourth transistor T4, the gate electrode Tg5 of the fifth transistor T5 is connected to the gate electrode Tg6 of the sixth transistor T6, the gate electrode Tg7 of the seventh transistor T7 is connected to the gate electrode Tg8 of the eighth transistor T8, the gate electrode Tg9 of the ninth transistor T9 is connected to the gate electrode Tg10 of the tenth transistor T10, and the gate electrode Tg11 of the eleventh transistor T11 is connected to the gate electrode Tg12 of the twelfth transistor T12.

[0177] As Figure 12eAs shown, the connecting vias may include a first via V1 to a twenty-eighth via V28. Each resistor is provided with a first via V1 and a second via V2, and the active layer of each transistor is provided with a third via V3 and a fourth via V4; as Figure 12f and Figure 12g, the source-drain metal layer may include a detection line L0, a first voltage signal line VGH, a second voltage signal line VGL, the second poles (AL1 to AL12) of the first transistor T1 to the twelfth transistor T12, and the first connection electrodes ZL1 to the twelfth connection electrodes ZL12. The main body L01 of the detection line L0 may extend along the second direction Y. In the first direction X, the active layers of the first transistor T1 to the twentieth transistor T12 may be located on both sides of the main body of the detection line L0. The detection line L0 may be electrically connected to the active layers of the first transistor T1 to the twelfth transistor T12 through the third vias V3 in the first transistor T1 to the twelfth transistor T12, and the detection line L0 may serve as the first pole of the first transistor T1 to the twelfth transistor T12; the second pole AL1 of the first transistor T1 may be connected to the first structural part VGH1 of the first voltage signal line through the seventeenth via V17, connected to the active layer of the first transistor T1 through the fourth via V4 on the active layer AT1 of the first transistor T1, and connected to the first resistor R1 through the first via V1 on the first resistor R1. The first connection electrode ZL1 may be connected to the first resistor R1 through the second via V2 on the first resistor R1 and connected to the gate electrode Tg1 of the first transistor T1 through the fifth via V5; the second pole AL2 of the second transistor T2 may be connected to the first structural part VGH1 of the first voltage signal line through the eighteenth via V18, connected to the active layer of the second transistor T2 through the fourth via V4 on the second transistor T2, and connected to the second resistor R2 through the first via V1 on the second resistor R2. The second connection electrode ZL2 may be connected to the second resistor R2 through the second via V2 on the second resistor R2 and connected to the gate electrode Tg2 of the second transistor T2 through the sixth via V6; the second pole AL3 of the third transistor T3 may be connected to the first structural part VGL1 of the second voltage signal line through the nineteenth via V19, connected to the active layer of the third transistor T3 through the fourth via V4 on the active layer AT3 of the third transistor T3, and connected to the third resistor R3 through the first via V1 on the third resistor R3. The third connection electrode ZL3 may be connected to the third resistor R3 through the second via V2 on the third resistor R3 and connected to the gate electrode Tg3 of the third transistor T3 through the seventh via V7; the second pole AL4 of the fourth transistor T4 may be connected to the first structural part VGL1 of the second voltage signal line through the twentieth via V20, connected to the active layer of the fourth transistor T4 through the fourth via V4 on the fourth transistor T4, and connected to the fourth resistor R4 through the first via V1 on the fourth resistor R4. The fourth connection electrode ZL4 may be connected to the fourth resistor R4 through the second via V2 on the fourth resistor R4 and connected to the gate electrode Tg4 of the fourth transistor T4 through the eighth via V8;The second pole AL5 of the fifth transistor T5 can be connected to the first structural part VGL1 of the second voltage signal line through the nineteenth via V19, connected to the active layer of the fifth transistor T5 through the fourth via V4 on the active layer AT5 of the fifth transistor T5, and connected to the fifth resistor R5 through the first via V1 on the fifth resistor R5. The fifth connection electrode ZL5 can be connected to the fifth resistor R5 through the second via V2 on the fifth resistor R5 and connected to the gate electrode Tg5 of the fifth transistor T5 through the ninth via V9. The second pole AL6 of the sixth transistor T6 can be connected to the first structural part VGL1 of the second voltage signal line through the twentieth via V20, connected to the active layer of the sixth transistor T6 through the fourth via V4 on the sixth transistor T6, and connected to the sixth resistor R6 through the first via V1 on the sixth resistor R6. The sixth connection electrode ZL6 can be connected to the sixth resistor R6 through the second via V2 on the sixth resistor R6 and connected to the gate electrode Tg6 of the sixth transistor T6 through the tenth via V10. The second pole AL7 of the seventh transistor T7 can be connected to the second structural part VGH2 of the first voltage signal line through the twenty-first via V21, connected to the active layer of the seventh transistor T7 through the fourth via V4 on the active layer AT7 of the seventh transistor T7, and connected to the seventh resistor R7 through the first via V1 on the seventh resistor R7. The seventh connection electrode ZL7 can be connected to the seventh resistor R7 through the second via V2 on the seventh resistor R7 and connected to the gate electrode Tg7 of the seventh transistor T7 through the eleventh via V11. The second pole AL8 of the eighth transistor T8 can be connected to the second structural part VGH2 of the first voltage signal line through the twenty-second via V22, connected to the active layer of the eighth transistor T8 through the fourth via V4 on the eighth transistor T8, and connected to the eighth resistor R8 through the first via V1 on the eighth resistor R8. The eighth connection electrode ZL8 can be connected to the eighth resistor R8 through the second via V2 on the eighth resistor R8 and connected to the gate electrode Tg8 of the eighth transistor T8 through the twelfth via V12. The second pole AL9 of the ninth transistor T9 can be connected to the second structural part VGH2 of the first voltage signal line through the twenty-first via V21, connected to the active layer of the ninth transistor T9 through the fourth via V4 on the active layer AT9 of the ninth transistor T9, and connected to the ninth resistor R9 through the first via V1 on the ninth resistor R9. The ninth connection electrode ZL9 can be connected to the ninth resistor R9 through the second via V2 on the ninth resistor R9 and connected to the gate electrode Tg9 of the ninth transistor T9 through the thirteenth via V13;The second pole AL10 of the tenth transistor T10 can be connected to the second structure VGH2 of the first voltage signal line through the twenty-second via V22, connected to the active layer of the tenth transistor T10 through the fourth via V4 on the tenth transistor T10, and connected to the tenth resistor R10 through the first via V1 on the tenth resistor R10. The tenth connection electrode ZL10 can be connected to the tenth resistor R10 through the second via V2 on the tenth resistor R10 and connected to the gate electrode Tg10 of the tenth transistor T10 through the fourteenth via V14. The second pole AL11 of the eleventh transistor T11 can be connected to the second structure VGL2 of the second voltage signal line through the twenty-third via V23, connected to the active layer of the eleventh transistor T11 through the fourth via V4 on the active layer AT11 of the eleventh transistor T11, and connected to the eleventh resistor R11 through the first via V1 on the eleventh resistor R11. The eleventh connection electrode ZL11 can be connected to the eleventh resistor R11 through the second via V2 on the eleventh resistor R11 and connected to the gate electrode Tg11 of the eleventh transistor T11 through the fifteenth via V15. The second pole AL12 of the twelfth transistor T12 can be connected to the second structure VGL2 of the second voltage signal line through the twenty-fourth via V24, connected to the active layer of the twelfth transistor T12 through the fourth via V4 on the twelfth transistor T12, and connected to the twelfth resistor R12 through the first via V1 on the twelfth resistor R12. The twelfth connection electrode ZL12 can be connected to the twelfth resistor R12 through the second via V2 on the twelfth resistor R12 and connected to the gate electrode Tg12 of the twelfth transistor T12 through the sixteenth via V16.;

[0178] In Figure 12a and Figure 12b In the first electrostatic discharge unit shown, the static electricity in the detection line L0 can be discharged to the first voltage signal line VGH or the second voltage signal line VGL. Usually, the signal of the first voltage signal line VGH is a high-level signal, and the second voltage signal line VGL is a low-level signal. For example, the first voltage signal line VGH can be connected to the first power supply line VDD, and the second voltage signal line VGL can be connected to the second power supply line VSS.

[0179] As Figures 11a to 11h shown, Figure 11a The figure shows a schematic plan view of the first electrostatic discharge unit. Figure 11b The figure shows a schematic circuit diagram of the first electrostatic discharge unit. Figure 11c The figure shows the semiconductor layer of the first electrostatic discharge unit. Figure 11d The figure shows the schematic diagram after the first electrostatic discharge unit forms the first gate metal layer. Figure 11e The figure shows the schematic diagram after the first electrostatic discharge unit forms the second gate metal layer. Figure 11fThe figure shows a schematic diagram after forming a connection via, Figure 11g and Figure 11i The figure shows a schematic diagram after forming a source / drain metal layer, Figure 11h is Figure 11g a schematic diagram of the source / drain metal layer in; As shown in Figure 11a and Figure 11b shown, the first electrostatic discharge unit ESD1 may include a plurality of anti-static capacitors CS connected in parallel, and the plurality of anti-static capacitors CS may include a first capacitor C1 to a nineteenth capacitor C19 connected in parallel; As shown in Figure 11c shown, the semiconductor layer may include first plates (C11 to C191) of the first capacitor C1 to the nineteenth capacitor C19, as shown in Figure 11d shown, the first gate metal layer may include a first annular connection structure HL1 and a second annular connection structure HL2, the second gate metal layer may include a first detection line L1 and a second detection line L2, and the source / drain metal layer may include a third annular connection structure HL3, a detection line L0, a second power supply line VSS connection structure VSSL, and a plurality of capacitor connection structures H1. A detection line L0 may be connected to a side of the third annular connection structure HL3 close to the first border region B1.

[0180] As shown in Figures 11a to 11h shown, a portion of the first annular connection structure HL1 overlapping with the first plates of the first capacitor C1 to the eleventh capacitor C11 serves as the second plate CS2 of the first capacitor C1 to the eleventh capacitor C11. The shape of the first annular connection structure HL1 is an annular structure. Among the first plates of the first capacitor C1 to the eleventh capacitor C11, at least a portion of the first plate of each capacitor is located within the region enclosed by the inner boundary of the first annular connection structure HL1, and at least a portion of the first plate of each capacitor is located on a side of the outer boundary of the first annular connection structure HL1 away from the inner boundary of the first annular structure HL1. A portion of the second annular connection structure HL2 overlapping with the first plates of the twelfth capacitor C12 to the nineteenth capacitor C19 serves as the second plate CS2 of the twelfth capacitor C12 to the nineteenth capacitor C19. The shape of the second annular connection structure HL2 is an annular structure. Among the first plates of the twelfth capacitor C12 to the nineteenth capacitor C19, at least a portion of the first plate of each capacitor is located within the region enclosed by the inner boundary of the second annular connection structure HL2, and at least a portion of the first plate of each capacitor is located on a side of the outer boundary of the second annular connection structure HL2 away from the inner boundary of the second annular connection structure HL2. The first annular connection structure HL1 and the second annular connection structure HL2 may serve as the second plate CS2 of the anti-static capacitor CS.

[0181] As shown in Figures 11a to 11hAs shown, the shape of the third annular connection structure HL3 is an annular structure, the shape of the capacitor connection structure H1 is approximately T-shaped, the first annular connection structure HL1 and the second annular connection structure HL2 are located within the area enclosed by the inner boundary of the third annular connection structure HL3, and the first capacitor C1 to the eleventh capacitor C11 at least partially overlap with the first annular connection structure HL1 and the third annular connection structure HL3; the twelfth capacitor C12 to the nineteenth capacitor C19 at least partially overlap with the second annular connection structure HL2 and the third annular connection structure HL3; at least part of the structures of the first capacitor C1 to the eleventh capacitor C11 are located within the area enclosed by the inner boundary of the first annular connection structure HL1 and at least partially overlap with at least part of the capacitor connection structure; at least part of the structures of the twelfth capacitor C12 to the nineteenth capacitor C19 are located within the area enclosed by the inner boundary of the second annular connection structure HL2 and at least partially overlap with at least part of the capacitor connection structure; multiple capacitor connection structures H1 are connected to the third annular connection structure HL3 and are located within the area enclosed by the inner boundary of the third annular connection structure HL3; the third annular connection structure HL3 can be electrically connected to the first plates of the first capacitor C1 to the nineteenth capacitor C19 through the twenty-ninth via V29, and each capacitor connection structure H1 can be electrically connected to the first plate of one of the capacitors among the first capacitor C1 to the nineteenth capacitor C19 through the thirtieth via V30. The third annular connection structure HL3 can be connected to the first detection line L1 through the thirty-first via V31 and connected to the second detection line L2 through the thirty-second via V32. The second power supply line VSS connection structure VSSL can be connected to the first annular connection structure HL1 through the thirty-third via V33 and connected to the second annular connection structure HL2 through the thirty-fourth via V34.

[0182] As Figure 11a and Figure 11i shown, the static electricity in the first detection line L1, the second detection line L2, and the detection line L0 can be released to the second power supply line VSS connection structure VSSL, and the second power supply line VSS connection structure VSSL is connected to the second power supply line VSS, which can enable the static electricity in the first detection line L1, the second detection line L2, and the detection line L0 to be released to the second power supply line VSS; in Figure 11a the shown structure, the width of the second plates C2 of the first capacitor C1 to the nineteenth capacitor C19 is greater than Figure 11i the width of the second plates C2 of the first capacitor C1 to the nineteenth capacitor C19 in Figure 11a , that is, Figure 11i the area of the second plate CS2 of the anti-static capacitor CS in

[0183] An embodiment of the present disclosure further provides a crack detection method for detecting cracks in a display substrate, such as Figure 6 and Figure 7 As shown, the display substrate may include a display area AA and a border area BB surrounding the display area AA. The border area BB may include a detection unit PCD. The detection unit PCD includes at least a first detection line L1 and a second detection line L2. The second detection line L2 is located on a side of the first detection line L1 away from the display area AA. The first detection line L1 and the second detection line L2 are electrically connected through at least one connection structure CL. At least one of the at least one connection structure CL is a non-linear structure. The first detection line L1 at least partially surrounds the display area AA. The second detection line L2 at least partially surrounds the display area AA. The detection unit PCD is configured to detect whether a crack appears in the display substrate; the crack detection method includes:

[0184] Testing the resistance of the detection unit PCD, and determining whether a crack appears in the display substrate according to the tested resistance.

[0185] In an exemplary embodiment, in the second direction Y, the border area BB may include a first border area B1 and a second border area B2 located on both sides of the display area AA. In the first direction X, the border area BB includes a third border area B3 and a fourth border area B4 located on both sides of the display area AA. In the plane of the substrate, the first direction X intersects with the second direction Y; at least a partial structure of the first detection line L1 and the second detection line L2 extends along the third border area B3, the second border area B2, and the fourth border area B4 and surrounds the display area AA. The first detection line L1 and the second detection line L2 merge into one detection line L0 in the first border area B1. The one detection line L0 may include a first end point N1 and a second end point N2. The first end point N1 is a connection node of the first detection line L1 and the second detection line L2 and the one detection line L0 located in the third border area B3. The second end point N2 is a connection node of the first detection line L1 and the second detection line L2 and the one detection line L0 located in the fourth border area B4;

[0186] The at least one connection structure CL includes a first connection structure CL1, a second connection structure CL2, and a third connection structure CL3. The first connection structure CL1 is located in the second border area B2. The second connection structure CL2 is located in the third border area B3. The third connection structure CL3 is located in the fourth border area B4;

[0187] Testing the resistance of the detection unit PCD may include: testing the resistance between the first end point N1 and the second end point N2.

[0188] In an exemplary embodiment, two test pins can be led out from the first end point N1 and the second end point N2. The test pins can be bound and connected to the flexible printed circuit board FPC. The first test point and the second test point are led out on the flexible printed circuit board FPC. The first test point is connected to the first end point N1, and the second test point is connected to the second end point N2. The resistance between the first end point N1 and the second end point N2 is tested through the first test point and the second test point. For example, the resistance can be tested with a multimeter, or the resistance can be calculated by providing a current to test the voltage.

[0189] In an exemplary embodiment, as Figures 9a to 9c shown, the first connection structure CL1 can be located in the middle of the second border area B2, the second connection structure CL2 can be located in the middle of the third border area B3, the third connection structure CL3 can be located in the middle of the fourth border area B4. The detection unit PCD can include a first area M1, a second area M2, a third area M3, and a fourth area M4. The first area M1 is located between the first connection structure CL1 and the second connection structure CL2. The second area M2 is located between the first connection structure CL1 and the third connection structure CL3. The third area M3 is located between the second connection structure CL2 and the first border area B1. The fourth area M4 is located between the third connection structure CL3 and the first border area B1.

[0190] The method can further include: determining the position of the crack on the display substrate according to the tested resistance; the crack position can include at least one of the first area M1, the second area M2, the third area M3, and the fourth area M4.

[0191] In an exemplary embodiment, the path length of the first connection structure CL1 can be from 5 cm to 15 cm, the path length of the second connection structure CL2 can be from 50 μm to 150 μm, and the path length of the third connection structure CL3 can be from 5 cm to 15 cm. For example, the path length of the first connection structure CL1 can be 10 cm, the path length of the second connection structure CL2 can be 100 μm, and the path length of the third connection structure CL3 can be 10 cm. The first connection structure CL1, the second connection structure CL2, and the third connection structure CL3 can be used as bridge resistors. When the widths are the same, the longer the path lengths of the first connection structure CL1, the second connection structure CL2, and the third connection structure CL3, the larger the bridge resistors. By setting the sizes of the path lengths of the first connection structure CL1, the second connection structure CL2, and the third connection structure CL3 (i.e., adjusting the values of the bridge resistors), the resistance value between the first end point N1 and the second end point N2 in the case where the detection unit PCD in different areas M1 to M4 is broken can be adjusted. Thus, it can be preliminarily determined which area among the first area M1 to the fourth area M4 has a crack according to the tested resistance value between the first end point N1 and the second end point N2.

[0192] In an exemplary embodiment, a first connection structure CL1 is disposed in the middle of a second border region B2, a second connection structure CL2 is disposed in the middle of a third border region B3, and a third connection structure CL3 is disposed in the middle of a fourth border region B4. The inspection unit PCD can be divided into a first region M1, a second region M2, a third region M3, and a fourth region M4, and the crack position can be accurately detected.

[0193] In an exemplary embodiment, during the crack detection process:

[0194] When neither the first detection line L1 nor the second detection line L2 is broken, the resistance between a first end point N1 and a second end point N2 is approximately 1AKΩ (where the value of A is 5 - 10, and the value of 1AKΩ is approximately 5KΩ to 10KΩ); the resistance tested between the first end point N1 and the second end point N2 does not include the resistances of the first connection structure CL1, the second connection structure CL2, and the third connection structure CL3, and the tested resistance is relatively small;

[0195] When the second detection line L2 is broken in the second region M2, the resistance between the first end point N1 and the second end point N2 is approximately 4.5AKΩ (where the value of A is 5 - 10, and the value of 4.5AKΩ is approximately 22.5KΩ to 45KΩ); the resistance tested between the first end point N1 and the second end point N2 includes the resistances of the first connection structure CL1 and the third connection structure CL3;

[0196] When the second detection line L2 is broken in the fourth region M4, the resistance between the first end point N1 and the second end point N2 is approximately 2.8AKΩ (where the value of A is 5 - 10, and 2.8AKΩ is approximately 14KΩ to 28KΩ); the resistance tested between the first end point N1 and the second end point N2 includes the resistance of the third connection structure CL3;

[0197] When the second detection line L2 is broken in the first region M1, the resistance between the first end point N1 and the second end point N2 is approximately 3.6AKΩ (where the value of A is 5 - 10, and 3.6AKΩ is approximately 18KΩ to 36KΩ); the resistance tested between the first end point N1 and the second end point N2 includes the resistances of the first connection structure CL1 and the second connection structure CL2;

[0198] When the second detection line L2 is broken in the third region M3, the resistance between the first end point N1 and the second end point N2 is approximately 2AKΩ (where the value of A is 5 - 10, and 2AKΩ is approximately 10KΩ to 20KΩ); the resistance tested between the first end point N1 and the second end point N2 includes the resistance of the first connection structure CL1.

[0199] In an exemplary embodiment, the region where the crack is located in the first region M1, the second region M2, the third region M3, and the fourth region M4 can be preliminarily determined by detecting the resistance between the first end point N1 and the second end point N2.

[0200] In an exemplary embodiment, as Figure 6 and Figure 7 shown, the border region BB may further include at least one first electrostatic discharge unit ESD1, and at least one first electrostatic discharge unit ESD1 is electrically connected to at least one of the first detection line L1 and the second detection line L2. The first electrostatic discharge unit ESD1 may adopt a structure as Figure 11a or as Figure 12a shown.

[0201] Embodiments of the present disclosure further provide a display device, as Figure 13 shown, the display device may include: a display substrate. The display substrate may be the display substrate provided in any of the foregoing embodiments.

[0202] In an exemplary embodiment, the display device may be a liquid crystal display device (Liquid Crystal Display, abbreviated as LCD) or an organic light emitting diode (Organic Light Emitting Diode, abbreviated as OLED) or a light emitting diode (Light Emitting Diode, abbreviated as LED) display device. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an active-matrix organic light emitting diode (active-matrix organic light emitting diode, abbreviated as AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function.

[0203] The display substrate, display device, and crack detection method provided by the embodiments of the present disclosure. The display substrate includes a display area and a border area located around the display area. The border area includes a detection unit and at least one first anti-static unit. The detection unit includes at least a first detection line and a second detection line. The second detection line is located on the side of the first detection line away from the display area. The first detection line and the second detection line are electrically connected through at least one connection structure. At least one of the at least one connection structure is a non-linear structure. The first detection line at least partially surrounds the display area, and the second detection line at least partially surrounds the display area. The detection unit is configured to detect whether a crack appears on the display substrate. The first anti-static unit is electrically connected to at least one of the first detection line and the second detection line. In the technical solution provided by the embodiments of the present disclosure, the detection unit is connected to the first anti-static unit, which can reduce the risk of electrostatic injury in the detection unit. At least one of the at least one connection structure being a non-linear structure can preliminarily detect the position where a crack appears on the display substrate.

[0204] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures can refer to the general design.

[0205] Without conflict, the features in the embodiments of the present disclosure, i.e., the embodiments, can be combined with each other to obtain new embodiments.

[0206] Although the disclosed embodiments are as described above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure and is not used to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of the present disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, Comprising: A substrate, the substrate comprising a display area and a border area surrounding the display area; A detection unit located in the border area, the detection unit at least comprising a first detection line and a second detection line, the second detection line being located on a side of the first detection line away from the display area, the first detection line and the second detection line being electrically connected by at least one connection structure, at least one of the at least one connection structure being a non-linear structure, the first detection line at least partially surrounding the display area, the second detection line at least partially surrounding the display area, the detection unit being configured to detect whether cracks occur in the display substrate; At least one first anti-static unit located in the border area, the at least one first anti-static unit being electrically connected to at least one of the first detection line and the second detection line.

2. The display substrate according to claim 1, wherein In a direction from the display area towards the border area, a width dimension of the second detection line is greater than a width dimension of the first detection line.

3. The display substrate according to claim 2, wherein In a direction from the display area towards the border area, the width dimension of the second detection line is greater than or equal to 15 micrometers, and the width dimension of the first detection line is less than 15 micrometers.

4. The display substrate according to claim 1, wherein In a second direction, the border area comprises a first border area and a second border area located on two sides of the display area, and in a first direction, the border area comprises a third border area and a fourth border area located on two sides of the display area, and in a plane where the substrate is located, the first direction intersects with the second direction; At least part of the structures of the first detection line and the second detection line extend along the third border area, the second border area, and the fourth border area and surround the display area, and the first detection line and the second detection line merge into one detection line in the first border area.

5. The display substrate according to claim 4, wherein The at least one first anti-static unit is located in the first border area and is electrically connected to the first detection line and the second detection line through the one detection line.

6. The display substrate according to claim 4, wherein The border area further comprises a first corner area and a second corner area, the first border area is connected to the third border area through the first corner area, and the first border area is connected to the fourth border area through the second corner area; The number of the at least one first anti-static unit is two, and the two first anti-static units are respectively located in the first corner area and the second corner area and are electrically connected to the first detection line and the second detection line through the one detection line.

7. The display substrate according to claim 1, wherein The at least one connection structure comprises a first connection structure, a second connection structure, and a third connection structure, the first connection structure is located in the second border area, the second connection structure is located in the third border area, and the third connection structure is located in the fourth border area.

8. The display substrate according to claim 7, wherein The first connection structure is located in the middle of the second border area, the second connection structure is located in the middle of the third border area, and the third connection structure is located in the middle of the fourth border area.

9. The display substrate according to claim 7 or 8, wherein At least one of the first connection structure, the second connection structure, and the third connection structure is a broken line or a curved line structure.

10. The display substrate according to claim 9, wherein The path length of the second connection structure is less than the path lengths of the first connection structure and the third connection structure.

11. The display substrate according to claim 10, wherein The path length of the first connection structure is 5 cm to 15 cm, the path length of the second connection structure is 50 μm to 150 μm, and the path length of the third connection structure is 5 cm to 15 cm.

12. The display substrate according to claim 6, wherein The first detection line and the second detection line are bent in the first corner region and the second corner region, and chamfers are provided at the bending positions.

13. The display substrate according to claim 1, wherein The display area further includes a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes a pixel driving circuit. The pixel driving circuit includes a plurality of transistors and at least one capacitor, and the plurality of transistors includes at least one first type of transistor; In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate on one side of the substrate, and a second electrode plate on a side of the first electrode plate away from the substrate; the first type of transistor includes: an active layer, a control electrode, a first electrode, and a second electrode. The active layer of the first type of transistor is located between the first electrode plate and the substrate, the control electrode of the first type of transistor is provided on the same layer as the first electrode plate, and the first electrode and the second electrode are located on a side of the second electrode plate away from the substrate; At least part of the structures of the first detection line and the second detection line is provided on the same layer as at least one of the first electrode plate and the second electrode plate, and the at least one connection structure is provided on the same layer as the first detection line and the second detection line.

14. The display substrate according to claim 13, wherein The plurality of transistors further includes at least one second type of transistor. The second type of transistor includes: an active layer, a control electrode, a first electrode, and a second electrode. In a direction perpendicular to the plane of the substrate, the active layer of the second type of transistor is located on a side of the second electrode plate away from the substrate, the control electrode of the second type of transistor is located on a side of the active layer of the second type of transistor away from the substrate, and the first electrode and the second electrode of the second type of transistor, and the first electrode and the second electrode of the first type of transistor are located on a side of the control electrode of the second type of transistor away from the substrate; At least part of the structures of the first detection line and the second detection line is provided on the same layer as at least one of the first electrode plate, the second electrode plate, and the control electrode of the second type of transistor.

15. The display substrate according to claim 14, wherein It further includes at least one jumper wire. The at least one jumper wire includes at least one first jumper wire and at least one second jumper wire. The first jumper wire is electrically connected to the first detection line, and the second jumper wire is electrically connected to the second detection line; The first jumper wire and the second jumper wire are provided on the same layer as the first electrode and the second electrode, or the first jumper wire and the second jumper wire are located on a side of the first electrode and the second electrode away from the substrate.

16. The display substrate according to claim 15, wherein A first patch cord and a second patch cord are respectively arranged in the third border area and the fourth border area. The two first patch cords located in the third border area and the fourth border area are symmetric with respect to the first median line, and the two second patch cords located in the third border area and the fourth border area are symmetric with respect to the first median line. The first median line is the median line of the display substrate extending along the second direction.

17. The display substrate according to claim 14, characterized in that, The border area further includes a low-voltage power supply line, a first corner area, and a second corner area. At least part of the structure of the low-voltage power supply line is located in the first corner area and the second corner area. The first border area is connected to the third border area through the first corner area, and the first border area is connected to the fourth border area through the second corner area; The one detection line, the low-voltage power supply line are arranged on the same layer as the first pole and the second pole, or the one detection line, the low-voltage power supply line are located on the side of the first pole and the second pole away from the substrate; The number of the at least one first static electricity prevention unit is two. The two first static electricity prevention units are respectively located in the first corner area and the second corner area. The first static electricity prevention unit includes a plurality of static electricity prevention capacitors connected in parallel. The plurality of static electricity prevention capacitors include a first electrode plate and a second electrode plate; In the same first static electricity prevention unit: the first electrode plates of the plurality of static electricity prevention capacitors are electrically connected to the one detection line, the second electrode plates of the plurality of static electricity prevention capacitors are electrically connected to the low-voltage power supply line, the first electrode plates of the static electricity prevention capacitors are arranged on the same layer as the active layer of the first type of transistor, and the second electrode plates of the static electricity prevention capacitors are arranged on the same layer as the control electrode of the first type of transistor.

18. The display substrate according to claim 17, wherein In the same static electricity prevention unit: the second electrode plates of the plurality of static electricity prevention capacitors are in a closed ring structure, the first electrode plates of the plurality of static electricity prevention capacitors are a plurality of independent block structures, and in the closed ring structure, the width of the overlapping area with the plurality of independent block structures is greater than the width of the non-overlapping area with the plurality of independent block structures.

19. The display substrate according to claim 13 or 14, characterized in that, The first border area includes a first voltage signal line and a second voltage signal line. The one detection line, the first voltage signal line, and the second voltage signal line are arranged on the same layer as the first pole and the second pole, or the one detection line, the first voltage signal line, and the second voltage signal line are located on the side of the first pole and the second pole away from the substrate; The number of the at least one first static electricity prevention unit is two. The two first static electricity prevention units are located in the first border area. And in the first direction, one of the first static electricity prevention units is located on the side of the first border area close to the third border area, and the other first static electricity prevention unit is located on the side of the first border area close to the fourth border area.

20. A display device, characterized in that, Including the display substrate according to any one of claims 1 to 19.

21. A crack detection method, characterized in that, For detecting cracks in a display substrate, the display substrate includes a display area and a border area surrounding the display area. The border area includes a detection unit, and the detection unit at least includes a first detection line and a second detection line. The second detection line is located on a side of the first detection line away from the display area. The first detection line and the second detection line are electrically connected through at least one connection structure, and at least one of the at least one connection structure is a non-linear structure. The first detection line at least partially surrounds the display area, and the second detection line at least partially surrounds the display area. The detection unit is configured to detect whether a crack appears in the display substrate; The crack detection method includes: Testing the resistance of the detection unit, and determining whether a crack appears in the display substrate according to the tested resistance.

22. The crack test method according to claim 21, wherein, In a second direction, the border area includes a first border area and a second border area located on both sides of the display area. In a first direction, the border area includes a third border area and a fourth border area located on both sides of the display area. In the plane where the substrate is located, the first direction intersects with the second direction. At least partial structures of the first detection line and the second detection line extend along the third border area, the second border area, and the fourth border area and surround the display area. The first detection line and the second detection line merge into one detection line in the first border area. The one detection line includes a first end point and a second end point. The first end point is a connection node of the first detection line and the second detection line located in the third border area and the one detection line, and the second end point is a connection node of the first detection line and the second detection line located in the fourth border area and the one detection line; The at least one connection structure includes a first connection structure, a second connection structure, and a third connection structure. The first connection structure is located in the second border area, the second connection structure is located in the third border area, and the third connection structure is located in the fourth border area; The testing the resistance of the detection unit includes: testing the resistance between the first end point and the second end point.

23. The crack testing method according to claim 22, characterized in that, The first connection structure is located in the middle of the second border area, the second connection structure is located in the middle of the third border area, and the third connection structure is located in the middle of the fourth border area. The detection unit includes a first area, a second area, a third area, and a fourth area. The first area is located between the first connection structure and the second connection structure, the second area is located between the first connection structure and the third connection structure, the third area is located between the second connection structure and the first border area, and the fourth area is located between the third connection structure and the first border area; The method further includes: determining the position of the crack in the display substrate according to the tested resistance; the crack position includes at least one of the first area, the second area, the third area, and the fourth area.

24. The crack testing method according to any one of claims 21 to 23, characterized in that, The border area further includes at least one first anti-static unit, and the at least one first anti-static unit is electrically connected to at least one of the first detection line and the second detection line.

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