Display panel, crack detection method thereof and display device

Abstract

The invention provides a display panel, a crack detection method thereof and a display device, and relates to the technical field of display, the display panel comprises a display area and a frame area, and the frame area is provided with a crack detection line and a control circuit; the crack detection line comprises a first detection line and a second detection line, the first detection line and the second detection line are located on the two sides of the central axis of the display panel, the first end of the first detection line is electrically connected with the first output end, and the first end of the second detection line is electrically connected with the second output end; the control circuit comprises a first control unit and a second control unit. The first end of the first control unit and the first end of the second control unit are electrically connected with the same detection input end. The second end of the first control unit is electrically connected with the second end of the first detection line, the control end of the first control unit is electrically connected with the first control end, the second end of the second control unit is electrically connected with the second end of the second detection line, and the control end of the second control unit is electrically connected with the second control end.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel, a method for detecting cracks thereof, and a display device. Background Art

[0002] Currently, in organic light-emitting diode (OLED) or liquid crystal display (LCD) products, due to damage during the manufacturing process or defects in materials, such as stress caused by cutting, etc., minute cracks may be generated in the display panel. For example, micro-cracks may occur at the edge of the OLED screen.

[0003] If the micro-cracks are not detected and processed in a timely manner, the cracks will deteriorate during long-term use or reliability tests, resulting in display abnormalities or other reliability problems, causing a series of problems such as material failure and reduced service life. Summary of the Invention

[0004] The present application provides a display panel, a method for detecting cracks thereof, and a display device, which can solve the problems of display abnormalities or other reliability problems caused by micro-cracks in the existing display panel.

[0005] In a first aspect, the present application provides a display panel. The display panel includes a display area and a border area at least partially surrounding the display area. The border area is provided with a crack detection line and a control circuit;

[0006] The crack detection line includes a first detection line and a second detection line. The first detection line is located on one side of the central axis of the display panel, and the second detection line is located on the other side of the central axis. The first end of the first detection line is electrically connected to a first output terminal, and the first end of the second detection line is electrically connected to a second output terminal;

[0007] The control circuit includes a first control unit and a second control unit. The first ends of the first control unit and the second control unit are electrically connected to the same detection input terminal; the second end of the first control unit is electrically connected to the second end of the first detection line, the control end of the first control unit is electrically connected to a first control end, the second end of the second control unit is electrically connected to the second end of the second detection line, and the control end of the second control unit is electrically connected to a second control end.

[0008] Optionally, the display area is provided with a plurality of data lines. The plurality of data lines include at least one first data line and at least one second data line. The first data line and the first detection line are located on the same side of the central axis, and the second data line and the second detection line are located on the same side of the central axis;

[0009] The border area further includes a first switching circuit corresponding to each of the first data lines and a second switching circuit corresponding to each of the second data lines; a first end of the first switching circuit is electrically connected to the first output end, a second end of the first switching circuit is electrically connected to the first data line, and a control end of the first switching circuit is electrically connected to a second end of the first control unit;

[0010] A first end of the second switching circuit is electrically connected to the second output end, a second end of the second switching circuit is electrically connected to the second data line, and a control end of the second switching circuit is electrically connected to a second end of the second control unit.

[0011] Optionally, the display area is provided with a plurality of data lines, the plurality of data lines includes at least one first data line and at least one second data line, the first data line and the first detection line are on the same side of the central axis, and the second data line and the second detection line are on the same side of the central axis;

[0012] The border area further includes a first switching circuit corresponding to each of the first data lines and a second switching circuit corresponding to each of the second data lines; a first end of the first switching circuit is electrically connected to the first output end, and a second end is electrically connected to the first data line; a first end of the second switching circuit is electrically connected to the second output end, and a second end of the second switching circuit is electrically connected to the second data line;

[0013] The control circuit further includes a third control unit and a fourth control unit, a first end of the third control unit and a first end of the fourth control unit are respectively electrically connected to the detection input end; a second end of the third control unit is electrically connected to the control end of the first switching circuit, a control end of the third control unit is electrically connected to a third control end, a second end of the fourth control unit is electrically connected to the control end of the second switching circuit, and a control end of the fourth control unit is electrically connected to a fourth control end.

[0014] Optionally, the third control unit includes a third transistor, the fourth control unit includes a fourth transistor, a first pole of the third transistor and a first pole of the fourth transistor are respectively electrically connected to the detection input end;

[0015] A second pole of the third transistor is electrically connected to the control end of the first switching circuit, a control pole of the third transistor is electrically connected to the third control end, a second pole of the fourth transistor is electrically connected to the control end of the second switching circuit, and a control pole of the fourth transistor is electrically connected to the fourth control end.

[0016] Optionally, the first control unit includes a first transistor, the second control unit includes a second transistor, and a first pole of the first transistor and a first pole of the second transistor are respectively electrically connected to the detection input terminal;

[0017] A second pole of the first transistor is electrically connected to a second end of the first detection line, a control pole of the first transistor is electrically connected to the first control terminal, a second pole of the second transistor is electrically connected to a second end of the second detection line, and a control pole of the second transistor is electrically connected to the second control terminal.

[0018] Optionally, the second pole of the first transistor is further electrically connected to a control terminal of a first switch circuit, and the second pole of the second transistor is further electrically connected to a control terminal of a second switch circuit.

[0019] Optionally, the first transistor and the third transistor have the same transistor type, and / or the second transistor and the fourth transistor have the same transistor type.

[0020] Optionally, the border area includes a first area provided with a bonding area, and the control circuit, the detection input terminal, the first control terminal, and the second control terminal are respectively provided in the first area.

[0021] In a second aspect, the present application provides a display device, the display device includes a display driving circuit and a display panel as described in the first aspect, and the display driving circuit is respectively electrically connected to the detection input terminal, the first control terminal, the second control terminal, the first output terminal, and the second output terminal.

[0022] In a third aspect, the present application provides a crack detection method, characterized in that the crack detection method includes:

[0023] Inputting a first detection signal to a detection input terminal corresponding to a crack detection line in the display panel;

[0024] Receiving a second detection signal output from a detection output terminal corresponding to the crack detection line, and determining a crack detection result of the display panel according to waveform distortion information of the second detection signal.

[0025] Optionally, the inputting a first detection signal to a detection input terminal connected to a crack detection line in the display panel includes:

[0026] Inputting a first detection signal having a first level range to the detection input terminal;

[0027] The determining a crack detection result of the display panel according to waveform distortion information of the second detection signal includes:

[0028] Determine the crack detection result according to the rising time and / or falling time of the first level interval in the second detection signal; wherein, the waveform distortion information includes the rising time and / or falling time of the first level interval.

[0029] Optionally, the inputting the first detection signal to the detection input terminal connected to the crack detection line in the display panel includes:

[0030] Input a digital code to the detection input terminal as the first detection signal;

[0031] The determining the crack detection result of the display panel according to the waveform distortion information of the second detection signal includes:

[0032] Use the deviation between the coding information corresponding to the second detection signal and the digital code as the waveform distortion information, and determine the crack detection result according to the waveform distortion information.

[0033] Optionally, the receiving the second detection signal output from the detection output terminal corresponding to the crack detection line and determining the crack detection result of the display panel according to the waveform distortion information of the second detection signal includes:

[0034] Input the second detection signal output from the first output terminal of the display panel and the second detection signal output from the second output terminal of the display panel into an adder;

[0035] Determine the crack detection result of the display panel according to the output result of the adder.

[0036] Optionally, the inputting the first detection signal to the detection input terminal connected to the crack detection line in the display panel includes:

[0037] Within at least one target detection period, input the first detection signal with multiple target level intervals to the detection input terminal; wherein, the target level interval is the first level interval, or the target level interval is the level interval corresponding to the target coding value, and the digital code includes the target coding value;

[0038] The crack detection method further includes:

[0039] Within the target detection period, input a first control signal to the first control terminal of the display panel and input a second control signal to the second control terminal of the display panel; wherein, within the target detection period, the effective level interval of the first control signal at least partially coincides with one of the target level intervals of the first detection signal in time sequence, and the effective level interval of the second control signal at least partially coincides with one of the target level intervals of the first detection signal in time sequence.

[0040] Optionally, the crack detection method further includes:

[0041] During the target detection period, a third control signal is input to the third control terminal of the display panel, and a fourth control signal is input to the fourth control terminal of the display panel; wherein, during the target detection period, the effective level interval of the third control signal at least partially overlaps in time sequence with one of the target level intervals of the first detection signal, and the effective level interval of the fourth control signal at least partially overlaps in time sequence with one of the target level intervals of the first detection signal.

[0042] A display panel, a crack detection method thereof, and a display device provided by the present application have at least the following advantages: By inputting a first detection signal to the detection input terminal corresponding to the crack detection line in the display panel, receiving a second detection signal output from the detection output terminal corresponding to the crack detection line, and determining the crack detection result of the display panel according to the waveform distortion information of the second detection signal. In this way, the micro-cracks of the display panel can be visually identified according to the waveform distortion of the second detection signal, and it can be determined whether there are micro-cracks in the display panel. By detecting and processing the micro-cracks in time, the abnormal phenomena of the display panel can be reduced, the reliability of the display panel can be improved, and problems such as material failure and reduced service life can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1 is one of the structural schematic diagrams of a display panel provided by an embodiment of the present application;

[0045] Figure 2 is one of the structural schematic diagrams of a display device provided by an embodiment of the present application;

[0046] Figure 3 is the second structural schematic diagram of a display device provided by an embodiment of the present application;

[0047] Figure 4 is the third structural schematic diagram of a display device provided by an embodiment of the present application;

[0048] Figure 5 is the structural schematic diagram of a display panel in the related art;

[0049] Figure 6It is a schematic diagram of the steps of a crack detection method provided by an embodiment of the present application;

[0050] Figure 7 It is one of the waveform schematic diagrams of a crack detection method provided by an embodiment of the present application;

[0051] Figure 8 It is the second waveform schematic diagram of a crack detection method provided by an embodiment of the present application;

[0052] Figure 9 It is the third waveform schematic diagram of a crack detection method provided by an embodiment of the present application;

[0053] Figure 10 It is the fourth waveform schematic diagram of a crack detection method provided by an embodiment of the present application;

[0054] Figure 11 It is the fifth waveform schematic diagram of a crack detection method provided by an embodiment of the present application;

[0055] Figure 12 It is the sixth waveform schematic diagram of a crack detection method provided by an embodiment of the present application;

[0056] Figure 13 It is a schematic diagram of the verification principle of an adder provided by an embodiment of the present application;

[0057] Figure 14 It is the circuit schematic diagram of a half adder provided by an embodiment of the present application;

[0058] Figure 15 It is the circuit schematic diagram of a full adder provided by an embodiment of the present application. Detailed implementation manners

[0059] Next, the technical solutions in some embodiments will be clearly and completely described in conjunction with the accompanying drawings in some embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0060] In some embodiments, multiple signals have a first level and a second level. The first level and the second level only represent that the level of the signal has two states, and do not represent that the first level or the second level has a specific value.

[0061] The transistors employed in the display panel of some embodiments may be thin film transistors (TFTs) or metal oxide semiconductor (MOS) field effect transistors. For example, they may be N-channel TFTs or P-channel TFTs, and the embodiments of the present application are not limited thereto.

[0062] Figure 1 is one of the schematic structural diagrams of a display panel provided by the embodiments of the present application. As Figure 1 shown, the display panel includes a display area and a border area at least partially surrounding the display area. The border area is provided with a crack detection line 10 and a control circuit 20;

[0063] The crack detection line 10 includes a first detection line 101 and a second detection line 102. The first detection line 101 is located on one side of the central axis of the display panel, and the second detection line 102 is located on the other side of the central axis. The first end of the first detection line 101 is electrically connected to a first output terminal, and the first end of the second detection line 102 is electrically connected to a second output terminal;

[0064] The control circuit 20 includes a first control unit 201 and a second control unit 202. The first ends of the first control unit 201 and the second control unit 202 are electrically connected to the same detection input terminal; the second end of the first control unit 201 is electrically connected to the second end of the first detection line 101, the control end of the first control unit 201 is electrically connected to a first control end, the second end of the second control unit 202 is electrically connected to the second end of the second detection line 102, and the control end of the second control unit 202 is electrically connected to a second control end.

[0065] In some embodiments, the display panel may be an organic light-emitting diode (OLED) panel or a liquid crystal display (LCD) panel. The display panel includes a display area and a border area. The border area at least includes a first area provided with a bonding area for bonding the display driving circuit of the display panel, such as a display driver integrated circuit (DDIC).

[0066] In some embodiments, the crack detection line 10 includes a first end and a second end. The first end and the second end are provided in other border areas close to the first area, or the first end and the second end are provided in the first area. As Figure 1As shown, the extending direction of the central axis is parallel to the first direction, and the first direction may be the extending direction of the data line. The central axis passes through the display area and the border area below the display area, i.e., the first area, and the first detection line 101 and the second detection line 102 are located on the left and right sides of the central axis.

[0067] In some embodiments, the border area further includes a second area disposed opposite to the first area, and third and fourth areas that connect the first area and the second area and are disposed opposite to each other. As Figure 1 shown, the first detection line 101 on the left side of the central axis is distributed in the first area, the second area, and the third area, and the second detection line 102 on the right side is distributed in the first area, the second area, and the fourth area.

[0068] In some embodiments, a detection input end and a detection output end are provided in the border area. The first end of the crack detection line 10 is electrically connected to the detection output end, and the second end of the crack detection line 10 is electrically connected to the detection input end. The detection input end can receive a crack detection signal such as a first detection signal, and the detection output end is used to output a detection signal corresponding to the crack detection result, such as a second detection signal. The detection input end (PCDE / PCD1 / PCD2 / PCD_ALL) can be electrically connected to the test pins of the display driving circuit, such as the pins used in Cell test and MDL test in the DDIC.

[0069] In some embodiments, the detection output end includes a first output end and a second output end. The first output end corresponds to the first detection line 101, and the first end of the first detection line 101 is electrically connected to the first output end. The second output end corresponds to the second detection line 102, and the first end of the second detection line 102 is electrically connected to the second output end. The first output end (PCDL) and the second output end (PCDR) can be electrically connected to the test pins of the display driving circuit, such as the pins that can test the waveforms TR / TF in the DDIC, where TR represents the rise time and TF represents the fall time.

[0070] In some embodiments, the detection input end and the detection output end can also be electrically connected to the test terminals of the test fixture. The test fixture needs to have the ability to output and receive waveforms, as well as the ability to judge resistance and identify high and low levels.

[0071] In some embodiments, a control circuit 20 is provided between the second end of the crack detection line 10 and the detection input end. The control circuit 20 is used to control the on / off between the second end of the crack detection line 10 and the detection input end. As Figure 1As shown, a first control unit 201 is provided between the second end of the first detection line 101 and the detection input terminal, and a second control unit 202 is provided between the second end of the second detection line 102 and the detection input terminal. The control circuit 20 corresponding control terminals are also provided in the border area of the display panel, including a first control terminal and a second control terminal. The first control terminal and the second control terminal can be electrically connected to the control output terminals of the display driving circuit, receive the control signals sent by the display driving circuit, and respectively control the on and off between the first detection line 101 and the second detection line 102 and the detection input terminal under the action of the control signals. Among them, the control output terminals of the display driving circuit, such as the output Pins in the DDIC, can output control signals.

[0072] Specifically, the first end of the first control unit 201 is electrically connected to the detection input terminal, the second end of the first control unit 201 is electrically connected to the second end of the first detection line 101, and the control terminal of the first control unit 201 is electrically connected to the first control terminal. When the first control unit 201 conducts the first end and the second end under the action of the first control signal input at the first control terminal, the second end of the first detection line 101 is conducted with the detection input terminal, and the crack detection signal input from the detection input terminal, such as the first detection signal, can be transmitted to the first detection line 101.

[0073] Similarly, the first end of the second control unit 202 is also electrically connected to the detection input terminal, the second end of the second control unit 202 is electrically connected to the second end of the second detection line 102, the control terminal of the second control unit 202 is electrically connected to the second control terminal, and the second control unit 202 can control the second detection line 102 to be conducted with the detection input terminal, so that the first detection signal is transmitted to the second detection line 102.

[0074] In some embodiments, the first ends of the first control unit 201 and the second control unit 202 are electrically connected to the same detection input terminal. In this way, only one crack detection signal needs to be input to one detection input terminal, which can reduce the area occupied by the detection input terminal in the border area. For example, the bonding Pitch (dot pitch) between the first area and the middle bonding area can be increased, the process requirements can be reduced, and the process fluctuation redundancy can be improved.

[0075] In the embodiments of the present application, by providing the first control unit 201 between the first detection line 101 and the detection input terminal, and by providing the second control unit 202 between the second detection line 102 and the detection input terminal, the on and off between the detection input terminal and the first detection line 101 and the second detection line 102 can be respectively controlled by the first control unit 201 and the second control unit 202, so that the crack detection signals transmitted from the detection input terminal to the first detection line 101 and the second detection line 102 are more flexible in timing, and the control flexibility of crack detection of the display panel is improved.

[0076] Optionally, the first control unit 201 includes a first transistor, and the second control unit 202 includes a second transistor. A first pole of the first transistor and a first pole of the second transistor are respectively electrically connected to the detection input terminal;

[0077] A second pole of the first transistor is electrically connected to a second end of the first detection line 101, a control pole of the first transistor is electrically connected to a first control terminal, a second pole of the second transistor is electrically connected to a second end of the second detection line 102, and a control pole of the second transistor is electrically connected to a second control terminal.

[0078] In some embodiments, the first pole of the first transistor serves as a first end of the first control unit 201, the second pole of the first transistor serves as a second end of the first control unit 201, and the control pole of the first transistor serves as a control terminal of the first control unit 201. The first pole of the first transistor is electrically connected to the detection input terminal, the second pole of the first transistor is electrically connected to the second end of the first detection line 101, and the control pole of the first transistor is electrically connected to the first control terminal.

[0079] In some embodiments, the first pole of the second transistor serves as a first end of the second control unit 202, the second pole of the second transistor serves as a second end of the second control unit 202, and the control pole of the second transistor serves as a control terminal of the second control unit 202. The first pole of the second transistor is electrically connected to the detection input terminal, the second pole of the second transistor is electrically connected to the second end of the second detection line 102, and the control pole of the second transistor is electrically connected to the second control terminal.

[0080] In the embodiments of the present application, the first transistor controls the on / off between the second end of the first detection line 101 and the detection input terminal, and the second transistor controls the on / off between the second end of the second detection line 102 and the detection input terminal, so that the control circuit 20 has a simple structure, reduces the area occupied by the border area of the display panel, and is beneficial to the display panel to achieve a narrow border. Among them, the first transistor and the second transistor can be TFTs or MOS transistors, and the transistor types of the first transistor and the second transistor can be the same or different, that is, the first transistor and the second transistor can be N-type or P-type. This is only an example here, and the embodiments of the present application do not limit this.

[0081] Optionally, a plurality of data lines are provided in the display area. The plurality of data lines include at least one first data line 301 and at least one second data line 302. The first data line 301 and the first detection line 101 are on the same side of the central axis, and the second data line 302 and the second detection line 102 are on the same side of the central axis;

[0082] The border area further includes a first switching circuit 401 corresponding to the first data line 301 one by one, and a second switching circuit 402 corresponding to the second data line 302 one by one; a first end of the first switching circuit 401 is electrically connected to the first output end, a second end of the first switching circuit 401 is electrically connected to the first data line 301, and a control end of the first switching circuit 401 is electrically connected to a second end of the first control unit 201;

[0083] A first end of the second switching circuit 402 is electrically connected to the second output end, a second end of the second switching circuit 402 is electrically connected to the second data line 302, and a control end of the second switching circuit 402 is electrically connected to a second end of the second control unit 202.

[0084] In some embodiments, the data lines extend in a first direction, and multiple data lines are arranged in a second direction perpendicular to the first direction. Among the multiple data lines, the data lines arranged on the same side as the first detection line 101 are called first data lines 301, and the data lines arranged on the same side as the second detection line 102 are called second detection lines 102. One side of the central axis may include one or more first data lines 301, and the other side of the central axis may include one or more second data lines 302.

[0085] In some embodiments, a switching circuit corresponding to the data line is provided in the border area. For example, the switching circuit is provided in a first area of the border area including the bonding area and is disposed close to the display area for electrical connection with the data line. The switching circuit is used to control the on / off of the data line and the detection output end, and the switching circuit may include a transistor, such as a TFT or a MOS transistor.

[0086] In some embodiments, the first switching circuit 401 corresponding to the first data line 301 is provided in the first area. The first data line 301 and its first switching circuit 401 are located on the same side of the central axis, and the first switching circuit 401 is disposed close to the first data line 301 in the display area. Similarly, the second switching circuit 402 corresponding to the second data line 302 is provided in the first area, and the second data line 302 and its second switching circuit 402 are located on the same side of the central axis, and the second switching circuit 402 is disposed close to the second data line 302 in the display area.

[0087] Figure 2 is one of the schematic structural diagrams of a display device provided by an embodiment of the present application, such as Figure 2As shown, the display device includes a display panel and a display driving circuit, and the display driving circuit is a DDIC. The display panel includes a display area and a border area surrounding the display area. The peripheral traces on the left and right sides of the display area are crack detection lines 10, including a first detection line 101 on the left side of the central axis and a second detection line 102 on the right side of the central axis. The display area includes a first data line 301 on the left side of the central axis and a second data line 302 on the right side of the central axis. The first data line 301 and the second data line 302 are respectively electrically connected to a P-type transistor, and the P-type transistor is a switching circuit corresponding to the data line.

[0088] As Figure 2 shown, a control circuit 20 is provided in a first area of the border area close to the DDIC side. The control circuit 20 includes a first transistor (Mux1) and a second transistor (Mux2). The first poles of the first transistor and the second transistor are respectively electrically connected to a detection input terminal (PCD_ALL_1). The second pole of the first transistor is electrically connected to the second end of the first detection line 101, and the second pole of the second transistor is electrically connected to the second end of the second detection line 102.

[0089] As Figure 2 shown, a detection input terminal (PCD_ALL_1) is also provided in the border area. PCD_ALL_1 can be electrically connected to a Pin used in Cell test or a Pin used in MDL test in the DDIC, etc. A first output terminal (PCDL) and a second output terminal (PCDR) are also provided in the border area. PCDL and PCDR can be electrically connected to a Pin in the DDIC that can test waveforms TR / TF. The control poles of the first transistor (Mux1) and the second transistor (Mux2) can be respectively electrically connected to an output Pin in the DDIC that can output a control signal. Figure 2 In, the control pole of the first transistor can be used as a first control terminal, and the control pole of the second transistor can be used as a second control terminal. The first control terminal and the second control terminal can be electrically connected to an output Pin in the DDIC that can output a control signal.

[0090] As Figure 2As shown, a switch control terminal (SW) is also provided in the border area, including an SWL terminal on the left side of the central axis and an SWR terminal on the right side of the central axis. The control terminal of the first switch circuit 401 can be electrically connected to the SWL terminal, and the control terminal of the second switch circuit 402 can be electrically connected to the SWR terminal. Among them, the first switch circuit 401 can include a transistor electrically connected to the first data line 301 on the left side of the central axis, and the second switch circuit 402 can include a transistor connected to the second data line 302 on the right side of the central axis. The SWL terminal and the SWR terminal can be respectively electrically connected to the output Pins in the DDIC that can output control signals. For example, the SWL terminal and the SWR terminal are respectively the output Pins of the left / right source swap unit. By sending switch control signals to the SWL terminal and the SWR terminal respectively, the opening or closing of the first switch circuit 401 and the second switch circuit 402 can be controlled.

[0091] In some embodiments, the control terminal of the first switch circuit 401 can be electrically connected to the second terminal of the first control unit 201, and the control terminal of the second switch circuit 402 can be electrically connected to the second terminal of the second control unit 202. In this way, the crack detection signal input from the detection input terminal can control the first switch circuit 401 and the second switch circuit 402 to turn on, where the crack detection signal needs to include the effective levels corresponding to the first switch circuit 401 and the second switch circuit 402 respectively.

[0092] Optionally, the second pole of the first transistor is also electrically connected to the control terminal of the first switch circuit 401, and the second pole of the second transistor is also electrically connected to the control terminal of the second switch circuit 402.

[0093] In some embodiments, the second pole of the first transistor is used as the second terminal of the first control unit 201 and is electrically connected to the control terminal of the first switch circuit 401. When the first transistor is turned on, the crack detection signal input from the detection input terminal can be transmitted to the control terminal of the first switch circuit 401, and then the first data line 301 and the first output terminal are turned on. Similarly, the second pole of the second transistor is used as the second terminal of the second control unit 202 and is electrically connected to the control terminal of the second switch circuit 402. When the second transistor is turned on, the crack detection signal can control the on / off of the second data line 302 and the second output terminal.

[0094] Figure 3 is the second structural schematic diagram of a display device provided by an embodiment of the present application. As Figure 3 shown, the control terminal of the first switch circuit 401 is electrically connected to the SWL terminal, and the control terminal of the second switch circuit 402 is electrically connected to the SWR terminal. The difference from the Figure 2 display device shown is that the SWL terminal and the SWR terminal are not directly electrically connected to the DDIC. Figure 3The SWL terminal is electrically connected to the second pole of the first transistor, and the SWR terminal is electrically connected to the second pole of the second transistor. In addition, the detection input terminal is marked as (PCD_ALL_2). In this way, the number of Pinouts of the DDIC connected to the display panel can be reduced. When the area of the bonding region is fixed, the bonding pitch can be increased, the process requirements can be reduced, and the process fluctuation redundancy can be improved.

[0095] Optionally, a plurality of data lines are provided in the display area. The plurality of data lines include at least one first data line 301 and at least one second data line 302. The first data line 301 and the first detection line 101 are on the same side of the central axis, and the second data line 302 and the second detection line 102 are on the same side of the central axis.

[0096] The border area further includes a first switch circuit 401 corresponding to the first data line 301 one by one, and a second switch circuit 402 corresponding to the second data line 302 one by one. The first end of the first switch circuit 401 is electrically connected to the first output end, and the second end is electrically connected to the first data line 301. The first end of the second switch circuit 402 is electrically connected to the second output end, and the second end of the second switch circuit 402 is electrically connected to the second data line 302.

[0097] The control circuit 20 further includes a third control unit 203 and a fourth control unit 204. The first ends of the third control unit 203 and the fourth control unit 204 are respectively electrically connected to the detection input terminal. The second end of the third control unit 203 is electrically connected to the control end of the first switch circuit 401, the control end of the third control unit 203 is electrically connected to the third control end, the second end of the fourth control unit 204 is electrically connected to the control end of the second switch circuit 402, and the control end of the fourth control unit 204 is electrically connected to the fourth control end.

[0098] In some embodiments, a corresponding control unit may be provided for the switch circuit corresponding to the data line to control the opening or closing of the switch unit by the control unit. Specifically, the control circuit 20 includes a third control unit 203 corresponding to the first switch circuit 401 and a fourth control unit 204 corresponding to the second switch circuit 402. The third control unit 203 is disposed between the control end of the first switch circuit 401 and the detection input terminal, and the fourth control unit 204 is disposed between the control end of the second switch circuit 402 and the detection input terminal. The third control unit 203 and the fourth control unit 204 are located in the border area, and the third control unit 203 and the fourth control unit 204 may be in the same border area as the first control unit 201 and the second control unit 202. For example, the third control unit 203 and the fourth control unit 204 are located in the first area of the border area including the bonding area.

[0099] In some embodiments, the control terminals corresponding to the control circuit 20 further include a third control terminal and a fourth control terminal. The third control terminal and the fourth control terminal can be electrically connected to the control output terminals of the display driving circuit, receive the control signals sent by the display driving circuit, and respectively control the on / off of the control terminal of the first switching circuit 401, the control terminal of the second switching circuit 402 and the detection input terminal under the action of the control signals. Among them, the control output terminals of the display driving circuit, for example, the output Pins that can output control signals in the DDIC.

[0100] Specifically, the first end of the third control unit 203 is electrically connected to the detection input terminal, the second end of the third control unit 203 is electrically connected to the control terminal of the first switching circuit 401, and the control terminal of the third control unit 203 is electrically connected to the third control terminal. The first end of the fourth control unit 204 is electrically connected to the detection input terminal, the second end of the fourth control unit 204 is electrically connected to the control terminal of the second switching circuit 402, and the control terminal of the fourth control unit 204 is electrically connected to the fourth control terminal.

[0101] In the embodiments of the present application, by providing the third control unit 203 between the control terminal of the first switching circuit 401 and the detection input terminal, and by providing the fourth control unit 204 between the control terminal of the second switching circuit 402 and the detection input terminal, the first switching circuit 401 and the second switching circuit 402 can be respectively controlled to be turned on or off by the third control unit 203 and the fourth control unit 204, which is equivalent to the superposition control of the first control unit 201 and the third control circuit 20, and the superposition control of the second control unit 202 and the fourth control unit 204, making the overall control mode of the control circuit 20 more flexible and further improving the control flexibility for crack detection of the display panel.

[0102] Optionally, the third control unit 203 includes a third transistor, and the fourth control unit 204 includes a fourth transistor. The first poles of the third transistor and the fourth transistor are respectively electrically connected to the detection input terminal;

[0103] The second pole of the third transistor is electrically connected to the control terminal of the first switching circuit 401, the control pole of the third transistor is electrically connected to the third control terminal, the second pole of the fourth transistor is electrically connected to the control terminal of the second switching circuit 402, and the control pole of the fourth transistor is electrically connected to the fourth control terminal.

[0104] In some embodiments, the first pole of the third transistor serves as the first end of the third control unit 203, the second pole of the third transistor serves as the second end of the third control unit 203, and the control pole of the third transistor serves as the control terminal of the third control unit 203. The first pole of the third transistor is electrically connected to the detection input terminal, the second pole of the third transistor is electrically connected to the control terminal of the first switching circuit 401, and the control pole of the third transistor is electrically connected to the third control terminal.

[0105] In some embodiments, the first pole of the fourth transistor serves as the first end of the fourth control unit 204, the second pole of the fourth transistor serves as the second end of the fourth control unit 204, and the control pole of the fourth transistor serves as the control end of the fourth control unit 204. The first pole of the fourth transistor is electrically connected to the detection input terminal, the second pole of the fourth transistor is electrically connected to the control end of the second switch circuit 402, and the control pole of the fourth transistor is electrically connected to the fourth control end.

[0106] In the embodiments of the present application, the third transistor controls the on / off between the control end of the first switch circuit 401 and the detection input terminal, and the fourth transistor controls the on / off between the control end of the second switch circuit 402 and the detection input terminal, so that the control circuit 20 has a simple structure, reduces the area occupied by the border area of the display panel, and is beneficial to the display panel to achieve a narrow border. Among them, the third transistor and the fourth transistor can be TFTs or MOS transistors, and the transistor types of the third transistor and the fourth transistor can be the same or different, that is, the third transistor and the fourth transistor can be N-type or P-type. This is only an example here, and the embodiments of the present application do not limit this.

[0107] Figure 4 is the third schematic diagram of the structure of a display device provided by the embodiments of the present application, as Figure 4 shown, different from the display device shown in Figure 2 or Figure 3 is that the control circuit 20 further includes a third transistor (Mux3) and a fourth transistor (Mux4). The first poles of the third transistor and the fourth transistor are respectively electrically connected to the detection input terminal (PCD_ALL_3), the second pole of the third transistor is electrically connected to the SWL terminal, and then electrically connected to the control end of the first switch circuit 401, and the second pole of the fourth transistor is electrically connected to the SWR terminal, and then electrically connected to the control end of the second switch circuit 402. Figure 4 In this case, the control pole of the third transistor can serve as the third control end, the control pole of the fourth transistor can serve as the fourth control end, and the third control end and the fourth control end can be electrically connected to the output Pin in the DDIC that can output control signals.

[0108] Optionally, the transistor types of the first transistor and the third transistor are the same, and / or the transistor types of the second transistor and the fourth transistor are the same.

[0109] In some embodiments, the first transistor and the third transistor jointly act on the control of the first data line 301 and the first detection line 101 arranged on the same side. Therefore, the first transistor and the second transistor can adopt the same type of transistor, such as both N-type transistors or both P-type transistors. The control electrodes of the first transistor and the second transistor can be electrically connected to the same control output terminal in the display driving circuit, such as the DDIC. In this way, the number of Pinouts of the DDIC connected to the display panel can be reduced. When the area of the bonding region is fixed, the bonding pitch can be increased, the process requirements can be reduced, and the process fluctuation redundancy can be improved.

[0110] Alternatively, although the control electrodes of the first transistor and the second transistor are electrically connected to different control output terminals, control signals with the same effective level can also be sent to the control electrodes of the first transistor and the second transistor during the crack detection process. Since the transistor types of the first transistor and the second transistor are the same, the corresponding effective levels are also the same, such as both being high-level effective or both being low-level effective. In this way, the control logic of the crack detection process can be simplified and the control difficulty can be reduced.

[0111] Similarly, the second transistor and the fourth transistor jointly act on the control of the second data line 302 and the second detection line 102 arranged on the same side. The second transistor and the fourth transistor can adopt the same type of transistor, such as both N-type transistors or both P-type transistors. The control output terminals to which the second transistor and the fourth transistor are electrically connected to the display driving circuit are similar to those of the first transistor and the third transistor, and will not be elaborated here.

[0112] Optionally, the border region includes a first region provided with a bonding region, and the control circuit 20, the detection input terminal, the first control terminal, and the second control terminal are respectively arranged in the first region.

[0113] In some embodiments, the bonding region in the first region can bond the display driving circuit of the display panel, such as the DDIC. The first end and the second end of the crack detection line 10 can be arranged in the first region. As Figures 2 - 4 shown, the first end and the second end of each of the first detection line 101 and the second detection line 102 are located in the first region, and the first end and the second end of the first detection line 101 are located on the left side of the central axis, and the first end and the second end of the second detection line 102 are located on the right side of the central axis.

[0114] Among them, the first end of the first detection line 101 can be used as the first output end. If the first end of the first detection line 101 is arranged in the first area, the first output end is arranged in the first area. Similarly, the first end of the second detection line 102 can be used as the second output end. If the first end of the second detection line 102 is arranged in the first area, the second output end is arranged in the first area. Here is only an example, and the embodiments of the present application do not limit this.

[0115] In some embodiments, taking Figure 4 as an example, the control circuit 20 is arranged in the first area. The control circuit 20 includes a first transistor (Mux1), a second transistor (Mux2), a third transistor (Mux3), and a fourth transistor (Mux4). As Figure 4 shown, the detection input terminal (PCD_ALL_3), the first control terminal, i.e., the control electrode of the first transistor, and the second control terminal, i.e., the control electrode of the second transistor, are also arranged in the first area. In addition, the third control terminal, i.e., the control electrode of the third transistor, and the fourth control terminal, i.e., the control electrode of the fourth transistor, are also arranged in the first area.

[0116] In some embodiments, the data lines extend along a first direction parallel to the central axis. The display area includes a plurality of first data lines 301 and a plurality of second data lines 302. Then, a plurality of first switching circuits 401 corresponding to the plurality of first data lines 301 and a plurality of second switching circuits 402 corresponding to the plurality of second data lines 302 are arranged in the border area. The number of the plurality of first data lines 301 and the number of the plurality of second data lines 302 may be the same or different, and the first switching circuits 401 are in one-to-one correspondence with the first data lines 301, and the second switching circuits 402 are in one-to-one correspondence with the second data lines 302.

[0117] In some embodiments, the plurality of first switching circuits 401 and the plurality of second switching circuits 402 are located in the first area. The plurality of first switching circuits 401 and the plurality of second switching circuits 402 may be arranged along a second direction, and the second direction is perpendicular to the first direction. In addition, the central axis penetrates the first area. The plurality of first switching circuits 401 may be on the same side of the central axis as the plurality of first data lines 301, and the plurality of second switching circuits 402 may be on the same side of the central axis as the plurality of second data lines 302.

[0118] In some embodiments, when multiple first data lines 301 and multiple second data lines 302 are provided in the display area, in order to accurately determine which data line has a micro crack, corresponding third control units 203 may be provided for the multiple first data lines 301 respectively, and corresponding fourth control units 204 may be provided for the multiple second data lines 302 respectively. The control circuit 20 includes these third control units 203 and fourth control units 204. Referring to the relevant descriptions of the third control unit 203 and the fourth control unit 204 in the foregoing embodiments, for example, the first ends of these third control units 203 and fourth control units 204 may be electrically connected to the same detection input terminal, and these third control units 203 and fourth control units 204 may be provided in the first area together, which will not be elaborated here.

[0119] In some embodiments, during the crack detection process, a third control unit 203 may be controlled individually to perform a targeted test on the first data line 301 corresponding to the third control unit 203. Similarly, a fourth control circuit 20 may be controlled individually to perform a targeted test on the second data line 302 corresponding to the fourth control unit 204. In this way, the crack detection result output by the detection output terminal may be used as a feedback signal, such as the second detection signal as the feedback signal, so as to accurately determine the position of the Data NG line through the feedback signal, that is, determine which data line has a micro crack, and then perform compensation (repair) on the Data NG line to improve the production cycle and yield.

[0120] An embodiment of the present application further provides a display device, which includes a display driving circuit and a display panel as described in the foregoing embodiments. The display driving circuit is electrically connected to the detection input terminal, the first control terminal, the second control terminal, the first output terminal, and the second output terminal respectively.

[0121] In some embodiments, the display driving circuit is, for example, a DDIC. The DDIC includes pins for Cell test, pins for MDL test, pins for testing waveforms TR / TF, and output pins for outputting control signals, etc. The detection input terminal may be electrically connected to the pins for Cell test or the pins for MDL test in the DDIC. The first output terminal (PCDL) and the second output terminal (PCDR) may be electrically connected to the pins for testing waveforms TR / TF in the DDIC. The first control terminal and the second control terminal may be electrically connected to the output pins for outputting control signals in the DDIC.

[0122] In some embodiments, the third control terminal and the fourth control terminal may also be electrically connected to the output pins in the DDIC that can output control signals. The switch control terminals (SW), such as the SWL terminal and the SWR terminal, corresponding to the first switch circuit 401 and the second switch circuit 402 may also be electrically connected to the output pins in the DDIC that can output control signals. Alternatively, the SWL terminal and the SWR terminal are not directly electrically connected to the DDIC. For example, Figure 3 the SWL terminal is electrically connected to the second pole of the first transistor, and the SWR terminal is electrically connected to the second pole of the second transistor. This is only an example, and the embodiments of the present application are not limited thereto.

[0123] The embodiments of the present application further provide another display device. The display device includes a display panel and a driving circuit board bound to the display panel. The display panel may be, for example, Figure 5 the display panel as shown. The control circuit 20 and the display driving circuit may be provided on the driving circuit board. In this way, the area occupied by the control circuit 20 in the border area of the display panel can be reduced, which is beneficial to the display panel to achieve a narrow border. The crack detection of the display panel can be completed through the control circuit 20 and the display driving circuit on the driving circuit board to complete the crack detection logic control.

[0124] Figure 6 is a schematic diagram of the steps of a crack detection method provided by the embodiments of the present application. As Figure 6 shown, the crack detection method includes:

[0125] Step S1, input a first detection signal to the detection input terminal corresponding to the crack detection line in the display panel.

[0126] Step S2, receive the second detection signal output from the detection output terminal corresponding to the crack detection line, and determine the crack detection result of the display panel according to the waveform distortion information of the second detection signal.

[0127] In some embodiments, this crack detection method can perform crack detection on the display panel in this embodiment. For example, Figures 1 - 4 for the display panel in, the detection input terminals corresponding to the crack detection line 10 may be PCD_ALL_1, PCD_ALL_2 or PCD_ALL_3, and the detection output terminals corresponding to the crack detection line 10 include Figures 1 - 4 PCDL and PCDR in.

[0128] Alternatively, this crack detection method can also perform crack detection on the display panel as Figure 5 shown. Then Figure 5 for the left crack detection line 10 in, the detection input terminal may be the left PCDE or PCD1, and for the right crack detection line 10, the detection input terminal may be the right PCDE or PCD2. Figure 5The detection output ends corresponding to the middle crack detection line 10 include PCDL and PCDR.

[0129] In some embodiments, the first detection signal is input into the crack detection line 10 as a crack detection signal through the detection input end. If there is no micro crack in the distribution area of the crack detection line 10, the signal waveform of the second detection signal output from the detection output end should be almost the same as the signal waveform of the first detection signal. If there is an obvious waveform distortion in the second detection signal, resulting in a large difference between the waveform of the second detection signal and the first detection signal, it indicates that there is a micro crack in the distribution area of the crack detection line 10. In this way, it is possible to determine whether there is a micro crack in the display panel according to the waveform distortion information of the second detection signal, that is, to obtain the crack detection result of the display panel.

[0130] Among them, the waveform distortion information of the second detection signal may refer to whether there is an obvious waveform distortion phenomenon in the second detection signal compared with the first detection signal. For example, the increase of the waveform TR / TF leads to abnormal waveform, so that the effective level time of the second detection signal is compressed. Or, the waveform distortion information may refer to a large signal deviation between the first detection signal and the second detection signal, so that there are problems of information loss or information error in the second detection signal. For example, the first detection signal is digitally encoded, while there are problems of encoding information loss or error in the second detection signal. This is only an example here, and the embodiments of the present application are not limited thereto.

[0131] It should be noted that for panel crack detection (PCD) in the related art, impedance detection or bright line detection is usually performed using DDIC and cell test (CT). Among them, impedance detection means that the DDIC or CellTest fixture forms a loop with the detection output end, such as PCDL or PCDR, through the detection input end, such as PCD1, PCD2 or PCDE, to identify the impedance level of the peripheral trace (crack detection line 10), so as to identify whether there is a crack and detect defective products.

[0132] Among them, for bright line detection, a low level is input to the SWL terminal or SWR terminal. As Figure 5 shown, the transistor electrically connected to the data line is turned on, so that the PCD detection unit is turned on, and a high voltage is input to the detection input ends PCD1, PCD2 or PCDE. By identifying whether the corresponding bright line is output from the data line, it is determined whether there is a break in the peripheral trace. However, micro cracks are different from cracks. Micro cracks are generally initial tiny cracks and will not be manifested from the impedance results of existing tests in the initial stage. Therefore, the current impedance detection or bright line detection methods cannot detect micro cracks.

[0133] In the embodiments of the present application, a first detection signal is input to the detection input end corresponding to the crack detection line 10 in the display panel, the second detection signal output from the detection output end corresponding to the crack detection line 10 is received, and the crack detection result of the display panel is determined according to the waveform distortion information of the second detection signal. In this way, the micro-cracks of the display panel can be visually identified according to the waveform distortion of the second detection signal, and it can be determined whether there are micro-cracks in the display panel. By detecting and processing the micro-cracks in time, the abnormal phenomena of the display panel can be reduced, the reliability of the display panel can be improved, and problems such as material failure and shortened service life can be avoided.

[0134] Optionally, step S1 may include the following sub-steps:

[0135] Sub-step A1, input a first detection signal with a first level to the detection input end;

[0136] Step S2 may include the following sub-steps:

[0137] Sub-step B1, determine the crack detection result according to the rise time and / or fall time of the first level interval in the second detection signal; wherein, the waveform distortion information includes the rise time and / or fall time of the first level interval.

[0138] In some embodiments, the time constant τ = RC can affect the rise time (TR) and fall time (TF) of the signal waveform, and further manifest as the compression of the effective level of the signal. Specifically, due to the existence of micro-cracks, RC will increase, that is, the time constant τ increases, and TR / TF will increase, resulting in waveform abnormalities, so that the effective level time is compressed. Therefore, if the effective level time of the second detection signal is too short, it is determined that there are micro-cracks in the display panel.

[0139] In some embodiments, the first detection signal may be a detection signal with a specific waveform, that is, the first detection signal has a first level interval, and the first level interval may be a low level interval or a high level interval. Input a first detection signal with a first level interval to the detection input end, and then receive the second detection signal output from the detection output end. The waveform distortion information of the second detection signal may be manifested as whether the rise time and / or fall time of the first level interval in the second detection signal increases.

[0140] In some embodiments, a threshold may be set for TR / TF in advance. If the change of TR / TF of the second detection signal exceeds the set threshold, it is determined that there are micro-cracks in the display panel, and the display panel is determined to be NG. Among them, a threshold may be set for TR or TF alone, or thresholds may be set for both TR and TF. The embodiments of the present application do not limit this.

[0141] Ideally, TR / TF should be 0. However, in actual production, it can be corrected according to the verification data. For example, if the actual TR / TF is 0.5 microseconds (us), the threshold is set based on the difference between screens with a deviation of ±25% on the basis of 0.5 us. If it exceeds this set threshold, it is determined that there are microcracks in the display panel. Among them, 0.5 us is obtained based on 1H = 3.4 us, and 1H represents the unit line scan duration.

[0142] Figure 7 It is one of the waveform schematic diagrams of a crack detection method provided by an embodiment of the present application. Taking Figure 5 the display panel in as an example, a low-level signal is sent to the SWL terminal to turn on the transistor electrically connected to the left data line, and a first detection signal with a low-level interval is sent to the PCD1 / PCDE terminal, and the second detection signal output by the detection output terminal PCDL is received. And, a low-level signal is sent to the SWR terminal to turn on the transistor electrically connected to the right data line, and a first detection signal with a low-level interval is sent to the PCD2 / PCDE terminal, and the second detection signal output by the detection output terminal PCDR is received. Among them, Figure 5 in the display panel shown, the PCDL / R terminal can be electrically connected to the Pin for testing the waveform TR / TF in the DDIC. In this way, the TR / TF of the second detection signal can be the delay (Latency) time for the DDIC to receive the high and low level conversion.

[0143] Then, the crack detection result is determined according to the TR / TF in the low-level interval of the second detection signal. As Figure 7 (a) shows, when there are no microcracks, the waveform is normal, the TR / TF of the second detection signal output by PCDL / PCDR is almost zero, and the effective level time in the low-level interval of the second detection signal is not compressed, so it is determined that there are no microcracks in the display panel. And as Figure 7 (b) shows, when there are microcracks, the waveform is abnormal, the TR / TF in the low-level interval of the second detection signal output by PCDL / PCDR increases, and the increase in TR / TF causes the effective level time in the low-level interval to be severely compressed, manifested as obvious waveform distortion of the second detection signal, so it is determined that there are microcracks in the display panel.

[0144] Optionally, step S1 may include the following sub-steps:

[0145] Sub-step A2, inputting a digital code to the detection input terminal as the first detection signal;

[0146] Step S2 may include the following sub-steps:

[0147] Sub-step B2, taking the deviation between the encoded information corresponding to the second detection signal and the digital code as the waveform distortion information, and determining the crack detection result according to the waveform distortion information.

[0148] In some embodiments, a digital code may be input to the detection input terminal in the form of a high-frequency signal as the first detection signal. For example, a high-frequency clock (CLK) signal is input to the detection input terminal, that is, a digital code "010101" is input to the detection input terminal. If there are microcracks in the display panel, the correct digital code, that is, "010101", cannot be received from the detection output terminal, and it is determined that the display panel is NG. On the contrary, if there are no microcracks in the display panel, the correct digital code "010101" can be received from the detection output terminal.

[0149] In some embodiments, the encoded information corresponding to the second detection signal may be compared with the first detection signal, that is, the input digital code, and the deviation between the received encoded information and the input digital code is used as the waveform distortion information of the second detection signal. For example, if the encoded information corresponding to the second detection signal is "111111", it means that the low level of the clock signal cannot be received from the detection output terminal, that is, there is a phenomenon of waveform distortion in the second detection signal, thereby determining that there are microcracks in the display panel.

[0150] Optionally, step S1 may include the following sub-steps:

[0151] Sub-step A3, within at least one target detection period, input a first detection signal with multiple target level intervals to the detection input terminal; wherein, the target level interval is the first level interval, or the target level interval is the level interval corresponding to the target encoded value, and the digital code includes the target encoded value;

[0152] The crack detection method further includes:

[0153] Step S3, within the target detection period, input a first control signal to the first control terminal of the display panel and input a second control signal to the second control terminal of the display panel; wherein, within the target detection period, the effective level interval of the first control signal at least partially coincides with one target level interval of the first detection signal in time sequence, and the effective level interval of the second control signal at least partially coincides with another target level interval of the first detection signal in time sequence.

[0154] In some embodiments, the target detection period refers to the detection period for performing a crack detection process on the crack detection lines 10 on the left and right sides of the display panel. Within the target detection period, a first detection signal is input to the crack detection lines 10 on the left and right sides of the display panel, and whether there are microcracks in the display panel is determined according to the waveform distortion condition of the feedback second detection signal.

[0155] In some embodiments, in order to improve the crack detection accuracy, the signal frequency of the first detection signal can be increased. Specifically, the period of the target level interval corresponding to the first detection signal within the target detection period can be shortened to increase the frequency of the first detection signal within the target detection period, thereby improving the crack detection accuracy. This is because the shorter the period / the higher the frequency of the first detection signal, the shorter the effective level time of the first detection signal. If there are micro-cracks in the display panel, the influence of the micro-cracks on the signal waveform of the first detection signal is more severe, and thus it is easier to be manifested in the waveform distortion of the second detection signal, so that the crack detection accuracy can be improved.

[0156] In some embodiments, within the target detection period, a first detection signal with multiple target level intervals can be input to the detection corresponding to the crack detection line 10. This increases the number of target level intervals within the target detection period and can shorten the period of the target level interval in the target detection period, thereby increasing the signal frequency of the first detection signal.

[0157] In some embodiments, the target level interval can be the first level interval in the foregoing embodiments. The first level interval can be a low level interval or a high level interval. Then, the first detection signal within the target detection period has multiple first level intervals. Furthermore, it can be determined whether there are micro-cracks in the display panel according to whether the rising time and / or falling time of the first level interval in the second detection signal increases.

[0158] In some embodiments, the first detection signal can be a digital code such as "010101". Then, the target level interval can be the level interval corresponding to a specific code value in the digital code. In this embodiment, this specific code value is called the target code value. For example, the target code value is "0". Then, the target code value "0" included in the digital code "010101", the target level interval is the low level interval corresponding to the target code value "0". This is only an example, and the embodiments of the present application are not limited thereto.

[0159] In some embodiments, only one target detection period can be set, and within this target detection period, the first detection signal is sent to the crack detection lines 10 on both the left and right sides of the display panel respectively. For example, within a target detection period of 1 second (s), a low level signal is sent to the crack detection lines 10 on both the left and right sides of the display panel respectively. Or, multiple target detection periods can be set, and high-frequency signals such as high-frequency clock signals are input to the crack detection lines 10 on both the left and right sides of the display panel within multiple target detection periods.

[0160] In some embodiments, for the display panel provided in this embodiment, as Figures 1 - 4For the display panel with the structure shown in the figure, the crack detection method further needs to send a corresponding control signal to the control circuit 20 in the border area of the display panel, so that the control circuit 20 conducts the connection between the detection input end and the crack detection line 10, enabling the first detection signal to be transmitted to the crack detection line 10 through the detection input end.

[0161] Specifically, within each target detection period, a first control signal is input to the first control end of the display panel. The first control signal acts on the control end of the first control unit 201, causing the first control unit 201 to conduct the connection between the second end of the first detection line 101 and the detection input end. Within each target detection period, a second control signal is input to the second control end of the display panel. The second control signal acts on the control end of the second control unit 202, causing the second control unit 202 to conduct the connection between the second end of the second detection line 102 and the detection input end.

[0162] In some embodiments, the first control unit 201 may include a first transistor. The level state of the first control signal may be consistent with the effective level of the first transistor, enabling the first control signal to control the first transistor to turn on. Similarly, the second control unit 202 includes a second transistor. The level state of the second control signal may be consistent with the effective level of the second transistor, enabling the second control signal to control the second transistor to turn on.

[0163] For example, for Figures 2 - 4 the display panel in the figure, within each target detection period, a low-level signal may be input to the control electrode of the first transistor (Mux1) to turn on the first transistor (Mux1), and a low-level signal may be input to the control electrode of the second transistor (Mux2) to turn on the second transistor (Mux2), thereby respectively conducting the connection between the detection input end and the first detection line 101, and the connection between the detection input end and the second detection line 102.

[0164] In some embodiments, within each target detection period, the effective level interval of the first control signal at least partially overlaps in time with a target level interval of the first detection signal. In this way, when the first control signal causes the first control unit 201 to conduct the connection between the detection input end and the second end of the first detection line 101, the first detection signal with the target level interval can be transmitted from the detection input end to the first detection line 101. Similarly, within each target detection period, the effective level interval of the second control signal at least partially overlaps in time with a target level interval of the first detection signal. In this way, when the second control signal causes the second control unit 202 to conduct the connection between the detection input end and the second end of the second detection line 102, the first detection signal with the target level interval can be transmitted from the detection input end to the second detection line 102.

[0165] In some embodiments, if the first detection signal input to the detection input end within the target detection period only includes two target level intervals, the effective level interval of the first control signal can at least partially overlap with one of the target level intervals in terms of timing, while the effective level interval of the second control signal can at least partially overlap with the other target level interval in terms of timing. In this way, when the frequency of the first detection signal is increased, the effect of detecting cracks in both the left and right regions on the central axis of the display panel can be achieved. When the first detection signal has more than two target level intervals, the target level intervals corresponding to the first control signal and the target level intervals corresponding to the second control signal should also be as different as possible, so as to ensure the detection integrity while improving the crack detection accuracy.

[0166] In some embodiments, in order to further improve and flexibly adjust the crack detection accuracy, the degree of interval overlap can also be regulated in terms of timing. This is because the higher the degree of overlap between the effective level intervals of the first control signal and the second control signal and the target level intervals of the first detection signal, the longer the effective level time of the first detection signal transmitted to the crack detection line 10. On the contrary, the lower the degree of overlap, the shorter the corresponding effective level time. Therefore, reducing the degree of overlap between the effective level interval and the target level interval can further improve the detection accuracy. In practical applications, adjusting the degree of interval overlap can also make the control of the crack detection method more flexible.

[0167] Optionally, the crack detection method further includes:

[0168] Step S4, within the target detection period, input a third control signal to the third control end of the display panel and input a fourth control signal to the fourth control end of the display panel; wherein, within the target detection period, the effective level interval of the third control signal at least partially overlaps with one of the target level intervals of the first detection signal in terms of timing, and the effective level interval of the fourth control signal at least partially overlaps with the other target level interval of the first detection signal in terms of timing.

[0169] In some embodiments, if the control circuit 20 of the display panel further includes control units for the switch circuits corresponding to the data lines, such as the third control unit 203 and the fourth control unit 204, then within each target detection period, a third control signal also needs to be input to the third control end of the display panel. The third control signal acts on the control end of the third control unit 203, so that the third control unit 203 conducts the connection between the control end of the first switch circuit 401 and the detection input end. Within each target detection period, a fourth control signal is input to the fourth control end of the display panel. The fourth control signal acts on the control end of the fourth control unit 204, so that the fourth control unit 204 conducts the connection between the control end of the second switch circuit 402 and the detection input end.

[0170] In some embodiments, the third control unit 203 may include a third transistor, and the level state of the third control signal may be consistent with the effective level of the third transistor, so that the third control signal can control the third transistor to turn on. Similarly, the fourth control unit 204 includes a fourth transistor, and the level state of the fourth control signal may be consistent with the effective level of the fourth transistor, so that the fourth control signal can control the fourth transistor to turn on.

[0171] For example, for Figure 4 the display panel in, within each target detection period, a low-level signal may be input to the control electrode of the third transistor (Mux3) to turn on the third transistor (Mux3), and a low-level signal may be input to the control electrode of the fourth transistor (Mux4) to turn on the fourth transistor (Mux4), so as to respectively conduct the connection between the detection input end and the control end of the first switch circuit 401, and the connection between the detection input end and the control end of the second switch circuit 402.

[0172] In some embodiments, similar to the first control signal and the second control signal, within each target detection period, at least part of the effective level interval of the third control signal overlaps with one target level interval of the first detection signal in time sequence, and at least part of the effective level interval of the fourth control signal overlaps with another target level interval of the first detection signal in time sequence, so that the first detection signal with the target level interval can be transmitted from the detection input end to the control ends of the first switch circuit 401 and the second switch circuit 402 respectively.

[0173] In some embodiments, if within the target detection period, the first detection signal input to the detection input end only includes two target level intervals, then at least part of the effective level interval of the third control signal may overlap with one target level interval in time sequence, and at least part of the effective level interval of the fourth control signal may overlap with the other target level interval in time sequence. In this way, the detection integrity can be ensured while improving the crack detection accuracy, which will not be elaborated here. Similarly, reducing the overlapping degree between the effective level interval and the target level interval can further improve the detection accuracy, and adjusting the interval overlapping degree in practical applications can also make the control of the crack detection method more flexible.

[0174] Figure 8 is the second waveform schematic diagram of a crack detection method provided by an embodiment of the present application. Taking Figure 2Taking the display panel in as an example, a low-level signal is sent to the SWL terminal to turn on the transistor connected to the first data line 301, and a low-level signal is sent to the SWR terminal to turn on the transistor connected to the second data line 302. Also, a first detection signal is sent to the detection input terminal PCD_ALL_1. The first detection signal includes two consecutive low-level intervals. And, a first control signal with a low-level interval is sent to the control electrode of the first transistor (Mux1), and a first control signal with a low-level interval is sent to the control electrode of the second transistor (Mux2). As Figure 8 shown, the low-level interval of the first control signal substantially coincides with one low-level interval of the first detection signal, and the low-level interval of the second control signal substantially coincides with the other low-level interval of the first detection signal.

[0175] Then, second detection signals respectively output from the first output terminal PCDL and the second output terminal PCDR are received, and the crack detection result can be determined according to the TR / TF of the low-level interval in the second detection signal. As Figure 8 (a) shown, when there is no micro-crack, the waveform is normal, and the TR / TF of the second detection signal output by PCDL / PCDR is almost zero. The effective level time of the low-level interval in the second detection signal is not compressed, so it is determined that the display panel has no micro-crack. And as Figure 8 (b) shown, when there is a micro-crack, the waveform is abnormal, and the TR / TF of the low-level interval in the second detection signal output by PCDL / PCDR increases. The increase in TR / TF causes the effective level time of the low-level interval to be severely compressed, manifested as obvious waveform distortion in the second detection signal, so it is determined that the display panel has a micro-crack.

[0176] In some embodiments, such as Figure 7 and Figure 8 the low-level signals sent to the SWL / SWR terminals in , in this embodiment, a first switch signal can also be input to the control terminal of the first switch circuit 401 in the display panel and a second switch signal can be input to the control terminal of the second switch circuit 402 in the display panel. The first switch signal is, for example, a low-level signal sent to the SWL, and the second switch signal is, for example, a low-level signal sent to the SWR terminal. Among them, the effective level interval of the first switch signal at least partially coincides with a target level interval of the first detection signal in time sequence, and the effective level interval of the second switch signal at least partially coincides with a target level interval of the first detection signal in time sequence.

[0177] Figure 9 is the third waveform schematic diagram of a crack detection method provided by an embodiment of the present application. Taking Figure 3 the display panel in as an example, Figure 3The SWL terminal is electrically connected to the second pole of the first transistor, the SWR terminal is electrically connected to the second pole of the second transistor, and the detection input terminal is marked as (PCD_ALL_2). As Figure 9 shown, a first detection signal is sent to the detection input terminal PCD_ALL_2. The first detection signal includes two consecutive low-level intervals. Moreover, a first control signal with a low-level interval is sent to the control pole of the first transistor (Mux1), and a first control signal with a low-level interval is sent to the control pole of the second transistor (Mux2). As Figure 9 shown, the low-level interval of the first control signal substantially coincides with one low-level interval of the first detection signal, and the low-level interval of the second control signal substantially coincides with the other low-level interval of the first detection signal.

[0178] Then, the second detection signals respectively output by the first output terminal PCDL and the second output terminal PCDR are received, and the crack detection result can be determined according to the TR / TF of the low-level interval in the second detection signal. As Figure 9 (a) shows that when there is no micro-crack, the waveform is normal, the TR / TF of the second detection signal output by PCDL / PCDR is almost zero, and the effective level time of the low-level interval in the second detection signal is not compressed, so it is determined that the display panel has no micro-crack. And as Figure 9 (b) shows that when there is a micro-crack, the waveform is abnormal, the TR / TF of the low-level interval in the second detection signal output by PCDL / PCDR increases, and the increase in TR / TF causes the effective level time of the low-level interval to be severely compressed, manifested as obvious waveform distortion of the second detection signal, so it is determined that the display panel has a micro-crack.

[0179] Figure 10 is the fourth waveform schematic diagram of a crack detection method provided by an embodiment of the present application. Taking Figure 4 the display panel in it as an example, the control circuit 20 further includes a third transistor (Mux3) and a fourth transistor (Mux4), and the detection input terminal is marked as (PCD_ALL_3). As Figure 10 shown, a first detection signal is sent to the detection input terminal PCD_ALL_3. The first detection signal includes two consecutive low-level intervals. Moreover, a first control signal with a low-level interval is sent to the control poles of the first transistor (Mux1) and the third transistor (Mux3) simultaneously, and a first control signal with a low-level interval is sent to the control poles of the second transistor (Mux2) and the fourth transistor (Mux4) simultaneously. As Figure 9 shown, the low-level interval of the first control signal / the third control signal substantially coincides with one low-level interval of the first detection signal, and the low-level interval of the second control signal / the fourth control signal substantially coincides with the other low-level interval of the first detection signal.

[0180] Then, receive the second detection signals respectively output by the first output terminal PCDL and the second output terminal PCDR, and the crack detection result can be determined according to the TR / TF in the low-level interval of the second detection signal. As Figure 10 (a) shows, when there is no micro-crack, the waveform is normal, the TR / TF of the second detection signal output by PCDL / PCDR is almost zero, and the effective level time in the low-level interval of the second detection signal is not compressed, so it is determined that the display panel has no micro-crack. And as Figure 10 (b) shows, when there is a micro-crack, the waveform is abnormal, the TR / TF in the low-level interval of the second detection signal output by PCDL / PCDR increases, and the increase of TR / TF causes the effective level time in the low-level interval to be severely compressed, manifested as obvious waveform distortion of the second detection signal, so it is determined that the display panel has a micro-crack.

[0181] Figure 11 It is the fifth waveform schematic diagram of a crack detection method provided by an embodiment of the present application. Still taking the Figure 4 display panel in it as an example, but the detection input terminal is marked as (PCD_ALL_4). Figure 11 The crack detection method shown in Figure 10 is different from the crack detection method shown in Figure 11 that, on the one hand, the signal frequency corresponding to the first detection signal input to the detection input terminal PCD_ALL_4 can be increased, Figure 10 and the corresponding signal frequency is 2 times or 3 times the signal frequency shown in

[0182] Then, receive the second detection signals respectively output by the first output terminal PCDL and the second output terminal PCDR, and the crack detection result can be determined according to the TR / TF in the low-level interval of the second detection signal. As Figure 11 (a) shows, when there is no micro-crack, the waveform is normal, the TR / TF of the second detection signal output by PCDL / PCDR is almost zero, and the effective level time in the low-level interval of the second detection signal is not compressed, so it is determined that the display panel has no micro-crack. And as Figure 11 (b) shows, when there is a micro-crack, the waveform is abnormal, the TR / TF in the low-level interval of the second detection signal output by PCDL / PCDR increases, and the increase of TR / TF causes the effective level time in the low-level interval to be severely compressed, manifested as obvious waveform distortion of the second detection signal, so it is determined that the display panel has a micro-crack.

[0183] Figure 12 This is the sixth waveform schematic diagram of a crack detection method provided by an embodiment of the present application. Still taking the Figure 4 display panel in Figure 12 as an example, the detection input terminal is marked as (PCD_ALL_4). As Figure 12 shown, the first detection signal input to the detection input terminal PCD_ALL_4 can be a digital code. Figure 12 It shows that within two target detection periods, the digital code input in each target detection period is "0101", that is,

[0184] It shows that the first detection signal includes four low-level intervals, where the target code value is "0" and the target level interval is the low-level interval. Figure 12 (a) shows that when there is no micro-crack, the waveform is normal, and the TR / TF of the second detection signal output by PCDL / PCDR is almost zero, and the effective level time of the low-level interval in the second detection signal is not compressed, so it is determined that the display panel has no micro-crack. And as Figure 12 (b) shows that when there is a micro-crack, the waveform is abnormal, the TR / TF in the low-level interval of the second detection signal output by PCDL / PCDR increases, and the increase in TR / TF causes the effective level time of the low-level interval to be severely compressed, manifested as obvious waveform distortion in the second detection signal, so it is determined that the display panel has a micro-crack.

[0185] Optionally, step S2 may include the following sub-steps:

[0186] Sub-step B3: Input the second detection signal output by the first output terminal of the display panel and the second detection signal output by the second output terminal of the display panel into an adder;

[0187] Sub-step B4: Determine the crack detection result of the display panel according to the output result of the adder.

[0188] In some embodiments, if the first detection signal input to the detection input terminal is a digital code, the second detection signals output by the first output terminal and the second output terminal can be checked by an adder (Checksum), and it is determined whether the display panel has a micro-crack according to the output result of the adder, that is, the crack detection result of the display panel is determined according to the output result of the adder. Among them, the adder can be an adder in the peripheral circuit of the display device, or the adder can be an adder inside the display driving circuit, such as an adder inside the DDIC. The adder can be a half adder or a full adder, and the adder can use a binary adder, a decimal adder, etc., which are not limited in the embodiments of the present application.

[0189] In some embodiments, if the adder is a half adder, the two second detection signals output from the first output terminal and the second output terminal can be used as the two input signals of the inputs A and B of the half adder. If the adder is a full adder, among the inputs A, B, and C of the full adder, the two second detection signals output from the first output terminal and the second output terminal can be used as the two input signals of the inputs A and B, and another second detection signal output from the first output terminal or the second output terminal can be added to the output terminal C.

[0190] For example, if the digital code is "010101" and the second detection signal is "010101" when there is no microcrack in the display panel, the output result of the adder is 1. On the contrary, if there is a microcrack in the display panel and the second detection signal is "111111", the output result of the adder is 0.

[0191] Figure 13 This is a schematic diagram of the verification principle of an adder provided by an embodiment of the present application. As Figure 13 shown, a four-bit synchronous binary adder of D0 - D3 is used, and the timing is synchronized based on the CLK signal. D0 - D3 are adders. If D0 - D3 are all at low level (Low = 0), the addition result is 0, indicating that the signal of the low-level clock (CLKLOW) can be normally output. On the contrary, if the addition result is greater than 1, it indicates that there is a microcrack.

[0192] In some embodiments, the second detection signal can be used as a feedback signal to accurately determine the position of the DataNG line through the feedback signal. For example, in the foregoing embodiment, a third control unit 203 is separately controlled to perform a targeted test on the first data line 301 corresponding to the third control unit 203, and a fourth control circuit 20 can be separately controlled to perform a targeted test on the second data line 302 corresponding to the fourth control unit 204. In this embodiment, in the electrical test (ET), it can be set that the adders D0 - D4 respectively correspond to the data lines Data0 - Data4, and the second detection signal is used as a feedback signal to accurately determine the position of the Data NG line, that is, to determine which data line has a microcrack, and then compensate (Repair) the Data NG line to improve the production rhythm and yield.

[0193] Figure 14 This is the circuit schematic diagram of the half adder provided by the embodiment of the present application. As Figure 14As shown, signals are input to input terminal A and input terminal B respectively, and the output results Sum and Cout are obtained through logical operations. It is possible to determine whether the detection output terminal can correctly output Low = 0 based on Sum and Cout, and further determine whether there are microcracks in the display panel. The input / output of the half adder is shown in Table 1. Among them, the principle of the 2-bit half adder refers to the following formulas (1) and (2)

[0194]

[0195] C = AB (2)

[0196] Table 1 Input / Output of Half Adder

[0197] A B Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

[0198] Figure 15 is the circuit schematic diagram of the full adder provided by the embodiment of the present application. As Figure 15 shown, signals are input to input terminal A, input terminal B, and input terminal C respectively, and the output results Sum and Cout are obtained through logical operations. It is possible to determine whether the detection output terminal can correctly output Low = 0 based on Sum and Cout, and further determine whether there are microcracks in the display panel. The input / output of the full adder is shown in Table 2.

[0199] Table 2 Input / Output of Full Adder

[0200] A B C Sum Cout 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1

[0201] Among them, the principle of the full adder refers to the following formulas (3) and (4)

[0202]

[0203] C = (A&B)|(B&C)|(A&C) (4)

[0204] Among them, formula (3) means that in the input terminals ABC, if the number of inputs of 1 is odd, then S is 1; if the number of inputs of 1 is even (including zero), then S is 0. Formula (4) means that if two or more of the three input terminals ABC are 1, then C is 1.

[0205] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to describe the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0206] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to describe the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0207] Although the preferred embodiments of the embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0208] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0209] The above has introduced in detail a display panel, a crack detection method thereof, and a display device provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a border area at least partially surrounding the display area, and a crack detection line and a control circuit are provided in the border area; The crack detection line includes a first detection line and a second detection line. The first detection line is located on one side of the central axis of the display panel, and the second detection line is located on the other side of the central axis. The first end of the first detection line is electrically connected to a first output terminal, and the first end of the second detection line is electrically connected to a second output terminal; The control circuit includes a first control unit and a second control unit. The first ends of the first control unit and the second control unit are electrically connected to the same detection input terminal; the second end of the first control unit is electrically connected to the second end of the first detection line, the control end of the first control unit is electrically connected to a first control terminal, the second end of the second control unit is electrically connected to the second end of the second detection line, and the control end of the second control unit is electrically connected to a second control terminal.

2. The display panel according to claim 1, wherein A plurality of data lines are provided in the display area. The plurality of data lines include at least one first data line and at least one second data line. The first data line and the first detection line are located on the same side of the central axis, and the second data line and the second detection line are located on the same side of the central axis; The border area further includes a first switch circuit corresponding to the first data line one by one, and a second switch circuit corresponding to the second data line one by one; the first end of the first switch circuit is electrically connected to the first output terminal, the second end of the first switch circuit is electrically connected to the first data line, and the control end of the first switch circuit is electrically connected to the second end of the first control unit; The first end of the second switch circuit is electrically connected to the second output terminal, the second end of the second switch circuit is electrically connected to the second data line, and the control end of the second switch circuit is electrically connected to the second end of the second control unit.

3. The display panel according to claim 1, characterized in that A plurality of data lines are provided in the display area. The plurality of data lines include at least one first data line and at least one second data line. The first data line and the first detection line are located on the same side of the central axis, and the second data line and the second detection line are located on the same side of the central axis; The border area further includes a first switch circuit corresponding to the first data line one by one, and a second switch circuit corresponding to the second data line one by one; the first end of the first switch circuit is electrically connected to the first output terminal, and the second end is electrically connected to the first data line; the first end of the second switch circuit is electrically connected to the second output terminal, and the second end of the second switch circuit is electrically connected to the second data line; The control circuit further includes a third control unit and a fourth control unit. A first end of the third control unit and a first end of the fourth control unit are respectively electrically connected to the detection input terminal; a second end of the third control unit is electrically connected to a control end of the first switch circuit, a control end of the third control unit is electrically connected to a third control terminal, a second end of the fourth control unit is electrically connected to a control end of the second switch circuit, and a control end of the fourth control unit is electrically connected to a fourth control terminal.

4. The display panel according to claim 3, wherein The third control unit includes a third transistor, and the fourth control unit includes a fourth transistor. A first pole of the third transistor and a first pole of the fourth transistor are respectively electrically connected to the detection input terminal; A second pole of the third transistor is electrically connected to a control end of the first switch circuit, a control pole of the third transistor is electrically connected to the third control terminal, a second pole of the fourth transistor is electrically connected to a control end of the second switch circuit, and a control pole of the fourth transistor is electrically connected to the fourth control terminal.

5. The display panel according to any one of claims 1-4, characterized in that, The first control unit includes a first transistor, and the second control unit includes a second transistor. A first pole of the first transistor and a first pole of the second transistor are respectively electrically connected to the detection input terminal; A second pole of the first transistor is electrically connected to a second end of the first detection line, a control pole of the first transistor is electrically connected to the first control terminal, a second pole of the second transistor is electrically connected to a second end of the second detection line, and a control pole of the second transistor is electrically connected to the second control terminal.

6. The display panel according to claim 5, characterized in that, A second pole of the first transistor is further electrically connected to a control end of the first switch circuit, and a second pole of the second transistor is further electrically connected to a control end of the second switch circuit.

7. The display panel according to claim 5, wherein The first transistor and the third transistor have the same transistor type, and / or the second transistor and the fourth transistor have the same transistor type.

8. The display panel according to any one of claims 1-4, characterized in that, The border area includes a first area provided with a bonding area, and the control circuit, the detection input terminal, the first control terminal, and the second control terminal are respectively arranged in the first area.

9. A display device, characterized in that, The display device includes a display driving circuit and a display panel as described in any one of claims 1-8. The display driving circuit is respectively electrically connected to the detection input terminal, the first control terminal, the second control terminal, the first output terminal, and the second output terminal.

10. A crack detection method, characterized in that, The crack detection method includes: Inputting a first detection signal to a detection input terminal corresponding to a crack detection line in the display panel; Receiving a second detection signal output from a detection output terminal corresponding to the crack detection line, and determining a crack detection result of the display panel according to waveform distortion information of the second detection signal.

11. The crack detection method according to claim 10, characterized in that, The step of inputting a first detection signal to a detection input terminal connected to a crack detection line in the display panel includes: Inputting a first detection signal having a first level range to the detection input terminal; The step of determining a crack detection result of the display panel according to waveform distortion information of the second detection signal includes: Determine the crack detection result according to the rising time and / or falling time of the first level interval in the second detection signal; wherein, the waveform distortion information includes the rising time and / or falling time of the first level interval.

12. The crack detection method according to claim 10, characterized in that, The inputting of the first detection signal to the detection input terminal connected to the crack detection line in the display panel includes: Input a digital code to the detection input terminal as the first detection signal; The determining of the crack detection result of the display panel according to the waveform distortion information of the second detection signal includes: Use the deviation between the coding information corresponding to the second detection signal and the digital code as the waveform distortion information, and determine the crack detection result according to the waveform distortion information.

13. The crack detection method according to claim 12, wherein, The receiving of the second detection signal output from the detection output terminal corresponding to the crack detection line and the determining of the crack detection result of the display panel according to the waveform distortion information of the second detection signal includes: Input the second detection signal output from the first output terminal of the display panel and the second detection signal output from the second output terminal of the display panel into an adder; Determine the crack detection result of the display panel according to the output result of the adder.

14. The crack detection method according to any one of claims 10-13, characterized in that, The inputting of the first detection signal to the detection input terminal connected to the crack detection line in the display panel includes: Within at least one target detection period, input the first detection signal having a plurality of target level intervals to the detection input terminal; wherein, the target level interval is the first level interval, or the target level interval is the level interval corresponding to the target coding value, and the digital code includes the target coding value; The crack detection method further includes: Within the target detection period, input a first control signal to the first control terminal of the display panel and input a second control signal to the second control terminal of the display panel; wherein, within the target detection period, the effective level interval of the first control signal at least partially coincides with one of the target level intervals of the first detection signal in terms of timing, and the effective level interval of the second control signal at least partially coincides with one of the target level intervals of the first detection signal in terms of timing.

15. The crack detection method according to claim 14, wherein, The crack detection method further includes: Within the target detection period, input a third control signal to the third control terminal of the display panel and input a fourth control signal to the fourth control terminal of the display panel; wherein, within the target detection period, the effective level interval of the third control signal at least partially coincides with one of the target level intervals of the first detection signal in terms of timing, and the effective level interval of the fourth control signal at least partially coincides with one of the target level intervals of the first detection signal in terms of timing.

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