PLC-based power failure detection and reporting method and circuit

Abstract

The invention discloses a PLC-based power failure detection and reporting method and circuit, and the method comprises the steps: judging whether a power failure event occurs or not through the real-time detection of the input voltage change of a PA chip on a PLC module; and S2, when a power-down event occurs, actively reporting power-down event information through a PLC technology by using a time window when the power supply voltage drops from a threshold value to 0V. The circuit comprises a voltage detection circuit which is used for detecting the input voltage change of a PA chip in real time and generating a power-down trigger signal; and the reporting circuit is used for actively reporting power-down event information in a voltage drop window period through the PLC communication module after the power-down trigger signal is detected.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a PLC-based power-off detection and reporting method and circuit. Background Art

[0002] With the rapid development of science and technology, smart home systems have gradually become an important part of modern families and commercial environments. Smart homes integrate various smart devices and sensors to realize automatic control and management of home environments, greatly improving the convenience and safety of life. In these smart home systems, power line communication (PLC) technology has become a key means to achieve the interconnection of smart devices and information interaction and transmission by virtue of its advantage of using existing power lines for data transmission. PLC not only saves wiring costs and simplifies the installation process, but also maintains a stable communication connection in a complex power environment. Therefore, it is widely used in various scenarios of smart homes.

[0003] However, as the number and complexity of smart home devices continue to increase, the stability of power supply has put forward higher requirements for the normal operation of the system. Power failure or power failure will not only cause sudden power outages of smart devices, affecting the overall function of the system, but may also cause safety hazards, such as the failure of smart security systems. Therefore, timely and accurate detection of power anomalies and reporting of status have become key issues that need to be urgently addressed in the design of smart home systems.

[0004] At present, the common power-off detection method mainly relies on independent battery-powered devices to determine whether a power outage has occurred by monitoring the power status. Although this type of method can maintain operation during a power outage, it has disadvantages such as high cost and complex maintenance, and it is difficult to adapt to the needs of large-scale smart home applications. In addition, although the software detection method based on heartbeat polling is low-cost, it also has significant problems: on the one hand, as the number of devices increases, the heartbeat polling cycle will continue to increase, resulting in an increase in the detection delay of power-off events; on the other hand, since power-off events are extremely rare events, frequent heartbeat polling will occupy a large amount of channel resources, resulting in resource waste, especially in a high-density device environment, this problem is more prominent. Summary of the invention

[0005] In view of the problems existing in the above-mentioned prior art, the present invention proposes a power-off detection and reporting method and circuit based on PLC. By combining the efficient communication capability and low-cost hardware design of PLC technology, the system complexity and cost are greatly reduced while ensuring the real-time and reliability of detection and reporting, thereby providing an efficient and economical power-off detection and reporting solution for smart home systems.

[0006] According to one aspect of the present invention, a power failure detection and reporting method based on PLC is proposed, including the following steps: S1. Determine whether a power failure event occurs by detecting the change of the input voltage of the PA chip on the PLC module in real time; S2. When a power failure event occurs, utilize the time window during which the power supply voltage drops from the threshold to 0V to actively report the power failure event information through PLC technology.

[0007] Further, it also includes an anti-false detection protection step:

[0008] S3. Prevent false detection through the following solutions S31 and S32:

[0009] S31. Continuously sample the ADC multiple times, and only trigger the reporting of the power failure event when the number of sampling values lower than the threshold exceeds half of the total number of samplings;

[0010] S32. When the GPIO detects a low level, detect again after delaying a preset time. If it is still a low level, trigger the reporting of the power failure event.

[0011] Further, step S1 specifically includes: S11. Monitor the input voltage of the PA chip, and determine it as a power failure event when the input voltage is lower than the threshold; S12. Divide the input voltage of the PA chip to the detectable range through a voltage dividing circuit to adapt to the detection pin of the PLC module.

[0012] Further, step S2 specifically includes: S21. Encode the power failure event information through PLC signals within the time window during which the power supply voltage drops from the threshold to 0V; S22. Send the encoded power failure event information to the main control system through power line carrier communication.

[0013] Further, at least one of the following three hardware detection solutions is adopted in step S1 to detect the change of the input voltage of the PA chip on the PLC module:

[0014] ① Adopt a detection solution combining a voltage dividing resistor and one-channel ADC, and input the divided voltage to the ADC pin for detection;

[0015] ② Adopt a detection solution combining a voltage dividing resistor and a Schmidt-mode GPIO, and trigger the detection through the change of the GPIO level;

[0016] ③ Adopt a detection solution combining a voltage dividing resistor and a reset chip with a common GPIO, and utilize the low-level signal output by the reset chip to trigger the detection.

[0017] Further, the threshold is 10V.

[0018] According to another aspect of the present invention, a power failure detection and reporting circuit based on PLC is proposed, including: a voltage detection circuit for real-time detecting the change of the input voltage of the PA chip and generating a power failure trigger signal; a reporting circuit for actively reporting power failure event information through the PLC module within the voltage drop window period after detecting the power failure trigger signal.

[0019] Further, the voltage detection circuit includes: a voltage dividing resistor module connected to the input end of the PA chip for dividing the input voltage of the PA chip to a preset low voltage; a detection module including one of an ADC, a Schmidt mode GPIO, and a reset chip for converting the divided signal into a logic level or a digital signal.

[0020] Further, the input voltage of the PA chip is 12V, and the preset low voltage is below 3.3V.

[0021] Further, the reporting circuit includes: a PLC communication chip for modulating and sending power failure event information; a power management module for maintaining the power supply of the PLC communication chip within the voltage drop window period to ensure complete data transmission.

[0022] The beneficial effects of the technical solution of the present invention are reflected in: The present invention makes full use of the characteristics of power line carrier communication, adds a low-cost power failure detection circuit on the basis of the existing PLC module, and can detect power anomalies in real time and accurately. When a power failure event is detected, the system can immediately report actively without relying on periodic heartbeat polling. This design not only avoids the detection delay caused by the traditional heartbeat polling method, significantly improves the timeliness of power failure event detection and reporting, but also avoids frequent occupation of the PLC communication channel, effectively saving the limited channel resources.

[0023] In addition, the present invention adopts a low-cost hardware solution such as a voltage dividing resistor combined with an ADC, a Schmidt mode GPIO or a reset chip, which greatly reduces the system complexity and cost, and is especially suitable for large-scale smart home application scenarios. By combining the high-efficiency communication ability and low-cost design of PLC technology, the present invention effectively saves channel resources while ensuring real-time performance and reliability, and provides an efficient and economical power failure detection solution for the smart home system. Description of the Drawings

[0024] Figure 1 is the flowchart of the power failure detection and reporting method based on PLC in the embodiment of the present invention.

[0025] Figure 2 is the schematic diagram of the current PLC module in the embodiment of the present invention.

[0026] Figure 3 is the circuit diagram of the low-cost power failure detection solution 1 in the embodiment of the present invention.

[0027] Figure 4 It is the circuit diagram of the low-cost power-down detection solution 2 in the embodiment of the present invention.

[0028] Figure 5 It is the circuit diagram of the low-cost power-down detection solution 3 in the embodiment of the present invention.

[0029] Figure 6 It is the flowchart of the misdetection prevention mechanism solution 1 in the embodiment of the present invention.

[0030] Figure 7 It is the flowchart of the misdetection prevention mechanism solution 2 in the embodiment of the present invention. Specific implementation manners

[0031] The present invention will be further described below in conjunction with the accompanying drawings, specific implementation manners and embodiments. It should be understood that the purpose of providing the embodiments is only for illustration, rather than imposing any limitation on the protection scope of the present invention.

[0032] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, the connection can be for fixing or for circuit connection.

[0033] The embodiment of the present invention provides a power-down detection and reporting method based on PLC. Please refer to Figure 1 , and the process of this method includes the following steps S1 to S4:

[0034] S1. Power-down detection and judgment: By detecting the change of the input voltage of the PA (power amplifier) chip on the PLC module in real time, judge whether a power-down event occurs.

[0035] S2. Implementation of low-cost detection circuit: Provide a variety of hardware implementation solutions, specifically including:

[0036] Solution 1: Adopt a detection solution combining a voltage-dividing resistor and an ADC (analog-to-digital converter);

[0037] Solution 2: Adopt a detection solution combining a voltage-dividing resistor and a Schmitt-mode GPIO (general-purpose input / output pin);

[0038] Solution 3: Adopt a detection solution combining a voltage-dividing resistor, a reset chip and a general GPIO.

[0039] S3. Misdetection prevention mechanism: Prevent misdetection through the following solutions to ensure the accuracy of the detection results:

[0040] Solution 1: Sample the ADC multiple times. Only when the number of samples below the threshold exceeds half of the total number of samples, trigger the reporting of the power-off event.

[0041] Solution 2: When the GPIO detects a low level, detect again after a delay. If it is still low, trigger the reporting of the power-off event.

[0042] S4. Reporting of the power-off event: Utilize the time window when the power supply voltage drops from the threshold to 0V. After detecting the power-off event, actively report it through the PLC signal to ensure that the system can respond and handle the anomaly in a timely manner.

[0043] In step S1, the power line carrier communication (PLC) technology realizes power supply (AC to DC) and communication functions through the existing power supply lines. When the power supply line is interrupted, the power supply of the PLC module will also stop accordingly. Since the PLC module has communication functions and certain general computing capabilities, it can meet the basic requirements of the power-off detection sensor. The key is that the PLC module needs to quickly detect the power-off state after the power-off event occurs and send this event information using the PLC technology.

[0044] As Figure 2 shown, the current PLC module usually includes a PLC communication chip powered by 3.3V and a PA chip responsible for amplifying analog signals. The input voltage of the PA chip is usually required to be 12V. Therefore, the target of power-off detection can be set to monitor the 12V input voltage of the PA chip. When it is detected that the 12V voltage is lower than the threshold (for example, 10V), it can be determined that a power-off event has occurred. At this time, the module can utilize the time period when the voltage drops from the threshold to 0V to send data through the PLC technology to notify the occurrence of the power-off event in a timely manner.

[0045] In step S2, based on the existing PLC module, in order to realize the power-off detection of the 12V input voltage of the PA chip, three low-cost hardware circuit implementation solutions are provided in the embodiments of the present invention.

[0046] Solution 1: Adopt a detection solution combining a voltage-dividing resistor and an ADC (analog-to-digital converter). The specific implementation is as Figure 3As shown. By configuring two appropriate voltage-dividing resistors R1 and R2, the input voltage of 12V of the PA chip is divided to about 3.3V and then input to the ADC pin of the PLC module. The system continuously monitors the divided voltage value read by the ADC. When it detects that the divided voltage value is lower than the preset divided voltage value (for example, the divided voltage value corresponding to an input voltage of 10V), it is determined as a power-off event and the corresponding processing mechanism is triggered. It should be noted that in this solution, as long as the combination of the two voltage-dividing resistors can meet the requirement of dividing 12V to below 3.3V, such as the combination of 27k and 10K, the combination of 47K and 18K, etc.; users can choose according to the resistors at hand as long as the required voltage-dividing effect can be achieved. The present invention does not limit this.

[0047] Solution 2: Adopt a detection solution that combines voltage-dividing resistors with a Schmidt-mode GPIO (General-Purpose Input / Output), and the specific implementation is as Figure 4 shown. By configuring two appropriate voltage-dividing resistors R1 and R2, the 12V voltage is divided and then input to the GPIO pin (Schmidt mode) of the PLC module. When the 12V voltage drops to the threshold value (such as 10V), the output voltage after voltage division is 1.3V. Since the GPIO pin is configured in the Schmidt input mode, when the input voltage is lower than the trigger voltage of the Schmidt mode (such as 1.3V), the GPIO will output a low level. The system continuously monitors the level status of the GPIO pin. Once a low level is detected, it can be determined as a power-off event and the corresponding processing mechanism is triggered. It should be noted that in this solution, as long as the combination of the two voltage-dividing resistors can meet the requirement that the divided voltage value of 12V is higher than the trigger voltage of the Schmidt mode of the GPIO pin (such as 1.3V), and the divided voltage value of the threshold value (such as 10V) can be slightly lower than the trigger voltage of the Schmidt mode of the GPIO pin.

[0048] Solution 3: Adopt a detection solution that combines voltage-dividing resistors, a reset chip, and a general GPIO, and the specific implementation is as Figure 5 shown. In this solution, by configuring two appropriate voltage-dividing resistors R1 and R2, the 12V voltage is divided and then connected to the input pin of the reset chip. At the same time, the output pin of the reset chip is connected to the general GPIO pin of the PLC module. When the 12V voltage drops to the threshold value (such as 10V), the output voltage after voltage division reaches the low-level trigger voltage of the reset chip (such as 2.6V), thereby triggering the reset chip to output a low level. The system continuously monitors the level status of the GPIO pin. Once a low level is detected, it can be determined as a power-off event and the corresponding processing mechanism is triggered. It should be noted that in this solution, as long as the combination of the two voltage-dividing resistors can meet the requirement that the divided voltage value of 12V is higher than the trigger voltage of the reset chip (such as 2.6V), and the divided voltage value of the threshold value (such as 10V) can be slightly lower than the trigger voltage of the reset chip.

[0049] To avoid false detection of power-off events, an anti-false detection algorithm needs to be introduced in software implementation. As in the aforementioned step S3, the embodiments of the present invention provide two anti-false detection schemes as follows:

[0050] Scheme 1: As Figure 6 shown, the voltage of the ADC pin is sampled continuously multiple times. Only when the number of times the sampled value is lower than the threshold exceeds half of the total number of samplings, is it determined as a valid power-off event and the reporting is triggered.

[0051] Scheme 2: As Figure 7 shown, when the GPIO detects a low level, it is detected again after a preset time delay. If the result of the second detection is still low level, it is determined as a valid power-off event and the reporting is triggered.

[0052] The reporting of the power-off event in step S4 specifically includes: using the time window when the power supply voltage drops from the threshold (such as 10V) to 0V, actively reporting the power-off event through the PLC communication technology, that is, encoding the power-off event information through the PLC signal; then sending the encoded power-off event information to the main control system through power line carrier communication. This mechanism ensures that the system can capture the abnormal state in time and make a quick response and processing.

[0053] It can be seen that the present invention has the following technical advantages:

[0054] 1. High real-time performance and accuracy

[0055] The present invention determines the power-off event by real-time monitoring of the input voltage change of the PA chip in the PLC module, and combines a variety of low-cost hardware solutions (such as voltage dividing resistors combined with ADC, Schmidt-mode GPIO, reset chips, etc.), which can quickly and accurately detect power anomalies. In addition, an anti-false detection mechanism is introduced at the software level, such as multiple sampling verifications and delay confirmations, which further improves the reliability of the detection results and avoids false alarm problems.

[0056] 2. Low cost and easy implementation

[0057] The present invention makes full use of the resources of the existing PLC module, and realizes power-off detection through low-cost components such as simple voltage dividing resistors, ADC or GPIO, without additional complex circuits or high-cost equipment. This design significantly reduces the hardware cost and system complexity, and is especially suitable for large-scale smart home application scenarios.

[0058] 3. Active reporting and efficient communication

[0059] The traditional heartbeat polling method has problems of detection delay and waste of channel resources. However, after detecting a power-down event, the present invention can immediately report actively through the PLC signal without relying on periodic polling. This active reporting mechanism not only improves the response speed but also avoids frequent occupation of the PLC communication channel, effectively saving the limited channel resources.

[0060] 4. Improve the reliability and security of the system

[0061] The smart home system has extremely high requirements for the stability of power supply. A power-down event may lead to equipment failure or safety hazards. Through the real-time detection and active reporting mechanism, the present invention ensures that the system can quickly respond to power anomalies, improving the overall reliability and security.

[0062] In summary, with the advantages of high real-time performance, low cost, active reporting, and improvement of system reliability, the present invention provides an efficient and economical power-down detection solution for the smart home system, having broad application prospects and significant technical advantages.

[0063] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those skilled in the technical field to which the present invention pertains, without departing from the concept of the present invention, several equivalent substitutions or obvious modifications can be made, and as long as the performance or use is the same, they should all be regarded as falling within the protection scope of the present invention.

Claims

1. A power-off detection and reporting method based on PLC, characterized in that, It includes the following steps: S1. By detecting the change in the input voltage of the PA chip on the PLC module in real time, determine whether a power failure event occurs; S2. When a power failure event occurs, utilize the time window during which the power supply voltage drops from the threshold to 0V, and actively report the power failure event information through PLC technology.

2. The power-off detection and reporting method according to claim 1, wherein It also includes an anti-false detection protection step: S3. Prevent false detection through the following solutions S31 and S32: S31. Continuously sample the ADC multiple times. Only when the number of sampling values lower than the threshold exceeds half of the total number of samplings, trigger the reporting of the power failure event; S32. When the GPIO detects a low level, detect again after a preset time delay. If it is still a low level, trigger the reporting of the power failure event.

3. The power-off detection and reporting method according to claim 1, characterized in that Step S1 specifically includes: S11. Monitor the input voltage of the PA chip. When the input voltage is lower than the threshold, determine it as a power failure event; S12. Divide the input voltage of the PA chip to the detectable range through a voltage dividing circuit to adapt to the detection pin of the PLC module.

4. The power-off detection and reporting method according to claim 1, wherein, Step S2 specifically includes: S21. During the time window when the power supply voltage drops from the threshold to 0V, encode the power failure event information through PLC signals; S22. Send the encoded power failure event information to the main control system through power line carrier communication.

5. The power-off detection and reporting method according to claim 1, wherein In step S1, at least one of the following three hardware detection schemes is adopted to detect the change in the input voltage of the PA chip on the PLC module: ① Adopt a detection scheme combining a voltage dividing resistor and one-channel ADC, and input the divided voltage into the ADC pin for detection; ② Adopt a detection scheme combining a voltage dividing resistor and a Schmidt-mode GPIO, and trigger detection through the change in GPIO level; ③ Adopt a detection scheme combining a voltage dividing resistor and a reset chip and an ordinary GPIO, and utilize the low-level signal output by the reset chip to trigger detection.

6. The power-off detection and reporting method according to any one of claims 1 to 5, characterized in that The threshold is 10V.

7. A power-off detection and reporting circuit based on PLC, characterized in that, It includes: A voltage detection circuit for detecting the change in the input voltage of the PA chip in real time and generating a power failure trigger signal; A reporting circuit for actively reporting the power failure event information through the PLC module within the voltage drop window period after detecting the power failure trigger signal.

8. The power-down detection and reporting circuit according to claim 7, wherein, The voltage detection circuit includes: A voltage dividing resistor module connected to the input end of the PA chip for dividing the input voltage of the PA chip to a preset low voltage; A detection module including one of an ADC, a Schmidt-mode GPIO, and a reset chip for converting the divided signal into a logic level or a digital signal.

9. The power-down detection and reporting circuit according to claim 8, characterized in that The input voltage of the PA chip is 12V, and the preset low voltage is below 3.3V.

10. The power-down detection and reporting circuit according to claim 7, wherein The reporting circuit includes: A PLC communication chip for modulating and sending the power failure event information; A power management module for maintaining the power supply of the PLC communication chip within the voltage drop window period to ensure the complete transmission of data.

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