Semiconductor structure and forming method thereof

Abstract

A method includes forming a sacrificial block on a substrate, reflowing the sacrificial block, performing a first etch process to etch the sacrificial block and the substrate until portions of the substrate are etched to form microlenses, forming a patterned etch mask, and performing a second etch process to etch the substrate. The microlens is located in the recess of the substrate at a time after the first etching process and the second etching process have been performed. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] Electrical signal conduction and optical signal conduction and processing are technologies for signal transmission and processing. In recent years, optical signal conduction and processing have been used in more and more applications and are often combined with electrical signal conduction and processing to provide comprehensive applications. Thus, a package may include optical (photonic) dies (including optical devices) and electronic dies (including electronic devices).

[0003] Micro-lenses are used to converge optical signals. Micro-lenses can be formed by etching a transparent substrate such that the surface of the etched portion of the transparent substrate is rounded. Summary of the Invention

[0004] Embodiments of the present disclosure provide a method of forming a semiconductor structure, including: forming a sacrificial block on a substrate; reflowing the sacrificial block; performing a first etching process to etch the sacrificial block and the substrate until a portion of the substrate is etched to form a micro-lens; forming a patterned etch mask; and performing a second etching process to etch the substrate, wherein, at a time after the first etching process and the second etching process have been performed, the micro-lens is located in a recess of the substrate.

[0005] Another embodiment of the present disclosure provides a semiconductor structure, including: a substrate; a plurality of protective walls forming a grid in a top view of the substrate, wherein the substrate includes a top surface; and a plurality of micro-lenses located in grid openings of the grid formed by the plurality of protective walls, wherein a topmost end of the plurality of micro-lenses is flush with or lower than the top surface of the plurality of protective walls, and wherein the plurality of protective walls are spaced apart from a corresponding nearest micro-lens of the plurality of micro-lenses.

[0006] Yet another embodiment of the present disclosure provides a semiconductor structure, including: a photonic package, including: a first die; and a second die located on the first die; and a substrate located above the photonic package, wherein the substrate includes: a recess located at a top surface of the substrate; a micro-lens located in the recess; and a portion of the substrate surrounding the micro-lens, wherein the recess is wider than the micro-lens. Brief Description of the Drawings

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1 to 4A and Figure 4B and Figure 5A and Figure 5B and Figures 6 to 8 and Figure 9A and Figure 9B and Figure 9C show views of intermediate stages in the formation of a microlens according to some embodiments.

[0009] Figures 10 to 13A and Figure 13B and Figure 14A and Figure 14B show views of intermediate stages in the formation of a microlens according to alternative embodiments.

[0010] Figure 15 shows a photonics package including a microlens according to some embodiments.

[0011] Figure 16 shows a process flow for forming a microlens according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the embodiments and / or configurations being discussed.

[0013] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Except for the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] A microlens structure and a method of forming the same are provided. According to some embodiments of the present disclosure, the microlens can be formed from a transparent substrate such as a silicon substrate. The forming process can include two etching processes, one of which is used to form a groove in the substrate. The other etching process is used to form the microlens, which is located within the groove and is thus embedded in the substrate. The embodiments discussed herein are intended to provide examples to enable the making or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] Figures 1 to 8 , Figure 9A , Figure 9B and Figure 9C FIGS. show cross-sectional views of intermediate stages in the formation of a microlens according to some embodiments of the present disclosure. The corresponding processes are also schematically reflected in process flow 200 as shown in Figure 16 .

[0016] Referring to Figure 1 , a wafer 10 is formed. The wafer 10 includes a substrate 20. According to some embodiments, there are no integrated circuit devices in the wafer 10. For example, the wafer 10 may not include any active devices (such as transistors) and passive devices (such as resistors, capacitors, inductors, etc.). The substrate 20 may be a blanket transparent substrate formed of a homogeneous material such as silicon (doped or undoped), and there are no metal regions, dielectric regions, etc. therein.

[0017] According to an alternative embodiment, the wafer 10 may be a device wafer that includes integrated circuit devices. For example, the wafer 10 may include active devices such as transistors and passive devices such as resistors, capacitors, inductors, etc. The active devices may be formed at the bottom surface of the substrate 20, and additional components (such as metal wires and dielectric layers) may be formed under the substrate 20 and electrically connected to the integrated circuit devices. The passive devices may also be formed in the dielectric layer and may or may not extend into the substrate 20 from the dielectric layer.

[0018] In the following discussion, it is assumed that the wafer 10 is a blanket wafer without active and passive devices. This discussion can also be applied to device wafers when the microlens is directly formed in the semiconductor substrate of the device wafer.

[0019] The wafer 10 may include a plurality of dielectric layers, such as layers 22, 24, and 26. According to some embodiments, layer 22 may be formed of or include a dielectric material, which may be an oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, fluorine-doped silicate glass (FSG), etc. Layer 22 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to an alternative embodiment of the present disclosure, layer 22 is formed by oxidizing the surface layer of the substrate 20 to form a thermal oxide layer. According to some embodiments, the entire layer 22 is formed of a homogeneous material, in which there is no other material different from the homogeneous material.

[0020] Layer 24 may be formed of or include a dielectric material, which may be a nitride-based material, such as silicon nitride, and it may also be formed of or include other materials, such as silicon oxynitride (SiON).

[0021] According to some embodiments, layer 26 is formed of or includes a dielectric material, which may be a nitrogen oxide-based material, such as silicon oxynitride (SiON), and it may also be formed of or include other materials, such as silicon oxide, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), etc.

[0022] Alignment marks 28 may be formed in the dielectric layers 22, 24, and / or 26, for example, in dielectric layer 24. According to some embodiments, the alignment marks 28 include metals, metal alloys, metal compounds, etc., to increase the contrast of the alignment marks 28 relative to the surrounding materials. According to some embodiments, the alignment marks 28 include metal regions formed of or including copper, copper alloy, tungsten, nickel, etc. An adhesion layer may or may not be formed under and lining the metal regions. The adhesion layer may be formed of or include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0023] The process of forming the alignment marks 28 may include etching the corresponding dielectric layer (such as dielectric layer 24) to form an opening, depositing (if formed) the adhesion layer as a conformal layer using physical vapor deposition (PVD), depositing a metal material over the adhesion layer, and then performing a chemical mechanical polishing (CMP) process to remove the excess portions of the adhesion layer and the metal material, leaving the alignment marks 28 in the dielectric layer 24.

[0024] Reference Figure 2 , a photoresist layer 30 is coated on the substrate 20. The corresponding process is shown as Figure 16Process 202 in the process flow 200 shown. According to some embodiments, the photoresist layer 30 is formed of a material capable of reflowing at an elevated temperature. After coating the photoresist layer 30, the photoresist layer 30 is soft baked to drive off the solvent and harden it.

[0025] According to some embodiments, prior to coating the photoresist layer 30, the entire top surface of the substrate 20 is exposed, and no additional layers and materials (such as oxide layers) contact the top surface of the substrate 20. There is also no deposited layer between the photoresist layer 30 and the substrate 20. According to some embodiments, prior to coating the photoresist layer 30, a cleaning process may be performed to remove any native oxide on the top surface of the substrate 20. The coated photoresist layer 30 may be located on the exposed top surface of the substrate 20, with no oxide therebetween. The cleaning process may be performed by a dry etching process, and the coating of the photoresist layer 30 may also be performed in the same vacuum chamber where the cleaning process is performed, without a vacuum break therebetween.

[0026] According to an alternative embodiment, a native oxide layer may be located between the photoresist layer 30 and the substrate 20, and no other layers are deposited on the substrate 20 and between the photoresist layer 30 and the substrate 20. If present, the thickness of the native oxide layer may be less than about 2 nm.

[0027] A photomask 32 is placed over the photoresist layer 30. The photomask 32 includes a plurality of opaque portions and a plurality of transparent portions. An exposure process is performed to expose the photoresist layer 30. The corresponding process is shown as Figure 16 Process 204 in the process flow 200 shown. After the exposure process, the exposed photoresist layer 30 may or may not be hard baked. The position of the photomask 32 may be aligned with the intended position of the wafer 10 by using alignment marks 28.

[0028] Then a development process is performed to remove some portions of the photoresist layer 30 (exposed or unexposed, depending on whether the photoresist 30 is positive or negative). Figure 3 The resulting structure is shown. The corresponding process is shown as Figure 16 Process 206 in the process flow 200 shown. Hereinafter, the remaining portion of the photoresist layer 30 is referred to as the photoresist block 30. The photoresist block 30 will be etched in subsequent processes and thus also serves as a sacrificial block 30 and is referred to as the sacrificial block 30. According to some embodiments, the photoresist blocks 30 are positioned in a repeating pattern (such as an array, honeycomb pattern, etc.). One or several photoresist blocks 30 may also be formed.

[0029] When from Figure 3When viewed in a top view of the structure shown, the photoresist blocks 30 may have the same top view shape and the same top view size. The top view shape may include a circle, a rectangle, a hexagon, an octagon, etc. According to some embodiments, the entire top surface of the substrate 20 is coplanar, and the entire top surface of the photoresist blocks 30 is coplanar, such that the photoresist blocks 30 at different parts of the wafer 10 have the same thickness and thus the same volume.

[0030] Further referring Figure 3 , a reflow process 36 is performed. The corresponding process is shown as process 208 in the process flow 200 as shown in Figure 16 . The reflow process is performed at an elevated temperature above the softening temperature of the photoresist blocks 30. According to some embodiments, the reflow process 36 is performed at a temperature in the range between about 155 °C and about 165 °C. The reflow process 36 may be performed for a duration in the range between about 305 seconds and about 345 seconds, for example. The actual temperature and duration are related to the material of the photoresist blocks 30 and may be higher / longer or lower / shorter.

[0031] Due to the reflow of the photoresist blocks 30, the photoresist blocks 30 melt and reform into a surface having a circular or oval shape when viewed from the side, as shown in Figure 4A and Figure 4B respectively. Throughout the description, a circle refers to a shape where the width W1 is equal to or greater than twice the height HA ( Figure 4A ). An oval refers to a shape where the width W1 is less than twice the height HB ( Figure 4A ). When viewed from the top, the reflowed photoresist blocks 30 may be circular. The top view shape of the reflowed photoresist blocks 30 may be substantially the same as the top view shape of the microlens 44 to be formed as shown in Figure 9B or Figure 9C . The top view size of the reflowed photoresist blocks 30 may be the same as or slightly larger or smaller than the top view size of the microlens 44 as shown in Figure 9B . The lateral dimension W1 of the reflowed photoresist blocks 30 may be in the range between about 100 μm and about 120 μm. The lateral dimension W1 may be the diameter since the reflowed photoresist blocks 30 may have a circular top view shape.

[0032] As shown in Figure 4A and Figure 4B , an etching process 40 is then performed to form the microlens 44 as shown in Figure 5A and Figure 5B , where the microlens 44 has a circular or oval shape respectively. The corresponding process is shown as in Figure 16Process 210 in the process flow 200 shown. At the start of the etching process 40, the reflowed photoresist block 30 can be in physical contact with the material of the substrate 20, such as silicon. Optionally, there can be a very thin native oxide layer between the reflowed photoresist block 30 and the substrate 20, and no deposition layer is on the native oxide layer.

[0033] The etching process 40 is an anisotropic etching process, and the anisotropic etching process is performed by using an etching gas that etches the substrate 20 and the reflowed photoresist block 30. The etching rate ER30 of the reflowed photoresist block 30 and the etching rate ER20 of the substrate 20 can also be close to each other. For example, the etching rate ratio ER20 / ER30 can be in the range between about 0.8 and about 1.2, and can be in the range between about 0.9 and about 1.1. According to some embodiments, the etching process 40 is performed using an etching gas including NF3, CO, O2, CF4, Cl2, etc.

[0034] As the etching process 40 proceeds, the exposed portions of the reflowed photoresist block 30 and the substrate 20 are etched downward, and the surface shape and surface size of the exposed portion of the substrate 20 are the same as or slightly smaller than the surface shape and size of the reflowed photoresist block 30. As the etching process proceeds, more and more surface portions of the reflowed photoresist block 30 are consumed, exposing the surface portion of the substrate 20 directly below the edge portion of the reflowed photoresist block 30, and the exposed portion of the substrate 20 is also etched. More and more portions of the substrate directly below the reflowed photoresist block 30 are exposed and begin to be etched. Thus, the shape and surface profile of the reflowed photoresist block 30 are transferred into the substrate 20.

[0035] As Figure 4A and Figure 4B shown, before the start of the etching process 40, the substrate 20 has a top surface 20TS1. The etching process 40 causes a reduction in the height of the flat top surface of the substrate 20 to the top surface 20TS2, as Figure 5A and Figure 5B shown. The height difference between the top surfaces 20TS2 and 20TS1 is greater than the height H1 of the microlens 44.

[0036] The etching process 40 continues until all of the reflowed photoresist blocks 30 are consumed. Figure 5A and Figure 5B show the resulting structure. According to some embodiments, the top surface of the etched substrate 20 is circular, and thus a microlens 44 is formed. When observed in a side view, the microlens 44 can have a circular surface and may have an elliptical surface. The microlens 44 can form a repeating pattern, such as an array or a honeycomb pattern. Figure 9B or Figure 9CA top view of a portion of the wafer 10 is shown, in which some microlenses 44 are shown. The lateral dimension W1’ of the microlenses 44 ( Figure 5A and Figure 5B ) can be the diameter and can be the same as or slightly smaller than the width W1 of the sacrificial block 30 ( Figure 4A and Figure 4B ).

[0037] Figures 6 to 8 A process of lowering / sinking the microlenses 44 into the substrate 20 is shown, such that the microlenses 44 are protected. Figure 6 The formation of the etch mask 46 is shown, and the etch mask 46 includes a second photoresist. The corresponding process is shown as process 212 in the process flow 200 as shown in Figure 16 . According to some embodiments, the etch mask 46 includes a single photoresist layer. According to alternative embodiments, the etch mask 46 has a bilayer structure, including a bottom anti-reflection coating and the overlying photoresist. According to yet another alternative embodiment, the etch mask 46 has a trilayer structure, including a bottom layer, an intermediate layer, and a top layer formed of the photoresist. According to some embodiments, the etch mask 46 can include the patterned photoresist 46 and is thus hereinafter referred to as the photoresist 46.

[0038] The material of the photoresist 46 can be the same as or different from the material of the photoresist 30. For example, one of the photoresist layer 30 and the photoresist 46 can be a positive photoresist and the other can be a negative photoresist, or both the photoresist layer 30 and the photoresist 46 can be positive photoresists or negative photoresists. The photoresist layer 30 and the photoresist 46 can also have the same or different hardening temperatures. The patterned photoresist 46 has an opening 48. The center of the opening 48 can be aligned with the center of the microlens 44 (or offset to one side of the center of the microlens 44), which is achieved by using the alignment mark 28.

[0039] The lateral dimension W2 of the opening 48 in the patterned photoresist 46 can be in the range between about 110 μm and about 130 μm. The lateral dimension W2 is also greater than the width W1’ of the microlens 44. For example, the difference (W2 - W1’) is greater than about 0.2 μm, greater than about 1 μm, greater than about 5 μm, and can be in the range between about 5 μm and about 20 μm. According to some embodiments, the spacing S1 can be equal to (W2 - W1’) / 2. When the centers of the microlenses 44 are all offset to the same side (or different sides) of the corresponding centers of the openings 48, the spacing S1 can be greater than or less than (W2 - W1’) / 2. For example, the spacing S1A can be greater than the spacing S1B. When the opening 48 has a rectangular top view shape, the lateral dimension W2 can be the length or the width, or when the opening 48 has a circular top view shape, it can be the diameter.

[0040] According to some embodiments, the formation of the patterned photoresist 46 includes coating a blanket photoresist, performing a soft bake process, performing an exposure process using a photomask (not shown), and developing the exposed photoresist 46. Then, a hard bake process can be performed on the patterned photoresist 46. In the hard bake process, the patterned photoresist 46 does not reflow and maintains the developed shape. For example, this can be achieved by baking the patterned photoresist 46 and the underlying wafer 10 at a temperature below the softening temperature of the photoresist 46. For example, the hard bake process can be performed at a temperature in the range between about 120°C and about 140°C.

[0041] Reference Figure 9B Or Figure 9C Discuss the top view shape of the patterned photoresist 46. According to some embodiments in which the microlenses 44 are formed to have an array pattern, the patterned photoresist 46 can be formed as a grid. The grid includes horizontal portions having a longitudinal direction in the X direction (when viewed in top view) and vertical portions having a longitudinal direction in the Y direction. According to some embodiments, label the horizontal and vertical portions of the patterned photoresist 46.

[0042] According to an alternative embodiment, in which the microlenses 44 are positioned to have a pattern other than an array, the patterned photoresist 46 can be formed to have a corresponding pattern, such as a honeycomb pattern.

[0043] Next, as Figure 6 shown, an etching process 50 is performed to etch the substrate 20, where the patterned photoresist 46 is used as an etching mask. Thus, the microlenses 44 are lowered into the substrate 20. The corresponding process is shown as process 214 in process flow 200 as shown in Figure 16 shown. The etching is performed using an anisotropic etching process. According to some embodiments, the etching gas includes fluorine gas (F2); chlorine gas (Cl2); hydrogen chloride (HCl); hydrogen bromide (HBr); bromine (Br2); C2F6; CF4; SO2; a mixture of HBr, Cl2, and O2; a mixture of NF3, HBr, Cl2, O2, CO, CH2F2, etc.

[0044] Due to the anisotropic etching, the height of the exposed top surface of the substrate 20 (including the top surface of the substrate 20) is uniformly reduced, thus forming a structure as shown in Figure 7 shown. Thus, a groove 52 is formed in the substrate 20. The recessed depth D1 is greater than the height H1 of the microlenses 44 such that the top of the microlenses 44 is below the top surface 20TS2 of the substrate 20. The lateral dimension W2' of the groove 52 can be equal to or greater than the width W2 ( Figure 6 ), and can be in the range between about 110 μm and about 130 μm.

[0045] In the recess 52, the substrate 20 may include some portions (referred to as the recess bottom) directly below the recess 52 and next to the microlens 44. The recess bottom also has a top surface 20TS3 that is lower than the top surface 20TS2. The top surface 20TS3 may also be flat or curved due to the etching and masking of the photoresist 46. Different from the first etching process 40, after the second etching process 50, the photoresist 46 that may have thinned during the etching process 50 still retains a bottom portion.

[0046] Then the remaining photoresist 46 is removed, and Figure 8 the resulting structure is shown. The corresponding process is shown as process 216 in process flow 200 as shown in Figure 16 The microlens 44 is formed in the recess 52 of the substrate 20. The substrate 20 includes a protective wall 54 that separates adjacent recesses 52 and separates adjacent microlenses 44. According to some embodiments, the top end of the microlens 44 is flush with or lower than the top surface 20TS2 of the protective wall 54. According to some embodiments, the height difference ΔH (i.e., the height difference between the topmost end of the microlens 44 and the top surface 20TS2) is greater than 0 μm and less than about 20 μm, or may be less than about 100 μm, or less than about 20 μm. When the difference ΔH is greater than 0 μm, the top end of the microlens 44 is recessed to be lower than the top surface 20TS2. Thus, when the wafer 10 is flipped and placed on another surface, the microlens 44 will be higher than and spaced apart from the other surface and will not be damaged.

[0047] The lateral dimension W2' of the recess 52 is less than the pitch P1 of the microlens 44 to leave space for forming the protective wall 54. According to some embodiments, the width W3 of the protective wall 54 may be in the range between about 100 μm and about 300 μm. The spacing S1' between the edge of the microlens 44 and the corresponding nearest edge of the protective wall 54 may be equal to or close to (e.g., the difference is less than 10%) the spacing S1 ( Figure 6 ). The spacing S1' may be greater than about 0.1 μm and may be in the range between about 0.1 μm and about 5 μm, and may also be in the range between about 1 μm and 5 μm.

[0048] Figure 9A The formation of the protective layer 56 according to some embodiments is shown. The corresponding process is shown as process 218 in process flow 200 as shown in Figure 16 The protective layer 56 may be formed of or include a transparent material such as silicon oxide, silicon oxynitride, etc. The formation process may include a conformal deposition process such as ALD, CVD, etc. Optionally, the protective layer 56 may be formed by thermal oxidation of the substrate 20 (e.g., forming silicon oxide). Then a sawing process may be performed to cut the wafer 10 into die 10'.

[0049] Figure 9B Shows a top view of a portion of a wafer 10 and a device 10' according to some embodiments. The grooves 52 are formed as discrete grooves separated from each other by the protective walls 54. According to some embodiments, due to two etching processes, the top view shape of the grooves 52 is different from the top view shape of the microlenses 44. For example, the grooves 52 may have a square top view shape, while the lenses 44 may have a circular top view shape. According to alternative embodiments, the grooves 52 may have other top view shapes, including but not limited to circular, hexagonal, octagonal, etc. As Figure 9B shown, the protective walls 54 form a grid, and the grooves 52 are the grid openings of the grid. The microlenses 44 are located at the centers of the grooves 52, or may be slightly offset from the corresponding centers of the grooves 52 in the same direction.

[0050] According to some embodiments, different portions of the microlenses 44 may have different spacings from the nearest portions of the protective walls 54. For example, the spacing S1'-A may be different from the spacing S1'-B. Additionally, the grooves 52 may be concentric with the corresponding microlenses 44 therein, as Figure 9B or Figure 9C shown. Optionally, the two etching processes may cause the centers of the grooves 52 to be eccentric with the centers of the corresponding microlenses 44 therein.

[0051] Figure 9C Shows an embodiment in which the grooves 52 also have a circular top view shape. According to some embodiments, the microlenses 44 and the corresponding grooves 52 have a common center. Optionally, the center of the groove 52 may be slightly offset from the center of the corresponding microlens 44 therein.

[0052] Figures 10 to 1 3 shows the formation of a wafer 10 and a die 10' according to an alternative embodiment. These embodiments are substantially the same as the foregoing embodiments except that the order of forming the microlenses 44 and the grooves 52 is reversed. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are substantially the same as those of the same components denoted by the same reference numerals in the foregoing embodiments. Throughout the description, the details of the materials, structures, and formation processes provided for each embodiment may be applied to any other applicable embodiment.

[0053] Referring to Figure 10 a reference, the wafer 10 is formed. The structure and material of the wafer 10 are the same as those of the reference Figure 1The discussion is basically the same and will not be repeated here. Next, a patterned etch mask 46 is formed over the substrate 20. According to some embodiments, the patterned etch mask 46 includes photoresist and may or may not include other layers under the photoresist. The process of forming the photoresist in the etch mask 46 may include spin-coating a photoresist layer, performing a soft bake process to expel the solvent therein and harden the photoresist layer, and exposing and then developing the photoresist layer. After the development process, a hard bake process is performed. In the hard bake process, the photoresist does not flow back. For example, the temperature used in the hard bake process may be lower than the softening temperature of the photoresist.

[0054] Then, an etching process 50 is performed to etch the substrate 20, where the etch mask 46 defines the pattern. Thereby, a groove 52 and a protective wall 54 are formed. Then, the etch mask 46 is removed. Figure 11 The resulting structure is shown. The size and positioning of the groove 52 may be substantially the same as those discussed with reference to Figure 9B and Figure 9C Therefore, the top view shape of the groove 52 may have a rectangular top view shape, a circular top view shape, a hexagonal top view shape, an octagonal top view shape, etc. The bottom surface of the groove 52 is flat, such that the subsequently formed microlens 44 can have a circular and smooth surface as needed.

[0055] Referring to Figure 12 , a photoresist block 30 is formed. According to some embodiments, the process of forming the photoresist block 30 may include spin-coating a photoresist layer. Since the photoresist block 30 is formed in the groove 52, when the spin-coating of the photoresist layer is completed, the top surface of the photoresist layer is higher than the top surface 20TS1 of the substrate 20 to allow the photoresist layer to flow over the entire wafer 10. The formation of the photoresist block 30 further includes performing a soft bake process to expel the solvent therein and harden the photoresist layer, and exposing and then developing the photoresist layer.

[0056] The top surface of the resulting photoresist block 30 is also higher than the top surface 20TS1 of the substrate 20. Since the top surface of the photoresist block 30 is relatively high compared to the top surface 20TS1, the width (which may be the diameter) of the photoresist block 30 is controlled such that after the subsequent reflow process, the width of the reflowed photoresist block 30 has a desired value.

[0057] Further referring to Figure 12 , a reflow process 36 is performed. Figure 13A and Figure 13BThe resulting reflowed photoresist blocks 30 are respectively shown therein, where the photoresist blocks 30 respectively have circular and elliptical shapes. The reflow process 36 is performed using process conditions that can cause melting but not damage to the photoresist blocks 30. The process conditions can be the same as those discussed in the foregoing embodiments and will not be repeated here. After melting and curing, the reflowed photoresist blocks 30 have a circular top surface and a circular top view shape. When viewed from the side, the reflowed photoresist blocks 30 can have a circular or elliptical surface. In addition, as discussed in the foregoing embodiments, the reflowed photoresist blocks 30 are separated from the nearest sidewall of the substrate 20 by a non-zero spacing S1. Depending on the etching rate ratio ER20 / ER30 in the subsequent etching process, the topmost end of the reflowed photoresist blocks 30 can be lower than the top surface 20TS1 of the substrate 20, flush with the top surface 20TS1 of the substrate 20, or slightly higher than the top surface 20TS1 of the substrate 20.

[0058] In a subsequent process, an etching process 40 is performed. According to some embodiments, the etching is performed using an etching gas that can etch both the reflowed photoresist blocks 30 and the substrate 20. The etching is also anisotropic such that the profile of the top surface of the reflowed photoresist blocks 30 is transferred to the resulting microlenses. The reflowed photoresist blocks 30 are completely consumed during the etching process 40. As shown respectively in Figure 14A and Figure 14B microlenses 40 are formed, where the photoresist blocks 30 respectively have circular and elliptical shapes. At the same time, due to the etching process 40, the protective wall 54 is lowered.

[0059] The etching gas is selected to adjust the ratio ER20 / ER30 to an appropriate value, which can be in the range between about 0.8 and about 1.2. By selecting an appropriate etching gas, the topmost end of the microlens 44 is slightly lower than the top surface 20TS2. For example, the height difference ΔH is greater than 1 μm and less than about 20 μm, or can be less than about 100 μm or a slightly larger value. The structures shown in Figure 14A or Figure 14B can have substantially the same structure and the same parameters as Figure 9A and thus the details will not be repeated here. The top view shapes of the microlens 44, the groove 52, and the protective wall 54 can be substantially the same as the top view shapes shown and discussed with reference to Figure 9B and Figure 9C and will not be repeated here.

[0060] Figure 15 A photonics package 58 according to some embodiments is shown, where the structure as shown in Figure 9A , Figure 9B and Figure 9CThe die 10' shown. According to some embodiments, the photonics package 58 includes a photonics die 60, an electronics die 62 located above and bonded to the photonics die 60, and a die 10' located above and bonded to the electronics die 62. The bonding of the die 10' to the electronics die 62 can be by fusion bonding, while the bonding of the electronics die 62 to the photonics die 60 can be by bonding (including metal-to-metal direct bonding) and fusion bonding.

[0061] According to some embodiments, the photonics die 60 can include photonics devices such as waveguides, grating couplers, edge couplers, modulators, etc. For example, by way of example, a grating coupler 64 is shown. The grating coupler 64 can be used to emit a laser beam 66 or receive a laser beam 66 emitted from an optical fiber 68, or can be received by another coupler.

[0062] The electronics die 62 can be, for example, a semiconductor device, die, or chip that communicates with the photonics die 60 using electrical signals. The electronics die 62 includes a semiconductor substrate 67, an interconnect structure 68', and electrical connectors 70, which can be, for example, conductive pads, conductive pillars, etc.

[0063] The electronics die 62 can include an integrated circuit for interfacing with the photonics die 60, such as a circuit for controlling the operation of the photonics die 60. For example, the electronics die 62 can include a controller, driver, amplifier, etc. or a combination thereof. The electronics die 62 can also include a CPU. According to some embodiments, the electronics die 62 includes a circuit for processing electrical signals received from the photonics die 60. According to some embodiments, the electronics die 62 can also control the high-frequency signal conduction of the photonics die 60 based on electrical signals (digital or analog) received from another device or die. According to some embodiments, the electronics die 62 can be an electronic integrated circuit (EIC) that provides serializer / deserializer (SerDes) functionality, etc. In this way, the electronics die 62 can be used as part of an I / O interface between optical and electrical signals.

[0064] As discussed above, the die 10' can have a microlens 44. The forming process can be substantially the same as that discussed in the foregoing embodiments. According to some embodiments, after forming a rebuilt wafer by bonding and sealing a plurality of electronics dies to a photonics wafer, and after the wafer 10 ( Figure 1 ) is bonded to the rebuilt wafer, the microlens 44 is formed. The process of forming the microlens is performed on the resulting wafer including the wafer 10 and the rebuilt wafer. According to an alternative embodiment, the die 10' is formed using the process discussed in the foregoing embodiments, and then the corresponding wafer 10 is bonded to a package (or rebuilt wafer) including the photonics die 60 and the electronics die 62.

[0065] As Figure 14A orFigure 14B The microlens 44 shown has the function of converging the laser beam 66, and the laser beam 66 passes through the transparent dielectric layer 72 in the optical path. Accordingly, the optical fiber 68 and the photonic die 60 are used to transmit optical signals.

[0066] Embodiments of the present disclosure have some advantageous features. By performing two etching processes, it is not necessary to form a hard mask on the substrate, form a circular photoresist through an opening in the hard mask, and etch the substrate using the hard mask to define the boundary of the microlens. If a hard mask is used, the hard mask across the entire wafer may have thickness non-uniformities. This will translate into wafer-level non-uniformities in the size and shape of the resulting microlenses. According to embodiments of the present disclosure, since a hard mask is not used, non-uniformity problems will not occur.

[0067] According to some embodiments of the present disclosure, a method includes: forming a sacrificial block on a substrate; reflowing the sacrificial block; performing a first etching process to etch the sacrificial block and the substrate until a portion of the substrate is etched to form a microlens; forming a patterned etch mask; and performing a second etching process to etch the substrate, wherein at a time after the first etching process and the second etching process have been performed, the microlens is located in a recess of the substrate.

[0068] In an embodiment, when the first etching process is performed, a first top surface of the substrate directly below the sacrificial block is coplanar with a second top surface of the substrate between adjacent sacrificial blocks. In an embodiment, when the first etching process is performed, a first top surface of the substrate directly below the sacrificial block is lower than an additional top surface of the substrate. In an embodiment, the sacrificial block includes a first photoresist. In an embodiment, the patterned etch mask includes a second photoresist, and wherein the first photoresist and the second photoresist are formed of different photoresist materials.

[0069] In an embodiment, after the first etching process and the second etching process, the substrate includes some portions forming protective walls, wherein the recess is located between the protective walls. In an embodiment, the topmost end of the microlens is lower than the top surface of the protective wall. In an embodiment, the microlens is laterally spaced apart from the nearest portion of the protective wall by a spacing. In an embodiment, the spacing between the microlens and the nearest portion of the protective wall is greater than about 5 μm. In an embodiment, some portions of the substrate directly below the spacing have a flat top surface. In an embodiment, the sacrificial block is in physical contact with the substrate.

[0070] According to some embodiments of the present disclosure, a structure includes: a substrate including a transparent material; a plurality of protective walls forming a grid in a top view of the substrate, wherein the substrate includes a top surface; and a plurality of microlenses located in grid openings of the grid formed by the plurality of protective walls, wherein a topmost end of the plurality of microlenses is flush with or lower than a top surface of the plurality of protective walls, and wherein the plurality of protective walls are spaced apart from a corresponding nearest microlens among the plurality of microlenses. In an embodiment, a material of the plurality of protective walls is the same as a material of the plurality of microlenses.

[0071] In an embodiment, a portion of the substrate that is laterally located between the plurality of protective walls and the plurality of microlenses has a substantially flat top surface. In an embodiment, a spacing that separates the plurality of protective walls from the nearest microlens among the plurality of microlenses is greater than about 5 μm. In an embodiment, the topmost end of the plurality of microlenses is lower than the top surface of the plurality of protective walls. In an embodiment, the substrate includes silicon.

[0072] According to some embodiments of the present disclosure, a structure includes: a photonics package including a photonics die; and an electronic die located on the photonics die; and a transparent substrate located above the photonics package, wherein the transparent substrate includes a groove at a top surface of the transparent substrate; a microlens located in the groove; and a portion of the transparent substrate surrounding the microlens, wherein the groove is wider than the microlens. In an embodiment, the portion of the transparent substrate surrounding the microlens forms a full ring, and wherein a top view shape of the full ring is different from a top view shape of the microlens. In an embodiment, the portion of the transparent substrate surrounding the microlens includes a first top surface that is higher than a second top surface of the microlens.

[0073] Features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: Forming a sacrificial block on a substrate; Reflowing the sacrificial block; Performing a first etching process to etch the sacrificial block and the substrate until a portion of the substrate is etched to form a microlens; Forming a patterned etch mask; And Performing a second etching process to etch the substrate, wherein, at a time after the first etching process and the second etching process have been performed, the microlens is located in a groove of the substrate.

2. The method according to claim 1, wherein, When performing the first etching process, a first top surface of the substrate directly below the sacrificial block is substantially coplanar with a second top surface of the substrate between adjacent sacrificial blocks.

3. The method according to claim 1, wherein When performing the first etching process, a first top surface of the substrate directly below the sacrificial block is lower than an additional top surface of the substrate.

4. The method according to claim 1, wherein The sacrificial block comprises a first photoresist.

5. The method according to claim 4, wherein, The patterned etch mask comprises a second photoresist, and wherein the first photoresist and the second photoresist are formed of different photoresist materials.

6. The method according to claim 1, wherein After the first etching process and the second etching process, the substrate comprises some portions forming protective walls, wherein the groove is located between the protective walls.

7. The method according to claim 6, wherein, The topmost end of the microlens is lower than the top surface of the protective wall.

8. The method according to claim 6, wherein The microlens is laterally spaced apart from the nearest portion of the protective wall by a spacing.

9. A semiconductor structure, comprising: A substrate; A plurality of protective walls forming a grid in a top view of the substrate, wherein the substrate comprises a top surface; and A plurality of microlenses located in grid openings of the grid formed by the plurality of protective walls, wherein topmost ends of the plurality of microlenses are flush with or lower than the top surfaces of the plurality of protective walls, and wherein the plurality of protective walls are spaced apart from corresponding nearest microlenses among the plurality of microlenses.

10. A semiconductor structure, comprising: A photonics package, comprising: A first die; and A second die located on the first die; and A substrate located above the photonics package, wherein the substrate comprises: A groove located at a top surface of the substrate; A microlens located in the groove; and A portion of the substrate surrounding the microlens, wherein the groove is wider than the microlens.

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