Communication module and communication method for ARM and FPGA architecture of BMU

Abstract

The invention relates to the technical field of data acquisition, and particularly discloses a communication module and a communication method for an ARM and FPGA architecture of a BMU. The communication module comprises a battery management unit applied to a lithium battery energy storage system; the battery management unit comprises an ARM minimum system module, an FPGA minimum system module, an AFE cell sampling circuit module, a first ADC sampling module and a second ADC sampling module. The ARM minimum system module and the FPGA minimum system module are connected through an FSMC bus. The ARM minimum system module is connected with the AFE cell sampling circuit module; the FPGA minimum system module is connected with the battery pack voltage sampling circuit through the first ADC sampling module; the FPGA minimum system module is connected with the battery pack current sampling circuit through the second ADC sampling module; the FPGA minimum system module is connected with the battery cluster management unit through an optical fiber; according to the invention, real-time data acquisition and safe and stable battery state management of the energy storage system are realized through a collaborative architecture of the ARM and the FPGA in combination with the multi-stage sampling module and optical fiber communication.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition, and more specifically, to a communication module and a communication method for an ARM and FPGA architecture for a BMU. Background Art

[0002] The battery management system is used for the battery management and control of large and medium-sized energy storage power stations, centralized and distributed industrial and commercial energy storage. It can realize linkage control with PCS (energy storage converter), energy storage management system (EMS), etc., optimize control strategies, and ensure the stable and reliable operation of the battery management system.

[0003] The battery management system is a three-level architecture, including a stack controller (BAMS), a cluster controller (BCMU), and a battery PACK controller (BMU). Each BAMS can be connected to multiple BCMUs, and each BCMU is connected to multiple BMUs. Therefore, the BMU in the battery management system is the most basic control and data acquisition device, mainly used for the control of this battery PACK, collecting data such as the voltage and temperature of all batteries, estimating SOC, SOH, internal resistance, etc., and alarming and uploading overvoltage protection and temperature protection, etc., ensuring the stability and safety of the entire battery management system, and enabling the entire lithium battery energy storage system to operate stably and reliably.

[0004] However, the current battery PACK controller (BMU) still has the following problems:

[0005] First, the BMU and the BCMU use CAN communication. When the data volume is large, the communication rate is slow. When controlling 104 battery cells, the transmission of a complete set of data generally exceeds 100 ms, which cannot meet the actual requirements.

[0006] Second, currently, the battery BMU mainly uses an ARM as the main control chip and an ADC for sampling. The sampling speed affects the real-time performance of voltage and current sampling and the estimation accuracy of SOC. Therefore, fast sampling of voltage and current data cannot be achieved.

[0007] Third, although some BMUs have both ARM and FPGA chips, the ARM and FPGA use SPI or SCI communication, resulting in limited communication rate, affected reliability, and the problem of inability to reconnect after disconnection.

[0008] For the above reasons, there is currently no battery management unit BMU on the market that can effectively solve the problem of uploading data of 104 battery cells, improve the real-time sampling of the ADC, and ensure the stability of data interaction between the ARM and the FPGA. Summary of the Invention

[0009] The object of the present invention is to provide a communication module and a communication method for the ARM and FPGA architectures of the BMU, which realize high-precision real-time data acquisition and safe and stable battery state management of the lithium battery energy storage system through the collaborative architecture of the ARM and FPGA, combined with a multi-level sampling module and optical fiber communication.

[0010] To achieve the above object, the present invention provides the following technical solutions:

[0011] A communication module for the ARM and FPGA architectures of the BMU, including a battery management unit BMU applied to the lithium battery energy storage system;

[0012] The battery management unit BMU includes: an ARM minimum system module, an FPGA minimum system module, an AFE cell sampling circuit module, a first ADC sampling module, a second ADC sampling module, and an EEPROM storage circuit module;

[0013] The ARM minimum system module and the FPGA minimum system module are connected through an FSMC parallel bus; the ARM minimum system module is connected to the AFE cell sampling circuit module; the ARM minimum system module is connected to the EEPROM storage circuit module; the FPGA minimum system module is connected to the battery pack voltage sampling circuit through the first ADC sampling module; the FPGA minimum system module is connected to the battery pack current sampling circuit through the second ADC sampling module; the FPGA minimum system module is connected to the battery cluster management unit through an optical fiber; the FPGA minimum system module is connected to a 24V power conversion circuit through a 24V power interface.

[0014] Further, the AFE cell sampling circuit module is used to sample the voltage data and temperature data of 104 cells;

[0015] The EEPROM storage circuit module is used to store the fixed value data in the battery management unit BMU;

[0016] The battery pack voltage sampling circuit is used to collect the voltage data of the battery pack;

[0017] The battery pack current sampling circuit is used to collect the current data of the battery pack.

[0018] Further, the ARM minimum system module is connected to the local monitoring background through a CAN interface, and is used to upload the voltage data, temperature data, and alarm indication of 104 cells, and receive the setting of the fixed value data and control commands issued by the local monitoring background; wherein, the fixed value data includes: the thresholds of the voltage, current, and temperature of 104 cells and the battery pack;

[0019] The FPGA minimum system module is connected to the battery cluster management unit (BCMU) via optical fiber, and is used to upload voltage data, temperature data, and alarm information of the power-on cells, and receive the setting of the fixed value data and control commands issued by the battery cluster management unit (BCMU).

[0020] Further, a first communication status indicator is connected to the ARM minimum system module; a second communication status indicator is connected to the FPGA minimum system module.

[0021] The present invention also provides a communication method for the ARM and FPGA architectures of the BMU. The communication method includes the data interaction process of the ARM minimum system module. The data interaction process of the ARM minimum system module is specifically as follows:

[0022] After the program starts, first perform FSMC initialization, determine whether a remote control command is issued, then determine whether a remote adjustment command is issued. If the read completion flag of the ARM minimum system module is received, write the remote control program or remote adjustment program in the FSMC, and then set the FPGA write completion flag; if the read completion flag is not received within 1S, directly set the write completion flag of the FPGA minimum system module.

[0023] If the write completion flag of the ARM minimum system module is received, read the telemetry data and telecontrol data from the FSMC bus, and then set the FPGA read completion flag. If the write completion flag of the ARM minimum system module is not received, skip this program and end.

[0024] Further, the communication method further includes the data interaction process of the FPGA minimum system module, specifically as follows:

[0025] After the program starts, first perform FSMC initialization, determine whether the write completion flag of the FPGA minimum system module is received. If not, wait for a command; if so, determine whether it is a remote adjustment command or a remote control command, and execute the corresponding remote adjustment command or remote control command respectively.

[0026] Then, set the read completion flag of the ARM minimum system module, determine whether the FPGA read completion flag is received. If so, write the telemetry data and telecontrol data in the FSMC bus, and set the write completion flag of the ARM minimum system module; if not, wait for the FPGA read completion flag, then after 1S, set the ARM write completion flag, and then end this program.

[0027] According to the specific embodiments provided by the present invention, the following technical effects are disclosed by the present invention:

[0028] The present invention connects the ARM minimum system module and the FPGA minimum system module through the FSMC parallel bus, enabling high-speed data exchange and processing, and improving the response speed and efficiency of communication; the first ADC sampling module and the second ADC sampling module are respectively used for sampling the battery pack voltage and current, helping to more accurately monitor the battery status and prevent overcharging and over-discharging, thereby extending the battery life; the combination of the ARM and FPGA systems provides a flexible system configuration that can be adjusted and optimized according to different application requirements; the EEPROM storage circuit is used to store the historical data and key parameters of the battery, and the data can be retained even in the case of power failure; the FPGA minimum system module is connected to the battery cluster management unit through optical fiber, providing a high-speed and stable communication channel, reducing signal interference, and improving the reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings according to the provided drawings without creative efforts.

[0030] The following further describes the communication module and communication method of the ARM and FPGA architectures for BMU of the present invention in conjunction with the drawings;

[0031] Figure 1 is the overall connection schematic diagram of the communication module of the ARM and FPGA architectures for BMU provided by the present invention;

[0032] Figure 2 is the schematic diagram of the communication module of the ARM and FPGA architectures for BMU provided by the present invention applied to the battery management system;

[0033] Figure 3 is the flowchart of the communication method of the ARM and FPGA architectures for BMU provided by the present invention; among them, (a) is the flowchart of the data interaction process of the FPGA minimum system module; (b) is the flowchart of the data interaction process of the ARM minimum system module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The following further describes in detail the specific embodiments of the present invention in conjunction with the drawings and embodiments. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0035] In order to better understand the purpose, structure and function of the present invention, the following further describes the present invention in detail in conjunction with the drawings.

[0036] Embodiment 1

[0037] As Figure 1 shown, the present invention provides a communication module for the ARM and FPGA architectures of the BMU, including a battery management unit BMU applied to a lithium battery energy storage system;

[0038] The battery management unit BMU includes: an ARM minimum system module, an FPGA minimum system module, an AFE cell sampling circuit module, a first ADC sampling module, a second ADC sampling module, and an EEPROM storage circuit module;

[0039] The ARM minimum system module and the FPGA minimum system module are connected through an FSMC parallel bus; the ARM minimum system module is connected to the AFE cell sampling circuit module; the ARM minimum system module is connected to the EEPROM storage circuit module; the FPGA minimum system module is connected to the battery pack voltage sampling circuit through the first ADC sampling module; the FPGA minimum system module is connected to the battery pack current sampling circuit through the second ADC sampling module; the FPGA minimum system module is connected to the battery cluster management unit through an optical fiber; the FPGA minimum system module is connected to a 24V power conversion circuit through a 24V power interface.

[0040] The AFE cell sampling circuit module is used to sample the voltage data and temperature data of 104 cells;

[0041] The EEPROM storage circuit module is used to store the fixed value data in the battery management unit BMU;

[0042] The battery pack voltage sampling circuit is used to collect the voltage data of the battery pack;

[0043] The battery pack current sampling circuit is used to collect the current data of the battery pack.

[0044] The ARM minimum system module is connected to the local monitoring background through a CAN interface, and is used to upload the voltage data, temperature data, and alarm indication of 104 cells, and receive the setting of fixed value data and control commands issued by the local monitoring background; among them, the fixed value data includes: the thresholds of the voltage, current, and temperature of 104 cells and the battery pack;

[0045] The FPGA minimum system module is connected to the battery cluster management unit BCMU through an optical fiber, and is used to upload the voltage data, temperature data, and alarm information of the cells, and receive the setting of fixed value data and control commands issued by the battery cluster management unit BCMU.

[0046] In this embodiment, the battery management unit BMU adopts an ARM+FPGA architecture. Communication between the ARM and the FPGA is carried out using FSMC, which is used to implement the logical control and data processing of the battery management unit BMU, battery data sampling, voltage and current sampling of the lithium battery pack, alarm and protection processing, etc. CAN mainly communicates with the monitoring background. Sampling of cell data such as cell voltage and temperature, EEPROM is used for storing fixed value data, and LED is used to indicate the communication status with the BCMU.

[0047] As Figure 2 shown, the battery management unit BMU of the battery management system is mainly applied in the lithium battery energy storage system. Each set of lithium battery energy storage system includes 1 battery stack management system BAMS, multiple battery cluster management units BCMU, multiple BMU, and several other external devices.

[0048] The ARM minimum system is connected to the local monitoring background through the CAN interface.

[0049] Embodiment 2

[0050] As Figure 3 shown in (b) of the figure, the present invention also provides a communication method for the ARM and FPGA architectures of the BMU. The communication method includes the data interaction process of the ARM minimum system module. The data interaction process of the ARM minimum system module is specifically as follows:

[0051] After the program starts, first perform FSMC initialization, determine whether there is a remote control command issued, then determine whether there is a remote adjustment command issued. If the read completion flag of the ARM minimum system module is received, write the remote control program or the remote adjustment program in the FSMC, and then set the FPGA write completion flag; if the read completion flag is not received within 1S, directly set the write completion flag of the FPGA minimum system module.

[0052] If the write completion flag of the ARM minimum system module is received, read the telemetry data and the telemetry data from the FSMC bus, and then set the FPGA read completion flag. If the write completion flag of the ARM minimum system module is not received, skip this program and end.

[0053] Furthermore, as Figure 3 shown in (a) of the figure, the communication method also includes the data interaction process of the FPGA minimum system module, specifically as follows:

[0054] After the program starts, first perform FSMC initialization, determine whether the write completion flag of the FPGA minimum system module is received. If not, wait for the received command; if so, determine whether it is a remote adjustment command or a remote control command, and execute the corresponding remote adjustment command or remote control command respectively.

[0055] Then, set the read completion flag of the minimum ARM system module, and determine whether the FPGA read completion flag is received. If so, write the telemetry data and telecontrol data to the FSMC bus, and set the write completion flag of the minimum ARM system module; if not, wait for the FPGA read completion flag. Then, after 1 second, set the ARM write completion flag, and then end the program.

[0056] In this embodiment, the FSMC bus is used for communication between the ARM and the FPGA. The dual-port RAM is used as the shared memory inside the FPGA, allowing two independent data ports of the ARM and the FPGA to operate on the RAM. In addition, four GPIOs are used as the read completion flag, write completion flag of the ARM, and the read completion flag, write completion flag of the FPGA respectively. When the FPGA reads and writes data, it directly operates on this dual-port RAM. When the ARM reads and writes data, it operates on this dual-port RAM through the FSMC bus. Through the read and write flags, it is possible to prevent simultaneous read or write operations on the dual-port RAM.

[0057] In this embodiment, the ARM and the FPGA execute their respective data interaction programs, ensuring stable and reliable data interaction. Do not perform simultaneous operations on the FSMC to avoid data loss and errors, and also handshake with each other through the respective setting methods, improving the reliability of data interaction.

[0058] In summary, compared with the prior art, the present invention has at least the following beneficial technical effects:

[0059] 1) It can improve the real-time performance of data communication. Using the BMU in this method, data such as the voltage, temperature, SOC, and SOH of 104 battery cells can be sent to the BCMU within 10 ms.

[0060] 2) Improve the real-time performance of alarm and protection. Using the BMU in this method, alarm and protection data can be sent to the BCMU within 1 ms, realizing fast response of data and improving the reliability of the system.

[0061] 3) The ARM and the FPGA use the FSMC parallel bus for communication, improving the real-time performance of data interaction. A new data interaction method is adopted at the application layer to avoid data loss and errors caused by simultaneous operations on the FSMC, and also ensure the reliability of data interaction through mutual handshake and timed repeated handshake.

[0062] 4) It has better portability: When communicating between the ARM and the FPGA in different BMU or other products that require the ARM and the FPGA, this method can also be selected.

[0063] The foregoing description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A communication module with an ARM and FPGA architecture for a BMU, characterized in that, It includes a Battery Management Unit (BMU) applied in a lithium battery energy storage system; The Battery Management Unit (BMU) includes: an ARM minimum system module, an FPGA minimum system module, an AFE cell sampling circuit module, a first ADC sampling module, a second ADC sampling module, and an EEPROM storage circuit module; The ARM minimum system module and the FPGA minimum system module are connected through an FSMC parallel bus; the ARM minimum system module is connected to the AFE cell sampling circuit module; the ARM minimum system module is connected to the EEPROM storage circuit module; the FPGA minimum system module is connected to the battery pack voltage sampling circuit through the first ADC sampling module; the FPGA minimum system module is connected to the battery pack current sampling circuit through the second ADC sampling module; the FPGA minimum system module is connected to the battery cluster management unit through an optical fiber; the FPGA minimum system module is connected to a 24V power conversion circuit through a 24V power interface.

2. The communication module for the ARM and FPGA architectures used in the BMU according to claim 1, characterized in that, The AFE cell sampling circuit module is used to sample the voltage data and temperature data of 104 cells; The EEPROM storage circuit module is used to store the fixed value data in the Battery Management Unit (BMU); The battery pack voltage sampling circuit is used to collect the voltage data of the battery pack; The battery pack current sampling circuit is used to collect the current data of the battery pack.

3. The communication module for the ARM and FPGA architectures used in the BMU according to claim 2, characterized in that, The ARM minimum system module is connected to the local monitoring background through a CAN interface, and is used to upload the voltage data, temperature data and alarm indication of 104 cells, and receive the setting of the fixed value data and control commands issued by the local monitoring background; among them, the fixed value data includes: the thresholds of the voltage, current and temperature of 104 cells and the battery pack; The FPGA minimum system module is connected to the Battery Cluster Management Unit (BCMU) through an optical fiber, and is used to upload the voltage data, temperature data and alarm information of the cells, and receive the setting of the fixed value data and control commands issued by the Battery Cluster Management Unit (BCMU).

4. The communication module for the ARM and FPGA architectures used in the BMU according to claim 1, characterized in that, The ARM minimum system module is connected with a first communication status indicator light; the FPGA minimum system module is connected with a second communication status indicator light.

5. A communication method for the ARM and FPGA architectures of a BMU, characterized in that, Applied to the communication module of the ARM and FPGA architectures for BMU according to any one of claims 1-4, the communication method includes the data interaction process of the ARM minimum system module, and the data interaction process of the ARM minimum system module is specifically as follows: After the program starts, first perform FSMC initialization, judge whether there is a remote control command issued, then judge whether there is a remote adjustment command issued. If the ARM minimum system module read completion flag is received, write the remote control program or remote adjustment program in the FSMC, and then set the FPGA write completion flag; if the read completion flag is not received within 1S, directly set the write completion flag of the FPGA minimum system module. If the ARM minimum system module write completion flag is received, read the telemetry data and telemetry data from the FSMC bus, and then set the FPGA read completion flag. If the ARM minimum system module write completion flag is not received, skip this program and end.

6. The communication method for the ARM and FPGA architectures used in the BMU according to claim 1, characterized in that, The communication method further includes the data interaction process of the FPGA minimum system module, specifically as follows: After the program starts, first perform FSMC initialization, and determine whether the write completion flag of the FPGA minimum system module is received. If not, wait for the received command; if so, determine whether it is a remote adjustment command or a remote control command, and execute the corresponding remote adjustment command or remote control command respectively; Then, set the read completion flag of the ARM minimum system module, and determine whether the FPGA read completion flag is received. If so, write the telemetry data and telecontrol data in the FSMC bus, and set the write completion flag of the ARM minimum system module; if not, wait for the FPGA read completion flag to be received, then after 1 second, set the ARM write completion flag again, and then end the program.

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