Buck-boost voltage regulator circuit and electronic equipment

Abstract

The invention provides a buck-boost voltage stabilizer circuit and electronic equipment, in the circuit, a power supply output end is coupled to a load capacitor, a first end of an LDO module is coupled to a power supply input end, a second end of the LDO module is coupled to an upper pole plate of a charge pump capacitor through a first diode, and the upper pole plate of the charge pump capacitor is further coupled to the power supply output end through a second diode. The third end of the LDO module obtains the first divided voltage of the power supply output end; the LDO module is used for clamping the voltage of the power supply output end when the first divided voltage is greater than the reference voltage, so that the first divided voltage is equal to the reference voltage; the charge pump module is used for controlling the voltage of the lower pole plate when the second divided voltage of the power supply output end is smaller than or equal to the reference voltage so as to charge the load capacitor and enable the second divided voltage to reach the reference voltage. According to the circuit, buck-boost can be realized without an inductor, and the circuit is relatively high in efficiency and relatively good in stability.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular, to a buck-boost voltage regulator circuit and an electronic device. Background Art

[0002] With the wide popularity of portable electronic devices, intelligent Internet of Things devices, sensor nodes, and various other small low-power electronic devices, the technology of stable voltage power supply has become increasingly important. Such devices usually need to convert the input power supply into a stable and reliable voltage for power supply under the condition of large fluctuations in the input power supply voltage, so as to ensure the normal operation of the system.

[0003] Existing voltage regulation schemes generally include low dropout linear regulators (LDOs), buck voltage regulators (Buck), boost voltage regulators (Boost), Buck-Boost buck-boost voltage regulators, and charge pumps (Charge Pump, CP), etc. However, in the case where the relationship between the input voltage and the output voltage is uncertain, the device usually can only select a Buck-Boost buck-boost voltage regulator. However, the Buck-Boost voltage regulator needs to use inductive components, and has disadvantages such as high cost, large volume, and complex layout, which are not conducive to cost-sensitive or space-constrained application scenarios.

[0004] Therefore, how to design a buck-boost voltage regulator circuit that does not require an inductor and has a relatively high conversion efficiency has become a technical problem that the industry urgently needs to solve at present. Summary of the Invention

[0005] The present invention provides a buck-boost voltage regulator circuit and an electronic device, which solve the technical problem of how to design a buck-boost voltage regulator circuit that does not require an inductor and has a relatively high conversion efficiency.

[0006] According to the first aspect of the present invention, an embodiment of the present invention provides a buck-boost voltage regulator circuit. The buck-boost voltage regulator circuit is coupled between a power supply input terminal and a power supply output terminal. The power supply output terminal is further coupled to a first end of a load capacitor, and a second end of the load capacitor is grounded; the circuit includes:

[0007] An LDO module, a first end of which is coupled to the power supply input terminal, a second end of which is coupled to an upper plate of a charge pump capacitor through a first diode, and the upper plate of the charge pump capacitor is further coupled to a third end of the LDO module and the power supply output terminal respectively through a second diode. A control end of the LDO module receives a reference voltage, and a third end of the LDO module is used to obtain a first divided voltage, and the first divided voltage is a voltage obtained by dividing the voltage of the power supply output terminal.

[0008] A charge pump module, whose first end is coupled to the power supply input terminal to obtain a second divided voltage, whose second end is coupled to the lower plate of the charge pump capacitor, and whose control end receives the reference voltage. The second divided voltage is the voltage obtained by dividing the voltage of the power supply input terminal; wherein:

[0009] The LDO module is configured to: compare the magnitudes of the first divided voltage and the reference voltage, and clamp the voltage of the power supply output terminal when the first divided voltage is greater than the reference voltage, such that the first divided voltage is equal to the reference voltage;

[0010] The charge pump module is used to control the voltage of the lower plate when the second divided voltage is less than or equal to the reference voltage, so as to charge the load capacitor and make the second divided voltage reach the reference voltage.

[0011] Optionally, the method for controlling the voltage of the lower plate includes:

[0012] Controlling the voltage of the lower plate to periodically switch between the ground level and the voltage of the power supply input terminal.

[0013] Optionally, the charge pump module includes a first comparator and a driving unit;

[0014] The first input terminal of the first comparator is coupled to the power supply input terminal through a voltage dividing module to obtain the second divided voltage, its second input terminal receives the reference voltage, and its output terminal is coupled to the input terminal of the driving unit. The driving unit is coupled to the lower plate of the charge pump capacitor; wherein:

[0015] The first comparator is used to compare the magnitudes of the second divided voltage and the reference voltage and output a first signal;

[0016] The driving unit is configured to: control the voltage of the lower plate only when the first signal indicates that the second divided voltage is less than or equal to the reference voltage.

[0017] Optionally, the control end of the charge pump module also receives a clock signal, and the clock signal includes a first level and a second level. Then the method for controlling the voltage of the lower plate includes:

[0018] When the clock signal is at the first level, controlling the voltage of the lower plate to be the ground level, so that the LDO module charges the charge pump capacitor;

[0019] When the clock signal is at the second level, controlling the voltage of the lower plate to be equal to the voltage of the power supply input terminal, so that the charge pump capacitor charges the load capacitor.

[0020] Optionally, the charge pump module includes a second comparator, a control unit, a first PMOS transistor, and a first NMOS transistor;

[0021] A first input terminal of the second comparator is coupled to the power supply input terminal through a first voltage dividing module to obtain the second divided voltage, a second input terminal thereof receives the reference voltage, and an output terminal thereof is coupled to a first input terminal of the control unit. A second input terminal of the control unit receives the clock signal, and an output terminal thereof is configured to output a high-side control signal and a low-side control signal respectively;

[0022] A source electrode of the first PMOS transistor is coupled to the power supply input terminal, a drain electrode thereof is respectively coupled to a drain electrode of the first NMOS transistor and the lower plate, a source electrode of the first NMOS transistor is grounded, a gate electrode of the first PMOS transistor receives the high-side control signal, and a gate electrode of the first NMOS transistor receives the low-side control signal;

[0023] The second comparator is configured to compare magnitudes of the second divided voltage and the reference voltage, and output a first signal;

[0024] The control unit is configured to, when the first signal indicates that a voltage of the power supply input terminal is less than or equal to the reference voltage, output the high-side control signal and the low-side control signal respectively based on the clock signal, and the high-side control signal and the low-side control signal are complementary signals to each other.

[0025] Optionally, the control unit includes an AND logic sub-unit, an inverter, a high-side drive sub-unit, and a low-side drive sub-unit;

[0026] A first input terminal of the AND logic sub-unit is coupled to an output terminal of the second comparator, a second input terminal thereof receives the clock signal, an output terminal thereof is respectively coupled to an input terminal of the high-side drive sub-unit and an input terminal of the inverter, an output terminal of the inverter is coupled to the low-side drive sub-unit, an output terminal of the high-side drive sub-unit is configured to output a high-side control signal, and an output terminal of the low-side drive sub-unit is configured to output a low-side control signal.

[0027] Optionally, the first voltage dividing module includes a first resistor and a second resistor;

[0028] A first end of the first resistor is coupled to the power supply input terminal, a second end thereof is respectively coupled to a first input terminal of the second comparator and a first end of the second resistor, and a second end of the second resistor is grounded.

[0029] Optionally, the LDO module includes a third comparator and a second PMOS transistor;

[0030] The first input terminal of the third comparator is coupled to the power supply output terminal through a voltage dividing module to obtain the first divided voltage, its second output terminal receives the reference voltage, its output terminal is coupled to the gate of the second PMOS transistor, the source of the second PMOS transistor is coupled to the power supply input terminal, and its drain is coupled to the upper plate of the charge pump capacitor through the first diode.

[0031] Optionally, the output terminal of the third comparator is coupled to the gate of the second PMOS transistor through a driver.

[0032] Optionally, the LDO module includes an error amplifier, a first current mirror, and a second current mirror;

[0033] The first input terminal of the error amplifier is coupled to the power supply output terminal through a second voltage dividing module to obtain the first divided voltage, its second input terminal receives the reference voltage, the input terminal of the first current mirror is coupled to the error amplifier for obtaining an error current, the input terminal of the second current mirror is coupled to the output terminal of the first current mirror, the output terminal of the second current mirror is coupled to the upper plate through the first diode, the power supply terminal of the second current mirror is coupled to the power supply input terminal, and the error current is used to meet the demand of the load current at the power supply output terminal.

[0034] Optionally, the error amplifier includes a bias current source, a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor, the first current mirror includes a fourth NMOS transistor, and the second current mirror includes a fifth PMOS transistor and a sixth PMOS transistor;

[0035] The bias current source is respectively coupled to the source of the third PMOS transistor and the source of the fourth PMOS transistor, the gate of the third PMOS transistor is coupled to the power supply output terminal, its drain is coupled to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded, the gate of the fourth PMOS transistor receives the reference voltage, its drain is coupled to the drain of the third NMOS transistor, the gate of the third NMOS transistor is coupled to the drain of the third NMOS transistor, and its source is grounded;

[0036] The gate of the fourth NMOS transistor is respectively coupled to the drain and the gate of the second NMOS transistor, its source is grounded, its drain is coupled to the drain of the fifth PMOS transistor, the source of the fifth PMOS transistor is coupled to the power supply input terminal, its gate is respectively coupled to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor, the source of the sixth PMOS transistor is coupled to the power supply input terminal, and its drain is coupled to the upper plate through the first diode;

[0037] Wherein, the gate-source voltage of the second NMOS transistor matches the gate-source voltage of the third NMOS transistor.

[0038] Optionally, the second voltage dividing module includes a third resistor and a fourth resistor;

[0039] The first end of the third resistor is coupled to the power supply output terminal, and its second end is respectively coupled to the first input terminal of the error amplifier and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.

[0040] According to a second aspect of the present invention, an embodiment of the present invention provides an electronic device, including a buck-boost voltage regulator circuit according to any one of the first aspects of the present invention.

[0041] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0042] In the buck-boost voltage regulator circuit and the electronic device of the technical solution of the present invention, the power supply output terminal in the circuit is coupled to the load capacitor, the first end of the LDO module is coupled to the power supply input terminal, its second end is coupled to the upper plate of the charge pump capacitor through a first diode, and the upper plate of the charge pump capacitor is also coupled to the power supply output terminal through a second diode. The third end of the LDO module obtains the first divided voltage of the power supply output terminal; the LDO module is used to clamp the voltage of the power supply output terminal when the first divided voltage is greater than the reference voltage, so that the first divided voltage is equal to the reference voltage; the charge pump module is used to control the voltage of the lower plate when the second divided voltage of the power supply output terminal is less than or equal to the reference voltage, so as to charge the load capacitor and make the second divided voltage reach the reference voltage. The circuit of the present invention can realize buck-boost without an inductor, and has high circuit efficiency and good stability. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 is a schematic structural diagram of a buck-boost voltage regulator circuit provided by an embodiment of the prior art;

[0045] Figure 2 is a schematic structural diagram of a buck-boost voltage regulator circuit provided by an embodiment of the present invention;

[0046] Figure 3 is a schematic structural diagram of a buck-boost voltage regulator circuit provided by another embodiment of the present invention;

[0047] Figure 4 It is a schematic structural diagram of a buck - boost voltage regulator circuit provided by another embodiment of the present invention;

[0048] Figure 5 It is a schematic structural diagram of a buck - boost voltage regulator circuit provided by still another embodiment of the present invention. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0050] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above - mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non - exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or sub - units does not necessarily have to be limited to those steps or sub - units clearly listed, but may include other steps or sub - units not clearly listed or inherent to these processes, methods, products or devices.

[0051] Next, the technical solutions of the present invention will be described in detail with specific embodiments. These several specific embodiments below can be combined with each other, and for the same or similar concepts or processes, they may not be repeated in some embodiments.

[0052] As described in the background art, it is difficult to design a buck - boost voltage regulator circuit without an inductor in the prior art while achieving relatively high conversion efficiency. The following will be described in detail with reference to the accompanying drawings.

[0053] Existing voltage regulation schemes generally include low - dropout linear regulators (LDOs), buck voltage regulators (Buck), boost voltage regulators (Boost), Buck - Boost buck - boost voltage regulators, and charge pumps (Charge Pump, CP), etc.

[0054] Among them, the low - dropout linear regulator (LDO) has the characteristics of simple structure and low noise, but it can only step down the voltage, and the output load current needs to be entirely provided by the input power supply.

[0055] Although the buck regulator and boost regulator have relatively high efficiency, they can only achieve voltage conversion in a single direction respectively and are not applicable to the situation where the input voltage may vary within a wide range.

[0056] The Buck - Boost regulator can effectively handle scenarios where the input voltage is higher or lower than the output voltage. However, such solutions usually have to use inductive components with relatively high cost and large volume, and the characteristics of the input power supply current change with the operating mode, which is not conducive to miniaturization and low - cost requirements.

[0057] The traditional charge pump (CP) has a relatively simple structure and low cost, and completes energy transfer through capacitors. However, ordinary charge pumps usually only have the boost function and cannot achieve flexible buck or buck - boost functions, so their application scope is limited.

[0058] Figure 1 is a schematic diagram of the structure of a charge pump that can step - up and step - down.

[0059] Please refer to Figure 1 , the charge pump is used to receive the power supply voltage and provide a stable output voltage, including:

[0060] Charge pump capacitor Cx;

[0061] Multiple switches (S1 - S4), used to connect the charge pump capacitor to the power supply voltage;

[0062] Switch timing control circuit, used to control the conduction states of the multiple switches (S1 - S4);

[0063] Error amplifier, generating a control signal according to the reference voltage V REF and the output voltage V OUT ;

[0064] Variable current source IS1, in response to the control signal from the error amplifier, the variable current source provides a stable charging current when the charge pump capacitor Cx is charging.

[0065] It can be seen that this circuit uses capacitive elements to replace inductors and can flexibly achieve boost or buck operating modes. Compared with traditional solutions, this circuit structure is simple and compact, and the cost is low, which is especially suitable for small - load scenarios and cost - sensitive electronic product applications.

[0066] However, the conversion efficiency of this circuit is relatively poor. For example, in a buck application, when the input voltage VIN is 6V, the output voltage VOUT is 3.3V, and the average load current is 75mA, this solution can achieve an average input current of about 150mA at the input end. It can be seen that in a buck application, this conversion efficiency is only 27.5%, while in a low - dropout linear regulator, this conversion efficiency can be close to 55%.

[0067] To solve the above problems, an embodiment of the present invention provides a buck-boost voltage regulator circuit. In the circuit, the power supply output terminal is coupled to the load capacitor. The first terminal of the LDO module is coupled to the power supply input terminal, and its second terminal is coupled to the upper plate of the charge pump capacitor through a first diode. The upper plate of the charge pump capacitor is also coupled to the power supply output terminal through a second diode. The third terminal of the LDO module obtains the first divided voltage of the power supply output terminal; the LDO module is used to clamp the voltage of the power supply output terminal when the first divided voltage is greater than the reference voltage, so that the first divided voltage is equal to the reference voltage; the charge pump module is used to control the voltage of the lower plate when the second divided voltage of the power supply output terminal is less than or equal to the reference voltage, so as to charge the load capacitor and make the second divided voltage reach the reference voltage. The circuit of the present invention can achieve buck-boost without an inductor, and has high circuit efficiency and good stability.

[0068] To make the above objects, features and beneficial effects of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the present invention with reference to the accompanying drawings.

[0069] Figure 2 is the buck-boost voltage regulator circuit of the embodiment of the present invention. The buck-boost voltage regulator circuit is coupled between the power supply input terminal and the power supply output terminal. The power supply output terminal is also coupled to the load capacitor C load at its first terminal, and the second terminal of the load capacitor C load is grounded; the circuit includes:

[0070] An LDO module 10, whose first terminal is coupled to the power supply input terminal, and whose second terminal is coupled to the upper plate CP1 of the charge pump capacitor C0 through a first diode D1. The upper plate CP1 of the charge pump capacitor C0 is also coupled to the third terminal of the LDO module 10 and the power supply output terminal through a second diode D2 respectively. The control terminal of the LDO module 10 receives the reference voltage V REF , and the third terminal of the LDO module 10 is used to obtain the first divided voltage, and the first divided voltage is the voltage of the power supply output terminal after voltage division;

[0071] A charge pump module 20, whose first terminal is coupled to the power supply input terminal to obtain a second divided voltage, whose second terminal is coupled to the lower plate CP2 of the charge pump capacitor C0, and whose control terminal receives the reference voltage V REF , and the second divided voltage is the voltage of the power supply input terminal after voltage division; where:

[0072] The LDO module 10 is configured to: compare the magnitudes of the first divided voltage and the reference voltage V REF and, when the first divided voltage is greater than the reference voltage V REFClamp the voltage of the power supply output terminal at that time, so that the first divided voltage is equal to the reference voltage V REF ;

[0073] The charge pump module 20 is used to control the voltage of the lower plate CP2 when the second divided voltage is less than or equal to the reference voltage V REF to charge the load capacitor C load so that the second divided voltage reaches the reference voltage V REF .

[0074] It should be understood that the voltage of the upper plate CP1 of the charge pump capacitor C0 is the sum of the voltage of the power supply output terminal and the conduction voltage of the second diode D2. Furthermore, the first divided voltage and the second divided voltage are not equal.

[0075] In the embodiment of the present invention, the LDO module 10 makes the first divided voltage equal to the reference voltage V through a loop REF , so that the charge pump capacitor C0 can also be understood as the capacitive load on the loop node of the LDO module 10. Furthermore, in the embodiment of the present invention, the LDO module 10 only provides a charging current for the upper plate CP1 of the charge pump capacitor C0 when the internal loop is unstable.

[0076] In one implementation, the method for controlling the voltage of the lower plate CP2 includes:

[0077] Control the voltage of the lower plate CP2 to periodically switch between the ground level and the voltage of the power supply input terminal.

[0078] It can be seen that when the first divided voltage of the buck-boost voltage regulator circuit of the present invention is greater than the reference voltage V REF , the voltage regulator operates in the LDO mode, improving efficiency and reducing the current required to be provided by the power supply input terminal;

[0079] When the second divided voltage is less than or equal to the reference voltage V REF , the voltage regulator operates in the charge pump mode. Moreover, the present invention multiplexes the circuit of the LDO module 10, enabling the LDO module 10 to achieve the charging current of the upper plate CP1 when the voltage regulator operates in the charge pump mode. The charge pump module 20 only needs to switch the voltage of the lower plate CP2 of the charge pump capacitor C0, reducing the switching loss and eliminating the noise source. At the same time, it combines the advantages of the high power supply rejection ratio, low output ripple, and more stable voltage output performance of the LDO module 10 compared with the traditional charge pump (CP).

[0080] It should be understood that the embodiments of the present invention do not limit the specific structures of the LDO module 10 and the charge pump module 20. As long as they can operate based on the voltage at the power supply output terminal and the voltage at the power supply input terminal, and the LDO module 10 can charge the upper plate CP1 current when the voltage regulator operates in the charge pump mode, they are all within the protection scope of the present invention.

[0081] Now, the specific structure of the charge pump module 20 will be further elaborated.

[0082] In a specific embodiment, please refer to Figure 3 , the charge pump module 20 includes a first comparator CMP1 and a driving unit 201;

[0083] The first input terminal of the first comparator CMP1 is coupled to the power supply input terminal through a voltage dividing module to obtain the second divided voltage V FB2 , its second input terminal receives the reference voltage V REF , its output terminal is coupled to the input terminal of the driving unit 201, and the driving unit 201 is coupled to the lower plate CP2 of the charge pump capacitor C0; where:

[0084] The first comparator CMP1 is used to compare the magnitude of the second divided voltage V FB2 and the reference voltage V REF , and output a first signal CP_EN;

[0085] The driving unit 201 is configured to: only when the first signal CP_EN indicates that the second divided voltage V FB2 is less than or equal to the reference voltage V REF , control the voltage of the lower plate CP2.

[0086] Among them, the first signal CP_EN can be understood as being used to control whether to enable the charge pump mode.

[0087] In actual operation, the comparator in the embodiments of the present invention will use a hysteresis comparator to avoid the circuit switching between two operating modes when the second divided voltage V FB2 is near the reference voltage V REF .

[0088] Please continue to refer to Figure 3 , in a preferred embodiment, the voltage dividing module includes a first resistor R1 and a second resistor R2;

[0089] The first end of the first resistor R1 is coupled to the power supply input terminal, and its second end is respectively coupled to the first input terminal of the first comparator CMP1 and the first end of the second resistor R2. The second end of the second resistor R2 is grounded.

[0090] In another specific embodiment, the control terminal of the charge pump module 20 further receives a clock signal, and the clock signal includes a first level and a second level. Then, the method for controlling the voltage of the lower plate CP2 includes:

[0091] When the clock signal is at the first level, control the voltage of the lower plate CP2 to be the ground level, so that the LDO module 10 charges the charge pump capacitor C0;

[0092] When the clock signal is at the second level, control the voltage of the lower plate CP2 to be equal to the voltage VIN of the power supply input terminal, so that the charge pump capacitor C0 charges the load capacitor C load Charge.

[0093] On this basis, please refer to Figure 4 In one embodiment, the charge pump module 20 includes a second comparator CMP2, a control unit 202, a first PMOS transistor MP1, and a first NMOS transistor MN1;

[0094] The first input terminal of the second comparator CMP2 is coupled to the power supply input terminal through a first voltage dividing module to obtain the second divided voltage V FB2 , its second input terminal receives the reference voltage V REF , its output terminal is coupled to the first input terminal of the control unit 202. The second input terminal of the control unit 202 receives the clock signal CLK, and its output terminal is used to output a high-side control signal and a low-side control signal respectively;

[0095] The source of the first PMOS transistor MP1 is coupled to the power supply input terminal, its drain is respectively coupled to the drain of the first NMOS transistor MN1 and the lower plate CP2, the source of the first NMOS transistor MN1 is grounded, the gate of the first PMOS transistor MP1 receives the high-side control signal HS_CMD, and the gate of the first NMOS transistor MN1 receives the low-side control signal LS_CMD;

[0096] The second comparator CMP2 is used to compare the magnitude of the second divided voltage V FB2 with the reference voltage V REF and output a first signal CP_EN;

[0097] The control unit 202 is configured to be used when the first signal CP_EN represents that the second divided voltage VFB2 less than or equal to the reference voltage V REF When it is, based on the clock signal CLK, the high-side control signal HS_CMD and the low-side control signal LS_CMD are respectively output, and the high-side control signal HS_CMD and the low-side control signal LS_CMD are complementary signals to each other.

[0098] In a preferred embodiment, the high-side control signal HS_CMD and the low-side control signal LS_CMD can be complementary signals with a dead zone.

[0099] In actual implementation, please refer to Figure 4 , the first voltage dividing module includes a first resistor R1 and a second resistor R2;

[0100] The first end of the first resistor R1 is coupled to the power supply input terminal, and its second end is respectively coupled to the first input terminal of the second comparator CMP2 and the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0101] In a specific embodiment, please refer to Figure 5 , the control unit 202 includes an AND logic sub-unit 2021, an inverter 2022, a high-side drive sub-unit 2023 and a low-side drive sub-unit 2024;

[0102] The first input terminal of the AND logic sub-unit 202 is coupled to the output terminal of the second comparator CMP2, its second input terminal receives the clock signal CLK, its output terminal is respectively coupled to the input terminal of the high-side drive sub-unit 2023 and the input terminal of the inverter 2022, the output terminal of the inverter 2022 is coupled to the low-side drive sub-unit 2024, the output terminal of the high-side drive sub-unit 2023 is used to output the high-side control signal HS_CMD, and the output terminal of the low-side drive sub-unit 2024 is used to output the low-side control signal LS_CMD.

[0103] Obviously, when the first signal CP_EN represents that the second divided voltage V FB2 is less than or equal to the reference voltage V REF When it is, the AND logic sub-unit 202 will output the high-side control signal HS_CMD and the low-side control signal LS_CMD with high and low level changes, thereby controlling the on and off of the first PMOS transistor MP1 and the first NMOS transistor MN1.

[0104] When the first signal CP_EN represents that the second divided voltage V FB2 is greater than the reference voltage V REFWhen this occurs, the high-side control signal HS_CMD and the low-side control signal LS_CMD will both be at a low level, which causes the first NMOS transistor MN1 to be always on and the first PMOS transistor MP1 to be always off, effectively turning off the charge pump mode.

[0105] Now, the specific structure of the LDO module 10 will be further elaborated.

[0106] In a specific implementation manner, please refer to Figure 3 , the LDO module 10 includes a third comparator CMP3 and a second PMOS transistor MP2;

[0107] The first input terminal of the third comparator CMP3 is coupled to the power supply output terminal through a voltage division module to obtain the first divided voltage V FB1 , its second output terminal receives the reference voltage V REF , its output terminal is coupled to the gate of the second PMOS transistor MP2, the source of the second PMOS transistor MP2 is coupled to the power supply input terminal, and its drain is coupled to the upper plate CP1 of the charge pump capacitor C0 through the first diode D1.

[0108] In a preferred implementation manner, please continue to refer to Figure 3 , the output terminal of the third comparator CMP3 is coupled to the gate of the second PMOS transistor MP2 through a driver 101.

[0109] In actual implementation, this voltage division module includes a third resistor R3 and a fourth resistor R4;

[0110] The first end of the third resistor R3 is coupled to the power supply output terminal, its second end is respectively coupled to the first input terminal of the third comparator CMP3 and the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded.

[0111] In this case, the first input terminal of the third comparator CMP3 receives the first divided voltage V FB1 .

[0112] In another specific implementation manner, please continue to refer to Figure 4 , the LDO module 10 includes an error amplifier 102, a first current mirror 103, and a second current mirror 104;

[0113] The first input terminal of the error amplifier 102 is coupled to the power supply output terminal through a second voltage division module to obtain the first divided voltage V FB1 , its second input terminal receives the reference voltage V REF, the input terminal of the first current mirror 103 is coupled to the error amplifier 102 for obtaining an error current. The input terminal of the second current mirror 104 is coupled to the output terminal of the first current mirror 103. The output terminal of the second current mirror 104 is coupled to the upper plate CP1 through the first diode D1. The power supply terminal of the second current mirror 104 is coupled to the power supply input terminal. The error current is used to meet the load current requirement of the power supply output terminal.

[0114] In actual implementation, please continue to refer to Figure 4 , the second voltage dividing module includes a third resistor R3 and a fourth resistor R4;

[0115] The first end of the third resistor R3 is coupled to the power supply output terminal, and its second end is respectively coupled to the first input terminal of the error amplifier 102 and the first end of the fourth resistor R4. The second end of the fourth resistor R4 is grounded.

[0116] As an example, the above error amplifier 102 can be a five-transistor amplifier.

[0117] On this basis, please refer to Figure 5 , in a specific implementation manner, the error amplifier 102 includes a bias current source Ibias, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second NMOS transistor MN2, and a third NMOS transistor MN3. The first current mirror 103 includes a fourth NMOS transistor MN4. The second current mirror 104 includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6;

[0118] The bias current source Ibias is respectively coupled to the source electrodes of the third PMOS transistor MP3 and the fourth PMOS transistor MP4. The gate of the third PMOS transistor MP3 is coupled to the power supply output terminal, and its drain is coupled to the drain of the second NMOS transistor MN2. The source of the second NMOS transistor MN2 is grounded. The gate of the fourth PMOS transistor MP4 receives the reference voltage V REF , and its drain is coupled to the drain of the third NMOS transistor MN3. The gate of the third NMOS transistor MN3 is coupled to the drain of the third NMOS transistor MN3, and its source is grounded;

[0119] The gate of the fourth NMOS transistor MN4 is coupled to the drain and gate of the second NMOS transistor MN2 respectively. Its source is grounded, and its drain is coupled to the drain of the fifth PMOS transistor MP5. The source of the fifth PMOS transistor MP5 is coupled to the power supply input terminal. Its gate is coupled to the drain of the fifth PMOS transistor MP5 and the gate of the sixth PMOS transistor MP6 respectively. The source of the sixth PMOS transistor MP6 is coupled to the power supply input terminal, and its drain is coupled to the upper plate CP1 through the first diode D1.

[0120] Wherein, the gate-source voltage of the second NMOS transistor MN2 matches the gate-source voltage of the third NMOS transistor MN3.

[0121] Now Figure 5 The working principle of the buck-boost voltage regulator circuit shown will be further described.

[0122] When the first signal CP_EN represents that the second divided voltage V FB2 is greater than the reference voltage V REF the circuit operates in the low dropout linear regulator (LDO) mode. At this time, the charge pump mode is turned off, which is reflected in that the first NMOS transistor MN1 in the charge pump module 20 is always on, and the first PMOS transistor MP1 is always off.

[0123] In this case, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 serve as the input stage of the error amplifier 102. The voltage VIN of the power supply input terminal is detected through the second voltage dividing module, and the error current is output through the first current mirror MN2 / MN4 and the second current mirror MP5 / MP6, so that the power supply output terminal can provide the current required by the load for the load. In actual implementation, the first current mirror 103 and / or the second current mirror 104 will amplify the current flowing through the third PMOS transistor MP3 to meet the current demand of the load.

[0124] Wherein, the gate and drain of the third NMOS transistor MN3 are short-circuited, and its VGS matches the VGS of the second NMOS transistor MN2, so that the VDS voltages of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 match, thereby eliminating the influence of the channel length effect of the fourth PMOS transistor MP4 on the LDO input stage MP3 / MP4.

[0125] In summary, in Figure 5 the example, the bias current source Ibias, the input stage MP3 / MP4, the first NMOS transistor MN1, the first current mirror 103MN2 / MN4, the second current mirror 104MP5 / MP6, and the second voltage dividing module constitute a single-stage transconductance amplifier structure (OTA), which only generates a single pole at the power supply output terminal, and the loop is stable.

[0126] When the second divided voltage V FB2 is less than or equal to the reference voltage V REF , the circuit operates in the charge pump (CP) mode, which is manifested as the on / off states of the first PMOS transistor MP1 and the first NMOS transistor MN1 being controlled by the clock signal CLK, operating in a half-bridge mode with a 50% duty cycle to drive the lower plate CP2.

[0127] When the clock is in the low phase, the first NMOS transistor MN1 is turned on and the first PMOS transistor MP1 is turned off, and the voltage of the lower plate CP2 is pulled to ground. At this time, the upper plate CP1 is charged by the LDO module 10, and this charging current is controlled, and the magnitude of the charging current is controlled by the input stage MP3 / MP4 of the error amplifier 102 of the LDO module 10.

[0128] Specifically, the LDO module 10 controls the magnitude of the charging current provided by the circuit for the upper plate CP1 in this phase based on the divided voltage V FB1 at the power supply output terminal.

[0129] In actual implementation, the clock signal CLK has a fixed known frequency. Furthermore, the charging charge on the charge pump capacitor C0 will be Q = I MP6 ×(T / 2), where I MP6 is the current provided to the source of the sixth PMOS transistor MP6, and its magnitude is controlled by the input stage MP3 / MP4 of the LDO, and T is the period of the clock signal CLK.

[0130] When the clock is in the high phase, the first NMOS transistor MN1 is turned off and the first PMOS transistor MP1 is turned on, and the voltage of the lower plate CP2 is pulled to the same as the voltage VIN of the power supply input terminal. In this case, the first diode D1 is reverse-biased, and the upper plate CP1 of the charge pump capacitor C0 charges the load capacitor C load through the second diode D2, and the charging charge amount is the charge Q that the LDO module 10 charged the charge pump capacitor C0 in the previous phase.

[0131] Moreover, since the frequency of the clock signal CLK is much greater than the LDO loop bandwidth, the loop of the circuit in the charge pump mode in the embodiments of the present invention is equivalent to the loop of the circuit in the LDO mode. Therefore, since the present invention has loop stability in the LDO mode, the loop stability of the present invention in the charge pump mode can also be guaranteed. It can be seen that the buck-boost voltage regulator circuit provided by the present invention can maintain a stable and reliable output voltage in both operating modes.

[0132] In addition, an embodiment of the present invention further provides an electronic device, including the buck-boost voltage regulator circuit described in any one of the above. As an example, the electronic device may be a portable electronic device, a sensor, etc. The present invention does not limit this. Any electronic device that needs to convert an input power supply voltage into a stable and reliable voltage for power supply under the condition of large-range fluctuations of the input power supply voltage is within the protection scope of the present invention.

[0133] In summary, in the embodiment of the present invention, the power supply output end in the circuit is coupled to the load capacitor, the first end of the LDO module is coupled to the power supply input end, the second end is coupled to the upper plate of the charge pump capacitor through a first diode, and the upper plate of the charge pump capacitor is also coupled to the power supply output end through a second diode. The third end of the LDO module obtains the first divided voltage of the power supply output end; the LDO module is used to clamp the voltage of the power supply output end when the first divided voltage is greater than the reference voltage, so that the first divided voltage is equal to the reference voltage; the charge pump module is used to control the voltage of the lower plate when the second divided voltage of the power supply output end is less than or equal to the reference voltage, so as to charge the load capacitor and make the second divided voltage reach the reference voltage. The circuit of the present invention can achieve buck-boost without an inductor, and has high circuit efficiency and good stability.

[0134] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A buck-boost voltage regulator circuit, characterized in that, The buck-boost regulator circuit is coupled between a power supply input terminal and a power supply output terminal. The power supply output terminal is further coupled to a first end of a load capacitor, and a second end of the load capacitor is grounded; The circuit includes: An LDO module, a first end of which is coupled to the power supply input terminal, and a second end of which is coupled to an upper plate of a charge pump capacitor through a first diode. The upper plate of the charge pump capacitor is further coupled to a third end of the LDO module and the power supply output terminal respectively through a second diode. A control end of the LDO module receives a reference voltage, and the third end of the LDO module is used to obtain a first divided voltage, and the first divided voltage is a voltage obtained by dividing the voltage of the power supply output terminal. A charge pump module, a first end of which is coupled to the power supply input terminal to obtain a second divided voltage, a second end of which is coupled to a lower plate of the charge pump capacitor, and a control end of which receives the reference voltage. The second divided voltage is a voltage obtained by dividing the voltage of the power supply input terminal; Wherein: The LDO module is configured to: compare the magnitudes of the first divided voltage and the reference voltage, and clamp the voltage of the power supply output terminal when the first divided voltage is greater than the reference voltage, so that the first divided voltage is equal to the reference voltage. The charge pump module is used to control the voltage of the lower plate when the second divided voltage is less than or equal to the reference voltage to charge the load capacitor so that the second divided voltage reaches the reference voltage.

2. The buck-boost voltage regulator circuit according to claim 1, wherein A method for controlling the voltage of the lower plate includes: Controlling the voltage of the lower plate to periodically switch between the ground level and the voltage of the power supply input terminal.

3. The buck-boost voltage regulator circuit according to claim 1, wherein, The charge pump module includes a first comparator and a driving unit; A first input terminal of the first comparator is coupled to the power supply input terminal through a voltage dividing module to obtain the second divided voltage, a second input terminal of which receives the reference voltage, and an output terminal of which is coupled to an input terminal of the driving unit. The driving unit is coupled to the lower plate of the charge pump capacitor; Wherein: The first comparator is used to compare the magnitudes of the second divided voltage and the reference voltage and output a first signal; The driving unit is configured to: control the voltage of the lower plate only when the first signal indicates that the second divided voltage is less than or equal to the reference voltage.

4. The buck-boost voltage regulator circuit according to claim 2, wherein, A control end of the charge pump module further receives a clock signal, and the clock signal includes a first level and a second level. Then, the method for controlling the voltage of the lower plate includes: When the clock signal is at the first level, controlling the voltage of the lower plate to be the ground level so that the LDO module charges the charge pump capacitor; When the clock signal is at the second level, controlling the voltage of the lower plate to be equal to the voltage of the power supply input terminal so that the charge pump capacitor charges the load capacitor.

5. The buck-boost voltage regulator circuit according to claim 4, characterized in that The charge pump module includes a second comparator, a control unit, a first PMOS transistor, and a first NMOS transistor; The first input terminal of the second comparator is coupled to the power supply input terminal through a first voltage dividing module to obtain the second divided voltage, its second input terminal receives the reference voltage, and its output terminal is coupled to the first input terminal of the control unit. The second input terminal of the control unit receives the clock signal, and its output terminal is used to output a high-side control signal and a low-side control signal respectively; The source electrode of the first PMOS transistor is coupled to the power supply input terminal, its drain electrode is respectively coupled to the drain electrode of the first NMOS transistor and the lower plate, the source electrode of the first NMOS transistor is grounded, the gate electrode of the first PMOS transistor receives the high-side control signal, and the gate electrode of the first NMOS transistor receives the low-side control signal; The second comparator is used to compare the magnitudes of the second divided voltage and the reference voltage and output a first signal; The control unit is configured to, when the first signal indicates that the voltage of the power supply input terminal is less than or equal to the reference voltage, based on the clock signal, output the high-side control signal and the low-side control signal respectively, and the high-side control signal and the low-side control signal are complementary signals to each other.

6. The buck-boost voltage regulator circuit according to claim 5, wherein The control unit includes an AND logic sub-unit, an inverter, a high-side drive sub-unit, and a low-side drive sub-unit; The first input terminal of the AND logic sub-unit is coupled to the output terminal of the second comparator, its second input terminal receives the clock signal, its output terminal is respectively coupled to the input terminal of the high-side drive sub-unit and the input terminal of the inverter, the output terminal of the inverter is coupled to the low-side drive sub-unit, the output terminal of the high-side drive sub-unit is used to output the high-side control signal, and the output terminal of the low-side drive sub-unit is used to output the low-side control signal.

7. The buck-boost voltage regulator circuit according to claim 5, characterized in that, The first voltage dividing module includes a first resistor and a second resistor; The first end of the first resistor is coupled to the power supply input terminal, its second end is respectively coupled to the first input terminal of the second comparator and the first end of the second resistor, and the second end of the second resistor is grounded.

8. The buck-boost voltage regulator circuit according to claim 1, wherein The LDO module includes a third comparator and a second PMOS transistor; The first input terminal of the third comparator is coupled to the power supply output terminal through a voltage dividing module to obtain the first divided voltage, its second output terminal receives the reference voltage, its output terminal is coupled to the gate electrode of the second PMOS transistor, the source electrode of the second PMOS transistor is coupled to the power supply input terminal, and its drain electrode is coupled to the upper plate of the charge pump capacitor through the first diode.

9. The buck-boost voltage regulator circuit according to claim 8, wherein, The output terminal of the third comparator is coupled to the gate electrode of the second PMOS transistor through a driver.

10. The buck-boost voltage regulator circuit according to claim 1, wherein, The LDO module includes an error amplifier, a first current mirror, and a second current mirror; The first input terminal of the error amplifier is coupled to the power supply output terminal through a second voltage dividing module to obtain the first divided voltage, its second input terminal receives the reference voltage, the input terminal of the first current mirror is coupled to the error amplifier for obtaining an error current, the input terminal of the second current mirror is coupled to the output terminal of the first current mirror, the output terminal of the second current mirror is coupled to the upper plate through the first diode, the power supply terminal of the second current mirror is coupled to the power supply input terminal, and the error current is used to meet the load current requirement of the power supply output terminal.

11. The buck-boost voltage regulator circuit according to claim 10, wherein, The error amplifier includes a bias current source, a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor. The first current mirror includes a fourth NMOS transistor, and the second current mirror includes a fifth PMOS transistor and a sixth PMOS transistor. The bias current source is respectively coupled to the source electrodes of the third PMOS transistor and the fourth PMOS transistor. The gate of the third PMOS transistor is coupled to the power supply output terminal, and its drain is coupled to the drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The gate of the fourth PMOS transistor receives the reference voltage, and its drain is coupled to the drain of the third NMOS transistor. The gate of the third NMOS transistor is coupled to the drain of the third NMOS transistor, and its source is grounded. The gate of the fourth NMOS transistor is respectively coupled to the drain and the gate of the second NMOS transistor. Its source is grounded, and its drain is coupled to the drain of the fifth PMOS transistor. The source of the fifth PMOS transistor is coupled to the power supply input terminal. Its gate is respectively coupled to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor. The source of the sixth PMOS transistor is coupled to the power supply input terminal, and its drain is coupled to the upper plate through the first diode. Wherein, the gate-source voltage of the second NMOS transistor matches the gate-source voltage of the third NMOS transistor.

12. The buck-boost voltage regulator circuit according to claim 10, characterized in that, The second voltage dividing module includes a third resistor and a fourth resistor. The first end of the third resistor is coupled to the power supply output terminal, its second end is respectively coupled to the first input terminal of the error amplifier and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.

13. An electronic device, characterized in that, It includes a buck-boost voltage regulator circuit according to any one of claims 1 to 12.

Images