Resistance aging background calibration circuit for frequency reference source

Abstract

The invention discloses a resistor aging background calibration circuit for a frequency reference source, the resistor aging background calibration circuit comprises a reference branch, an aging branch and a background aging calibration branch, the aging branch is used for temperature coefficient calibration of the frequency reference source and generating an aging branch level based on an aging resistor in the aging branch; the aging resistor has an aging phenomenon; the reference branch is used for generating a reference branch level based on a reference resistor by using ultra-low duty cycle clock control; and the background aging calibration branch is used for comparing the aging branch level with the reference branch level and feeding back and calibrating the resistance value of the aging resistor in the aging branch according to the comparison result, so that the aging calibration circuit with small area and high energy efficiency is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of design of mixed-signal integrated circuits, and particularly relates to a resistance aging background calibration circuit for a frequency reference source. Background Art

[0002] In order to obtain higher performance, microcontroller units (MCUs) have been manufactured using more advanced processes. A fully integrated radio frequency MCU requires a high-precision frequency reference source to support the real-time clock wake-up function, and even in the case of temperature changes, voltage fluctuations, and resistance aging, its frequency error still needs to be less than ±1%.

[0003] However, achieving this stringent requirement faces many challenges, especially for the frequency reference source of MCUs in advanced processes, such as RC oscillators. Although the current temperature compensation technology for the frequency reference source of MCUs has been relatively mature, and many solutions have achieved a temperature coefficient of dozens of ppm / °C or lower, the aging calibration ability is still a shortcoming.

[0004] Therefore, how to design a small-area and high-energy-efficiency aging calibration circuit for the frequency reference source of MCUs has become an important issue. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a resistance aging background calibration circuit for a frequency reference source.

[0006] The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] The present invention provides a resistance aging background calibration circuit for a frequency reference source, and the resistance aging background calibration circuit includes a reference branch, an aging branch, and a background aging calibration branch;

[0008] The aging branch is used for calibrating the temperature coefficient of the frequency reference source and generating an aging branch level based on the aging resistor in the aging branch; the aging resistor has an aging phenomenon;

[0009] The reference branch is used to be controlled by an ultra-low duty cycle clock and generate a reference branch level based on the reference resistor in the reference branch;

[0010] The background aging calibration branch is used to compare the aging branch level and the reference branch level and feedback and calibrate the resistance value of the aging resistor in the aging branch according to the comparison result.

[0011] Optionally, the resistance aging background calibration circuit further includes a PMOS-only oscillator and a current-domain comparator;

[0012] The second input end of the background aging calibration branch is connected to the output end of the current-domain comparator, the input end of the current-domain comparator is connected to the first end of the PMOS-only oscillator, and the second end of the PMOS-only oscillator is connected to the second input end of the aging branch.

[0013] Optionally, the background aging calibration branch includes a dynamic comparator, a counter, a level shifter, a 15 divider, a combinational logic circuit, and a decoder;

[0014] The first input end of the dynamic comparator is connected to the output end of the aging branch, the second input end of the dynamic comparator is connected to the output end of the reference branch, the input end of the counter is connected to the output end of the dynamic comparator, the output end of the counter is connected to the input end of the combinational logic circuit, the output end of the combinational logic circuit is connected to the input end of the decoder, the output end of the decoder is connected to the first input end of the aging branch, and the 15 input end of the divider is connected to the output end of the current-domain comparator, and the 15 output end of the divider is connected to the input end of the level shifter. The first output end of the level shifter is connected to the enable end of the dynamic comparator, and the second output end of the level shifter is connected to the input end of the reference branch.

[0015] Optionally, the level shifter includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0016] The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The gate of the first NMOS transistor is connected to the clock CK’, the gate of the second NMOS transistor is connected to the clock CKB’. The drain of the first NMOS transistor is connected to the drains of the fifth PMOS transistor and the third PMOS transistor and the gate of the fourth PMOS transistor. The drain of the second NMOS transistor is connected to the drains of the fourth PMOS transistor and the seventh PMOS transistor and the gate of the third PMOS transistor. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to a 4-fold mirror current source. The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected to the external enable level EN DIV , the source of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor, the source of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor, and the sources of the sixth PMOS transistor and the eighth PMOS transistor are connected to VDD.

[0017] Optionally, the dynamic comparator includes a signal inverter, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a sixth inverter, and a redundant inverter;

[0018] The signal inverter is controlled by an external control level EN SW and receives the aging branch level at its first input terminal and the reference branch level at its second input terminal. The first output terminal of the signal inverter is connected to the gate of the tenth PMOS transistor, and the second output terminal of the signal inverter is connected to the gate of the eleventh PMOS transistor. The sources of the tenth PMOS transistor and the eleventh PMOS transistor are connected to the drain of the ninth PMOS transistor. The gate of the ninth PMOS transistor is connected to the clock CKB CMP , and the source of the ninth PMOS transistor is connected to a 4-fold mirror current source. The drain of the tenth PMOS transistor is connected to the source of the twelfth PMOS transistor, and the drain of the eleventh PMOS transistor is connected to the source of the thirteenth PMOS transistor. The gates of the twelfth PMOS transistor and the third NMOS transistor are connected to the drains of the thirteenth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor and the input terminal of the sixth inverter. The gates of the thirteenth PMOS transistor and the fifth NMOS transistor are connected to the drains of the twelfth PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor and the input terminal of the redundant inverter. The gates of the fourth NMOS transistor and the sixth NMOS transistor are connected to the clock CKB CMP , and the sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are grounded. The output terminal of the sixth inverter is connected to the counter.

[0019] Optionally, the counter includes a transmission gate, a first-stage second D flip-flop, a second-stage second D flip-flop, a third-stage second D flip-flop, a fourth-stage second D flip-flop, a first AND gate, a first NOR gate, and a second NOR gate;

[0020] The transmission gate is controlled by EN CNT and its input terminal is connected to the output terminal of the sixth inverter in the dynamic comparator. The output terminal of the transmission gate is connected to the CLK terminal of the first-stage second D flip-flop. The D terminal of the first-stage second D flip-flop is connected to its own Q terminal. The Q terminal of the first-stage second D flip-flop is connected to the CLK terminal of the second-stage second D flip-flop. The D terminal of the second-stage second D flip-flop is connected to its The Q terminal of the second D flip-flop of the second stage is connected to the CLK terminal of the second D flip-flop of the third stage, and the D terminal of the second D flip-flop of the third stage is connected to its terminal. The Q terminal of the second D flip-flop of the third stage is connected to the CLK terminal of the second D flip-flop of the fourth stage, and the D terminal of the second D flip-flop of the fourth stage is connected to its terminal. The Q terminal of the second D flip-flop of the fourth stage is connected to the input terminals of the first AND gate and the first NOR gate. The output terminals of the first AND gate and the first NOR gate are connected to the input terminal of the second NOR gate, and the output terminal of the second NOR gate outputs the EN CNT .

[0021] Optionally, the 2 15 -divider includes a divider and a polyphase clock generation circuit.

[0022] Optionally, the divider includes a first inverter and 15 cascaded first D flip-flops.

[0023] Optionally, the polyphase clock generation circuit includes a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, and a third NAND gate;

[0024] The input terminal of the second inverter inputs the high-frequency clock CK N , the output terminal of the second inverter is connected to the first input terminal of the first NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the third NAND gate, the output terminal of the second NAND gate is connected to the input terminal of the fourth inverter and outputs CKB AG ’, the output terminal of the fourth inverter is connected to the second input terminal of the third NAND gate and outputs CK AG ’, the output terminal of the third NAND gate is connected to the input terminal of the fifth inverter and outputs CKB CMP ’, and the output terminal of the fifth inverter outputs CK CMP ’.

[0025] In a resistance aging background calibration circuit for a frequency reference source provided by the present invention, an aging branch is used for calibrating the temperature coefficient of the frequency reference source and generating an aging branch level based on an aging resistor in the aging branch; the aging resistor has an aging phenomenon; a reference branch is used to be controlled by an ultra-low duty cycle clock and generate a reference branch level based on a reference resistor; a background aging calibration branch is used to compare the aging branch level and the reference branch level and feedback and calibrate the resistance value of the aging resistor in the aging branch according to the comparison result. Since the reference branch level of the reference branch is generated based on the ultra-low duty cycle clock generated by the frequency reference source itself, the anti-aging ability of the reference resistor is provided. By adopting a current multiplexing technology, the area of the aging resistor in the aging circuit is reduced compared with the area of the aging resistor in the existing aging circuit, and a small-area, high-energy-efficiency, anti-aging resistance aging background calibration circuit for a frequency reference source is realized.

[0026] The following will further describe the present invention in detail with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of a resistance aging background calibration circuit for a frequency reference source provided by an embodiment of the present invention;

[0028] Figure 2 is a schematic flow diagram of temperature coefficient and resistance background aging calibration provided by an embodiment of the present invention;

[0029] Figure 3 is a schematic structural diagram of a frequency divider and a multi-phase clock generation circuit provided by an embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of input and output waveforms of a frequency divider and a multi-phase clock generation circuit provided by an embodiment of the present invention;

[0031] Figure 5 is a schematic structural diagram of a level shifter provided by an embodiment of the present invention;

[0032] Figure 6 is a schematic structural diagram of a dynamic comparator and a counter provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The following further describes the present invention in detail with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0034] In order to improve the aging calibration ability of the frequency reference source of the existing MCU, an embodiment of the present invention provides a resistance aging background calibration circuit for a frequency reference source. Refer to Figure 1 , Figure 1It is a schematic structural diagram of a resistor aging background calibration circuit for a frequency reference source provided by an embodiment of the present invention. The resistor aging background calibration circuit includes a reference branch, an aging branch, a background aging calibration branch, a PMOS-only oscillator, and a current-domain comparator;

[0035] Among them, the output ends of the reference branch and the aging branch are both connected to the first input end of the background aging calibration branch. The first input end of the aging branch is connected to the first output end of the background aging calibration branch. The second output end of the background aging calibration branch is connected to the input end of the reference branch. The second input end of the background aging calibration branch is connected to the output end of the current-domain comparator. The input end of the current-domain comparator is connected to the first end of the PMOS-only oscillator. The second end of the PMOS-only oscillator is connected to the second input end of the aging branch.

[0036] In the embodiment of the present invention, the aging branch is used for temperature coefficient calibration of the frequency reference source and generates an aging branch level based on the aging resistor in the aging branch; the aging resistor has an aging phenomenon;

[0037] The reference branch is used to generate a reference branch level V REF ;

[0038] The background aging calibration branch is used to compare the aging branch level V AG and the reference branch level V REF , and feedback and calibrate the resistance value of the aging resistor in the aging branch according to the comparison result.

[0039] In the embodiment of the present invention, the aging branch includes a reference current branch and a multiplexed oscillator current branch. The reference current branch provides a mirrored reference current I REF for the multiplexed oscillator current branch, the current-domain comparator, the reference branch, and the background aging calibration branch, reducing the overall power consumption of the circuit. Due to the current multiplexing technology, 1 reference current and 4 oscillator reference currents all flow through the aging resistor R AG , reducing the area of R AG to 1 / 5 of the area of the existing aging resistor. The aging branch current is controlled by signals TCT<3:0>, FT<3:0>, and AT<3:0>. Among them, TCT<3:0> is used to adjust the aspect ratio of the first PMOS transistor M P1 connected in the reference current branch, thereby affecting the temperature coefficient of the reference current I REF ; FT<3:0> adjusts the size of the aging resistor, thereby adjusting the operating frequency of the frequency reference source; after R AG experiences a deviation in resistance value after long-term use, the background aging calibration branch controls AT<3:0> to adjust the resistance value of R AG for calibration.

[0040] Reference branch, controlled by an ultra-low duty cycle clock, generates an aging-resistant resistor R REF and the reference branch level V REF , controlled by signals ENB AG 、ENB AT 、CKB AG 、RRT<3:0> and OST<3:0>, where RRT<3:0> is set to be the same as FT<3:0> to maintain the similarity between the reference branch and the multiplexed oscillator current branch; when ENB AT is turned on, the reference branch performs pre-calibration, continuously adjusts OST<3:0>, and eliminates the V REF 、I REF offset caused by the mismatch of the reference resistor R REF ; ENB AG enables the aging resistor calibration function; CKB AG is an ultra-low duty cycle clock, which significantly reduces the working time of the resistor in the reference branch and improves its anti-aging ability.

[0041] In one implementation, the background aging calibration branch includes a dynamic comparator, a counter, a level converter, a 2 15 divider, a combinational logic circuit, and a decoder;

[0042] Among them, the first input terminal of the dynamic comparator is connected to the output terminal of the aging branch, the second input terminal of the dynamic comparator is connected to the output terminal of the reference branch, the input terminal of the counter is connected to the output terminal of the dynamic comparator, the output terminal of the counter is connected to the input terminal of the combinational logic circuit, the output terminal of the combinational logic circuit is connected to the input terminal of the decoder, the output terminal of the decoder is connected to the first input terminal of the aging branch, and the input terminal of the 2 15 divider is connected to the output terminal of the current domain comparator, and the output terminal of the 2 15 divider is connected to the input terminal of the level converter. The first output terminal of the level converter is connected to the enable terminal of the dynamic comparator, and the second output terminal of the level converter is connected to the input terminal of the reference branch.

[0043] In the embodiment of the present invention, the 2 15 divider is enabled by the signal EN DIV , its input is the clock CK P output by the frequency reference source, and it divides the frequency by 2 15 and outputs, and through a multi-phase clock generation circuit, generates CK CMP ’ with a specific duty cycle, CKB CMP ’, CK AG ’ and CKB AG’ and is used to control the on / off of the dynamic comparator and the reference branch after passing through a level converter; the level converter amplifies the signal swing output by the multi-phase clock generation circuit to rail-to-rail, facilitating the subsequent operation of the digital circuit; the input of the dynamic comparator is the reference branch level V REF and the aging branch level V AG . When the difference between the two reaches the decision threshold of the dynamic comparator, a high-level pulse is output to the counter, and the counter controls AT<3:0> after decoding to calibrate the resistor R AG .

[0044] In the embodiment of the present invention, a counter limiting module is built using combinational logic. When the counter reaches the counting limit, the transmission gate is turned off and the counting is stopped to prevent frequency mutation caused by the mutation of the aging resistor.

[0045] In the embodiment of the present invention, based on the above-mentioned resistor aging background calibration circuit, a temperature coefficient and resistor background aging calibration process is provided. Refer to Figure 2 , Figure 2 which is the schematic diagram of the temperature coefficient and resistor background aging calibration provided by the embodiment of the present invention, as follows:

[0046] First, adjust FT<3:0> at room temperature to change the aging branch current, thereby adjusting the output clock frequency of the frequency reference source. Adjust TCT<3:0> to change the aspect ratio of the first PMOS transistor M P1 in the aging branch. According to the calibration factor (K = |V GS1 | / |V GS2 |), the temperature coefficient of R AG is offset. Readjust FT<3:0> to calibrate the frequency to eliminate the influence of temperature coefficient calibration. Considering the similarity between the multiplexed oscillator current branch and the reference branch, set RRT<3:0> to match FT<3:0>. Then, trim the V REF offset in the reference branch, turn on ENB AT to activate the reference branch, set EN SW to determine the aging direction, continuously set the counter and adjust OST<3:0> until the minimum value that keeps AT<3:0> constant is reached. At this time, V AG ≈V REF , and at this time, the aging pre-calibration is completed. Turn off ENB AT , turn on ENB AG to enable the normal operation of the reference branch, and then set the counter. After R AG continuously works and ages, release the counter setting, and the automatic aging resistor calibration can be achieved.

[0047] In an embodiment of the present invention, the aging branch is used for calibrating the temperature coefficient of the frequency reference source, and generates an aging branch level based on the aging resistor in the aging branch; the aging resistor has an aging phenomenon; the reference branch is used to be controlled by an ultra-low duty cycle clock and generate a reference branch level V based on the reference resistor REF ; the background aging calibration branch is used to, by comparing the aging branch level V AG and the reference branch level V REF , and feedback and calibrate the resistance value of the aging resistor in the aging branch according to the comparison result. Since the reference branch level V REF is generated based on the ultra-low duty cycle clock generated by the frequency reference source itself, the anti-aging ability of the reference resistor is provided. By adopting the current multiplexing technology, the area of the aging resistor in the aging circuit is reduced compared with the area of the aging resistor in the existing aging circuit, and a small-area, high-energy efficiency, anti-aging resistance aging background calibration circuit for the frequency reference source is realized.

[0048] In one implementation, the 2 15 -divider includes a divider and a multi-phase clock generation circuit. The divider and the multi-phase clock generation circuit process the high-frequency clock output by the frequency reference source and convert it into a signal with an extremely high duty cycle and output it to the level converter. See Figure 3 , Figure 3 which is a schematic structural diagram of the divider and the multi-phase clock generation circuit provided by the embodiment of the present invention.

[0049] In one implementation, the divider includes a first inverter INV1 and 15 cascaded first D flip-flops; the multi-phase clock generation circuit includes a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a first NAND gate NAND1, a second NAND gate NAND2, and a third NAND gate NAND3.

[0050] Among them, the CLK terminal of the first-stage first D flip-flop is connected to INV1, the input terminal of INV1 is connected to the high-frequency clock CK output by the first output terminal of the current-domain comparator P , the D terminal of the first-stage first D flip-flop and the terminal are connected, and the output is QB DIV <0>, the positive output terminal is connected to the clock input terminal CLK of the second-stage first D flip-flop, and the output is Q DIV <0>, and so on. 15 D flip-flops are cascaded to obtain Q DIV <14:0> and QB DIV <14:0>, and the reset terminals of all the first D flip-flops are connected to the external enable signal EN DIV . The terminals of the first-stage to fourth-stage first D flip-flops output QB DIV<3:0>, a 4-bit signal, is connected to the second to fourth input terminals of NAND1. The output bits Q of the Q terminals of the first to fifteenth first D flip-flops DIV <4:14>, an 11-bit signal, is connected to the input terminals of an 11-input NAND2. The input terminal of INV2 inputs the high-frequency clock CK output by the frequency reference source N , the output terminal of INV2 is connected to the first input terminal of a 5-input NAND1. The output terminal of NAND1 is connected to the input terminal of INV3. The output terminal of INV3 is connected to the first input terminal of a 2-input NAND3. The output terminal of NAND2 is connected to the input terminal of INV4 and outputs CKB AG ’, the output terminal of INV4 is connected to the second input terminal of NAND3 and outputs CK AG ’, the output terminal of NAND3 is connected to the input terminal of INV5 and outputs CKB CMP ’, the output terminal of INV5 outputs CK CMP ’.

[0051] The above-mentioned frequency divider and polyphase clock generation circuit altogether use 2 times the reference current I REF for power supply, reducing the system power consumption.

[0052] See Figure 4 , Figure 4 is a schematic diagram of the input and output waveforms of the frequency divider and polyphase clock generation circuit provided by the embodiment of the present invention. The frequency reference source outputs a differential clock CK of 32.768 kHz P and CK N , and a frequency divider composed of 15 cascaded first D flip-flops divides it. Among them, Q DIV <0> and QB DIV <0> are the positive and negative outputs of the first D flip-flop of the first stage, which is a divided-by-two clock of CK P . Q DIV <1> and QB DIV <1> are the positive and negative outputs of the second D flip-flop of the second stage, which is a divided-by-four clock of CK P . And so on, the outputs Q DIV <14:0> and QB DIV <14:0> are obtained. Finally, Q DIV <14> is a 1 Hz clock. The polyphase clock generation circuit composed of logic gates performs a NAND operation on Q DIV <14:4> to obtain a 1 Hz clock CKB with a duty cycle AG , and this clock is the aforementioned ultra-low duty cycle clock; perform a NAND operation on CKB N and Q DIV <14:0> to obtain a 1 Hz clock CKB with a duty cycleCMP And CKB AG and CKB CMP are aligned at the rising edge. The low-level duration of CKB AG is 16T, ensuring that the level V of the reference branch REF is fully stable before comparison. CKB CMP turns on the dynamic comparator at low level to compare V AG with V REF .

[0053] In the embodiment of the present invention, the level converter realizes the low-power swing recovery function. Refer to Figure 5 , Figure 5 which is the structural schematic diagram of the level converter provided by the embodiment of the present invention. The level converter includes six high-voltage PMOS transistors M P3～8 and two high-voltage NMOS transistors M N1～2 .

[0054] Specifically, the level converter includes a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a sixth PMOS transistor M P6 , a seventh PMOS transistor M P7 , an eighth PMOS transistor M P8 , a first NMOS transistor M N1 and a second NMOS transistor M N2 .

[0055] Among them, the source electrodes of the first NMOS transistor M N1 and the second NMOS transistor M N2 are both grounded. The gate of M N1 is connected to the clock CK' output by the polyphase clock generation circuit. The gate of M N2 is connected to the clock CKB’ output by the polyphase clock generation circuit. The drain of M N1 is connected to the drains of M P5 , M P3 and the gate of M P4 , and outputs CKB. The drain of M N2 is connected to the drains of M P4 , M P7 and the gate of M P3 , and outputs CK. The source electrodes of M P3 and M P4 are connected to the 4-fold mirror current source of the reference current branch. The gates of M P5 , M P6 , M P7 and M P8 are connected to the external enable level EN DIV , MP5 The source of P6 is connected to the drain of M P7 The source of P8 is connected to the drain of M P6 and M P8 The source is connected to the power supply potential VDD.

[0056] In an embodiment of the present invention, since the frequency divider and the multi-phase clock generation circuit are powered by a reference current and their outputs only have a swing of ~0.7V, in order to quickly output a rail-to-rail clock, the input stage of the level converter uses a pair of NMOS transistors that can flip at a low voltage to increase the output swing, facilitating the operation of subsequent digital circuits.

[0057] See Figure 6 , Figure 6 which is a schematic structural diagram of the dynamic comparator and counter provided by an embodiment of the present invention. The dynamic comparator controlled by CKB CMP includes 1 signal inverter SEL, 5 high-voltage PMOS transistors M P9～13 , 4 high-voltage NMOS transistors M N4～6 and 1 inverter INV6.

[0058] Specifically, the dynamic comparator includes a signal inverter SEL, a ninth PMOS transistor M P9 , a tenth PMOS transistor M P10 , an eleventh PMOS transistor M P11 , a twelfth PMOS transistor M P12 , a thirteenth PMOS transistor M P13 , a third NMOS transistor M N3 , a fourth NMOS transistor M N4 , a fifth NMOS transistor M N5 , a sixth NMOS transistor M N6 and a sixth inverter INV6.

[0059] Among them, SEL is controlled by an external control level EN SW . The first input terminal of SEL inputs the aging branch level V AG , the second input terminal of SEL inputs the reference branch level V REF . The first output terminal of SEL is connected to the gate of M P10 , the second output terminal of SEL is connected to the gate of M P11 . The sources of M P10 and M P11 are connected to the drain of M P9 . The gate of M P9 is connected to the clock CKB CMP output by the level converter. The source of M P9 is connected to a 4-fold mirror current source of the reference branch.P10 The drain of M is connected to P12 the source of M P11 The drain of M is connected to P13 the source of M P12 and M N3 The gate of M is connected to P13 and M N5 and M N6 the drain of M and the input terminal of INV6 P13 and M N5 The gate of M is connected to P12 and M N3 and M N4 the drain of M and the input terminal of the redundant inverter N4 and M N6 The gate of M is connected to the clock CKB output by the level shifter CMP and M N3 and M N4 and M N5 and M N6 The sources of M and M are grounded to the ground level GND, and the output terminal of INV6 is connected to the input terminal of the counter.

[0060] In one implementation, the counter circuit of the counting module includes 1 transmission gate TRAN1, 4 second D flip - flops, 1 AND gate AND1, and two NOR gates NOR 1～2 .

[0061] Specifically, the counter circuit includes a transmission gate TRAN1, a first - stage second D flip - flop, a second - stage second D flip - flop, a third - stage second D flip - flop, a fourth - stage second D flip - flop, a first AND gate AND1, a first NOR gate NOR1, and a second NOR gate NOR2.

[0062] Among them, TRAN1 is controlled by EN CNT . The input terminal of TRAN1 is connected to the output terminal of INV6, and the output terminal of TRAN1 is connected to the input clock CLK of the first - stage second D flip - flop. The input terminal (D terminal) of the first - stage second D flip - flop is connected to its inverted output terminal ( terminal), and its output terminal (Q terminal) is connected to the clock input terminal (CLK terminal) of the second - stage second D flip - flop and outputs Q A <0>. And so on, to achieve a cascade of four - stage second D flip - flops; the D terminal of the second - stage second D flip - flop is connected to its terminal, and the Q terminal of the second - stage second D flip - flop is connected to the CLK terminal of the third - stage second D flip - flop and outputs Q A <1>; the D terminal of the third - stage second D flip - flop is connected to its terminal, and the Q terminal of the third - stage second D flip - flop is connected to the CLK terminal of the fourth - stage second D flip - flop and outputs Q A<2>; The D terminal of the fourth-stage second D flip-flop is connected to its terminal, and the output is Q A <3>; The set terminals Set of all second D flip-flops are connected to the external control level ST, and the counting direction of the counter is controlled by the external signal EN SW The input terminals of the four-input AND gate AND1 and the four-input first NOR gate NOR1 are connected to Q A <3:0>, and the output terminals are connected to the input terminals of the two-input second NOR gate NOR2; The output terminal of NOR2 is EN CNT , which is used to control the opening of TRAN1.

[0063] Specifically, before the circuit starts, first select the corresponding EN according to the aging direction of the resistor R AG , so as to ensure that the dynamic comparator can output a correct high-level pulse after the aging of R SW . For example, when R AG decreases with time, the voltage V of the aging branch AG will continue to decrease. When V AG reaches the decision threshold of the dynamic comparator, the counter detects a high-high level pulse, triggers the background calibration logic, and increases the resistance of R AG . This feedback loop continues until the comparator can no longer sufficiently distinguish V AG and V REF and V AG up to. At the same time, in order to prevent frequency mutation when reaching the counting limit, a limit counting module is added to the counter.

[0064] The above resistor aging background calibration circuit for the frequency reference source realizes the resistor background aging calibration of the fully integrated RC oscillator, greatly reducing the frequency offset problem caused by resistor aging in the frequency reference source. At the same time, the technologies such as current source power supply, level shift, and current multiplexing adopted reduce the power consumption and area of the aging calibration. The resistor aging background calibration circuit provided by the embodiments of the present invention is applicable to the circuit design of frequency reference sources with small area, high energy efficiency, and anti-aging.

[0065] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are only examples of devices and methods consistent with some aspects of the present invention.

[0066] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0067] Although the present invention has been described in connection with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosure. In the description of the present invention, the term "comprising" does not exclude other components or steps, the term "a" or "an" does not exclude a plurality of cases, and the meaning of "a plurality" is two or more, unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0068] In the present invention, unless otherwise clearly defined and limited, terms such as "installed", "connected", "connected to", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0069] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A resistor aging background calibration circuit for a frequency reference source, characterized in that The background calibration circuit for resistor aging includes a reference branch, an aging branch, and a background aging calibration branch; The aging branch is used for calibrating the temperature coefficient of the frequency reference source and generating an aging branch level based on the aging resistor in the aging branch; The aging phenomenon exists in the aging resistor; The reference branch is used to be controlled by an ultra-low duty cycle clock and generate a reference branch level based on the reference resistor in the reference branch; The background aging calibration branch is used to compare the aging branch level and the reference branch level and feedback and calibrate the resistance value of the aging resistor in the aging branch according to the comparison result.

2. The resistor aging background calibration circuit according to claim 1, wherein The background calibration circuit for resistor aging further includes a PMOS-only oscillator and a current domain comparator; The second input end of the background aging calibration branch is connected to the output end of the current domain comparator, the input end of the current domain comparator is connected to the first end of the PMOS-only oscillator, and the second end of the PMOS-only oscillator is connected to the second input end of the aging branch.

3. The back-end calibration circuit for resistor aging according to claim 2, characterized in that, The background aging calibration branch includes a dynamic comparator, a counter, a level shifter, 2 15 frequency dividers, a combinational logic circuit, and a decoder; The first input terminal of the dynamic comparator is connected to the output terminal of the aging branch, the second input terminal of the dynamic comparator is connected to the output terminal of the reference branch, the input terminal of the counter is connected to the output terminal of the dynamic comparator, the output terminal of the counter is connected to the input terminal of the combinational logic circuit, the output terminal of the combinational logic circuit is connected to the input terminal of the decoder, the output terminal of the decoder is connected to the first input terminal of the aging branch, the 2 15 The input terminal of the 2 15 frequency divider is connected to the output terminal of the current-domain comparator, the output terminal of the 2 frequency divider is connected to the input terminal of the level shifter, the first output terminal of the level shifter is connected to the enable terminal of the dynamic comparator, and the second output terminal of the level shifter is connected to the input terminal of the reference branch.

4. The resistor aging background calibration circuit according to claim 3, wherein The level shifter includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The gate of the first NMOS transistor is connected to the clock CK'. The gate of the second NMOS transistor is connected to the clock CKB'. The drain of the first NMOS transistor is connected to the drains of the fifth PMOS transistor and the third PMOS transistor and the gate of the fourth PMOS transistor. The drain of the second NMOS transistor is connected to the drains of the fourth PMOS transistor and the seventh PMOS transistor and the gate of the third PMOS transistor. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to a 4-fold mirror current source. The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected to the external enable level EN DIV , the source of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor, the source of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor, and the sources of the sixth PMOS transistor and the eighth PMOS transistor are connected to VDD.

5. The resistor aging background calibration circuit according to claim 3, wherein The dynamic comparator includes a signal inverter, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a sixth inverter, and a redundant inverter; The signal inverter is controlled by an external control level EN SW The aging branch level is input to the first input terminal of the signal inverter, and the reference branch level is input to the second input terminal of the signal inverter. The first output terminal of the signal inverter is connected to the gate of the tenth PMOS transistor, and the second output terminal of the signal inverter is connected to the gate of the eleventh PMOS transistor. The sources of the tenth PMOS transistor and the eleventh PMOS transistor are connected to the drain of the ninth PMOS transistor. The gate of the ninth PMOS transistor is connected to the clock CKB CMP The source of the ninth PMOS transistor is connected to a 4-fold mirror current source. The drain of the tenth PMOS transistor is connected to the source of the twelfth PMOS transistor. The drain of the eleventh PMOS transistor is connected to the source of the thirteenth PMOS transistor. The gates of the twelfth PMOS transistor and the third NMOS transistor are connected to the drains of the thirteenth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor and the input terminal of the sixth inverter. The gates of the thirteenth PMOS transistor and the fifth NMOS transistor are connected to the drains of the twelfth PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor and the input terminal of the redundant inverter. The gates of the fourth NMOS transistor and the sixth NMOS transistor are connected to the clock CKB CMP The sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are grounded. The output terminal of the sixth inverter is connected to the counter.

6. The background calibration circuit for resistor aging according to claim 3, wherein The counter includes a transmission gate, a first-stage second D flip-flop, a second-stage second D flip-flop, a third-stage second D flip-flop, a fourth-stage second D flip-flop, a first AND gate, a first NOR gate, and a second NOR gate; The transmission gate is controlled by EN CNT The input end of the transmission gate is connected to the output end of the sixth inverter in the dynamic comparator. The output end of the transmission gate is connected to the CLK end of the first-stage second D flip-flop. The D end of the first-stage second D flip-flop is connected to its own end. The Q end of the first-stage second D flip-flop is connected to the CLK end of the second-stage second D flip-flop. The D end of the second-stage second D flip-flop is connected to its own end. The Q end of the second-stage second D flip-flop is connected to the CLK end of the third-stage second D flip-flop. The D end of the third-stage second D flip-flop is connected to its own end. The Q end of the third-stage second D flip-flop is connected to the CLK end of the fourth-stage second D flip-flop. The D end of the fourth-stage second D flip-flop is connected to its own end. The Q end of the fourth-stage second D flip-flop is connected to the input ends of the first AND gate and the first NOR gate. The output ends of the first AND gate and the first NOR gate are connected to the input end of the second NOR gate. The output end of the second NOR gate outputs the EN CNT .

7. The background calibration circuit for resistor aging according to claim 3, characterized in that, The said 2 15 The frequency divider includes a frequency divider and a polyphase clock generation circuit.

8. The back-end calibration circuit for resistor aging according to claim 7, wherein The frequency divider includes a first inverter and 15 cascaded first D flip-flops.

9. The back-end calibration circuit for resistor aging according to claim 8, wherein The multi-phase clock generation circuit includes a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, and a third NAND gate; The input terminal of the second inverter receives the high-frequency clock CK N , the output terminal of the second inverter is connected to the first input terminal of the first NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the third NAND gate, the output terminal of the second NAND gate is connected to the input terminal of the fourth inverter and outputs CKB AG ’, the output terminal of the fourth inverter is connected to the second input terminal of the third NAND gate and outputs CK AG ’, the output terminal of the third NAND gate is connected to the input terminal of the fifth inverter and outputs CKB CMP ’, the output terminal of the fifth inverter outputs CK CMP ’.

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