Parallel CRC error detection device, method and equipment

Abstract

The invention relates to the technical field of data transmission, and provides a parallel CRC error detection device, method and equipment, and the device comprises a signal transmitter which is used for outputting original data; the signal receiver is connected to the signal transmitter and is used for receiving the original data; in the signal transmitter and the signal receiver, each communication channel is provided with a group of parallel CRC detection modules which are used for parallelly calculating CRC check codes corresponding to original data of the signal transmitter and performing consistency judgment so as to determine whether the original data received by the signal receiver are correct or not. Through the technical scheme, the error detection function can be completely realized, the calculation of the CRC check code can be realized at a relatively high speed, and the working efficiency of the system is improved.

Description

Technical Field

[0001] This application relates to the field of data transmission technologies, and in particular, to a parallel CRC error detection device, method, and equipment.

Background Art

[0002] With the development of integrated circuit technologies and the increasing demand for the performance of electronic systems, the data converters (including analog-to-digital converters ADC and digital-to-analog converters DAC) applied in multiple fields such as wired communication, mobile communication, instrumentation, and medical electronics have been operating at an increasingly higher rate, increasing from dozens to hundreds of Msps in previous years to the current level of 10 Gsps. At this speed, the sampling bits have also reached 10 - 14 bits. At such a high speed, traditional parallel CMOS interfaces and LVDS interfaces cannot work due to problems such as a large number of data connection lines and significant data crosstalk. Therefore, the JESD204 series protocol based on high-speed Serdes interfaces emerged, solving the problem of difficult communication for data converters at high speeds.

[0003] JESD204C is the latest publicly available version of the JESD204 series protocol. Compared with the previous version JESD204B, the single-channel rate of JESD204C has been increased from 12.5 Gbps to 32 Gbps, and the encoding method has been changed from 8B10B to 64B66B, making it more suitable for the application scenarios of the high-speed data converters described in the previous paragraph.

[0004] Currently, the structure of the CRC error detection module applied in this protocol is mostly a serial shift error detector based on LFSR or a parallel structure directly derived therefrom. The former requires data to enter and output in a serial manner, demanding a relatively high clock rate for the entire system; while the latter has a large XOR operation array, introducing a relatively high combinational logic delay, which limits the maximum operating speed of the system. If the latter is directly used for CRC error detection in the JESD204C protocol, the operating speed of the system will be restricted.

Summary of the Invention

[0005] Embodiments of this application provide a parallel CRC error detection device, method, and equipment, aiming to solve the technical problems existing in the related art.

[0006] In a first aspect, embodiments of this application provide a parallel CRC error detection device, including:

[0007] A signal transmitter, configured to output original data;

[0008] A signal receiver, connected to the signal transmitter, configured to receive the original data;

[0009] In the signal transmitter and the signal receiver, each communication channel is provided with a group of parallel CRC detection modules for calculating the CRC check code corresponding to the original data of the signal transmitter in parallel and performing consistency judgment to determine whether the original data received by the signal receiver is correct.

[0010] In one embodiment, optionally, the parallel CRC detection module includes a first CRC check circuit, a second CRC check circuit, and a CRC error reporting circuit.

[0011] Among them, the signal transmitter includes a transmitting upper-layer circuit, at least one first CRC check circuit, and a transmitting lower-layer circuit connected in sequence.

[0012] The signal receiver includes a receiving upper-layer circuit, at least one second CRC check circuit, at least one CRC error reporting circuit, and a receiving lower-layer circuit connected in sequence.

[0013] The transmitting upper-layer circuit is configured to output the original data to the first CRC check circuit and the transmitting lower-layer circuit.

[0014] The first CRC check circuit is configured to calculate a first CRC check code within a plurality of clock cycles according to the original data provided by the transmitting upper-layer circuit and output it to the transmitting lower-layer circuit.

[0015] The transmitting lower-layer circuit is configured to transmit the original data and the first CRC check code to the signal receiver via a channel.

[0016] The receiving upper-layer circuit is configured to receive the original data and the first CRC check code, output the original data to the second CRC check circuit and the receiving upper-layer circuit, and output the first CRC check code to the CRC error reporting circuit.

[0017] The second CRC check circuit is configured to calculate a second CRC check code within a plurality of clock cycles according to the original data provided by the receiving upper-layer circuit and output it to the CRC error reporting circuit.

[0018] The CRC error reporting circuit is configured to receive the first CRC check code and the second CRC check code, compare the first CRC check code and the second CRC check code, and output an error signal when the two are inconsistent.

[0019] In one embodiment, optionally, the CRC check circuit includes:

[0020] A plurality of CRC check code generation circuits, where each CRC check code generation circuit generates one-bit CRC output data to form the CRC check code.

[0021] A CRC checksum initialization logic circuit for receiving an EoMB signal and outputting a strobe signal to ensure continuous data operation;

[0022] An output valid signal generation and control circuit connected to the CRC checksum initialization logic circuit for outputting a CRC checksum valid signal.

[0023] In one embodiment, optionally, each CRC checksum generation circuit includes:

[0024] A forward exclusive-OR logic parallel operation unit for receiving parallel data and generating intermediate term data after exclusive-OR logic processing;

[0025] An operation data merging and combining logic unit, the first input end of the operation data merging and combining logic unit is connected to the output end of the forward exclusive-OR logic parallel operation unit, the second input end of the operation data merging and combining logic unit is connected to the feedback exclusive-OR strobe logic unit, and the output end of the operation data merging and combining logic unit is connected to the CRC checksum register for merging the intermediate term data and the feedback signal output by the feedback exclusive-OR strobe logic circuit to generate a complete intermediate result;

[0026] A CRC checksum register for storing the complete intermediate result and outputting it with clock alignment;

[0027] A feedback exclusive-OR strobe logic unit, the first input end of the feedback exclusive-OR strobe logic unit is connected to the output end of the CRC checksum initialization logic unit, the second input end of the feedback exclusive-OR strobe logic unit is connected to the second input end of the operation data merging and combining logic unit, and the output end of the feedback exclusive-OR strobe logic unit is connected to the output end of the CRC checksum register for outputting a feedback signal.

[0028] In one embodiment, optionally, the forward exclusive-OR logic parallel operation unit includes a plurality of exclusive-OR logic nets and D flip-flops, wherein each exclusive-OR logic net corresponds to a D flip-flop, the output end of the exclusive-OR logic net is connected to the input of the D flip-flop, and the output end of the D flip-flop is connected to the operation data merging and combining logic unit.

[0029] For 64-bit input data, the CRC checksum generation circuit includes 12 identical basic operation units. Each operation unit outputs a 1-bit checksum signal, and the checksum output by the CRC checksum generation circuit is formed by splicing 12 operation units. Each operation unit includes the following parts: a forward exclusive-OR logic parallel operation unit, an operation data merging combinational logic unit, a CRC checksum register, a feedback exclusive-OR gating logic unit, a CRC checksum initialization logic unit, and an output valid signal generation and control unit. The working clocks of each module are all from the same source and are synchronous with the 64-bit input data.

[0030] For the CRC checksum generation circuit, the connection relationships and functions of its internal basic units are as follows: The forward exclusive-OR logic parallel operation unit splits dozens of exclusive-OR terms into several different parts (split into 4 parts in the real-time example in the figure) for parallel calculation, thereby reducing the required number of combinational logic levels and improving the operation speed; The CRC checksum register stores the 12-bit intermediate result of each clock cycle, and gives this intermediate result to the operation data merging combinational logic unit in front of the register via the feedback exclusive-OR gating logic unit, and together with the operation result of the forward exclusive-OR logic parallel operation unit, forms the operation result after one clock cycle, and updates the CRC checksum register in the next clock cycle; When all 32 64-bit data specified by the protocol are input, the EoMB signal input by the previous-stage circuit is processed by the CRC checksum initialization logic unit and used as a clear signal through the feedback exclusive-OR gating logic circuit to act on the CRC checksum register, causing it to enter the next working cycle; The peripheral control circuit gives the valid signal of the output data and controls the entire processing process to run in sequence. The result stored in the CRC checksum register is directly output, and the valid signal indicates whether the output result is the finally calculated CRC check result.

[0031] In one embodiment, optionally, the CRC error reporting circuit includes:

[0032] A logic delay unit for delaying the second CRC checksum to align the first CRC checksum and the second CRC checksum;

[0033] A numerical comparator connected to the logic delay unit for numerically comparing the aligned first CRC checksum and the second CRC checksum to determine whether they are the same;

[0034] An output control unit for generating and controlling an error signal.

[0035] In one embodiment, optionally, the output control unit includes:

[0036] An AND gate connected to the numerical comparator for controlling the output result;

[0037] A D flip-flop, connected to the output end of the AND gate, is used to latch and output the output result to output an error signal.

[0038] In one embodiment, optionally, the original data includes 64-bit parallel data, a 64-bit parallel valid signal, and an EoMB signal.

[0039] In a second aspect, an embodiment of the present application provides a parallel CRC error detection method for the parallel CRC error detection device described in any one of the embodiments of the first aspect. The method includes:

[0040] At the signal transmitter end, according to the original data, calculate and output a first CRC check code within multiple clock cycles;

[0041] At the signal receiver end, according to the original data, calculate and output a second CRC check code within multiple clock cycles;

[0042] Align and compare the first CRC check code and the second CRC check code within the same clock cycle to determine whether they are consistent;

[0043] When they are consistent, it is determined that the original data received by the signal receiver is correct; otherwise, it is determined that the original data received by the signal receiver is incorrect, and an error signal is output.

[0044] In a third aspect, a chip device is provided, including the parallel CRC error detection device described in any one of the embodiments of the first aspect.

[0045] In the solutions implemented by the above parallel CRC error detection device, method, and device, at the signal transmitter end, according to the original data, calculate and output a first CRC check code within multiple clock cycles; at the signal receiver end, according to the original data, calculate and output a second CRC check code within multiple clock cycles; align and compare the first CRC check code and the second CRC check code within the same clock cycle to determine whether they are consistent; when they are consistent, it is determined that the original data received by the signal receiver is correct; otherwise, it is determined that the original data received by the signal receiver is incorrect, and an error signal is output. In this way, the function of error detection can be fully realized, and the calculation of the CRC check code can be realized at a relatively high speed, improving the working efficiency of the system.

Description of the Drawings

[0046] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0047] Figure 1 FIG. shows a schematic block diagram of a parallel CRC error detection device according to an embodiment of the present application.

[0048] Figure 2 FIG. shows a schematic diagram of a CRC check circuit in a parallel CRC error detection device according to an embodiment of the present application.

[0049] Figure 3 FIG. shows a schematic diagram of a CRC error reporting circuit in a parallel CRC error detection device according to an embodiment of the present application.

[0050] Figure 4 FIG. shows a schematic diagram of the working timing of a CRC check circuit according to an embodiment of the present application.

[0051] Figure 5 FIG. shows a flowchart of a parallel CRC error detection method according to an embodiment of the present application.

[0052] Among them, 3 represents 64-bit parallel data, 4 represents a 64-bit parallel data valid signal, 5 represents an EoMB signal, 6 represents 12-bit parallel data output by a CRC check code register, 7 represents a CRC check code valid signal, 8 represents a transmitted CRC check code, and 9 represents an error reporting signal.

Specific Embodiments

[0053] To better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0054] It should be clear that the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0055] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the", and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0056] To solve the technical problems such as the limitation of the system working speed caused by using the existing parallel CRC error detection structure in the JESD204C protocol in the related art, the present application proposes a parallel CRC error detection device, method and equipment.

[0057] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0058] Please refer to Figure 1 , Figure 1 FIG. shows a schematic block diagram of a parallel CRC error detection device according to an embodiment of the present application. The parallel CRC error detection device is used to solve the technical problems such as the limitation of the system working speed caused by using the existing parallel CRC error detection structure in the JESD204C protocol in the related art.

[0059] As Figure 1 shown, a parallel CRC error detection device 10 according to an embodiment of the present application includes:

[0060] A signal transmitter 11, configured to output original data;

[0061] In one embodiment, optionally, the original data includes 64-bit parallel data 3, 64-bit parallel valid signal 4, and EoMB signal 5.

[0062] A signal receiver 12, connected to the signal transmitter, configured to receive the original data;

[0063] In the signal transmitter and the signal receiver, a group of parallel CRC detection modules 13 are arranged in each communication channel, configured to calculate the CRC check code corresponding to the original data of the signal transmitter in parallel and perform consistency judgment to determine whether the original data received by the signal receiver is correct.

[0064] In one embodiment, optionally, the parallel CRC detection module 13 includes a first CRC check circuit 131, a second CRC check circuit 132, and a CRC error reporting circuit 133;

[0065] Among them, the signal transmitter 11 includes a transmitting upper layer circuit 111, at least one first CRC check circuit 131, and a transmitting lower layer circuit 112 connected in sequence;

[0066] The signal receiver 12 includes a receiving upper layer circuit 121, at least one second CRC check circuit 132, at least one CRC error reporting circuit 133, and a receiving lower layer circuit 122 connected in sequence;

[0067] The transmitting upper - layer circuit 111 is used to output the original data to the first CRC check circuit 131 and the transmitting lower - layer circuit 112;

[0068] The first CRC check circuit 131 is used to calculate the first CRC check code based on the original data provided by the transmitting upper - layer circuit within multiple clock cycles and output it to the transmitting lower - layer circuit;

[0069] The transmitting lower - layer circuit 112 is used to transmit the original data and the first CRC check code to the signal receiver via a channel;

[0070] The receiving upper - layer circuit 121 is used to receive the original data and the first CRC check code, output the original data to the second CRC check circuit and the receiving upper - layer circuit, and output the first CRC check code to the CRC error reporting circuit 133;

[0071] The second CRC check circuit 132 is used to calculate the second CRC check code based on the original data provided by the receiving upper - layer circuit within multiple clock cycles and output it to the CRC error reporting circuit;

[0072] The CRC error reporting circuit 133 is used to receive the first CRC check code and the second CRC check code, compare the first CRC check code and the second CRC check code, and output an error signal when they are inconsistent.

[0073] Among them, the working clocks of each circuit or module are of the same source and are synchronous with the 64 - bit input data.

[0074] As Figure 2 shown, in one embodiment, optionally, the CRC check circuit (including the first CRC check circuit and the second CRC check circuit) includes:

[0075] A plurality of CRC check - code generating circuits 100, where each CRC check - code generating circuit generates one - bit CRC output data to form the CRC check code;

[0076] The CRC check - code initialization logic circuit 105 is used to receive the EoMB signal and output a gating signal to ensure continuous data operation;

[0077] The output valid signal generating and controlling circuit 106 is connected to the CRC check - code initialization logic circuit and is used to output a CRC check - code valid signal.

[0078] In one embodiment, optionally, each CRC check - code generating circuit 100 includes:

[0079] The forward exclusive-OR logic parallel operation unit 101 is used to receive parallel data and generate intermediate-term data after exclusive-OR logic processing;

[0080] The operation data merging and combining logic unit 102, the first input end of the operation data merging and combining logic unit is connected to the output end of the forward exclusive-OR logic parallel operation unit, the second input end of the operation data merging and combining logic unit is connected to the feedback exclusive-OR gating logic unit, and the output end of the operation data merging and combining logic unit is connected to the CRC check code register, and is used to merge the intermediate-term data and the feedback signal output by the feedback exclusive-OR gating logic circuit to generate a complete intermediate result;

[0081] The CRC check code register 103 is used to store the complete intermediate result and output it with clock alignment;

[0082] The feedback exclusive-OR gating logic unit 104, the first input end of the feedback exclusive-OR gating logic unit is connected to the output end of the CRC check code initialization logic unit, the second input end of the feedback exclusive-OR gating logic unit is connected to the second input end of the operation data merging and combining logic unit, and the output end of the feedback exclusive-OR gating logic unit is connected to the output end of the CRC check code register, and is used to output a feedback signal.

[0083] In one embodiment, optionally, the forward exclusive-OR logic parallel operation unit 101 includes a plurality of exclusive-OR logic wire meshes and D flip-flops, wherein each exclusive-OR logic wire mesh corresponds to a D flip-flop, the output end of the exclusive-OR logic wire mesh is connected to the input of the D flip-flop, and the output end of the D flip-flop is connected to the operation data merging and combining logic unit.

[0084] For 64-bit input data, it includes 12 identical CRC check code generation circuits, each CRC check code generation circuit outputs a 1-bit check code signal, and the check code output by the CRC check code generation circuit is formed by splicing 12 CRC check code generation circuits. Each CRC check code generation circuit includes the following parts: a forward exclusive-OR logic parallel operation unit, an operation data merging and combining logic unit, a CRC check code register, a feedback exclusive-OR gating logic unit, a CRC check code initialization logic unit, and an output valid signal generation and control unit. The working clocks of each module are of the same source and are synchronized with the 64-bit input data.

[0085] For the RC checksum generation circuit, the connection relationships and functions of its internal basic units are as follows: The forward exclusive-OR logic parallel operation unit splits dozens of exclusive-OR terms into several different parts (split into 4 parts in the real-time example in the figure) for parallel calculation, thereby reducing the required number of combinational logic levels and improving the operation speed; The CRC checksum register stores the 12-bit intermediate result of each clock cycle and gives this intermediate result to the operation data merging combinational logic unit in front of the register via the feedback exclusive-OR gating logic unit, and together with the operation result of the forward exclusive-OR logic parallel operation unit, forms the operation result after one clock cycle, and updates the CRC checksum register in the next clock cycle; After all 32 64-bit data specified by the protocol are input, the EoMB signal input by the previous-stage circuit is processed by the CRC checksum initialization logic unit and used as a clear signal through the feedback exclusive-OR gating logic circuit to act on the CRC checksum register, enabling it to enter the next working cycle; The peripheral control circuit gives the valid signal of the output data and at the same time controls the entire processing process to run in sequence. The result stored in the CRC checksum register is directly output, and the valid signal indicates whether the output result is the finally calculated CRC check result.

[0086] Specifically, the connection relationships between the units are obtained through grouping, logic splitting, and logic merging based on the parallel checksum exclusive-OR operation formula derived from the serial CRC calculator based on the LFSR structure provided by the protocol. This operation reduces the combinational logic length of each stage and improves the system operation speed and working efficiency to a certain extent.

[0087] Since there are both input terms and previous state terms in this operation formula and it cannot be directly split in the way of grouping and combining terms, it is necessary to process the feedback part containing the previous state terms. In this embodiment, the feedback part is jointly implemented by the CRC checksum register 103 and the feedback exclusive-OR gating logic unit 104; The remaining operation formula containing only input terms can be implemented by the forward exclusive-OR logic parallel operation unit 101 and the operation data merging combinational logic circuit 102.

[0088] In this embodiment, the previous XOR operation expression is divided into 4 groups, and each group is only responsible for the XOR of some bits in 64 bits. The 64-bit input data generates an intermediate term after XOR logic. This intermediate term is registered and then given to the operation data merging and combining logic unit 102, where it continues to perform an XOR operation with the result of the previous cycle stored in the CRC check code register 103. The operation result is registered in the CRC check code register 103 when the clock arrives, obtaining a 1-bit CRC intermediate result output. The intermediate results of all 12 CRC check code generation circuits together form a 12-bit CRC intermediate result. The CRC check code initialization logic unit 105 receives the EoMB signal 5 and sets the output result of the feedback XOR gating logic circuit 104 to 0 at the second clock edge after this signal becomes valid, so that the first 64-bit data of the next 32 groups of data is XORed with 0, thus ensuring that when the input data is continuously input, the initial value in the CRC check code register 103 is correct in a new calculation cycle, enabling the data to be continuously input without interruption, meeting the basic requirement of the non-interrupted data stream in the JESD204C protocol.

[0089] When the valid signal 4 of the 64-bit data is valid, this signal is fed to the output valid signal generation and control circuit 106, starting to allow the 12 CRC checksum generation circuits to operate, and at the same time allowing the relevant circuits that generate the valid signal to work. Thereafter, whenever an EoMB signal 5 is fed in, the internal state of the circuit will be re-initialized at the second clock edge thereafter, entering a new CRC checksum calculation cycle. The CRC calculation cycle of the CRC check circuit is given by the JESD204C protocol and is 32 groups of 64-bit parallel data, that is, 32 clock cycles. After the CRC check circuit is initialized and the data valid signal 4 is valid, the first group of 64-bit parallel data enters from 3, and the module starts to work, and outputs the intermediate result of the operation after two clock edges. When the 32nd data group arrives, the EoMB is synchronously pulled high, and at the next clock edge, the forward exclusive-OR logic parallel operation unit 101 completes the calculation of the input items; when the next clock cycle arrives, the module will perform four actions: one is that the CRC checksum register 103 acts to store the operation result corresponding to the 32nd data group (that is, the register group of the last data) to the output end, realizing the output of the CRC operation result; the second is that the delayed EoMB signal processed by the CRC checksum initialization logic unit 105 generates a CRC checksum valid signal 7 through the output valid signal generation and control circuit 106 and outputs it, indicating that the current output 12-bit data 6 is the CRC checksum of 32 groups of 64-bit data; the third is that the first group of data of the next 32 groups of 64-bit data enters the forward exclusive-OR logic parallel operation unit 101 and completes the operation of the intermediate result; the fourth is that the delayed EoMB signal acts on the feedback exclusive-OR gating logic circuit 104, making the exclusive-OR gate input end of the operation data merging and combining logic circuit 102 set to 0, and the intermediate result is directly sent to the input 103 of the CRC checksum register. This operation is equivalent to directly clearing the CRC checksum register 103, but this method avoids a cycle of waiting time. Through the above operations, the calculation of the CRC check circuit can be carried out continuously.

[0090] As Figure 3 shown, in one embodiment, optionally, the CRC error reporting circuit 133 includes:

[0091] A logic delay unit 201 for delaying the second CRC checksum to align the first CRC checksum and the second CRC checksum;

[0092] A numerical comparator 202 connected to the logic delay unit for numerically comparing the aligned first CRC checksum and the second CRC checksum to determine whether the two are the same;

[0093] An output control unit for generating and controlling an error signal.

[0094] In one embodiment, optionally, the output control unit includes:

[0095] An AND gate 203, connected to the numerical comparator, for controlling the output result;

[0096] A D flip-flop 204, connected to the output terminal of the AND gate, for latching and outputting the output result to output an error signal.

[0097] In this embodiment, according to the provisions in the JESD204C protocol, the first CRC check code 8 after transmission always arrives later than the calculation result of the second CRC check code in the receiver. Therefore, it is necessary to delay the calculation result 6 and the valid signal of the first CRC check circuit 131 through the logic delay unit 201 to achieve their alignment for the numerical comparator 202 to perform a correct comparison. The AND gate 203 controls the output result to ensure that an error signal is output only when the CRC calculation result 6 is valid; the D flip-flop 204 latches and outputs the foregoing signal, and the AND gate 203 and the D flip-flop 204 jointly generate an error report signal 9.

[0098] The working process of the CRC error reporting circuit 133 will be described in detail below. The CRC check code 8 after transmission given by the receiving upper-layer circuit is directly input to the numerical comparator 202, and the numerical comparator 202 compares it with the calculation result (including intermediate results) of the aligned second CRC check circuit 132. When the two are different, the numerical comparator 202 immediately outputs a high level. Note that at this time, the intermediate result and the CRC check code 8 after transmission are obviously different. Therefore, it is necessary to control the AND gate 203 by the delayed CRC check code enable signal to enable the output result. This circuit avoids outputting an incorrect error report signal; the generated error report signal is latched and output by the D flip-flop 204 to generate a final error report signal 9, which is input to the receiving lower-layer circuit for further processing.

[0099] Specifically, in the signal transmitter, the first CRC check circuit 131 receives the 64-bit data 3 input from the upper-level circuit. When the enabling signal 4 corresponding to this data is valid, the first CRC check circuit 131 starts to work. Under the indication of the EoMB signal 5, it calculates the 12-bit CRC check codes corresponding to 32 groups of 64-bit data. When the EoMB signal 5 is valid, it initializes the CRC check code register 103. At the same time, the output valid signal generation and control circuit 106 generates a CRC check code valid signal 7 corresponding to the 12-bit CRC check code, and together with the 12-bit CRC check code 6, they are fed into the lower-level transmission circuit, completing the process of generating the internal CRC check code of the transmitter implemented in this embodiment. This check code is incorporated into the synchronization header stream corresponding to the next 32 groups of 64-bit data through 64B66B in the TX lower-level circuit to achieve the transmission of the CRC check code word.

[0100] Specifically, as Figure 4 shown, in the receiver, the receiving upper-level circuit divides the decoded 64-bit data 3 and the corresponding enabling signal 4 into two identical paths. One path is fed into the lower-level receiving circuit for subsequent data processing, and the other path is fed into the second CRC check circuit 132 in this embodiment. Under the indication of the EoMB signal 5 recovered from the data by the receiver, it calculates the 12-bit CRC check codes corresponding to the received original 32 groups of 64-bit data. When the EoMB signal 5 is valid, it initializes the CRC check code register 103. At the same time, the output valid signal generation and control circuit 106 generates a CRC check code valid signal 7 corresponding to the 12-bit CRC check code, and together with the 12-bit CRC check code 6, they are fed into the CRC error reporting circuit 133 for further processing. While receiving the 12-bit CRC check code 6 and the corresponding CRC check code valid signal 7, the CRC error reporting circuit 133 decodes the 12-bit transmitted CRC check code 8 from the original data sent by the receiving upper-level circuit. When the CRC check code valid signal 7 is valid, the module operates to compare whether the two paths of CRC check codes are consistent: when they are consistent, the CRC error reporting circuit 133 considers that there is no error in the 32 groups of 64-bit data received by the receiving upper-level circuit; when they are inconsistent, the CRC error reporting circuit 133 considers that the received data has an error and generates an error reporting signal 9 to prompt the lower-level receiving circuit that the data has an error, so that it can perform further processing operations on the received data.

[0101] As can be seen from the above description of the embodiments, a parallel CRC error detection device applicable to the JESD204C protocol provided in this embodiment can complete and implement the CRC error detection and reporting functions required by the JESD204C protocol through the first CRC check circuit 131, the second CRC check circuit 132, and the CRC error reporting circuit 133. At the same time, the CRC check circuit given in this embodiment can calculate the CRC check code at a relatively high speed, thereby improving the working efficiency of the entire JESD204C system.

[0102] Figure 5 The flowchart of a parallel CRC error detection method according to an embodiment of the present application is shown.

[0103] As Figure 5 shown, in a second aspect, an embodiment of the present application provides a parallel CRC error detection method, including:

[0104] Step S501, at the signal transmitter end, calculate and output a first CRC check code according to the original data within a plurality of clock cycles;

[0105] Step S502, at the signal receiver end, calculate and output a second CRC check code according to the original data within a plurality of clock cycles;

[0106] Step S503, align and compare the first CRC check code and the second CRC check code within the same clock cycle to determine whether they are consistent;

[0107] Step S504, when they are consistent, determine that the original data received by the signal receiver is correct, otherwise, determine that the original data received by the signal receiver is incorrect and output an error signal.

[0108] In a third aspect, a chip device is provided, including the parallel CRC error detection device according to any one of the embodiments in the first aspect.

[0109] It should be understood that the term "and / or" used herein is only a relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0110] It should be understood that although the terms first, second, etc. may be used in the embodiments of the present application to describe the setting units, these setting units should not be limited to these terms. These terms are only used to distinguish the setting units from each other. For example, without departing from the scope of the embodiments of the present application, the first setting unit may also be referred to as the second setting unit, and similarly, the second setting unit may also be referred to as the first setting unit.

[0111] Depending on the context, the word "if" as used herein can be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" can be interpreted as "when determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)".

[0112] In several embodiments provided by the present application, it should be understood that the disclosed systems, systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of the system or unit can be in electrical, mechanical or other forms.

[0113] In addition, each functional unit in the various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware, or in the form of a hardware plus a software functional unit.

[0114] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0115] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A parallel CRC error detection device, characterized in that, Comprising: A signal transmitter for outputting original data; A signal receiver connected to the signal transmitter for receiving the original data; In the signal transmitter and the signal receiver, each communication channel is provided with a group of parallel CRC detection modules for calculating in parallel the CRC check codes corresponding to the original data of the signal transmitter and performing consistency judgment to determine whether the original data received by the signal receiver is correct.

2. The parallel CRC error detection device according to claim 1, wherein The parallel CRC detection module includes a first CRC check circuit, a second CRC check circuit, and a CRC error reporting circuit. Wherein, the signal transmitter includes a transmitting upper layer circuit, at least one first CRC check circuit, and a transmitting lower layer circuit connected in sequence; The signal receiver includes a receiving upper layer circuit, at least one second CRC check circuit, at least one CRC error reporting circuit, and a receiving lower layer circuit connected in sequence; The transmitting upper layer circuit is used for outputting original data to the first CRC check circuit and the transmitting lower layer circuit; The first CRC check circuit is used for calculating a first CRC check code within a plurality of clock cycles according to the original data provided by the transmitting upper layer circuit and outputting it to the transmitting lower layer circuit; The transmitting lower layer circuit is used for transmitting the original data and the first CRC check code to the signal receiver via a channel; The receiving upper layer circuit is used for receiving the original data and the first CRC check code, outputting the original data to the second CRC check circuit and the receiving upper layer circuit, and outputting the first CRC check code to the CRC error reporting circuit; The second CRC check circuit is used for calculating a second CRC check code within a plurality of clock cycles according to the original data provided by the receiving upper layer circuit and outputting it to the CRC error reporting circuit; The CRC error reporting circuit is used for receiving the first CRC check code and the second CRC check code, comparing the first CRC check code and the second CRC check code, and outputting an error signal when they are inconsistent.

3. The parallel CRC error detection device according to claim 1, wherein The CRC check circuit includes: A plurality of CRC check code generation circuits, wherein each CRC check code generation circuit generates one-bit CRC output data to form the CRC check code; A CRC check code initialization logic circuit for receiving an EoMB signal and outputting a gating signal to ensure continuous data operation; An output valid signal generation and control circuit connected to the CRC check code initialization logic circuit for outputting a CRC check code valid signal.

4. The parallel CRC error detection device according to claim 3, characterized in that, Each CRC check code generation circuit includes: A forward exclusive OR logic parallel operation unit for receiving parallel data and generating intermediate term data after exclusive OR logic processing; An operation data merging and combining logic unit, the first input end of the operation data merging and combining logic unit is connected to the output end of the forward exclusive-OR logic parallel operation unit, the second input end of the operation data merging and combining logic unit is connected to the feedback exclusive-OR gating logic unit, and the output end of the operation data merging and combining logic unit is connected to the CRC checksum register, which is used to merge the intermediate term data and the feedback signal output by the feedback exclusive-OR gating logic circuit to generate a complete intermediate result; A CRC checksum register, which is used to store the complete intermediate result and perform clock alignment output; A feedback exclusive-OR gating logic unit, the first input end of the feedback exclusive-OR gating logic unit is connected to the output end of the CRC checksum initialization logic unit, the second input end of the feedback exclusive-OR gating logic unit is connected to the second input end of the operation data merging and combining logic unit, and the output end of the feedback exclusive-OR gating logic unit is connected to the output end of the CRC checksum register, which is used to output a feedback signal.

5. The parallel CRC error detection device according to claim 4, wherein, The forward exclusive-OR logic parallel operation unit includes a plurality of exclusive-OR logic nets and D flip-flops. Among them, each exclusive-OR logic net corresponds to a D flip-flop. The output end of the exclusive-OR logic net is connected to the input of the D flip-flop, and the output end of the D flip-flop is connected to the operation data merging and combining logic unit.

6. The parallel CRC error detection device according to claim 1, characterized in that, The CRC error reporting circuit includes: A logic delay unit, which is used to delay the second CRC checksum to align the first CRC checksum and the second CRC checksum; A numerical comparator, which is connected to the logic delay unit, and is used to numerically compare the aligned first CRC checksum and the second CRC checksum to determine whether they are the same; An output control unit, which is used to generate and control an error signal.

7. The parallel CRC error detection device according to claim 1, wherein The output control unit includes: An AND gate, which is connected to the numerical comparator and is used to control the output result; A D flip-flop, which is connected to the output end of the AND gate and is used to beat the output result to output an error signal.

8. The parallel CRC error detection device according to claim 1, characterized in that, The original data includes 64-bit parallel data, 64-bit parallel valid signals, and EoMB signals.

9. A parallel CRC error detection method, characterized in that, For the parallel CRC error detection device according to any one of claims 1 to 8, the method includes: At the signal transmitter end, calculate and output the first CRC checksum according to the original data within a plurality of clock cycles; At the signal receiver end, calculate and output the second CRC checksum according to the original data within a plurality of clock cycles; Align and compare the first CRC checksum and the second CRC checksum in the same clock cycle to determine whether they are the same; When they are the same, determine that the original data received by the signal receiver is correct, otherwise, determine that the original data received by the signal receiver is incorrect and output an error signal.

10. A chip device, characterized in that, Includes: The parallel CRC error detection device according to any one of claims 1 to 8.

Images