Reinforced server mainboard managed by OpenBMC based on FPGA chip

Abstract

The invention belongs to the technical field of server mainboards, and particularly relates to a reinforced server mainboard based on OpenBMC management of an FPGA chip, the reinforced server mainboard comprises a CPU module, an FPGA chip module and a DCDC power supply module, the CPU module is connected with the FPGA chip module, and the FPGA chip module is connected with the DCDC power supply module; the FPGA chip module is provided with a PS end and a PL end, the PS end and the PL end are connected through an internal bus to perform data interaction, online loading of a program of the PL end is realized through the internal bus, and the PS end is provided with a plurality of resource interfaces; the PL end is provided with a plurality of GPIO (General Purpose Input / Output) resource interfaces and a plurality of analog IIC (Inter-Integrated Circuit) resource interfaces, and the PL end controls the DCDC power supply module through a power supply control signal; and the PL end controls the CPU module through the module control state signal. The FPGA chip module replaces a BMC and a CPLD as two independent chips, so that the circuit design of the board card is simplified, the reliability is improved, the physical space of the board card is saved, and the cost of a single board is saved.

Description

Technical Field

[0001] The invention belongs to the technical field of server mainboards, and in particular relates to a reinforced server mainboard managed by OpenBMC based on an FPGA chip. Background Art

[0002] With the development and maturity of Internet of Things technology, the demand for high-reliability reinforced servers in some harsh environments is increasing. In order to achieve such a high-reliability and high-performance reinforced server, the design requirements for the core CPU motherboard of the reinforced server are also more complex. At present, the motherboard design of general servers uses a dedicated BMC chip to manage the entire system of the server, and uses 1-2 CPLDs to complete the power timing control of the motherboard, external interface management, etc. Since BMC and CPLD are two independent chips that exist on the motherboard at the same time, they need to provide their own separate power supplies and necessary peripheral circuits, so they occupy a large physical space and have a high cost. Especially in the field of reinforced servers, the motherboard space of the current common 6UVPX standard architecture is very limited, and saving space has become very necessary.

[0003] As the steward of the server system, the BMC chip monitors and manages the server in many aspects, such as monitoring the operation status, recording events and performing fault analysis, deploying and configuring the system, and providing a series of other remote management functions. BMC supports the industry standard IPMI specification, provides NCSI interface, and can monitor and manage many peripherals through multiple IIC interfaces.

[0004] Therefore, how to simplify the board circuit design, save the board physical space and save the cost of the single board while increasing the reliability of the motherboard, is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the present invention is to provide a reinforced server motherboard managed by OpenBMC based on FPGA chip, so as to simplify the circuit design of the board, increase the reliability of the motherboard, save the physical space of the board, and save the cost of the single board.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0007] A reinforced server motherboard managed by OpenBMC based on FPGA chip, comprising a CPU module, an FPGA chip module and a DCDC power module, wherein the CPU module is connected to the FPGA chip module, and the FPGA chip module is connected to the DCDC power module;

[0008] The FPGA chip module is provided with a PS side and a PL side. The PS side and the PL side are connected through an internal bus for data interaction, and the online loading of the program on the PL side is realized through the internal bus. The PS side is provided with a plurality of resource interfaces;

[0009] The PL side is provided with a plurality of GPIO resource interfaces and a plurality of analog IIC resource interfaces. The PL side controls the DCDC power module through a power control signal;

[0010] The PL side controls the CPU module through a module control status signal.

[0011] Preferably, the resource interfaces of the PS side include LPC, IPMB, UART, NCSI, SPI, RGMII, QPSI, CAN, and USB.

[0012] Preferably, the FPGA chip module migrates the OpenBMC module to the FPGA chip module platform by means of transplantation.

[0013] Preferably, the OpenBMC module includes an OpenBMC image, and the OpenBMC image includes a bootloader, a Linux operating system kernel, and a software package for a specific board.

[0014] Preferably, the OpenBMC module has three layers, including a general layer, a Soc layer, and a circuit board layer. The general layer includes software packages for different circuit boards and BMC-Socs. The Soc layer contains codes related to system startup and operation including u-boot and kernel. The circuit board layer includes initialization scripts and tools exclusive to different circuit boards.

[0015] Preferably, the specific process of migrating the OpenBMC module to the FPGA chip module platform by means of transplantation is as follows:

[0016] Set up a cross-compilation environment, copy the folder of the OpenBMC module to bashrc and update the environment variables;

[0017] Enter the u-boot folder, clear the configuration file and compilation intermediate results, reconfigure to generate makefile, compile the specified tools required for development, and compile the kernel to generate ulmage;

[0018] Perform kernel compilation, and after the kernel compilation, call the compiled device tree compilation tool in the specified file in the kernel folder;

[0019] Compile and install the kernel module, update the file system, generate a startup image file, and set the u-boot environment variables.

[0020] Preferably, the OpenBMC module is provided with a remote server management module, and the remote server management module includes a KVM server side and a client interaction module;

[0021] When the OpenBMC module runs, the KVM server side starts. When the server receives a KVM request, the VGA driver and I / O driver in the BMC intercept the corresponding startup interface data and I / O data of the server motherboard, and then send the startup interface data and I / O data to the network driver module. The network driver module transmits the startup interface data and I / O data to the client interaction module through the network card;

[0022] The client interaction module adopts a KVM digital interaction method and performs remote control based on a web interface. After the client sends a KVM request, it downloads the corresponding application program to the local and communicates with the BMC through the application program.

[0023] The beneficial effects of the present invention include:

[0024] The rugged server motherboard based on OpenBMC management provided by the present invention includes a CPU module, an FPGA chip module, and a DCDC power module. The CPU module is connected to the FPGA chip module, and the FPGA chip module is connected to the DCDC power module; the FPGA chip module is provided with a PS side and a PL side, and the PS side and the PL side are connected through an internal bus for data interaction, and the online loading of the program on the PL side is realized through the internal bus. The PS side is provided with a plurality of resource interfaces; the PL side is provided with a plurality of GPIO resource interfaces and a plurality of analog IIC resource interfaces, and the PL side controls the DCDC power module through a power control signal; the PL side controls the CPU module through a module control status signal. By replacing the functions of the BMC and CPLD as two independent chips with the FPGA chip module, the board circuit design is simplified, the reliability is increased, the physical space of the board is saved, and the cost of a single board is saved.

[0025] First, the BMC chip in the prior art requires more IIC interfaces to manage components. The present invention realizes this through the PL side logic to simulate the IIC interface. The PS side and the PL side perform data interaction through the internal bus, and the PS side can complete the online loading of the program on the PL side through the internal bus. Use the PL side of the Zynq series of FPGAs to replace the CPLD chip to complete the control of the motherboard CPU module, DCDC power supply, etc.

[0026] Secondly, the OpenBMC module sets up a remote server management module, and the remote server management module includes a KVM server side and a client interaction module. When the OpenBMC module runs, the KVM server side starts. When the server receives a KVM request, the VGA driver and I / O driver in the BMC intercept the corresponding startup interface data and I / O data of the server motherboard, and then send the startup interface data and I / O data to the network driver module. The process of the driver module transmitting the startup interface data and I / O data to the client interaction module through the network card greatly reduces energy consumption, lightens the burden of motherboard design, eliminates the need for hardware line switching, facilitates transplantation and user operation, and only one BMC can replace the traditional connector output.

[0027] Thirdly, the Zynq7000 of the present invention completes the information interaction between the PS side (BMC) and the PL side (CPLD) through the internal bus, and can directly update the PL segment program online through the network, which is more convenient to use, simplifies the motherboard design circuit, saves PCB area and wiring resources, and has a lower cost advantage. Brief Description of the Drawings

[0028] Figure 1 It is the architecture structure diagram of the ruggedized server motherboard managed by OpenBMC based on the FPGA chip of the present invention.

[0029] Figure 2 It is the schematic diagram of the principle of transplanting the OpenBMC module of the present invention to the FPGA chip module platform. Detailed Description of the Invention

[0030] The following Figures 1 to 2 further details the present invention:

[0031] Embodiment 1

[0032] See the appendix Figure 1As shown in the figure, a rugged server motherboard based on OpenBMC management with an FPGA chip includes a CPU module, an FPGA chip module, and a DCDC power module. The CPU module is connected to the FPGA chip module, and the FPGA chip module is connected to the DCDC power module. The FPGA chip module is provided with a PS side and a PL side, which are connected through an internal bus for data interaction, and the online loading of the PL side program is realized through the internal bus. The PS side is provided with multiple resource interfaces. The PL side is provided with multiple GPIO resource interfaces and multiple analog IIC resource interfaces. The PL side controls the DCDC power module through a power control signal. The PL side controls the CPU module through a module control status signal. The resource interfaces of the PS side include LPC, IPMB, UART, NCSI, SPI, RGMII, QPSI, CAN, and USB.

[0033] In this embodiment, for the rugged server motherboard based on OpenBMC management with an FPGA chip of the present invention, the PS side (i.e., ARM) of the Zynq series of FPGAs is used to replace the BMC chip. The PS side has common resources such as UART, IIC, SPI, QPSI, CAN, USB, and RGMII, which basically meet the functional requirements of the BMC chip. Generally, a BMC chip requires more IIC interfaces to manage components, which can be realized by logically simulating the IIC interface on the PL side. The PS side and the PL side perform data interaction through the internal bus, and the PS side can complete the online loading of the PL side program through the internal bus. The PL side (i.e., FPGA) of the Zynq series of FPGAs is used to replace the CPLD chip to control the motherboard CPU module, DCDC power supply, etc. At the same time, taking advantage of the portability of OpenBMC, OpenBMC is transplanted to the Zynq7000 platform. Through the remote server management method of OpenBMC, the power consumption is greatly reduced, the burden of motherboard design is alleviated, there is no need for hardware line switching, it is convenient for transplantation and user operation, and only one BMC can replace the output of traditional connectors.

[0034] Embodiment 2

[0035] Based on Embodiment 1, the OpenBMC module is transplanted onto the FPGA chip module platform by transplantation. The OpenBMC module includes an OpenBMC image, and the OpenBMC image includes a bootloader, a Linux operating system kernel, and software packages for specific boards. The OpenBMC module has three layers, including a general layer, a Soc layer, and a circuit board layer. The general layer includes software packages for different circuit boards and BMC-Socs. The Soc layer contains code related to system startup and operation, including u-boot and kernel. The circuit board layer includes initialization scripts and tools exclusive to different circuit boards. By means of the Soc layer structure, the length of the connection lines between IC devices in the FPGA chip module is improved, thereby greatly reducing the signal transmission delay between the CPU and peripherals. Within the Soc layer, due to the lower impedance of the heterogeneous computing functional components, the flip delay of logic gates is reduced.

[0036] In this embodiment, the specific process of transplanting the OpenBMC module onto the FPGA chip module platform by transplantation is as follows: Set up a cross-compilation environment, copy the folder of the OpenBMC module to bashrc and update the environment variables; Enter the u-boot folder, clear the configuration file and compilation intermediate results, reconfigure to generate a makefile, compile the specified tools required for development, and compile the kernel to generate an ulmage; Perform kernel compilation, and after kernel compilation, call the compiled device tree compilation tool in the specified file under the kernel folder; Compile and install kernel modules, update the file system, generate a startup image file, and set the u-boot environment variables.

[0037] Embodiment 3

[0038] Based on Embodiment 1 or Embodiment 2, the OpenBMC module is provided with a remote server management module, and the remote server management module includes a KVM server-side and a client interaction module.

[0039] When the OpenBMC module runs, the KVM server-side starts. When the server receives a KVM request, the VGA driver and I / O driver in the BMC intercept the corresponding startup interface data and I / O data of the server motherboard, and then send the startup interface data and I / O data to the network driver module. The network driver module transmits the startup interface data and I / O data to the client interaction module through the network card; The client interaction module adopts the KVM digital interaction method and performs remote control based on the web interface. After the client sends a KVM request, it downloads the corresponding application program to the local and communicates with the BMC through the application program.

[0040] In summary, the rugged server motherboard based on OpenBMC management with an FPGA chip provided by the present invention includes a CPU module, an FPGA chip module, and a DCDC power module. The CPU module is connected to the FPGA chip module, and the FPGA chip module is connected to the DCDC power module. The FPGA chip module is provided with a PS side and a PL side, which are connected by an internal bus for data interaction and the online loading of the program on the PL side is achieved through the internal bus. The PS side is provided with multiple resource interfaces. The PL side is provided with multiple GPIO resource interfaces and multiple analog IIC resource interfaces. The PL side controls the DCDC power module through a power control signal. The PL side controls the CPU module through a module control status signal. By using the FPGA chip module to replace the functions of the BMC and CPLD as two independent chips, the circuit design of the board is simplified, the reliability is increased, the physical space of the board is saved, and the cost of a single board is saved.

[0041] The present invention is implemented by the PL side logically simulating the IIC interface. The PS side and the PL side perform data interaction through the internal bus, and the PS side can complete the online loading of the program on the PL side through the internal bus. The PL side of the Zynq series FPGA is used to replace the CPLD chip to complete the control of the motherboard CPU module, DCDC power supply, etc., avoiding the need for a large number of IIC interfaces in the existing BMC chip to manage components. By setting a remote server management module through the OpenBMC module, the remote server management module includes a KVM server side and a client interaction module. When the OpenBMC module runs, the KVM server side starts. The server receives a KVM request. The VGA driver and I / O driver in the BMC intercept the corresponding startup interface data and I / O data of the server motherboard, and then send the startup interface data and I / O data to the network driver module. The process of the driver module transmitting the startup interface data and I / O data to the client interaction module through the network card greatly reduces the energy consumption, reduces the burden of the motherboard design, does not require hardware line switching, is convenient for transplantation and user operation, and a single BMC can replace the output of a traditional connector. The Zynq7000 of the present invention completes the information interaction between the PS side (BMC) and the PL side (CPLD) through the internal bus, and the program on the PL segment can be updated online directly through the network, which is more convenient to use. The circuit design of the motherboard is simplified, the PCB area and wiring resources are saved, and it has a lower cost advantage.

Claims

1. A rugged server motherboard based on OpenBMC management with an FPGA chip, characterized in that, It includes a CPU module, an FPGA chip module, and a DCDC power module. The CPU module is connected to the FPGA chip module, and the FPGA chip module is connected to the DCDC power module; The FPGA chip module is provided with a PS side and a PL side. The PS side and the PL side are connected through an internal bus for data interaction, and the online loading of the PL side program is realized through the internal bus. The PS side is provided with multiple resource interfaces; The PL side is provided with multiple GPIO resource interfaces and multiple analog IIC resource interfaces. The PL side controls the DCDC power module through a power control signal; The PL side controls the CPU module through a module control status signal.

2. The rugged server motherboard for OpenBMC management based on an FPGA chip according to claim 1, wherein, The resource interfaces of the PS side include LPC, IPMB, UART, NCSI, SPI, RGMII, QPSI, CAN, and USB.

3. The rugged server motherboard for OpenBMC management based on the FPGA chip according to claim 1, wherein, The FPGA chip module migrates the OpenBMC module to the FPGA chip module platform by means of migration.

4. The rugged server motherboard for OpenBMC management based on an FPGA chip according to claim 3, wherein The OpenBMC module includes an OpenBMC image, and the OpenBMC image includes a bootloader, a Linux operating system kernel, and a software package for a specific board.

5. A rugged server motherboard for OpenBMC management based on an FPGA chip according to claim 3, characterized in that, The OpenBMC module has three layers, including a general layer, a Soc layer, and a circuit board layer. The general layer includes software packages for different circuit boards and BMC-Socs. The Soc layer contains codes related to system startup and operation including u-boot and kernel. The circuit board layer includes initialization scripts and tools exclusive to different circuit boards.

6. The rugged server motherboard for OpenBMC management based on an FPGA chip according to claim 3, wherein, The specific process of migrating the OpenBMC module to the FPGA chip module platform by means of migration is as follows: Set up a cross-compilation environment, copy the folder of the OpenBMC module to bashrc and update the environment variables; Enter the u-boot folder, clear the configuration file and the intermediate compilation results, reconfigure to generate a makefile, compile the specified tools required for development, and compile the kernel to generate an ulmage; Perform kernel compilation, and after the kernel compilation, call the compiled device tree compilation tool in a specified file in the kernel folder; Compile and install kernel modules, update the file system, generate a startup image file, and set u-boot environment variables.

7. The rugged server motherboard for OpenBMC management based on an FPGA chip according to claim 3, wherein The OpenBMC module is provided with a remote server management module, and the remote server management module includes a KVM server side and a client interaction module; When the OpenBMC module runs, the KVM server side starts. When the server receives a KVM request, the VGA driver and I / O driver in the BMC intercept the corresponding startup interface data and I / O data of the server motherboard, and then send the startup interface data and I / O data to the network driver module. The network driver module transmits the startup interface data and I / O data to the client interaction module through the network card; The client interaction module adopts the KVM digital interaction method and conducts remote control based on the web interface. After the client sends a KVM request, it downloads the corresponding application program to the local and communicates with the BMC through the application program.

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