Chip RTL code processing method, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a chip RTL code processing method, electronic equipment and a medium, and the method comprises the following steps: S1, obtaining a composition module set and an RTL file set corresponding to a to-be-processed IP; s2, traversing the code lines of the Fn line by line, if the current code line is the port information line, extracting the port information of the Mn, and if the current code line is the sub-module information line of the Mn, obtaining the sub-module interconnection information of the corresponding Mn in the Mn, and executing the step S3 after traversing; and S3, if only the port information exists in the Mn, determining the Mn as a minimum composition unit, generating Mn target data information based on the port information of the Mn, and if the port information and the sub-module interconnection information exist in the Mn, determining the Mn as a non-minimum composition unit, and generating Mn target data information based on the port information of the Mn and the sub-module interconnection information of the Mn. According to the invention, the chip development efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chips, and in particular, to a method for processing chip RTL code, an electronic device, and a medium. Background Art

[0002] In chip design and development, third-party IP (Intellectual Property) is usually introduced. The information corresponding to the third-party IP usually only includes RTL (Register Transfer Level) code. In the process of chip design and verification, users usually construct a data structure corresponding to each chip component module, and implement automated processes such as chip design and verification based on the corresponding data structure. During the processing, when encountering a third-party IP, since there is no corresponding data structure for the third IP, the automated processes such as chip design and verification cannot be implemented, reducing the chip development efficiency. It can be seen from this that how to extract information from the third-party IP, construct a corresponding data structure, implement automation such as chip design and verification, and improve chip development efficiency has become a technical problem to be solved urgently. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for processing chip RTL code, an electronic device, and a medium, which improves the chip development efficiency.

[0004] According to the first aspect of the present invention, there is provided a method for processing chip RTL code, including:

[0005] Step S1, obtaining a set of component modules {M1, M2,..., M n ,..., M N} and a set of RTL files {F1, F2,..., F n ,..., F N} corresponding to the IP to be processed, where M n is the nth component module of the IP to be processed, the value range of n is from 1 to N, N is the total number of component modules corresponding to the IP to be processed, the multiple component modules of the IP to be processed are hierarchically arranged, and F n is the RTL file corresponding to M n ;

[0006] Step S2, traversing the code lines of F n line by line. If the current code line is a port information line, extract the port information of M n . If the current line is a sub-module information line of M n , obtain the sub-module interconnection information of M n corresponding to M n in M

[0007] Step S3, if Mn If only port information exists, then determine M n As the minimum component unit, based on the port information of M n Generate the target data information of M n If M n has port information and sub-module interconnection information, then determine M n As a non-minimum component unit, based on the port information of M n and the sub-module interconnection information of M n generate the target data information of M n .

[0008] According to the second aspect of the present invention, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the first aspect of the present invention.

[0009] According to the third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions for executing the method described in the first aspect of the present invention.

[0010] The present invention has obvious advantages and beneficial effects compared with the prior art. By means of the above technical solutions, a chip RTL code processing method, an electronic device and a medium provided by the present invention can achieve considerable technical progressiveness and practicality, and have broad industrial utilization value. It has at least the following beneficial effects:

[0011] By traversing and analyzing the code lines of the IP to be processed, the present invention can reversely extract the target data information of the data structure corresponding to each chip component module constructed by the user, so that the third-party IP also has the same data structure as other chip component modules, facilitating the realization of automated processes such as chip design and verification, and improving the chip development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0013] Figure 1 It is a flowchart of the chip RTL code processing method provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0015] An embodiment of the present invention provides a method for processing chip RTL code, as Figure 1 shown, including:

[0016] Step S1, obtain the set of component modules {M1, M2,..., M n ,..., M N} corresponding to the IP to be processed and the set of RTL files {F1, F2,..., F n ,..., F N}, where M n is the nth component module of the IP to be processed, the value range of n is from 1 to N, N is the total number of component modules corresponding to the IP to be processed, the multiple component modules of the IP to be processed are hierarchically arranged, and F n is the RTL file corresponding to M n .

[0017] Among them, the IP to be processed is a third-party IP that only includes RTL code. The IP to be processed includes N component modules, and the N component modules are hierarchically arranged. The top-level component module corresponding to the IP to be processed has no parent module, the component module corresponding to the smallest component unit in the IP to be processed has no sub-module, and the other component modules in the IP to be processed have parent modules and sub-modules. Each component module of the IP to be processed corresponds to an RTL file, and the RTL file of the parent component module depends on the RTL file of the sub-component module.

[0018] Step S2, traverse the code lines of F n line by line. If the current code line is a port information line, extract the port information of M n . If the current line is a sub-module information line of M n , obtain the sub-module interconnection information of M n corresponding to M n in M

[0019] Among them, for each F n of the IP to be processed, step S2 needs to be executed. In order to improve the processing efficiency, it can be set to be executed in parallel. It can be understood that if there are multiple IPs to be processed, steps S1 - S3 can also be executed in parallel for the multiple IPs to be processed.

[0020] Step S3, if M nIf only port information exists, then determine M n as the minimum component unit, and generate M n target data information based on the port information of M n If M n has both port information and sub-module interconnection information, then determine M n as a non-minimum component unit, and generate M n target data information based on the port information of M n and the sub-module interconnection information of M n .

[0021] It should be noted that if M n only has port information, it means that there are no sub-modules in M n , so it can be determined that M n is the minimum component unit. The minimum component unit only needs to extract the port information and does not need to extract the internal information of the minimum unit. If M n has both port information and sub-module interconnection information, it means that M n is not the minimum component unit, but a component module composed of the interconnection of the minimum component unit or other component modules. Therefore, the target data information of M n requires both the port information of M n and the sub-module interconnection information of M n .

[0022] As an embodiment, F n ={L1 n ,L2 n ,...,L x n ,...,L f(n) n},where L x n is the x-th line of code of F n , and the value range of x is from 1 to f(n), where f(n) is the number of lines of code of F n . The step S2 includes:

[0023] Step S21: Initially set x = 1.

[0024] Step S22: If there is a preset port identifier in L x n , then execute step S23; if there is a preset sub-module identifier in L x n , then execute step S24; otherwise, execute step S27.

[0025] Among them, the preset port identifier can specifically be "port", and the preset sub-module identifier can specifically be "submodule". If neither the preset port identifier nor the preset sub-module identifier exists in the code line, it means that there is no information to be extracted in this code line, and it can be skipped directly.

[0026] Step S23: Extract the port name and port direction from L x n and store them in the preset port information cache database M n in the corresponding port list, and execute step S26.

[0027] It should be noted that when storing the port name and port direction in the preset port information cache database, a mapping relationship between the component module name, port name, and port direction will be established simultaneously, specifically in the form of the port list corresponding to M n for storage.

[0028] Step S24: Determine whether there is a port list of the sub-module of M n in the current cache database. If it exists, execute step S26; otherwise, execute step S25.

[0029] It should be noted that if the code file of the sub-module of M n has been processed, then there is already a port list of the sub-module of M n in the current cache database, and it can be directly reused. If it does not exist, the code file of the sub-module of M n needs to be adjusted to be processed first, which is specifically implemented through step S25.

[0030] Step S25: Determine the RTL file of the sub-module of M n based on the file path of the sub-module of M n , parse and obtain the port list of the sub-module of M n and store it in the cache database.

[0031] It should be noted that the port list of the sub-module of M n can be stored in the cache database, and the port list of the sub-module of M n can be read from the cache database in step S26, or it can be directly provided to step S26, but it also needs to be stored in the cache database. In this way, when processing the code file of the sub-module of M n , there is no need to repeatedly process the code file corresponding to the port, improving the code file processing efficiency.

[0032] Step S26: Read the port list of the sub-module of M n from the cache database to generate M nThe corresponding M n The sub-module interconnection information {W1 n , W2 n ,..., W y n ,..., W g(n) n}}, W y n Is the y-th interconnection information corresponding to the sub-module of M n , where the value range of y is from 1 to g(n), and g(n) is the total number of sub-module interconnection information of M n W y n = (W1 y n , W2 y n , W3 y n ), W1 y n Is the y-th port direction corresponding to W y n , W2 y n Is the port name of the corresponding sub-module of M n , W3 y n Is the port name interconnected with W2 y n .

[0033] It should be noted that W y n Is the interconnection information set based on the angle of the sub-module of M n . The port directions include input, output, inout. If W1 y n Is input, it means the signal is transmitted from W3 y n To W2 y n . If W2 y n Is output, it means the signal is transmitted from W2 y n To W3 y n . If W1 y n Is inout, it means the signal is transmitted bidirectionally between W2 y n , W3 y n .

[0034] Step S27: If x = f(n), then execute Step S3; if x < f(n), then set x = x + 1 and return to Step S22.

[0035] It should be noted that, in order to further improve the processing efficiency, Q preset code lines in F can be read each time, and f(n) in Steps S21 - S27 is replaced with Q for processing. When the processing is completed, another Q preset code lines are read, and f(n) in Steps S21 - S27 is replaced with Q for processing until all the code lines in F are processed. n n are processed.

[0036] As an embodiment, in Step S26, W y n also includes W4 y n , and W4 y n is the signal list corresponding to W y n , or is the bus generated based on the signal list corresponding to W y n , and specifically can be the AXI (Advanced eXtensible Interface) bus that follows the AXI protocol.

[0037] As an embodiment, in order to further improve the processing efficiency of the code file, for each F n Step S2 is executed in parallel. Step S22 further includes that if L x n has been processed, then execute Step S27. It can be understood that when Step S25 is executed, there will be a situation where some code related to ports in the code file has been processed in advance. In order to avoid repeated processing, save computing resources, and improve the processing efficiency, therefore, the processed code can be marked, and when the executed code has been processed, it can be directly skipped.

[0038] As an embodiment, in Step S3, the target data information of the minimum component unit includes the minimum component unit name and the port list, and the port list includes the port name and the port direction. The target data information of the non - minimum component unit includes the non - minimum component unit name, the port list, the sub - module name, and the sub - module interconnection information.

[0039] ​Taking a system-on-chip (SOC) including third-party IP as an example, non-third-party IPs in the SOC chip can all pre-establish target data information. After the third-party IP has established the target data information based on steps S1 - S3, it is possible to ensure that all component modules in the SOC chip have target data information with a consistent structure, thereby enabling an automated process in chip design and chip verification.

[0040] As an embodiment, during the process from chip logic layer design to physical design, the interconnection relationship between the smallest component units is kept unchanged, and other chip component modules are reorganized based on physical placement and routing. Specifically, after step S3, the following steps are further included:

[0041] Step S4: Obtain the target data information corresponding to the logic layer SOC chip containing the IP to be processed. The target data information corresponding to the logic layer SOC chip includes the target data information corresponding to each component module in the logic layer SOC chip, and the IP to be processed is a component module in the logic layer SOC chip.

[0042] It can be understood that the target data information corresponding to the IP to be processed is generated based on steps S1 - S3.

[0043] Step S5: Extract all the names of the smallest component units and the interconnection relationship between the smallest units from the target data information corresponding to the logic layer SOC chip.

[0044] It should be noted that the target data information corresponding to the logic layer SOC chip contains the interconnection relationship between all component modules and clearly marks which component modules are the smallest component units. Therefore, all the names of the smallest component units and the interconnection relationship between the smallest units can be quickly and accurately extracted.

[0045] Step S6: Generate physical grouping information for the smallest component units based on the physical placement and routing information.

[0046] It should be noted that based on the physical placement and routing, the target placement position of the smallest component units can be determined, thereby enabling physical grouping of the smallest component units.

[0047] Step S7: Group the smallest component units during the physical placement and routing process based on the physical grouping information of the smallest component units, and construct a physical interconnection based on the interconnection relationship between the smallest units to generate a physical layer SOC chip.

[0048] It should be noted that during the process from the logical layer to the physical layer, the interconnection relationship between the minimum constituent units remains unchanged. Therefore, after grouping, each group is a constituent module of the physical layer, and the constituent modules of the physical layer are also hierarchical. Based on the interconnection relationship between the minimum constituent units, corresponding ports are also generated on the constituent modules of the physical layer, and the interconnection between the minimum constituent units is constructed on the physical layer, thereby generating a physical layer SOC chip to achieve the recombination process.

[0049] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, and so on.

[0050] An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiments of the present invention.

[0051] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, and the computer instructions are used to execute the method described in the embodiments of the present invention.

[0052] By traversing and analyzing the code lines of the IP to be processed, the embodiment of the present invention can reversely extract the target data information of the data structure corresponding to each chip constituent module constructed by the user, so that the third-party IP can also have the same data structure as other chip constituent modules, facilitating the realization of automated processes such as chip design and verification, and improving the chip development efficiency.

[0053] As described above, the above are only preferred embodiments of the present invention, and there is no any form of limitation to the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or variations equivalent to the equivalent embodiments within the scope of the technical solution of the present invention without departing from the technical solution of the present invention. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for processing chip RTL code, characterized in that Comprising: Step S1: Obtain the set of component modules {M1, M2,..., M n ,..., M N} and the set of RTL files {F1, F2,..., F n ,..., F N}, where M n is the nth component module of the IP to be processed, the value range of n is from 1 to N, and N is the total number of component modules corresponding to the IP to be processed. The multiple component modules of the IP to be processed are hierarchically arranged. F n is the RTL file corresponding to M n ; Step S2: Traverse the code lines of F line by line. If the current code line is a port information line, extract the port information of M. If the current line is a sub-module information line of M, obtain the corresponding sub-module interconnection information of M in M. After the traversal is completed, execute Step S3; n If the current code line is a port information line, extract the port information of M n If the current line is a line of sub-module information of M n obtain the sub-module information of M n and the corresponding sub-module interconnection information of M in M n After the traversal is completed, execute Step S3; Step S3. If M n only has port information, then determine that M n is the minimum component unit, and generate the target data information of M n based on the port information of M. If M n has both port information and sub-module interconnection information, then determine that M n is not the minimum component unit, and generate the target data information of M n based on the port information of M n and the sub-module interconnection information of M n . n The target data information of M 2. The method according to claim 1, wherein: F n = {L1 n , L2 n ,..., L x n ,..., L f(n) n}, L x n is the x-th line of code of F n , where the value range of x is from 1 to f(n), and f(n) is the number of lines of code of F n , and the step S2 includes: Step S21: Initially set x = 1; Step S22: If there is a preset port identifier in L x n , then execute Step S23. If there is a preset sub-module identifier in L x n , then execute Step S24. Otherwise, execute Step S27; Step S23: Extract the port name and port direction from L x n and store them in the preset port information cache database M n In the corresponding port list, execute Step S26; Step S24: Determine whether there is an M in the current cache database n in the port list of the sub-module. If so, execute Step S26; otherwise, execute Step S25; Step S25: Determine the RTL file of the sub-module of M n based on the file path of the sub-module of M n Parse and obtain the port list of the sub-module of M n and store it in the cache database; Step S26: Read M from the cache database n Generate M from the port list of the sub-module n The corresponding M in n The sub-module interconnection information {W1 n , W2 n ,..., W y n ,..., W g(n) n}, where W y n Is the y-th interconnection information corresponding to the sub-module of M n , and the value range of y is from 1 to g(n), where g(n) is the total number of sub-module interconnection information of M n The sub-module interconnection information total number, W y n =(W1 y n , W2 y n , W3 y n ), where W1 y n Is the y-th port direction corresponding to W y n , W2 y n Is the port name of the corresponding sub-module of M n , and W3 y n Is the port name interconnected with W2 y n ; Step S27: If x = f(n), then execute Step S3; if x < f(n), then set x = x + 1 and return to Step S22.

3. The method according to claim 2, wherein: In step S26, W y n also includes W4 y n , and W4 y n is the signal list corresponding to W y n , or is a bus generated based on the signal list corresponding to W y n ​ 4. The method according to claim 2, wherein: For each F n Execute step S2 in parallel, and step S22 further includes that if L x n has been processed, then execute step S27.

5. The method according to claim 1, wherein: In the said Step S3, the target data information of the minimum component unit includes the minimum component unit name and the port list, and the port list includes the port name and the port direction; the target data information of the non - minimum component unit includes the non - minimum component unit name, the port list, the sub - module name, and the sub - module interconnection information.

6. The method according to claim 5, wherein: After the said Step S3, it further includes: Step S4: Obtain the target data information corresponding to the logic - layer SOC chip containing the IP to be processed. The target data information corresponding to the logic - layer SOC chip includes the target data information corresponding to each component module in the logic - layer SOC chip, and the IP to be processed is a component module in the logic - layer SOC chip; Step S5: Extract all the minimum component unit names and the interconnection relationships between the minimum units from the target data information corresponding to the logic - layer SOC chip; Step S6: Generate the physical grouping information of the minimum component units based on the physical layout and routing information; Step S7: Group the minimum component units during the physical layout and routing process based on the physical grouping information of the minimum component units, and construct physical interconnections based on the interconnection relationships between the minimum units to generate the physical - layer SOC chip.

7. An electronic device, characterized in that, Comprising: At least one processor; And a memory communicatively connected to the at least one processor; Wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method according to any one of the preceding claims 1 - 6.

8. A computer-readable storage medium, characterized in that, Stores computer - executable instructions for executing the method according to any one of the preceding claims 1 - 6.

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