Error frame reproduction method, electronic equipment and storage medium

Abstract

The invention relates to the technical field of electronic design automation, and provides an error frame reproduction method, electronic equipment and a storage medium, and the method comprises the steps: firstly, obtaining a process configuration file corresponding to each frame stored in a regression process under the condition of an EDA regression error, and reading a target configuration file corresponding to the error frame from the process configuration file, each frame comprising the error frame; and performing error frame reproduction based on the target configuration file corresponding to the error frame. According to the method, wrong frame reproduction is carried out through the target configuration file corresponding to the wrong frame, so that a scene with a regression error can be reproduced timely and accurately without depending on an environment and seeds, reproduction failure easily caused by a traditional method is avoided, time cost is saved, and reproduction efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular, to a method for reproducing misaligned frames, an electronic device, and a storage medium. Background Art

[0002] The verification work of large-scale integrated circuit design is of great significance for ensuring the functional correctness of the chip, and regression testing runs through the entire chip verification process.

[0003] In the related art, for the scenario where regression fails, the corresponding excitation is randomly generated by a seed to drive the Register Transfer Level (RTL) for reproduction. However, since the operating environment is in a continuous development state, the excitation randomly generated by the seed during reproduction is inconsistent with the excitation when regression fails, resulting in the problem that the regression failure cannot be reproduced normally. Summary of the Invention

[0004] The present invention provides a method for reproducing misaligned frames, an electronic device, and a storage medium, so as to solve the defect that the problem of regression failure in the prior art cannot be reproduced normally.

[0005] The present invention provides a method for reproducing misaligned frames, including: In the case of EDA regression failure, obtain the process configuration files corresponding to each frame stored during the regression process, and read the target configuration file corresponding to the misaligned frame from the process configuration files, where each frame includes the misaligned frame; Reproduce the misaligned frame based on the target configuration file corresponding to the misaligned frame.

[0006] According to the method for reproducing misaligned frames provided by the present invention, the process configuration files corresponding to each frame include relevant process parameters generated and recorded frame by frame when using a seed to drive RTL for regression.

[0007] According to the method for reproducing misaligned frames provided by the present invention, the reproducing the misaligned frame based on the target configuration file corresponding to the misaligned frame includes: Use the target configuration file corresponding to the misaligned frame as an excitation and input it to the RTL; Start the RTL to reproduce the misaligned frame.

[0008] According to the method for reproducing misaligned frames provided by the present invention, the construction process of the process configuration files corresponding to each frame includes: Obtain the bus driving timing recorded in real time during the EDA regression process; Divide the bus driving timing into frames to obtain the process configuration files corresponding to each frame.

[0009] According to the misframe reproduction method provided by the present invention, the bus driving timing is divided into frames to obtain a process configuration file corresponding to each frame, including: Obtain the fixed configuration parameters recorded in real time during the EDA regression process; Divide the bus driving timing and the fixed configuration parameters into frames respectively to obtain a process configuration file corresponding to each frame.

[0010] According to the misframe reproduction method provided by the present invention, the bus driving timing includes the initial phase of AXI and the bus interface timing signal of AXI.

[0011] According to the misframe reproduction method provided by the present invention, the obtaining of the bus driving timing recorded in real time during the EDA regression process includes: Record the bus driving timing in the EDA regression process according to a fixed bit width.

[0012] According to the misframe reproduction method provided by the present invention, the reading of the target configuration file corresponding to the misframe from the process configuration file includes: Obtain the frame number when the EDA regression goes wrong, and based on the frame number, read the target configuration file corresponding to the misframe pointed to by the frame number from the configuration file.

[0013] The present invention also provides a misframe reproduction device, including: A misframe recognition unit, configured to obtain the process configuration file corresponding to each frame stored during the regression process and read the target configuration file corresponding to the misframe from the process configuration file in case of an error in the EDA regression, and each frame includes the misframe; A misframe reproduction unit, configured to reproduce the misframe based on the target configuration file corresponding to the misframe.

[0014] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the misframe reproduction method as described in any one of the above is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the misframe reproduction method as described in any one of the above is implemented.

[0016] The present invention also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the misframe reproduction method as described in any one of the above is implemented.

[0017] In the case of an error in the EDA regression, the present invention first obtains the process configuration files corresponding to each frame stored during the regression process, and reads the target configuration file corresponding to the error frame from the process configuration files. Each frame includes the error frame. Then, the error frame is reproduced based on the target configuration file corresponding to the error frame. This method reproduces the error frame through the target configuration file corresponding to the error frame, which can not only reproduce the regression error scenario in a timely and accurate manner without relying on the environment and seeds. Moreover, only the error frame needs to be directly reproduced during the reproduction process, without starting from frame 0, thus saving time costs and improving the reproduction efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 is a schematic flowchart of the error frame reproduction method provided by the present invention.

[0020] Figure 2 is a schematic structural diagram of the error frame reproduction device provided by the present invention.

[0021] Figure 3 is a schematic structural diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0023] In the process of chip verification, electronic design automation (EDA) regression is a very necessary step. The types of EDA regression can include version iteration regression and random sufficiency regression, etc.

[0024] Considering the efficiency of regression verification, the existing EDA regression mechanism usually does not use a monitor to monitor the signal-level activities of the chip, nor does it display the waveform diagram of the signal spectrum distribution, that is, the process of dumping waveforms is not performed.

[0025] For the scenario where regression fails, the existing mechanism for reproducing EDA regression problems usually first generates stimuli randomly according to the operating environment and logic code during regression, as well as the seed when regression fails, to drive the RTL. Then, to ensure that the stimuli randomly generated by the seed are consistent with the stimuli when regression fails, by turning on the monitor, running from the first frame according to the operating process during regression, and performing the process of dumping waveforms to generate waveforms until the simulation stops when reaching the position where regression fails, which is convenient for design positioning.

[0026] Among them, for the stimuli randomly generated by the seed to be consistent with the configuration when regression fails, the conditions to be satisfied are that the logic versions are the same, the environment versions are the same, and other parameters when regression fails are the same. If the above conditions are not met, there may be differences between the two. However, since the operating environment is in a continuous development state, changes in the operating environment or logic code may both cause changes in the range of stimuli or constraints randomly generated by the seed, resulting in the stimuli randomly generated by the seed being inconsistent with the stimuli when regression fails, and it cannot be guaranteed that the configuration when regression fails is being run, thus possibly leading to the failure of reproducing the problem when regression fails.

[0027] In addition, for chip regression verification involving frame-by-frame debugging / display, the current reproduction mechanism needs to run from the beginning when reproducing, that is, running from the 0th frame may make the number of scenarios covered by the randomly generated stimuli consistent with the number of scenarios covered by the stimuli when regression fails. Running from the beginning has two problems. One is that the time cost is large, and the generated waveform data is large, occupying a large amount of memory. The other is that running from the beginning will run all the frames that have been compared correctly before, resulting in low reproduction efficiency. Moreover, the scenarios covered by the stimuli randomly generated by the seed will also affect the development of the operating environment, and adding new variables, etc. will increase or decrease the number of random scenarios.

[0028] In summary, the current reproduction mechanism for EDA regression problems has problems such as possible failure to reproduce successfully, long running time, large memory occupation, and affecting environment development.

[0029] To solve at least one of the above problems, an out-of-frame reproduction method that can be applied to efficiently reproduce EDA regression problems is provided in an embodiment of the present invention, which can surely reproduce the corresponding waveforms, and can only run out the out-of-frame, reproduce the problem faster, and does not affect the iterative development of the operating environment.

[0030] Figure 1 The flowchart of an out-of-frame reproduction method provided by an embodiment of the present invention is as Figure 1 shown. The method includes: S1, in the case of EDA regression failure, obtain the process configuration files corresponding to each frame stored during regression, and read the target configuration file corresponding to the out-of-frame from the process configuration files. Each frame includes the out-of-frame; S2, reproduce the misaligned frame based on the target configuration file corresponding to the misaligned frame.

[0031] Specifically, the misaligned frame reproduction method provided by the embodiments of the present invention can be applied to scenarios that require integrated circuit design verification. The execution subject can be an electronic device such as a terminal device, a computer, a server, a server cluster, or a specially designed misaligned frame reproduction device, or a verification device provided in the electronic device. The verification device can be implemented by software, hardware, or a combination of both.

[0032] First, execute step S1. When an EDA regression error occurs, obtain the process configuration files corresponding to each frame stored during the regression process.

[0033] It can be understood that in the embodiments of the present invention, during the EDA regression process, a set of seeds can be randomly generated, incentives can be generated based on the seeds, and the incentives can be input into the RTL description to drive the RTL for regression.

[0034] Here, a random number generator (such as a pseudo-random number generator) can be used to generate one or more random seeds, and each seed corresponds to a unique scenario.

[0035] It should be noted that if the environment changes, it may affect the number of random scenarios, and ultimately the scenarios that the same seed may generate may be different.

[0036] Therefore, in this embodiment, during the regression verification / test process, the process data of the regression verification can be recorded as the process configuration file. The process data is the process configuration parameters for the incentive to drive the RTL. These process configuration parameters can include fixed configuration parameters generated in advance through algorithms, or parameters generated in real time when the incentive drives the RTL.

[0037] In some examples, since the incentive is usually associated with registers, interfaces, and signals in the RTL description. Therefore, for example, the above-recorded process configuration parameters may include one or more of register configuration, image data, bus interface timing signals and initial phases of the Advanced Extensible Interface (AXI), clock, reset, etc.

[0038] Among them, the register configuration can be the correct register configuration generated in advance by an algorithm. During the regression process, the seed can generate this register configuration, and subsequently, the register configuration can be stored as one of the process configuration parameters.

[0039] The above RTL description is the RTL description of the Design under Test (DUT), which can be obtained by writing, or can be directly obtained as pre-written. The RTL description can include its interface definition, register mapping, signal connection, etc. The generated stimulus can be input into the RTL description by writing a testbench, which is responsible for providing stimulus to the RTL during simulation and capturing its response.

[0040] In the chip regression verification involving frame-by-frame debugging / display, when driving the RTL, the environment will output the stimulus generated by the seed in units / formats of frames. Therefore, it can be recorded frame by frame during the regression process and output in the form of a file, such as a text file, binary file, or database record. For example, the process configuration file can be a Bin format file, so as to obtain the process configuration files corresponding to each frame respectively, that is, each frame has a corresponding process configuration file.

[0041] Here, a unique frame number can be assigned to each frame, and the frame number can be added to the corresponding process configuration file to make the process configuration file correspond to the frame number one by one. Alternatively, the frame number can be added to the log during regression verification, and each frame has a corresponding frame number and a corresponding process configuration file.

[0042] After that, the process configuration files corresponding to each frame are stored for reproducing the wrong frame when an error occurs in the EDA regression.

[0043] After obtaining the process configuration files corresponding to each frame, the target configuration file corresponding to the wrong frame can be read from the process configuration files corresponding to each frame.

[0044] The wrong frame refers to the data frame that goes wrong or does not meet the expectations during the EDA regression process, and there can be one or more wrong frames. During the EDA regression process, the error information that appears can be recorded, and this error information can be included in the log. The error information can include one or more of the information such as the time point of the error, frame number, error type, and relevant data.

[0045] If the error information contains a frame number, the frame corresponding to the frame number contained in the error information is the wrong frame. If there is no clear frame number in the error information, the wrong frame is inferred based on the time point of the error and the logic of the test script.

[0046] Furthermore, the process configuration file containing the frame number of the wrong frame can be selected from the process configuration files of each frame as the target configuration file. If there are multiple wrong frames, there are also multiple target configuration files.

[0047] Then, step S2 is executed to reproduce the misaligned frame by using the target configuration file corresponding to the misaligned frame. The misaligned frame reproduction is a process of reproducing the scenario where the regression has problems. Here, the EDA regression process can be re-run using the target configuration file to achieve misaligned frame reproduction.

[0048] It should be noted that during reproduction, the driving data (incentive) of the RTL can be configured using the target configuration file corresponding to the misaligned frame, so as to directly reproduce the current misaligned frame by running the RTL, thereby avoiding problems such as instability of the seed-dependent environment and the need to start running from frame 0, which wastes a large amount of time cost.

[0049] The misaligned frame reproduction method provided by the embodiment of the present invention reproduces the misaligned frame through the target configuration file corresponding to the misaligned frame, which can not only reproduce the scenario where the regression goes wrong in a timely and accurate manner, without relying on the environment and seeds, but also avoid the reproduction failure caused by the traditional method due to environmental changes, not running all frames in sequence, and logic version changes. Moreover, during the reproduction process, only the misaligned frame needs to be directly reproduced, without starting to run from frame 0, thus saving time cost and improving the reproduction efficiency.

[0050] Based on the above embodiment, the process configuration file corresponding to each frame includes relevant process parameters generated and recorded frame by frame when using the seed to drive the RTL for regression.

[0051] Specifically, when starting the EDA regression process, the relevant process parameters generated by the randomly generated seed can be recorded to form a process configuration file.

[0052] For example, during EDA regression, the macro definition can be turned on. After configuring the register using the seed, the register configuration can be stored as relevant process parameters; when loading the image data into the DDR, the image data can be stored as relevant process parameters; when the AXI verification bus vip (Verification IP) feeds back the rdy (ready) and vld (valid) signals, the bus interface timing signals of each channel, such as the rdy and vld signals, can be stored as relevant process parameters.

[0053] In addition, the above process parameters can be saved as files in units of frames to form the process configuration file corresponding to each frame until the regression goes wrong and the simulation exits.

[0054] During reproduction, the configuration of the misaligned frame where the regression goes wrong can be read, that is, the target configuration file corresponding to the misaligned frame, and then the configuration at the time of regression error can be used as the incentive and input to the RTL description. Subsequently, the RTL can be directly started to run the simulation for misaligned frame reproduction.

[0055] After the wrong frame reproduction causes a logic error, the simulation will automatically exit. The waveform corresponding to the reproduced wrong frame can be fed back to the designer to confirm the reason for the appearance of the wrong frame. Thus, it no longer depends on the environment and seeds, but directly calls the current configuration of the regression when the wrong frame occurs to achieve waveform reproduction.

[0056] In the embodiment of the present invention, it is defined that the process configuration file corresponding to each frame includes relevant process parameters generated and recorded frame by frame when using seeds to drive RTL for regression, thereby providing a basis for the subsequent wrong frame reproduction process, and can significantly improve the efficiency and reliability of wrong frame reproduction.

[0057] In some examples, the wrong frame reproduction based on the target configuration file corresponding to the wrong frame includes: Taking the target configuration file corresponding to the wrong frame as an incentive and inputting it into the RTL; Starting the RTL to perform wrong frame reproduction.

[0058] Specifically, when performing wrong frame reproduction, a new case for reproduction can be created first. In this case, the target configuration file corresponding to the wrong frame where the error occurs can be found using the frame number, and then the relevant process configuration parameters in the target configuration file can be read. Subsequently, after converting the format to conform to the format of the RTL, it is used as an incentive and poured into the RTL. Further, the frame start register can be configured to start the RTL for simulation, thereby being able to reproduce the wrong frame.

[0059] Among them, the key relevant process configuration parameters for reproduction can be read from the target configuration file as an incentive. For example, the non-fixed configuration - bus driving timing can be read and converted into a format suitable for RTL description.

[0060] Format conversion can include operations such as data type conversion and data structure adjustment. Further, the relevant process configuration parameters after format conversion can be saved as a new file, and the file format can include text files (such as.txt,.dat), binary files (such as.bin), or formats specific to the verification environment (such as.vmem,.mif, etc.).

[0061] Specify the input path of the new file in the RTL description, input the new file into the RTL description, and load the new file into the verification environment to run.

[0062] In the embodiment of the present invention, by using the target configuration file corresponding to the wrong frame as an incentive to drive the RTL for wrong frame reproduction, which matches the source of the content in the process configuration file, the stability of wrong frame reproduction can be ensured.

[0063] On the basis of the above embodiment, the construction process of the process configuration file corresponding to each frame includes: Obtain the bus drive timing recorded in real time during the EDA regression process; Divide the bus drive timing by frame to obtain the process configuration file corresponding to each frame.

[0064] Specifically, the relevant process parameters in the process configuration file corresponding to each frame can all include the bus drive timing recorded in real time when driving the RTL for regression. This bus drive timing refers to various bus signals at each time point involved in data transmission, which is used to ensure the integrity and correctness of the transmitted data.

[0065] Therefore, when constructing the process configuration file corresponding to each frame, the bus drive timing recorded in real time during the EDA regression process can be obtained first, and then the bus drive timing recorded in real time is divided by frame to obtain the process configuration file corresponding to each frame.

[0066] In this embodiment, the bus drive timing, which is a non-fixed configuration parameter, can be printed in a fixed format. For example, based on the minimum time period of the bus interface timing of AXI, the non-fixed configuration can be printed and saved in a fixed format in real time.

[0067] Specifically, first, the timing requirements of the AXI bus need to be clarified, such as the clock cycle, the timing relationship of the handshake signals (VALID and READY), etc. Determine the minimum time period of the AXI bus interface according to the timing requirements of the AXI bus, that is, the minimum unit time of data transmission.

[0068] Monitor the timing signals of the AXI bus interface in real time, including the state changes of the VALID and READY signals. When it is detected that the VALID signal is high, it indicates that there is an effective data transmission, and at this time, data should be prepared to be read. Within the minimum time period of the AXI bus interface, read the non-fixed configuration data from the corresponding register or memory. Format the read non-fixed configuration data according to the pre-designed fixed format. During the formatting process, information such as timestamps and configuration item names can be added to facilitate subsequent analysis and processing. Print and save the formatted data to the console or log file in real time.

[0069] The above fixed format can be pre-set, which helps to ensure the consistency and readability of the printed information and is convenient for subsequent analysis and processing. For example, the phase and delay of the clock are formed into a Bin file with 12 bits as a group of data and printed with a fixed bit width.

[0070] In the embodiment of the present invention, the process configuration file corresponding to each frame includes the key signal of the bus drive timing, avoiding saving the entire frame of RTL waveform for wrong frame reproduction, and being able to improve the reproduction efficiency and accuracy at a lower cost.

[0071] Based on the above embodiments, dividing the bus driving timing in units of frames to obtain the process configuration file corresponding to each frame includes: Obtain the fixed configuration parameters recorded in real time during the EDA regression process; Divide the bus driving timing and the fixed configuration parameters in units of frames respectively to obtain the process configuration file corresponding to each frame.

[0072] Specifically, the relevant process parameters in the process configuration file corresponding to each frame may include, in addition to the bus driving timing, fixed configuration parameters.

[0073] Here, the fixed configuration parameters refer to the configuration information that is preset in the system or device and is not easy or does not need to be frequently changed. The fixed configuration parameters usually remain unchanged during the operation of the system.

[0074] The fixed configuration parameters may include image data and register configuration. The register configuration refers to the settings of the hardware registers used to store specific control information or status information. The register configuration determines the behavior or status of some parts of the system, such as the clock frequency, interrupt enable, etc.

[0075] Therefore, when constructing the process configuration file corresponding to each frame, the fixed configuration parameters recorded in real time during the EDA regression process can also be obtained, and then the bus driving timing and the fixed configuration parameters recorded in real time are divided in units of frames to obtain the process configuration file corresponding to each frame.

[0076] During the implementation of the solution, the structure and format of the frame can be defined according to the specific content of the fixed configuration parameters and the non-fixed configuration parameters. The structure of the frame should include a frame header (including information such as frame number, timestamp, etc.), a fixed configuration parameter area, a non-fixed configuration parameter area, and a frame tail, etc.

[0077] It should be noted that for the fixed configuration parameters, each frame corresponds to a set of image data and a set of register configurations; for the non-fixed configuration parameters, the minimum time period of the AXI bus interface timing also needs to be concerned. For example, if the timing duration of 1 frame is two minimum unit times, then during the process of generating the phase and timing signals in real time, 2 sets of phase and timing signals will be generated.

[0078] In the embodiments of the present invention, the process configuration file corresponding to each frame includes both the bus driving timing and the fixed configuration parameters, which can avoid the dependence of the wrong frame reproduction process on the environment and does not need to start running from frame 0 again, thus saving time costs and improving the reproduction efficiency.

[0079] In addition, it should be noted that, compared with fixed configuration parameters, the bus driving timing will change with the change of the operating environment to adapt to different operating requirements. Therefore, the bus driving timing can be referred to as non-fixed configuration parameters. Furthermore, the relevant process parameters can include fixed configuration parameters and non-fixed configuration parameters. By dividing the relevant process parameters into fixed configuration parameters and non-fixed configuration parameters, the implementation scenario of the image chip and the regression verification scenario are considered, which can improve the completeness of misframe reproduction.

[0080] Based on the above embodiments, the bus driving timing includes the initial phase of AXI and the bus interface timing signals of AXI.

[0081] Specifically, AXI is an advanced interface standard for connecting a processor and other components within a system, supporting high-performance and high-bandwidth data transmission. The AXI interface provides flexible connection and configuration options, supporting data transmission between multiple master devices and slave devices. The initial phase of AXI refers to the clock phase at the start of data transmission. The initial phase determines the starting point of data transmission and is one of the key factors to ensure correct data transmission.

[0082] The bus interface timing signals of AXI refer to various timing signals generated by the AXI interface during data transmission, such as the valid signal (VALID), the ready signal (READY), etc. These timing signals are used to coordinate data transmission between the master device and the slave device to ensure the correctness and integrity of the data.

[0083] In the embodiments of the present invention, by jointly constructing the process configuration file corresponding to each frame through the initial phase of AXI and the bus interface timing signals of AXI, the correctness and integrity of misframe reproduction can be guaranteed.

[0084] Based on the above embodiments, the obtaining of the bus driving timing recorded in real time during the EDA regression process includes: Recording the bus driving timing in the EDA regression process according to a fixed bit width.

[0085] Specifically, since there are multiple bus signals included in the bus driving timing and the bit widths of the respective bus signals are inconsistent, recording the bus driving timing in the EDA regression process according to a fixed bit width can facilitate subsequent parsing of the bus driving timing.

[0086] Based on the above embodiments, the reading of the target configuration file corresponding to the misframe from the process configuration file includes: Obtaining the frame number when the EDA regression fails, and based on the frame number, reading the target configuration file corresponding to the misframe pointed to by the frame number from the process configuration file.

[0087] Specifically, when reading the target configuration file, it can be determined by the error information that appears during the recorded EDA regression process. For example, when the error information contains a frame number, the frame number can be directly determined as the frame number of the misaligned frame. When there is no explicit frame number in the error information, the misaligned frame is inferred based on the time point of the error recorded in the error information and the logic of the test script, and then the frame number of the misaligned frame is determined.

[0088] Using the determined frame number of the misaligned frame, the frame numbers of the misaligned frames can be matched in each process configuration file. The process configuration file with the frame number of the misaligned frame is used as the target configuration file corresponding to the misaligned frame.

[0089] In the embodiments of the present invention, by determining the frame number of the misaligned frame, the target configuration file can be quickly read from each process configuration file, improving the reading efficiency of the target configuration file.

[0090] Based on the above embodiments, the embodiments of the present invention illustrate the involved EDA regression process and the misaligned frame reproduction process when an EDA regression error occurs.

[0091] First, the EDA regression process includes: Randomly generate a set of seeds, generate stimuli according to the seeds; input the stimuli into the RTL description. During the RTL operation process, relevant process configuration parameters can be recorded to obtain the process configuration file. The process configuration parameters can include fixed configuration parameters and non-fixed configuration parameters. The fixed configuration parameters include image data and register configuration, and the non-fixed configuration parameters include the initial phase of the Advanced eXtensible Interface AXI and the AXI bus interface timing signal.

[0092] During the EDA regression process, the fixed configuration parameters and non-fixed configuration parameters can be printed separately in a fixed format in real time and saved in a file format in the form of frames, obtaining the fixed configuration file and non-fixed configuration file corresponding to each frame respectively, and the non-fixed configuration is printed / saved in a fixed format in real time based on the minimum time period of the AXI bus interface timing.

[0093] When an error occurs during the regression, the simulation is exited. Subsequently, the misaligned frame can be determined from the printed log, and the target configuration file corresponding to the misaligned frame can be found for reproduction.

[0094] Second, the misaligned frame reproduction process includes: Read the process configuration files corresponding to each frame stored during the regression process, and load each process configuration file into the verification environment for operation; based on the frame number of the misaligned frame, determine the target configuration file corresponding to the misaligned frame from each process configuration file.

[0095] Perform format conversion on the target configuration file, input the new file after format conversion into the RTL description, and configure the start register to start the RTL running simulation for misaligned frame reproduction.

[0096] After the waiting logic encounters an error, the simulation automatically exits. After reproduction, let the designer view the waveform to confirm the problem point.

[0097] The following describes the wrong frame reproduction device provided by the present invention. The wrong frame reproduction device described below can be correspondingly referred to the wrong frame reproduction method described above.

[0098] Based on any of the above embodiments, Figure 2 is a schematic structural diagram of the wrong frame reproduction device provided by the present invention, as Figure 2 shown, the device includes: A wrong frame recognition unit 210, configured to obtain the process configuration file corresponding to each frame stored during the regression in the case of an error in the EDA regression, and read the target configuration file corresponding to the wrong frame from the process configuration file, each frame including the wrong frame; A wrong frame reproduction unit 220, configured to reproduce the wrong frame based on the target configuration file corresponding to the wrong frame.

[0099] For the device provided by the embodiment of the present invention, since the target configuration file corresponds to the frame that runs into an error, that is, the wrong frame, reproducing based on the target configuration file can reproduce the regression error scenario in a timely and accurate manner without relying on the environment and seeds. In addition, when reproducing based on the target configuration file, only the wrong frame needs to be directly reproduced, without starting from frame 0, thereby saving time costs and improving the reproduction efficiency.

[0100] Based on any of the above embodiments, the process configuration file corresponding to each frame includes relevant process parameters generated and recorded frame by frame when driving the RTL with seeds for regression.

[0101] Based on any of the above embodiments, the wrong frame reproduction is specifically used for: Taking the target configuration file corresponding to the wrong frame as an excitation and inputting it into the RTL; Starting the RTL to reproduce the wrong frame.

[0102] Based on any of the above embodiments, it further includes: A file construction module, configured to obtain the bus drive timing recorded in real time during the EDA regression; dividing the bus drive timing by frame to obtain the process configuration file corresponding to each frame.

[0103] Based on any of the above embodiments, the file construction module is specifically configured to obtain the fixed configuration parameters recorded in real time during the EDA regression; dividing the bus drive timing and the fixed configuration parameters by frame respectively to obtain the process configuration file corresponding to each frame.

[0104] Based on any of the above embodiments, the bus driving timing includes the initial phase of AXI and the bus interface timing signal of AXI.

[0105] Based on any of the above embodiments, the file construction module is specifically configured to record the bus driving timing in the EDA regression process according to a fixed bit width.

[0106] Based on any of the above embodiments, the misframe recognition unit 220 is specifically configured to obtain the frame number when an EDA regression error occurs, and based on the frame number, read the target configuration file corresponding to the misframe pointed to by the frame number from the process configuration file.

[0107] Figure 3 An example of the physical structure diagram of an electronic device is shown as Figure 3 As shown, the electronic device may include: a processor 310, a communication interface 320, a memory 330, and a communication bus 340. Among them, the processor 310, the communication interface 320, and the memory 330 complete mutual communication through the communication bus 340. The processor 310 can call the logical instructions in the memory 330 to execute the misframe reproduction method provided in each of the above embodiments.

[0108] In addition, when the logical instructions in the above-mentioned memory 330 are implemented in the form of a software functional unit and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc that can store program codes.

[0109] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the misframe reproduction method provided in each of the above embodiments.

[0110] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it is configured to execute the misframe reproduction method provided in each of the above embodiments.

[0111] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative effort.

[0112] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or equivalently replace some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for reproducing misaligned frames, characterized in that, Including: In the case of an error in the EDA regression, obtain the process configuration files corresponding to each frame stored during the regression process, and read the target configuration file corresponding to the error frame from the process configuration files, where each frame includes the error frame; Reproduce the error frame based on the target configuration file corresponding to the error frame.

2. The misaligned frame reproduction method according to claim 1, wherein The process configuration files corresponding to each frame include relevant process parameters generated and recorded frame by frame when using a seed to drive RTL for regression.

3. The misaligned frame reproduction method according to claim 1, characterized in that The reproducing the error frame based on the target configuration file corresponding to the error frame includes: Use the target configuration file corresponding to the error frame as an incentive and input it to the RTL; Start the RTL to reproduce the error frame.

4. The misaligned frame reproduction method according to claim 1, characterized in that The construction process of the process configuration files corresponding to each frame includes: Obtain the bus drive timing recorded in real time during the EDA regression process; Divide the bus drive timing in units of frames to obtain the process configuration files corresponding to each frame.

5. The misaligned frame reproduction method according to claim 4, wherein The dividing the bus drive timing in units of frames to obtain the process configuration files corresponding to each frame includes: Obtain the fixed configuration parameters recorded in real time during the EDA regression process; Divide the bus drive timing and the fixed configuration parameters in units of frames respectively to obtain the process configuration files corresponding to each frame.

6. The misframe reproduction method according to claim 4, wherein The bus drive timing includes the initial phase of the AXI and the bus interface timing signals of the AXI.

7. The misaligned frame reproduction method according to claim 4, wherein The obtaining the bus drive timing recorded in real time during the EDA regression process includes: Record the bus drive timing in the EDA regression process according to a fixed bit width.

8. The method for reproducing misaligned frames according to any one of claims 1 to 7, characterized in that, The reading the target configuration file corresponding to the error frame from the process configuration file includes: Obtain the frame number when the EDA regression encounters an error, and based on the frame number, read the target configuration file corresponding to the error frame pointed to by the frame number from the process configuration file.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the error frame reproduction method according to any one of claims 1 to 8.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the error frame reproduction method according to any one of claims 1 to 8.

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