Method and circuit system for chip hardware simulation

Abstract

Various embodiments of the invention provide an instruction reading method and a circuit system for chip hardware simulation. The method comprises the steps that a first flag bit in a plurality of flag bits is obtained from an instruction reading control table, the plurality of flag bits correspond to a plurality of simulation steps of a simulation period of a circuit to be tested, and the value of each flag bit in the plurality of flag bits indicates the instruction validity during the corresponding simulation step in the plurality of simulation steps. The method further includes causing a first instruction in the instruction space to be read for emulating the circuit under test based on determining that the value of the first flag bit indicates that an instruction during a first emulation step of the plurality of emulation steps is valid. In this way, by using the flag bits to indicate the instruction validity of the corresponding simulation steps, more instruction execution time can be conveniently supported by using a limited instruction space. Meanwhile, simulation steps involving invalid instructions can be reduced, so that the simulation period is shortened.

Description

Technical Field

[0001] Embodiments of the present disclosure mainly relate to the field of chip hardware emulation. More specifically, embodiments of the present disclosure relate to methods and circuit systems for chip hardware emulation. Background Art

[0002] Chip hardware emulation is an important part of the chip design and manufacturing process, which is used to perform hardware emulation verification on chip designs. Generally, the code describing the chip design can be compiled into a compiled version that can be executed on the dedicated hardware circuit of the hardware emulator, and then the hardware emulation instructions of the compiled version are executed by the hardware emulator to verify whether the chip design meets the expected goals.

[0003] Hardware emulation instructions are usually stored in an external memory communicating with the hardware emulator. Therefore, an instruction reading scheme is needed to efficiently transfer the hardware emulation instructions to the execution unit in the hardware emulator. Summary of the Invention

[0004] Currently, some instruction reading schemes for chip hardware emulation have problems of long instruction reading time and low efficiency. Embodiments of the present disclosure provide an instruction reading scheme for chip hardware emulation to at least partially solve the above problems.

[0005] In a first aspect of the present disclosure, an instruction reading method for chip hardware emulation is provided. The method includes: obtaining a first flag bit from an instruction reading control table, where the plurality of flag bits correspond to a plurality of simulation steps of the simulation cycle of the circuit under test, and the value of each flag bit in the plurality of flag bits indicates the instruction validity during the corresponding simulation step in the plurality of simulation steps. The method further includes: based on determining that the value of the first flag bit indicates that the instruction is valid during the first simulation step in the plurality of simulation steps, causing the first instruction in the instruction space to be read for emulating the circuit under test.

[0006] In this way, by using flag bits to indicate the instruction validity of the corresponding simulation steps, that is, using flag bits to indicate whether to execute an instruction in the corresponding simulation step, it is convenient to use the limited instruction space to support more instruction execution time. At the same time, the simulation steps involving invalid instructions can be reduced, thereby shortening the simulation cycle.

[0007] In some embodiments of the first aspect, the method further includes: after obtaining the first flag bit, the second flag bit among the multiple flag bits may be obtained from the instruction read control table, where the second flag bit corresponds to a second simulation step after the first simulation step among the multiple simulation steps; based on determining that the value of the second flag bit indicates that the instruction during the second simulation step is valid, the second instruction in the instruction space is read for simulating the circuit under test.

[0008] In some embodiments of the first aspect, the method further includes: after obtaining the first flag bit, the second flag bit among the multiple flag bits is obtained from the instruction read control table, where the second flag bit corresponds to a second simulation step after the first simulation step among the multiple simulation steps; based on determining that the value of the second flag bit indicates that the instruction during the second simulation step is invalid, after the second simulation step ends, the third flag bit among the multiple flag bits is obtained from the instruction read control table, where the third flag bit corresponds to a third simulation step after the second simulation step among the multiple simulation steps.

[0009] In some embodiments of the first aspect, the method further includes: based on determining that the value of the third flag bit indicates that the instruction during the third simulation step is valid, the second instruction in the instruction space is read for simulating the circuit under test, where the second instruction and the first instruction are read by the same or different execution units.

[0010] In some embodiments of the first aspect, multiple instructions for simulating the circuit under test are continuously stored at multiple addresses in the instruction space. In some embodiments of the first aspect, the number of the multiple instructions is less than the number of the multiple simulation steps. In this way, a smaller physical instruction space can be used to support more instruction execution times.

[0011] In a second aspect of the present disclosure, another method for chip hardware simulation is provided. The method includes: based on the hardware simulation compilation for the circuit under test, an instruction table and an instruction read control table for simulating the circuit under test are determined, where the instruction table includes multiple instructions for simulating the circuit under test, and the instruction read control table includes multiple flag bits corresponding to multiple simulation steps of the simulation cycle of the circuit under test, and the value of each flag bit among the multiple flag bits indicates the instruction validity during the corresponding simulation step among the multiple simulation steps.

[0012] In some embodiments of the second aspect, determining the instruction fetch control table for simulating the circuit under test may include: determining, based on the hardware simulation compilation, the dependencies between the multiple instructions for simulating the circuit under test; determining, based on the dependencies, one or more candidate simulation steps capable of executing each of the multiple instructions; determining, based on the one or more candidate simulation steps for each instruction, the target simulation step for executing each instruction; and determining, based on the target simulation step for each instruction, the value of each of the multiple flag bits corresponding to the multiple simulation steps. In this way, the circuit system can determine the instruction fetch control table for instruction fetch control.

[0013] In some embodiments of the second aspect, the multiple instructions in the instruction table are continuously stored at multiple addresses in the instruction space. In some embodiments of the second aspect, the number of the multiple instructions is less than the number of the multiple simulation steps. In this way, a smaller physical instruction space can be used to support more instruction execution times.

[0014] In a third aspect of the present disclosure, there is provided a circuit system for chip hardware simulation. The circuit system includes: a validity acquisition circuit system configured to obtain a first flag bit among multiple flag bits from an instruction fetch control table, the multiple flag bits corresponding to multiple simulation steps of a simulation cycle of a circuit under test, and the value of each of the multiple flag bits indicating the instruction validity during the corresponding simulation step among the multiple simulation steps; and a validity determination circuit system configured to, based on determining that the value of the first flag bit indicates that the instruction is valid during a first simulation step among the multiple simulation steps, cause a first instruction in the instruction space to be fetched for simulating the circuit under test.

[0015] In this way, by using the flag bits to indicate the instruction validity of the corresponding simulation steps, that is, using the flag bits to indicate whether to execute an instruction in the corresponding simulation step, it is possible to conveniently use a limited instruction space to support more instruction execution times. At the same time, the simulation steps involving invalid instructions can be reduced, thereby shortening the simulation cycle.

[0016] In some embodiments of the third aspect, the validity acquisition circuit system is further configured to: after obtaining the first flag bit, obtain a second flag bit among the multiple flag bits from the instruction fetch control table, the second flag bit corresponding to a second simulation step after the first simulation step among the multiple simulation steps; and the validity determination circuit system is further configured to: based on determining that the value of the second flag bit indicates that the instruction is valid during the second simulation step, cause a second instruction in the instruction space to be fetched for simulating the circuit under test.

[0017] In some embodiments of the third aspect, the validity acquisition circuit system is further configured to: after acquiring the first flag bit, acquire a second flag bit among the multiple flag bits from the instruction read control table, where the second flag bit corresponds to a second simulation step after the first simulation step among the multiple simulation steps;

[0018] The validity determination circuit system is further configured to: determine that the value of the second flag bit indicates that the instruction during the second simulation step is invalid,

[0019] The validity acquisition circuit system is further configured to: after the end of the second simulation step, acquire a third flag bit among the multiple flag bits from the instruction read control table, where the third flag bit corresponds to a third simulation step after the second simulation step among the multiple simulation steps.

[0020] In some embodiments of the third aspect, the validity determination circuit system is further configured to: based on determining that the value of the third flag bit indicates that the instruction during the third simulation step is valid, cause a second instruction in the instruction space to be read for simulating the circuit under test, where the second instruction and the first instruction are read by the same or different execution units.

[0021] In some embodiments of the third aspect, multiple instructions for simulating the circuit under test are continuously stored at multiple addresses in the instruction space. In some embodiments of the third aspect, the number of the multiple instructions is less than the number of the multiple simulation steps. In this way, a smaller physical instruction space can be used to support more instruction execution times.

[0022] In a fourth aspect of the present disclosure, another circuit system for chip hardware simulation is provided. The circuit system is configured to determine an instruction table and an instruction read control table for simulating the circuit under test based on a hardware simulation compilation for the circuit under test, where the instruction table includes multiple instructions for simulating the circuit under test, and the instruction read control table includes multiple flag bits corresponding to multiple simulation steps of a simulation cycle of the circuit under test, and the value of each flag bit among the multiple flag bits indicates the instruction validity during the corresponding simulation step among the multiple simulation steps.

[0023] In some embodiments of the fourth aspect, the circuit system is configured to: determine, based on the hardware simulation compilation, the dependencies between the multiple instructions for simulating the circuit under test; determine, based on the dependencies, one or more candidate simulation steps capable of executing each of the multiple instructions; determine, based on the one or more candidate simulation steps for each instruction, a target simulation step for executing each instruction; and determine, based on the target simulation step for each instruction, the value of each of the multiple flag bits corresponding to the multiple simulation steps. In this way, the circuit system can determine an instruction fetch control table for instruction fetch control.

[0024] In some embodiments of the fourth aspect, the multiple instructions are consecutively stored at multiple addresses in an instruction space. In some embodiments of the fourth aspect, the number of the multiple instructions is less than the number of the multiple simulation steps. In this way, a smaller physical instruction space can be used to support more instruction execution times. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In connection with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0026] Figure 1 A flowchart showing the design and manufacturing process of a chip;

[0027] Figure 2 A schematic diagram showing an example environment capable of implementing an instruction fetch process for chip hardware simulation according to an embodiment of the present disclosure;

[0028] Figure 3 A flowchart showing an example process of an instruction fetch method for chip hardware simulation according to some embodiments of the present disclosure;

[0029] Figure 4 A schematic diagram showing an example process of instruction fetch control according to some embodiments of the present disclosure;

[0030] Figure 5 A schematic diagram showing an example microarchitecture capable of implementing an instruction fetch process according to some embodiments of the present disclosure; and

[0031] Figure 6 A schematic diagram showing an example environment capable of implementing an instruction fetch process according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure.

[0033] In the description of the embodiments of the present disclosure, the term "comprising" and its like terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0034] As briefly mentioned above, there is currently a need for an instruction fetching scheme to efficiently transfer hardware simulation instructions to the execution unit in a hardware emulator. For this purpose, some related instruction fetching schemes have been proposed. For example, in a multi-phase mechanism, the simulation steps in the simulation cycle of the circuit under test can be distributed among multiple phases. The same instruction space can be accessed sequentially during each phase in the order of the phases to fetch instructions. Each valid instruction in the instruction space is marked with a corresponding phase identifier (ID). Each valid instruction will only be fetched and executed during the corresponding phase. In other words, in the multi-phase mechanism, multiple phases share the same limited physical instruction space. By polling the same instruction space multiple times, a smaller instruction space can be used to support more instruction execution times.

[0035] However, since the valid instructions in multiple phases are mutually exclusive in the arrangement in the instruction space, only the valid instruction for a specific phase can be stored at the same address in the instruction space. Therefore, when polling the instruction space multiple times in the order of multiple phases, the polling during the phases with later sorting may go through a large number of simulation steps involving invalid instructions, thus lengthening the overall simulation cycle of multiple phases.

[0036] To at least partially address the above problems and other potential problems, various embodiments of the present disclosure provide an instruction reading method for chip hardware simulation. The method includes: obtaining a first flag bit from an instruction reading control table, where the plurality of flag bits correspond to a plurality of simulation steps of a simulation cycle of a circuit under test, and the value of each flag bit in the plurality of flag bits indicates the instruction validity during the corresponding simulation step in the plurality of simulation steps. The method further includes: based on determining that the value of the first flag bit indicates that the instruction is valid during a first simulation step in the plurality of simulation steps, causing a first instruction in the instruction space to be read for simulating the circuit under test.

[0037] In this way, by using the flag bits in the instruction reading control table to indicate the instruction validity of the corresponding simulation steps, that is, using the flag bits to indicate whether to execute an instruction in the corresponding simulation step, it is convenient to use the limited instruction space to support more instruction execution times. At the same time, since there is no polling of multiple phases, the simulation steps involving invalid instructions can be reduced, thereby shortening the simulation cycle.

[0038] The following describes various example embodiments of the present disclosure with reference to the accompanying drawings. Figure 1 A flowchart of a design and manufacturing process 100 of a chip is shown. The design and manufacturing process 100 begins with specification 110. In the stage of specification 110, the requirements for the functions and performance that the integrated circuit needs to achieve are determined. In the stage of chip design 120, circuit design is carried out with the aid of electronic design automation (EDA) tools to obtain, for example, a layout file for chip manufacturing. Based on the differences in circuits (such as digital circuits or analog circuits), design 120 may include different design links. In the stage of manufacturing 140, an integrated circuit is formed on a wafer through processes such as lithography, etching, ion implantation, thin film deposition, and polishing. In the stage of packaging 150, the wafer is cut to obtain a die, and the die is packaged through processes such as bonding, soldering, and molding to obtain a chip. The obtained chip is tested in the stage of testing 160 to ensure that the performance of the finished chip meets the requirements determined in specification 110. The tested qualified chip 170 can be delivered to customers. It can be understood that the above process is only illustrative and does not limit the scope of the present disclosure. In some cases, the design and manufacturing process of the chip may be different. For example, tape-out may be performed before manufacturing 140. A small number of chips obtained from tape-out can be used for testing to verify whether the chip design meets the expectations. If it does not meet the expectations, this indicates that the tape-out fails, and it may be necessary to adjust the chip design or redesign the chip.

[0039] In some embodiments, the design 120 of a digital circuit may exemplarily include architecture design 121, register transfer level (RTL) design 123, functional simulation 125, synthesis 127, timing analysis 129, design for test (DFT) 131, verification check 133, placement and routing 135, design rule check (DRC) 137, and layout generation 139. The architecture design 121 includes, for example, designing the architecture of a chip. For example, EDA tools can be used to determine the types and quantities of components or sub-circuits included in a chip system, as well as the functions, connections, and interactions of each component or sub-circuit. In the stage of RTL design 123, the determined chip architecture can be described in code at the RTL level using a hardware programming language such as Verilog or VHDL. The functional simulation 125 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logic relationships of the designed circuit. Synthesis 127 can convert the RTL into a gate-level netlist. Synthesis 127 can include, for example, translation, optimization, and mapping. In one embodiment, the EDA tool for synthesis can first convert the RTL code into a general Boolean equation and compile it. The netlist can be optimized according to constraints such as delay and area imposed by the designer, and then the RTL netlist can be mapped to a process library to generate a gate-level netlist.

[0040] Timing analysis 129 is usually static timing analysis, which mainly involves the timing calculation and prediction of digital circuits. By performing timing analysis on the paths in the digital circuit, it is determined whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. This verification of digital circuits is usually done statically and does not require the simulation of digital logic. In the DFT 131 stage, various hardware logics for improving the testability of the chip (including controllability and observability) can be embedded in the design. By using this part of the logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can include, for example, test methods based on scan chains or built-in self-test circuits (BIST). In the verification check 133 stage, the circuit can be subjected to formal verification and / or equivalence check. Formal verification can use mathematical methods to prove its correctness or incorrectness according to certain formal specifications or properties. Formal verification can include, for example, abstract interpretation, formal model checking (also known as property checking), and theorem prover. Equivalence check can be used to verify the consistency between the register transfer level design and the gate-level netlist, and between the gate-level netlists.

[0041] In the physical design (placement and routing) 135 stage, the chip circuit can be placed and routed. Placement can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, power consumption, etc. After that, the components or sub-circuits that have been placed can be routed to connect them. Routing generally expects the total wire length to be short, the wire delay to meet the timing requirements, and to comply with the wire rules in the process (such as wire density). Although placement and routing are described separately here, this is only illustrative and does not limit the scope of the present disclosure. In some cases, placement and routing can be performed simultaneously or alternately to achieve the optimization of physical design.

[0042] In the DRC 137 stage, it can be checked whether the layout violates the design rules, which may cause potential open circuits, short circuits, or adverse effects. After passing the DRC, an EDA tool can generate 139 a file representing the layout, such as a GDSII file. It can be understood that the above steps are only exemplary and do not limit the scope of the present disclosure. In the actual design process, the above steps can be added, deleted, or modified according to design needs. In addition, some of the above steps can be implemented by different EDA tools or integrated in one or more EDA tools. The scope of the present disclosure is not limited here.

[0043] In one or more of the above stages, hardware emulation can be applied to verify the chip design. For example, after RTL design 123, after the synthesis 127 stage, and / or after the place and route 135, hardware emulation can be applied to verify the chip design. In some embodiments, a test bench can be established to provide control of the input and environment for the circuit under test (also referred to as the design under test, DUT). For example, stimuli can be injected into the DUT. The hardware emulator can execute hardware emulation instructions to simulate the behavior of the DUT on hardware. By comparing the output of the DUT with the expected target, the circuit under test can be verified.

[0044] Figure 2 A schematic diagram of an example environment 200 capable of implementing an instruction reading process for chip hardware emulation according to an embodiment of the present disclosure is shown. As Figure 2 shown, the environment 200 includes an emulation step control unit 210, an instruction reading control unit 220, an instruction reading control table 230, an instruction table 240, and an execution unit 250. The emulation step control unit 210 can be configured to control the emulation progress of the DUT within a single DUT working clock (DCLK). The emulation cycle of the DUT can be decomposed into multiple emulation steps. For example, a single DCLK can be decomposed into 4096 steps. The emulation step control unit 210 can include a counting module for counting the steps to control the emulation progress.

[0045] The instruction reading control unit 220 can be configured to determine the instruction validity for each emulation step, that is, to determine whether to execute hardware emulation instructions during each emulation step. The instruction reading control unit 220 can determine the instruction validity for each emulation step based on the instruction reading control table 230.

[0046] As Figure 2 shown, the instruction reading control table 230 includes multiple flag bits 235, such as flag 0, flag 1... flag T-2, flag T-1. The multiple flag bits correspond to multiple emulation steps in a single emulation cycle. That is, the number of the multiple flag bits 235 in the instruction reading control table 230 can correspond to the maximum length of the supported DCLK. The value of each flag bit among the multiple flag bits 235 indicates the instruction validity of the corresponding emulation step. For example, a flag bit value of 1 can indicate that the instruction in the corresponding emulation step is valid, that is, it indicates that hardware emulation instructions are to be executed during the corresponding emulation step. Conversely, a flag bit value of 0 can indicate that the instruction in the corresponding emulation step is invalid, that is, it indicates that hardware emulation instructions are not executed during the corresponding emulation step.

[0047] The instruction fetch control unit 220 can sequentially obtain the values of the corresponding flag bits from the instruction fetch control table 230 during each simulation step, and determine the instruction validity of the corresponding simulation step according to the values of the flag bits. Based on the determined instruction validity, the instruction fetch control unit 220 can control the fetch progress of the instructions in the instruction table 240.

[0048] As Figure 2 shown, the instruction table 240 includes multiple instructions 245 for simulating the circuit under test, such as instruction 0, instruction 1... instruction N-2, flag N-1. The multiple instructions 245 in the instruction table 240 can be continuously stored at multiple addresses in the instruction space. In other words, the multiple instructions 245 can be densely packed in the instruction space, and the valid table entries in the instruction table 240 can be continuously arranged starting from address 0 without any idle invalid entries in between.

[0049] The instruction fetch control unit 220 can continuously read the instruction fetch control table 230, read the value of the corresponding flag bit according to the current step, so as to control the execution progress of the instruction table 240, and further drive the execution unit 250 to complete the corresponding function, that is, drive the execution unit 250 to complete the hardware simulation behavior corresponding to the instruction. The execution unit 250 can be the main functional unit inside the hardware simulation chip (Emu chip), and is used to execute hardware simulation instructions to perform hardware simulation on the circuit under test.

[0050] For example, if the instruction fetch control unit 220 reads the value of the flag bit as 1 in the current step, it can perform an increment operation on the read address of the instruction table 240 to indicate that an instruction needs to be executed. The instruction fetch control unit 220 can further drive the execution unit 250 to execute the corresponding instruction, such as completing a logical "AND" operation.

[0051] It should be understood that Figure 2 the environment 200 shown in

[0052] Figure 3 is only exemplary and does not constitute a limitation on the scope of the present disclosure. The number of multiple instructions in the instruction table and the number of flag bits in the instruction fetch control table can be set according to specific application scenarios. The environment 200 may also include any other suitable components. Figure 2 shows a flowchart of an example process 300 of an instruction fetch method for chip hardware simulation according to some embodiments of the present disclosure. The process 300 can be implemented by any suitable logic or circuit system. Referring to

[0053] At block 310, the circuitry obtains a first flag bit among a plurality of flag bits from an instruction read control table, where the plurality of flag bits correspond to a plurality of simulation steps of a simulation period of a circuit under test, and the value of each flag bit among the plurality of flag bits indicates instruction validity during a corresponding simulation step among the plurality of simulation steps.

[0054] At block 320, based on determining that the value of the first flag bit indicates that an instruction during a first simulation step among the plurality of simulation steps is valid, a first instruction in an instruction space is read for simulating the circuit under test.

[0055] For example, referring to Figure 2 , the instruction read control unit 220 can obtain flag 0 among a plurality of flag bits 235 from the instruction read control table 230. Flag 0 corresponds to simulation step 0, and the value of flag 0 indicates instruction validity during simulation step 0. If it is determined that the value of flag 0 is 1, then the instruction read control unit 220 can determine that the instruction is valid during simulation step 0.

[0056] In some embodiments, after obtaining the first flag bit, a second flag bit among the plurality of flag bits can be obtained from the instruction read control table. The second flag bit corresponds to a second simulation step after the first simulation step among the plurality of simulation steps. Based on determining that the value of the second flag bit indicates that an instruction during the second simulation step is valid, a second instruction in the instruction space can be read for simulating the circuit under test.

[0057] For example, referring to Figure 2 , after obtaining flag 0, the instruction read control unit 220 can obtain flag 1 among the plurality of flag bits 235 from the instruction read control table 230. Flag 1 corresponds to simulation step 1, and the value of flag 1 indicates instruction validity during simulation step 1. If it is determined that the value of flag 1 is 1, then the instruction read control unit 220 can determine that the instruction is valid during simulation step 1. If it is determined that the value of flag 1 indicates that the instruction during simulation step 1 is valid, then the instruction read control unit 220 can cause an instruction 0 in the instruction space to be read by an execution unit, such as execution unit 250, for simulating the circuit under test.

[0058] In some embodiments, after obtaining the first flag bit, the second flag bit among the multiple flag bits may be obtained from the instruction read control table. The second flag bit corresponds to the second simulation step after the first simulation step among the multiple simulation steps. Based on determining that the value of the second flag bit indicates that the instruction during the second simulation step is invalid, after the end of the second simulation step, the third flag bit among the multiple flag bits is obtained from the instruction read control table. The third flag bit corresponds to the third simulation step after the second simulation step among the multiple simulation steps. In some embodiments, based on determining that the value of the third flag bit indicates that the instruction during the third simulation step is valid, the second instruction in the instruction space is read for simulating the circuit under test.

[0059] For example, referring to Figure 2 , after obtaining flag 0, the instruction read control unit 220 may obtain flag 1 among the multiple flag bits 235 from the instruction read control table 230. Flag 1 corresponds to simulation step 1, and the value of flag 1 indicates the instruction validity during simulation step 1. If it is determined that the value of flag 1 is 0, the instruction read control unit 220 may determine that the instruction is invalid during simulation step 1. In this case, the instruction read control unit 220 may wait for the end of simulation step 1, and then obtain the next flag 2 among the multiple flag bits 235 from the instruction read control table 230. Flag 2 corresponds to simulation step 2, and the value of flag 2 indicates the instruction validity during simulation step 2. If it is determined that the value of flag 2 indicates that the instruction is valid during simulation step 2, the instruction read control unit 220 may cause the instruction 1 in the instruction space to be read by an execution unit, such as execution unit 250, for simulating the circuit under test. In some embodiments, instruction 0 and instruction 1 may be read by the same or different execution units.

[0060] Figure 4 FIG. shows a schematic diagram of an example process 400 of instruction read control according to some embodiments of the present disclosure. Figure 4 FIG. shows an instruction read control table 410, an instruction table 420 stored in an instruction memory (such as a random access memory (RAM)), and an instruction execution step table 430. The instruction read control table 410 and the instruction table 420 may be specific examples of the instruction read control table 230 and the instruction table 240 shown in Figure 2 respectively. The instruction execution step table 430 may indicate whether an instruction is executed in each simulation step and may indicate which instruction is executed in the corresponding simulation step. The number of instructions in the instruction table 420 may be less than the number of simulation steps in the simulation period.

[0061] As Figure 4As shown, since the value of the flag bit corresponding to step 0 is 1, the instruction 0 in the instruction table 420 can be executed at step 0. Similarly, the instruction 1 in the instruction table 420 can be executed at step 1, the instruction 2 in the instruction table 420 can be executed at step 2, …… the instruction 509 in the instruction table 420 can be executed at step 509.

[0062] During step 510, since the value of the flag bit corresponding to step 510 is 0, no instruction is executed at step 510. Similarly, since the value of the flag bit corresponding to step 511 is 0, no instruction is executed at step 511. During step 512, since the value of the flag bit corresponding to step 512 is 1, an instruction can be executed. Therefore, the next instruction in the instruction table 420, that is, instruction 510, can be executed during step 512. Continuing to step 513, since the value of the flag bit corresponding to step 513 is 1, the next instruction 511 can be executed at step 513.

[0063] As can be seen from process 400, using the solution of the present disclosure, the actual execution progress of instructions can be controlled by the instruction validity indication (i.e., the value of the flag bit) in the instruction read control table. Therefore, the instruction RAM can be read only when needed, thereby enabling indirect addressing of the instruction space. In this way, the simulation steps involving invalid instructions can be reduced, thus shortening the simulation cycle.

[0064] For example, in Figure 4 the example shown, the instruction RAM can store 512 instructions. Due to the nature of the circuit under test, instructions 510 and 511 cannot be executed immediately after instruction 508, but need to wait for two steps after instruction 509 is executed. In this case, using the solution of the present disclosure, two empty steps can be configured in the instruction read control table 410 to indicate that no instruction is executed in these two steps. After these two empty steps, instructions 510 and 511 can be executed at step 512 and step 513 respectively. In this way, the execution of 512 instructions can be achieved in a simulation cycle of 514 steps.

[0065] In contrast, in the multi-phase mechanism, considering that instruction 510 needs to wait for two steps after instruction 509 is executed before being executed, instructions 0 to 509 can be marked with phase 0 to indicate that instructions 0 to 509 can be executed during phase 0, and instructions 510 and 511 can be marked with phase 1 to indicate that instructions 510 and 511 can be executed during phase 1. In this way, during the first phase, i.e., phase 0, instructions 0 to 509 can be executed in sequence from step 0 to step 509, and then wait for steps 510 and 511 to end. Then continue to execute the second phase, i.e., phase 1, and the second phase starts from step 512. Since polling needs to be performed in sequence starting from address 0 of the instruction space during the second phase, and instructions 0 to 509 stored at addresses 0 to 509 of the instruction space are invalid during the second phase, steps 512 to 1021 involving invalid instructions need to be experienced during the second phase until instruction 510 stored at address 510 can be executed at step 1022 and instruction 511 stored at address 511 can be executed at step 1023. Therefore, in the multi-phase mechanism, the execution of 512 instructions needs to be achieved in a simulation cycle of 1024 steps.

[0066] In addition, in the instruction fetching scheme according to the embodiments of the present disclosure, by using flag bits corresponding to simulation steps to indicate the validity of instructions in the corresponding simulation steps, a smaller instruction space can be used to support more instruction execution times or instruction execution counts. For example, in the absence of flag bits, Figure 4 the instruction space shown in can only support the execution of 510 instructions in 510 steps. In contrast, using the scheme of the present disclosure, Figure 4 the instruction space shown in can support the execution of 512 instructions in 514 steps. When the dependency relationship of instructions is more complex, for example, when more steps need to be waited between the execution of two instructions, using the scheme of the present disclosure can achieve a better instruction space utilization efficiency.

[0067] Embodiments of the present disclosure also provide an instruction fetch control method for chip hardware simulation. The process of this method can be implemented by any suitable logic or circuit system, for example, it can be implemented by the host system of a hardware emulator.

[0068] In this method, the circuit system can determine an instruction table and an instruction fetch control table for simulating the circuit under test based on hardware simulation compilation for the circuit under test. As described above, the instruction table includes multiple instructions for simulating the circuit under test, and the instruction fetch control table includes multiple flag bits. The multiple flag bits correspond to multiple simulation steps of the simulation cycle of the circuit under test, and the value of each flag bit in the multiple flag bits indicates the instruction validity during the corresponding simulation step in the multiple simulation steps.

[0069] In some embodiments, the circuit system can determine the dependency relationships among multiple instructions for simulating the circuit under test based on hardware simulation compilation. Based on the dependency relationships, one or more candidate simulation steps capable of executing each of the multiple instructions can be determined. Based on the one or more candidate simulation steps for each instruction, the circuit system can determine the target simulation step for executing each instruction. Based on the target simulation step for each instruction, the circuit system can determine the value of each flag bit in the multiple flag bits corresponding to the multiple simulation steps.

[0070] In this way, the circuit system can determine the instruction fetch control table for instruction fetch control. In the solution of the present disclosure, by using the valid instruction indication of the flag bits, the instruction arrangement in the instruction RAM only needs to satisfy the forward and backward dependencies of the instructions, without considering the instruction conflict problem at the same instruction address in multiple phases. In other words, multiple instructions can be directly arranged in the instruction space based on the result of hardware simulation compilation, without using the slotting mechanism in the multi-phase mechanism to arrange multiple instructions, thereby improving the simulation efficiency in most scenarios.

[0071] Figure 5 A schematic diagram of an example microarchitecture 500 capable of implementing an instruction fetch process according to some embodiments of the present disclosure is shown. As Figure 5 shown, the step control can control the simulation progress of the DUT within a single DUT working clock. For example, the step control module can perform step counting and control the internal logic. The flag bits in the instruction fetch control table can control the instruction execution progress. For example, one flag indication can be read in each step. If the flag value is 1, it means that the next instruction needs to be executed, otherwise it means that no instruction is executed in the current step. The multiple instructions in the instruction table are executed in the corresponding steps based on the indication in the instruction fetch control table.

[0072] In some embodiments, a logic D flip-flop (DFF) can be utilized to perform instruction fetch control. For example, DFF 511 can send a read enable signal (read_en) based on the indication in the instruction fetch control table, and DFF 512 can send the instruction address to be fetched (read_addr) based on the indication in the instruction fetch control table. The fetched instruction (rdata) can be transmitted to the execution unit in the hardware emulator for simulating the circuit under test. It should be understood that the above DFF 511 and 512 are merely exemplary and do not represent real circuits.

[0073] Figure 6 A schematic diagram of an example environment 600 capable of implementing an instruction fetch process according to some embodiments of the present disclosure is shown. Figure 6 A hardware emulation chip 610 designed based on a processor based emulator (PBE) is shown. As Figure 6 shown, the hardware emulation chip 610 can include multiple processors 615. Processor 616 among the multiple processors 615 is shown as an example for illustrating the structure of the processor. Processor 616 can include multiple execution units (labeled P0, P1, P2, P3, P4, P5, P6, and P7) and a data array.

[0074] The hardware emulation chip 610 can also include an interconnect module 618. The interconnect module 618 can be configured to be responsible for the data transfer function at the simulation step level (also known as cycle) of the data. The interconnect module 618 can utilize the instruction fetch scheme provided by the embodiments of the present disclosure to improve the efficiency of data transfer. For example, by using the instruction fetch control table 410 and the instruction table 420 as Figure 4 shown, on the premise that 512 instructions can be supported in the physical instruction space, the hardware emulation behavior with a time length of 4096 simulation steps can be supported, and multiple instructions in the instruction space can be arranged continuously, only needing to meet the constraint of the total number of valid instructions. It should be understood that the environment 600 is merely exemplary, and this solution can be applied to any applicable hardware emulator system.

[0075] In the above embodiments, one or more steps in the method flow can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or a terminal, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial optical cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by the server or the terminal, or a data storage device such as a server or a data center that integrates one or more available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, and a magnetic tape, etc.), an optical medium (such as a digital video disk (DVD), etc.), or a semiconductor medium (such as a solid-state drive, etc.).

[0076] In addition, although the operations are depicted in a particular order, this should be understood to require that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although a number of specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately or in any suitable sub-combination in multiple implementations.

[0077] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for chip hardware simulation, characterized in that, including: obtaining a first flag bit among a plurality of flag bits from an instruction read control table, where the plurality of flag bits correspond to a plurality of simulation steps of a simulation period of a circuit under test, and a value of each flag bit among the plurality of flag bits indicates instruction validity during a corresponding simulation step among the plurality of simulation steps; based on determining that the value of the first flag bit indicates that an instruction during a first simulation step among the plurality of simulation steps is valid, causing a first instruction in an instruction space to be read for simulating the circuit under test.

2. The method according to claim 1, wherein The method further includes: after obtaining the first flag bit, obtaining a second flag bit among the plurality of flag bits from the instruction read control table, where the second flag bit corresponds to a second simulation step after the first simulation step among the plurality of simulation steps; and based on determining that the value of the second flag bit indicates that an instruction during the second simulation step is valid, causing a second instruction in the instruction space to be read for simulating the circuit under test.

3. The method according to claim 1, wherein The method further includes: after obtaining the first flag bit, obtaining a second flag bit among the plurality of flag bits from the instruction read control table, where the second flag bit corresponds to a second simulation step after the first simulation step among the plurality of simulation steps; and based on determining that the value of the second flag bit indicates that an instruction during the second simulation step is invalid, after the second simulation step ends, obtaining a third flag bit among the plurality of flag bits from the instruction read control table, where the third flag bit corresponds to a third simulation step after the second simulation step among the plurality of simulation steps.

4. The method according to claim 3, wherein The method further includes: based on determining that the value of the third flag bit indicates that an instruction during the third simulation step is valid, causing the second instruction in the instruction space to be read for simulating the circuit under test, where the second instruction and the first instruction are read by the same or different execution units.

5. The method according to any one of claims 1 to 4, characterized in that A plurality of instructions for simulating the circuit under test are continuously stored at a plurality of addresses in the instruction space.

6. The method according to claim 5, wherein The number of the plurality of instructions is less than the number of the plurality of simulation steps.

7. A method for chip hardware simulation, characterized in that, including: based on hardware simulation compilation for a circuit under test, determining an instruction table and an instruction read control table for simulating the circuit under test, where the instruction table includes a plurality of instructions for simulating the circuit under test, and the instruction read control table includes a plurality of flag bits, the plurality of flag bits correspond to a plurality of simulation steps of a simulation period of the circuit under test, and a value of each flag bit among the plurality of flag bits indicates instruction validity during a corresponding simulation step among the plurality of simulation steps.

8. The method according to claim 7, wherein Determining the instruction read control table for simulating the circuit under test includes: based on the hardware simulation compilation, determining a dependency relationship between the plurality of instructions for simulating the circuit under test; based on the dependency relationship, determining one or more candidate simulation steps capable of executing each instruction among the plurality of instructions; based on the one or more candidate simulation steps for each instruction, determining a target simulation step for executing each instruction; and Determine the value of each of the plurality of flag bits corresponding to the plurality of simulation steps based on the target simulation steps for each of the instructions.

9. The method according to any one of claims 7 to 8, characterized in that, The plurality of instructions in the instruction table are consecutively stored at a plurality of addresses in the instruction space.

10. The method according to any one of claims 7 to 9, characterized in that, The number of the plurality of instructions is less than the number of the plurality of simulation steps.

11. A circuit system for chip hardware simulation, characterized in that, Comprising: A validity acquisition circuit system configured to acquire a first flag bit among the plurality of flag bits from an instruction read control table, the plurality of flag bits corresponding to a plurality of simulation steps of a simulation cycle of a circuit under test, and the value of each of the plurality of flag bits indicating instruction validity during a corresponding simulation step among the plurality of simulation steps; And A validity determination circuit system configured to, based on determining that the value of the first flag bit indicates that the instruction is valid during a first simulation step among the plurality of simulation steps, cause a first instruction in the instruction space to be read for simulating the circuit under test.

12. The circuit system according to claim 11, wherein: The validity acquisition circuit system is further configured to: after acquiring the first flag bit, acquire a second flag bit among the plurality of flag bits from the instruction read control table, the second flag bit corresponding to a second simulation step after the first simulation step among the plurality of simulation steps; The validity determination circuit system is further configured to: based on determining that the value of the second flag bit indicates that the instruction is valid during the second simulation step, cause a second instruction in the instruction space to be read for simulating the circuit under test.

13. The circuit system according to claim 11, wherein: The validity acquisition circuit system is further configured to: after acquiring the first flag bit, acquire a second flag bit among the plurality of flag bits from the instruction read control table, the second flag bit corresponding to a second simulation step after the first simulation step among the plurality of simulation steps; The validity determination circuit system is further configured to: determine that the value of the second flag bit indicates that the instruction is invalid during the second simulation step, The validity acquisition circuit system is further configured to: after the second simulation step ends, acquire a third flag bit among the plurality of flag bits from the instruction read control table, the third flag bit corresponding to a third simulation step after the second simulation step among the plurality of simulation steps.

14. The circuit system according to claim 13, wherein: The validity determination circuit system is further configured to: based on determining that the value of the third flag bit indicates that the instruction is valid during the third simulation step, cause the second instruction in the instruction space to be read for simulating the circuit under test, wherein the second instruction and the first instruction are read by the same or different execution units.

15. The circuit system according to any one of claims 11 to 14, wherein: A plurality of instructions for simulating the circuit under test are consecutively stored at a plurality of addresses in the instruction space.

16. The circuit system according to any one of claims 11 to 15, wherein: The number of the multiple instructions is less than the number of the multiple simulation steps.

17. A circuit system for chip hardware simulation, characterized in that: The circuit system is configured to determine an instruction table and an instruction reading control table for simulating the circuit under test based on a hardware simulation compilation for the circuit under test, where The instruction table includes multiple instructions for simulating the circuit under test, and The instruction reading control table includes multiple flag bits corresponding to multiple simulation steps of a simulation cycle of the circuit under test, and the value of each of the multiple flag bits indicates the instruction validity during the corresponding simulation step among the multiple simulation steps.

18. The circuit system according to claim 17, wherein The circuit system is configured to: Determine the dependency relationship between the multiple instructions for simulating the circuit under test based on the hardware simulation compilation; Determine one or more candidate simulation steps capable of executing each of the multiple instructions based on the dependency relationship; Determine a target simulation step for executing each instruction based on the one or more candidate simulation steps for each instruction; And Determine the value of each of the multiple flag bits corresponding to the multiple simulation steps based on the target simulation step for each instruction.

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