Complete hardware K-SAT solver based on dual-path macro array

Abstract

The invention provides a complete hardware K-SAT solver based on a dual-path macro array, the macro array comprises M * N processing units, the processing unit in the ith row corresponds to the ith clause of a Boolean formula, the processing unit in the ith row and the jth column is used for storing the jth variable in the ith clause, each processing unit comprises a static random access memory (SRAM) unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit and a K-SAT unit, the representation module is used for representing appearance forms of variables in clauses; the forward in-memory calculation unit is connected with one end of the SRAM unit and is used for deriving a clause state based on the variable assignment and the variable appearance form represented by the SRAM unit; and the backward index unit is connected with the other end of the SRAM unit and is used for reading all unassigned characters in the activation clause set so as to support updating of variable assignment. According to the method, a bidirectional derivation function from assignment to clause state and from clause state to assignment is realized, and a high-performance and low-energy-consumption hardware solution is provided for integrity analysis of a complex SAT problem.

Description

Technical Field

[0001] The present invention relates to the technical field of SAT problem solving, and in particular to a complete hardware K-SAT solver based on a dual-path macro array. Background Art

[0002] The Boolean satisfiability problem (K-SAT, K≥3) is one of the most representative NP (Non-deterministic Polynomially) complete problems in computer science. Its core task is to determine whether there exists a truth assignment of a set of Boolean variables such that all clauses represented in conjunctive normal form (CNF) are satisfied.

[0003] However, the existing application-specific integrated circuit (ASIC) K-SAT hardware solvers are incomplete solvers, which can only handle satisfiable (SAT) cases and cannot prove the existence of unsatisfiable (UNSAT) cases. This limitation significantly reduces the applicability of ASIC solvers in practical applications because the K-SAT problems in real scenarios usually require verifying whether the Boolean formula F(x) has a solution.

[0004] Therefore, how to achieve two-way derivation between clauses and variables, so as to provide a high-performance and low-power hardware solution for the integrity analysis of complex K-SAT problems is an urgent problem to be solved at present. Summary of the Invention

[0005] The present invention provides a complete hardware K-SAT solver based on a dual-path macro array, which is used to achieve two-way derivation between clauses and variables, and provide a high-performance and low-power hardware solution for the integrity analysis of complex K-SAT problems.

[0006] The present invention provides a complete hardware K-SAT solver based on a dual-path macro array. The macro array includes M×N processing units for solving the input Boolean formula. The Boolean formula includes at most M clauses, and each clause contains at most N variables. The processing units in the i-th row correspond to the i-th clause of the Boolean formula. The processing unit in the i-th row and the j-th column is used to store the j-th variable in the i-th clause. The processing unit includes: A static random access memory (SRAM) unit, which is used to represent the appearance form of variables in clauses; A forward in-memory computing unit, which is connected to one end of the SRAM unit and is used to deduce the clause state based on variable assignment and the variable appearance form represented by the SRAM unit; A backward indexing unit, connected to the other end of the SRAM unit, is configured to read all unassigned literals in the activated clause set to support the update of variable assignments.

[0007] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, the SRAM unit includes a first SRAM and a second SRAM, and the occurrence forms of variables in clauses include positive literals and negative literals. If a positive literal appears in a clause, the first SRAM corresponding to the positive literal is set to 1. If a negative literal appears in a clause, the second SRAM corresponding to the negative literal is set to 1. If a positive literal does not appear in a clause, the first SRAM corresponding to the positive literal is set to 0. If a negative literal does not appear in a clause, the second SRAM corresponding to the negative literal is set to 0.

[0008] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, the forward in-memory computing unit includes a Boolean satisfiability problem (SAT) computing unit, an unassigned literal detector, and a position encoding counter. The SAT computing unit is configured to determine the level state of the row-wise SAT line based on variable assignments and the variable occurrence forms represented by the SRAM unit. The unassigned literal detector is configured to detect unassigned literals in clauses. The position encoding counter is configured to count the number of unassigned literals in clauses.

[0009] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, the SAT computing unit is specifically configured to: Reset the state nodes and the row-wise SAT computing lines of the wire-OR in the unassigned literal detector to a low level through a reset signal. Activate the first-column variable assignment signal and the second-column variable assignment signal to calculate the clause state based on the first-column variable assignment signal, the second-column variable assignment signal, and the variable occurrence forms represented by the SRAM unit.

[0010] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, the SAT computing unit is specifically configured to: If the first-column variable assignment signal is 1, the second-column variable assignment signal is 0, and the variable occurrence form represented by the SRAM unit is a positive literal, charge the row-wise SAT line to a high level. If the first column variable assignment signal is 0, the second column variable assignment signal is 1, and the variable appearance form represented by the SRAM cell is a negative literal, then charge the row-wise SAT line to a high level.

[0011] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, the unassigned literal detector is specifically configured to charge the status node to a high level when both the first column variable assignment signal and the second column variable assignment signal are 0.

[0012] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, the position encoding counter is specifically configured to: When the status node in the unassigned literal detector is 0, use the 3-bit position encoding from the previous position encoding counter as the output of the current position encoding counter; When the status node in the unassigned literal detector is 1, shift the 3-bit position encoding from the previous position encoding counter to the right by 1 bit to obtain the output of the current position encoding counter; Based on the position of the target position encoding in the final output of the row-cascaded position encoding counter, determine the number of unassigned literals in the clause.

[0013] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, all position encoding counters of each row processing unit adopt a cascaded design; the clause status is determined in the following manner: If the row-wise SAT line is charged to a high level, it is determined that the clause has been satisfied; If the final output of the row-cascaded position encoding counter is 100, it is determined that all variable assignments in the clause are incorrect; If the final output of the row-cascaded position encoding counter is 010, it is determined that the clause is a unit clause; the unit clause is a clause that has not been satisfied but contains only one unassigned variable; If the final output of the row-cascaded position encoding counter is 001, it is determined that the clause contains two unassigned vectors; If the final output of the row-cascaded position encoding counter is 000, it is determined that the clause contains at least two unassigned vectors.

[0014] According to a completeness hardware K-SAT solver based on a dual-path macro array provided by the present invention, the backward index unit is specifically configured to: Through a reverse reset signal, charge all column-wise matching lines to a high level and activate the search line of the unsatisfied clause; If a negative literal appears in the clause and the positive literal has not been assigned, activate the discharge path to pull down the column-wise matching line corresponding to the negative literal to a low level; If a negative literal appears in a clause and a positive literal has been assigned a value, the discharge path is cut off.

[0015] A completeness hardware K-SAT solver based on a dual-path macroarray provided by the present invention further includes: A read / write circuit for obtaining an input Boolean formula; A decoder for obtaining a data address.

[0016] The completeness hardware K-SAT solver based on a dual-path macroarray provided by the present invention realizes the two-way derivation function from literal assignment to clause state and from clause state to literal assignment through a forward in-memory computing unit and a backward indexing unit, can handle both SAT cases and prove the existence of UNSAT cases, thereby realizing the integrity analysis for SAT problems. The present invention not only supports the efficient execution of unit propagation and heuristic decision-making, but also realizes the integrity analysis for SAT problems (including the verification of SAT and UNSAT) at the hardware level. Compared with traditional designs, the present invention can significantly improve the derivation efficiency, greatly reduce the area and power consumption of the hardware implementation, has broad scalability, and is applicable to solving SAT problems of different scales. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic diagram of an example of the K-SAT problem in the prior art.

[0019] Figure 2 It is one of the schematic diagrams of the architecture of a dual-path macroarray supporting two-way derivation provided by an embodiment of the present invention.

[0020] Figure 3 It is another schematic diagram of the architecture of a dual-path macroarray supporting two-way derivation provided by an embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of the circuit structure of the SRAM unit provided by an embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of the circuit structure of the forward in-memory computing unit provided by an embodiment of the present invention.

[0023] Figure 6It is a timing diagram of SAT calculation and unassigned literal detection provided by an embodiment of the present invention.

[0024] Figure 7 It is a logical schematic diagram of a position encoding counter provided by an embodiment of the present invention.

[0025] Figure 8 It is a circuit structure schematic diagram of a backward index unit provided by an embodiment of the present invention.

[0026] Figure 9 It is when clause j contains literal ¬x i It is a timing diagram of the backward index unit at this time.

[0027] Figure 10 It is an energy efficiency schematic diagram of a macro array provided by an embodiment of the present invention.

[0028] Figure 11 It is a schematic architecture diagram of a complete hardware K-SAT solver provided by an embodiment of the present invention. Detailed implementation manners

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0030] In the description of the embodiments of the present application, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the embodiments of the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0031] In the description of the embodiments of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations.

[0032] In the embodiments of the present application, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is less than that of the second feature.

[0033] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0034] The input of the K-SAT problem is a Boolean formula F(x). The Boolean formula can be composed of several clauses C, and each clause is a disjunctive expression containing at most K Boolean variables. If a variable assignment can be found such that all clauses in F(x) are true, then F(x) is said to be satisfiable (SAT); if there is no such variable assignment, then F(x) is said to be unsatisfiable (UNSAT).

[0035] Figure 1 is a schematic diagram of an example of the K-SAT problem in the prior art. Referring to Figure 1 , in Example 1, when x0 is 0 and x1 is 1, the two clauses in the Boolean formula are simultaneously satisfied, so this Boolean formula is satisfiable; conversely, in Example 2, no matter what values x0 and x1 take, the two clauses in the Boolean formula cannot be simultaneously satisfied, so this Boolean formula is unsatisfiable.

[0036] As the scale of variables and clauses increases, the computational complexity of the K-SAT problem grows exponentially, posing extremely high challenges to solving algorithms and hardware designs. Due to its theoretical importance and wide practical applications, the K-SAT problem is widely used in multiple fields. For example, in Electronic Design Automation (EDA), the K-SAT problem is used for circuit equivalence verification and test pattern generation; in formal verification, K-SAT solving is an important tool for verifying the logical consistency of systems; in fault diagnosis, K-SAT solvers are used to quickly locate the root causes of system errors. Currently, the mainstream K-SAT solving methods can be divided into two categories: completeness analysis and incompleteness analysis.

[0037] (1) Incompleteness analysis Incompleteness analysis solvers quickly find satisfiable solutions (SAT) through heuristic or approximate methods, but cannot verify whether a Boolean formula is definitely unsatisfiable (UNSAT). The advantage of this method is that it has lower energy consumption and hardware resource occupancy, and faster calculation speed, making it suitable for efficient solving in certain specific fields.

[0038] However, due to the lack of the ability to handle UNSAT cases, the applicable scope of incompleteness solvers is significantly limited. For example, in formal verification and EDA tasks, the satisfiability of the problem is often unknown, and the solver needs to verify both SAT and UNSAT cases to provide comprehensive results.

[0039] (2) Completeness analysis Completeness analysis solvers can systematically perform searches and derivations. They can not only find satisfiable solutions but also prove the unsatisfiability of formulas. This ability makes it the standard solution for current mainstream commercial software (such as MiniSAT and Glucose) and is widely used in key tasks such as formal verification, logic synthesis, and fault diagnosis.

[0040] However, completeness analysis requires supporting bidirectional derivation (both deriving clauses from assignments and updating assignments from clauses), and performing multi-level precise derivations on clause states, which significantly increases the computational complexity and the requirements for storage management, further posing higher requirements for hardware design.

[0041] Currently, all ASIC hardware implementations for the K-SAT problem are incompleteness solvers and cannot support the verification of UNSAT cases. This technical gap limits the practical application potential of the K-SAT problem in harsh scenarios, especially in scenarios where both SAT and UNSAT need to be verified.

[0042] In view of the above problems, embodiments of the present invention can achieve two-way derivation between clauses and variables, thereby significantly improving the solution efficiency of the K-SAT problem in fields such as formal verification, EDA, and fault diagnosis, and providing a high-performance and low-power hardware solution for the integrity analysis of complex K-SAT problems.

[0043] Figure 2 It is one of the schematic diagrams of the architecture of a dual-path macroarray supporting two-way derivation provided by an embodiment of the present invention. Refer to Figure 2 An embodiment of the present invention provides a complete hardware K-SAT solver based on a dual-path macroarray. The macroarray includes M×N processing units 200 for solving an input Boolean formula. The Boolean formula includes at most M clauses, and each clause contains at most N variables. The processing units in the i-th row correspond to the i-th clause of the Boolean formula, and the processing unit in the i-th row and j-th column is used to store the j-th variable in the i-th clause. The processing unit 200 may include: A static random access memory (SRAM) unit 210 for representing the occurrence form of a variable in a clause; A forward in-memory computing unit 220 connected to one end of the SRAM unit, for deriving the clause state based on variable assignment and the variable occurrence form represented by the SRAM unit; A backward indexing unit 230 connected to the other end of the SRAM unit, for reading all unassigned literals in the activated clause set to support updating variable assignment.

[0044] In an embodiment of the present invention, the dual-path macroarray may be composed of M×N processing elements (PEs). The N processing units in each row can store at most N Boolean variables respectively, so as to support the solution of SAT problems with at most M clauses and N variables. Wherein, i = 1, 2,..., M; j = 1, 2,..., N.

[0045] In some embodiments, when the number of clauses in the input Boolean formula is less than M, the clauses can be preferentially mapped to the processing units with higher positions according to the top-down arrangement order of the processing units; when the number of variables is less than N, the variables can be preferentially mapped to the processing units with left positions according to the left-right arrangement order of the processing units, which is beneficial to reducing hardware overhead.

[0046] Figure 3 It is the second schematic diagram of the architecture of a dual-path macroarray supporting two-way derivation provided by an embodiment of the present invention. As an example, refer to Figure 3, the macro array can be composed of 50×218 processing units, supporting SAT problem solving with up to 50 variables and 218 clauses. Specifically, each row in the macro array can correspond to a clause, and the 50 PEs in each row can respectively store variables X0 to X 49 .

[0047] In an embodiment of the present invention, the appearance form of a variable in a sentence can include a positive literal and a negative literal. The positive literal can represent the Boolean variable itself, and the negative literal can represent the negation of the Boolean variable. A Static Random-Access Memory (SRAM) cell can be used to represent the appearance form of a variable in a sentence.

[0048] In an embodiment of the present invention, each variable can be associated with two column variable assignment input signals AX and AXB, used to represent the assignment status of each column variable in the macro array, where the assignment of a variable can include 0 and 1.

[0049] As an example, continue to refer to Figure 3 , when AX0 = 1 and AXB0 = 0, the assignment of variable X0 is positive; when AX0 = 0 and AXB0 = 1, the assignment of variable X0 is negative; when AX0 = AXB0 = 0, variable X0 is in an unassigned state; when AX0 = AXB0 = 1, variable X0 has a conflict.

[0050] In an embodiment of the present invention, each processing unit includes an SRAM cell. The two ends of the SRAM cell are respectively connected to a forward in-memory computing unit and a backward index unit, so as to realize the bidirectional derivation function from literal assignment to clause state and from clause state to literal assignment. Among them, the backward index unit can read all unassigned literals in the active clause set, so as to facilitate the update of variable assignment.

[0051] The modular SAT solving hardware design framework provided by the embodiment of the present invention supports flexible expansion to adapt to SAT problems of different scales. For example, the scale of the macro array can be adjusted according to actual needs, and the bit width and structure of the forward in-memory computing unit can also be configured according to actual needs to optimize performance.

[0052] The complete hardware K-SAT solver based on a dual-path macroarray designed in the embodiments of the present invention realizes the bidirectional derivation function from literal assignment to clause state and from clause state to literal assignment through a forward in-memory computing unit and a backward indexing unit, can handle both SAT cases and prove the existence of UNSAT cases, thereby realizing the integrity analysis of SAT problems. The present invention not only supports the efficient execution of unit propagation and heuristic decision-making, but also realizes the integrity analysis of SAT problems (including the verification of SAT and UNSAT) at the hardware level. Compared with traditional designs, the present invention can significantly improve the derivation efficiency and greatly reduce the area and power consumption of hardware implementation, has broad scalability, and is applicable to the solution of SAT problems of different scales.

[0053] In an alternative embodiment, the SRAM unit includes a first SRAM and a second SRAM, and the forms of appearance of variables in clauses include positive literals and negative literals; If a positive literal appears in a clause, the first SRAM corresponding to the positive literal is set to 1; If a negative literal appears in a clause, the second SRAM corresponding to the negative literal is set to 1; If a positive literal does not appear in a clause, the first SRAM corresponding to the positive literal is set to 0; If a negative literal does not appear in a clause, the second SRAM corresponding to the negative literal is set to 0.

[0054] Figure 4 is a schematic circuit diagram of the SRAM unit provided by the embodiments of the present invention. Refer to Figure 4 , in a specific implementation, the SRAM unit can be designed with a standard 6T structure. Since each Boolean variable X can include two literals (positive literal x and negative literal ¬x), each processing unit needs to represent the variable state through two 6T SRAM units.

[0055] As an example, if the literal x0 (i.e., the positive literal) appears in the clause C0, the corresponding SRAM 0,0 can be set to 1 (indicating that x0 is in C0); if the literal ¬x0 (i.e., the negative literal) appears in C0, the corresponding SRAM 1,0 can be set to 1 (indicating that ¬x0 is in C0); if the literal x0 (i.e., the positive literal) does not appear in the clause C0, the corresponding SRAM 0,0 can be set to 0 (indicating that x0 is not in C0); if the literal ¬x0 (i.e., the negative literal) does not appear in C0, the corresponding SRAM 1,0 can be set to 0 (indicating that ¬x0 is not in C0).

[0056] The design that represents variable states through two SRAM cells enables the embodiments of the present invention to achieve efficient representation of variable and clause states, thereby providing a reliable hardware foundation for subsequent solving processes.

[0057] In an alternative embodiment, the forward in-memory computing unit 220 includes a Boolean satisfiability problem (SAT) computing unit 221, an unassigned literal detector 222, and a position-encoded counter 223. The SAT computing unit 221 is configured to determine the level state of the row-wise SAT line based on variable assignments and the variable occurrence forms represented by the SRAM cells. The unassigned literal detector 222 is used to detect unassigned literals in a clause. The position-encoded counter 223 is used to count the number of unassigned literals in a clause.

[0058] Figure 5 is a schematic diagram of the circuit structure of the forward in-memory computing unit provided by the embodiments of the present invention. Referring to Figure 5 , the forward in-memory computing unit 220 can be composed of three parts: a SAT computing unit 221, an unassigned literal detector 222, and a position-encoded counter 223 (Position-Encoded Counter, PEC) for counting the number of unassigned literals in a clause, thereby realizing the forward derivation of variable to clause states.

[0059] Among them, the level state can include a high level and a low level, and the high level and the low level can respectively represent the states of logic "1" and "0".

[0060] Among them, an unassigned literal can refer to a literal that has not been assigned a specific Boolean value (true or false) in a given Boolean formula.

[0061] In some embodiments, the position-encoded counters between the respective processing units in each row can be connected in sequence before and after to count the number of unassigned literals in the clause corresponding to the current row of the macroarray. Thus, through the compact position-encoded counter, the accumulation of on-chip data can be achieved with extremely low hardware overhead, and this accumulation structure can be widely applied to various in-memory computing architectures that require accumulation within the macroarray.

[0062] The embodiments of the present invention implement a processing-in-memory (PIM) architecture by integrating computing logic within the SRAM cells. The in-memory computing architecture avoids a large amount of off-chip data transmission, significantly reduces power consumption, and is suitable for high-performance SAT solving in resource-constrained environments.

[0063] In an alternative embodiment, the SAT calculation unit is specifically configured to: reset the state nodes and the row-oriented SAT calculation line of the wired-OR in the unassigned literal detector to a low level through a reset signal; activate the first-column variable assignment signal and the second-column variable assignment signal to calculate the clause state based on the first-column variable assignment signal, the second-column variable assignment signal, and the variable occurrence form represented by the SRAM unit.

[0064] In an embodiment of the present invention, the forward in-memory calculation unit can implement an efficient derivation from variables to clause states through wired-OR and two-step dynamic logic.

[0065] Figure 6 It is a timing diagram of SAT calculation and unassigned literal detection provided by an embodiment of the present invention. In an embodiment of the present invention, the reset signal PCHF can first reset the state node SW and the row-oriented (wired-OR) SAT calculation line in the unassigned literal detector to a low level (Voltage Source Substrate, VSS, ground voltage) (at this time, SW = 0). Subsequently, the first-column variable assignment signal AX and the second-column variable assignment signal AXB can be activated to calculate the clause state.

[0066] Among them, the state nodes in the unassigned literal detector can be used to help the solver manage and process the literals that have not been decided during the unassigned literal detection process.

[0067] In an alternative embodiment, the SAT calculation unit is specifically configured to: if the first-column variable assignment signal is 1, the second-column variable assignment signal is 0, and the variable occurrence form represented by the SRAM unit is a positive literal, charge the row-oriented SAT line to a high level; if the first-column variable assignment signal is 0, the second-column variable assignment signal is 1, and the variable occurrence form represented by the SRAM unit is a negative literal, charge the row-oriented SAT line to a high level.

[0068] In an embodiment of the present invention, assume that clause j contains the literal ¬x i (that is, SRAM 2i+1,j is programmed to 1). When the column variable assignment signals are AX0 = 0 and AXB0 = 1 (indicating x i = -1), the row-oriented SAT line can be charged to a high level (Voltage Drain, VDD, positive supply voltage) by the SAT calculation unit, indicating that the clause is satisfied by the literal ¬x i is satisfied.

[0069] In an embodiment of the present invention, assume that clause j contains the literal x i (that is, SRAM 2i,jis programmed to 1). When the column variable assignment signal is AX0 = 1 and AXB0 = 0 (indicating x i = 1), the row - direction SAT line can be charged to a high level (VDD) by the SAT calculation unit, indicating that the clause is satisfied by the literal x i is satisfied.

[0070] In an alternative embodiment, the unassigned literal detector is specifically configured to charge the status node to a high level (i.e., SW = 1 at this time) when both the first column variable assignment signal and the second column variable assignment signal are 0.

[0071] In an embodiment of the present invention, when the column variable assignment signals AX0 = AXB0 = 0 (indicating that x i is unassigned, i.e., x i = Φ), the unassigned literal detection unit is activated and can charge the status node SW to a high level (VDD).

[0072] In an alternative embodiment, the position - encoding counter is specifically configured to: when the status node in the unassigned literal detector is 0, use the 3 - bit position encoding from the previous position - encoding counter as the output of the current position - encoding counter; when the status node in the unassigned literal detector is 1, shift the 3 - bit position encoding from the previous position - encoding counter one bit to the right to obtain the output of the current position - encoding counter; determine the number of unassigned literals in the clause based on the position of the target position encoding in the final output of the row - concatenated position - encoding counter.

[0073] In an embodiment of the present invention, the subsequent position - encoding counter can be adjusted based on the logical state of the node SW in the unassigned literal detector.

[0074] Figure 7 is the logical schematic diagram of the position - encoding counter provided by an embodiment of the present invention. Referring to Figure 7 , in a specific implementation, when SW = 0 (i.e., when the status node SW is charged to a high level), the current position - encoding counter can maintain the output of the 3 - bit position encoding (Position Code, PC) from the previous position - encoding counter; when SW = 1 (i.e., when the status node SW remains at a low level), the current position - encoding counter can shift the 3 - bit position encoding from the previous position - encoding counter to the right and output it.

[0075] The position - encoding counters in each row - processing unit can work in a row - concatenated manner, and the initial value of the first position - encoding counter in each row is {100}. Therefore, in the end - coding output of the position - encoding counters in each row - processing unit, the position of the "1" can determine the number of unassigned literals in the corresponding clause of that row - processing unit.

[0076] The position encoding counter provided by the embodiment of the present invention is compact and efficient, can be used for high-precision derivation of multi-level clause states, and can accurately count clause states and unassigned literals with extremely low hardware overhead.

[0077] In an alternative embodiment, all the position encoding counters of each row processing unit adopt a cascaded design; the clause state is determined as follows: if the row-wise SAT line is charged to a high level, it is determined that the clause has been satisfied; if the final output of the position encoding counter cascaded in the row is 100, it is determined that all variable assignments in the clause are incorrect; if the final output of the position encoding counter cascaded in the row is 010, it is determined that the clause is a unit clause; the unit clause is a clause that has not been satisfied but contains only one unassigned variable; if the final output of the position encoding counter cascaded in the row is 001 or 000, it is determined that the clause contains at least two unassigned vectors.

[0078] In the embodiment of the present invention, combining the 3-bit position encoding (PC) of the SAT line and the final output of the position encoding counter cascaded in the row can accurately determine the state of each clause.

[0079] If the SAT line is charged to a high level (VDD), it indicates that the clause has been satisfied; if the SAT line remains at a low level (GND), the clause state can be determined by the 3-bit position encoding (PC) of the final output of the position encoding counter cascaded in the row.

[0080] When the final output position encoding is {100}, it can indicate that all variable assignments in the clause are incorrect, resulting in a conflict.

[0081] When the final output position encoding is {010}, it can indicate that the clause is a unit clause, that is, the clause has not been satisfied but contains only one unassigned variable, and can be used for unit propagation.

[0082] When the final output position encoding is {001}, it can indicate that the clause contains two unassigned variables; when the final output position encoding is {000}, it can indicate that the clause contains at least two unassigned variables. At this time, the clause will only be activated for heuristic decision-making when there is no unit propagation or conflict clause.

[0083] Through the above mechanism, the embodiment of the present invention can accurately judge the clause state through the forward in-memory computing unit. The judgment method of the clause state can be as shown in Table 1: Table 1

[0084] In the embodiment of the present invention, the position encoding counter adopts a cascaded design. Through dynamic logic combined with displacement operations, the accumulated sum of the row vector can be quickly read out in row analysis.

[0085] In an alternative embodiment, the backward index unit is specifically configured to: charge all column matching lines to a high level through a reverse reset signal and activate the search lines of unsatisfied clauses; if a negative literal appears in a clause and the positive literal has not been assigned a value, activate the discharge path to pull down the column matching line corresponding to the negative literal to a low level; if a negative literal appears in a clause and the positive literal has been assigned a value, cut off the discharge path.

[0086] Figure 8 is a schematic circuit diagram of the backward index unit provided by the embodiment of the present invention. Figure 9 is when clause j contains the literal ¬x provided by the embodiment of the present invention i time sequence diagram of the backward index unit.

[0087] Referring to Figure 8 and Figure 9 , during unit propagation and heuristic decision-making processes, the backward index unit can perform the derivation operation of retrieving unassigned literals in clauses, and there is a corresponding operation time waveform. Since the literals in unsatisfied clauses may be unassigned variables or wrongly assigned variables (i.e., their complementary literals have been assigned values), the backward index (BW-IDX) unit can use two-step dynamic CMOS (Complementary Metal-Oxide-Semiconductor) logic to eliminate wrongly assigned literals and index unassigned variables.

[0088] In a specific implementation, the reverse reset signal PCHB can first charge all column matching lines (Match Line, ML) to a high level (VDD). Subsequently, the search lines (Search Line, SL) of selected unsatisfied clauses can be activated.

[0089] When the literal ¬x i appears in clause Cj and its complementary value (i.e., the positive literal x i ) has not been assigned a value, the discharge path is activated, and the corresponding ML 2i+1 is pulled down to a low level (GND). On the contrary, when x i = 1 (i.e., the complementary value of the literal ¬x i x i ) has been assigned a value), the discharge path is cut off, and the matching line corresponding to ¬xi will not be discharged through this processing unit.

[0090] In the embodiment of the present invention, the backward index unit completes the efficient indexing operation of unassigned literals through the dynamic matching line and the search line, and can accurately identify the unassigned variables and misassigned variables in the unsatisfied clauses, providing necessary hardware support for assignment update.

[0091] Figure 10 is the schematic diagram of the energy efficiency of the macro array provided by the embodiment of the present invention. Refer to Figure 10 , the complete macro array provided by the embodiment of the present invention can be manufactured and implemented under TSMC 28nm. It can achieve a maximum area efficiency of 471.4 GOPS / mm at a supply voltage of 0.9V, while it can achieve a maximum energy efficiency of 47.8 TOPS / mm at a supply voltage of 0.65V. 2 2

[0092] Figure 11 is the schematic diagram of the architecture of the complete hardware K-SAT solver provided by the embodiment of the present invention. Refer to Figure 11 , the complete hardware K-SAT solver provided by the embodiment of the present invention may include hardware components such as a dual-path macro array supporting bidirectional derivation, a read-write circuit for obtaining the input Boolean formula, and a decoder for obtaining the data address.

[0093] Although the prior art has made certain breakthroughs in incomplete SAT solving, there are still many limitations: First, they only support incomplete solving and cannot handle the proof of unsatisfiability (UNSAT), which significantly limits their applicability in practical applications, especially in scenarios where both SAT and UNSAT problems need to be verified simultaneously; Second, these designs only support unidirectional derivation, that is, the derivation from variables to clauses, lacking the reverse derivation ability from clauses to variables, which makes them unable to complete the bidirectional derivation process required for integrity analysis; In addition, the prior designs have limitations in the derivation granularity, generally adopting the derivation method with a single-bit granularity, resulting in low parallelism and computational efficiency, and it is difficult to meet the solving requirements of large-scale K-SAT problems.

[0094] Aiming at the above problems, the present invention is significantly superior to the existing K-SAT solving hardware solutions in terms of supporting integrity analysis, bidirectional derivation ability, and computational efficiency, filling the gap in the prior art, and providing an efficient and general solution for the hardware solving of K-SAT problems: (1) The present invention is the first macro architecture for SAT solving that supports completeness analysis at the hardware level and can solve both SAT and UNSAT problems simultaneously. Existing macro architectures (such as RNNSAT and SnapSAT) only support non-completeness analysis and cannot handle the verification of unsatisfiability (UNSAT). This limitation significantly restricts their scope of application in practical scenarios. By introducing bidirectional derivation (from variables to clauses and from clauses to variables) and integrity analysis techniques, the present invention can provide a new hardware solution for complex SAT problems in practical application scenarios.

[0095] (2) Support for multi-bit position-encoded counters (PECs), by introducing a multi-bit in-memory computing scheme in the derivation from variables to clauses, significantly improves the derivation efficiency. The position-encoded counter proposed in the present invention can count the number of unassigned literals in a clause at the SAT solver level and supports the accurate reading of multi-bit clause states. This counter can also be used in some in-memory computing architectures. Compared with traditional adder structures, the position-encoded counter can greatly reduce its area and energy consumption.

[0096] (3) The present invention breaks through the limitations of the prior art and provides core support for the completeness analysis of complex K-SAT applications in fields such as formal verification, electronic design automation (EDA), and fault diagnosis, especially showing significant application potential in tasks that require simultaneous verification of SAT and UNSAT.

[0097] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solutions or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or equivalently replace some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A complete hardware K-SAT solver based on a dual-path macroarray, characterized in that The macro array includes M×N processing units for solving an input Boolean formula, where the Boolean formula includes at most M clauses, and each clause contains at most N variables; the processing units in the i-th row correspond to the i-th clause of the Boolean formula, and the processing unit in the i-th row and j-th column is used to store the j-th variable in the i-th clause. The processing unit includes: A static random access memory (SRAM) unit for representing the occurrence form of a variable in a clause; A forward in-memory computing unit connected to one end of the SRAM unit, for deriving the clause state based on variable assignment and the occurrence form of the variable represented by the SRAM unit; A backward index unit connected to the other end of the SRAM unit, for reading all unassigned literals in the active clause set to support updating variable assignment.

2. The completeness hardware K-SAT solver according to claim 1, characterized in that The SRAM unit includes a first SRAM and a second SRAM, and the occurrence form of the variable in the clause includes a positive literal and a negative literal; If a positive literal appears in the clause, the first SRAM corresponding to the positive literal is set to 1; If a negative literal appears in the clause, the second SRAM corresponding to the negative literal is set to 1; If a positive literal does not appear in the clause, the first SRAM corresponding to the positive literal is set to 0; If a negative literal does not appear in the clause, the second SRAM corresponding to the negative literal is set to 0.

3. The completeness hardware K-SAT solver according to claim 1, characterized in that, The forward in-memory computing unit includes a Boolean satisfiability (SAT) computing unit, an unassigned literal detector, and a position encoding counter; The SAT computing unit is used to determine the level state of the row-wise SAT line based on variable assignment and the occurrence form of the variable represented by the SRAM unit; The unassigned literal detector is used to detect unassigned literals in the clause; The position encoding counter is used to count the number of unassigned literals in the clause.

4. The completeness hardware K-SAT solver according to claim 3, characterized in that The SAT computing unit is specifically used for: Through a reset signal, reset the state node and the line-OR row-wise SAT computing line in the unassigned literal detector to a low level; Activate the first-column variable assignment signal and the second-column variable assignment signal to calculate the clause state based on the first-column variable assignment signal, the second-column variable assignment signal, and the occurrence form of the variable represented by the SRAM unit.

5. The completeness hardware K-SAT solver according to claim 4, characterized in that, The SAT computing unit is specifically used for: If the first-column variable assignment signal is 1, the second-column variable assignment signal is 0, and the occurrence form of the variable represented by the SRAM unit is a positive literal, charge the row-wise SAT line to a high level; If the first-column variable assignment signal is 0, the second-column variable assignment signal is 1, and the occurrence form of the variable represented by the SRAM unit is a negative literal, charge the row-wise SAT line to a high level.

6. The completeness hardware K-SAT solver according to claim 4, characterized in that, The unassigned literal detector is specifically used to charge the state node to a high level when both the first-column variable assignment signal and the second-column variable assignment signal are 0.

7. The completeness hardware K-SAT solver according to claim 3, characterized in that, The position encoding counter is specifically used for: When the state node in the unassigned literal detector is 0, use the 3-bit position encoding from the previous position encoding counter as the output of the current position encoding counter; When the state node in the unassigned literal detector is 1, shift the 3-bit position encoding from the previous position encoding counter one bit to the right to obtain the output of the current position encoding counter. Based on the position of the target position encoding in the final output of the row-cascaded position encoding counter, determine the number of unassigned literals in the clause.

8. The completeness hardware K-SAT solver according to claim 7, characterized in that, All position encoding counters of each row processing unit adopt a cascaded design; the clause status is determined as follows: If the row-oriented SAT line is charged to a high level, it is determined that the clause has been satisfied. If the final output of the row-cascaded position encoding counter is 100, it is determined that all variable assignments in the clause are incorrect. If the final output of the row-cascaded position encoding counter is 010, it is determined that the clause is a unit clause; the unit clause is a clause that has not been satisfied but contains only one unassigned variable. If the final output of the row-cascaded position encoding counter is 001, it is determined that the clause contains two unassigned vectors. If the final output of the row-cascaded position encoding counter is 000, it is determined that the clause contains at least two unassigned vectors.

9. The completeness hardware K-SAT solver according to claim 1, characterized in that The backward index unit is specifically used for: Charge all column-matching lines to a high level through a reverse reset signal and activate the search line of the unsatisfied clause. If a negative literal appears in the clause and the positive literal has not been assigned, activate the discharge path to pull down the column-matching line corresponding to the negative literal to a low level. If a negative literal appears in the clause and the positive literal has been assigned, cut off the discharge path.

10. The completeness hardware K-SAT solver according to any one of claims 1-9, characterized in that, The complete hardware K-SAT solver further includes: A read-write circuit for obtaining the input Boolean formula. A decoder for obtaining the data address.

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