Circuit board defect sample generation method based on two-stage edge repair model

Abstract

The invention discloses a circuit board defect sample generation method based on a two-stage edge repair model. The method comprises the following steps: firstly, generating a mask at a proper position of a circuit board image by using a mask generator to obtain a circuit board image containing the mask; the mask, the circuit board image containing the mask and the circuit board edge image without the mask are input into a first-stage edge repairing module of a LaM-based large model and a prior up-sampling method, and a circuit board edge image containing defects is generated; and finally, inputting the defective circuit board edge image, the mask image and the circuit board image into a two-stage image inner drawing module based on Fourier convolution to finally obtain a defective circuit board sample image. According to the method, the generation of high-quality circuit board defect samples is realized, the generated defects have diversity and authenticity, and the problem of insufficient model training data in a circuit board defect sample detection algorithm caused by rare circuit board defect samples and non-uniform type distribution at present is effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of defective sample generation, and in particular to a method for generating circuit board defective samples based on a two-stage edge repair model. Background Art

[0002] The circuit board widely used in various electronic products, its safety and reliability are related to the quality and performance of the product. Circuit board defect detection is a key link to ensure the quality of electronic products.

[0003] In recent years, computer vision and deep learning technologies have developed rapidly. The deep learning defect detection method based on camera sensors has been widely used in the field of circuit board defect detection. This method has high detection efficiency, can reduce labor costs, and effectively improves the yield of circuit boards. However, the defect detection algorithm based on deep learning relies on feature extraction and autonomous learning, and a large amount of labeled data is required for network training. Its detection effect is greatly affected by the scale and quality of the training data.

[0004] In the field of deep learning, large-scale natural image datasets such as ImageNet, CIFAR, COCO, and PASCAL VOC are often used for image processing tasks. These datasets contain tens of thousands or even millions of images, which can meet the needs of deep learning networks for a large amount of training data.

[0005] However, in the scenario of circuit board defect detection, collecting a large amount of image data and screening and labeling them are costly, and the actual operation is difficult. Moreover, the distribution of various defects is uneven, which brings great difficulties to the detection of defect categories with small quantities, seriously affecting the detection accuracy and comprehensiveness.

[0006] To overcome these problems, many researchers have carried out sample augmentation for unbalanced small sample data in related research to improve the detection effect, providing new ideas and directions for the development of circuit board defect detection technology.

[0007] In the field of sample augmentation for circuit board defect detection, traditional methods mainly achieve this by operations such as cropping, translation, flipping, filtering, adding noise, and contrast adjustment on images. However, these methods have significant limitations. They only perform simple transformations on the original images and cannot create new defect targets, resulting in a lack of diversity in the generated defective samples.

[0008] Traditional repair methods have obvious defects. On the one hand, they overly rely on simple image transformation operations, resulting in texture blurring during the repair process. On the other hand, the loss of key detail features is prominent, which seriously affects the subsequent quality inspection of the circuit board. For example, when repairing the line texture on a circuit board, the filtering operation may make the originally clear line texture blurred, causing deviations in the appearance and performance inspection of the repaired circuit board, and seriously affecting the quality of the repaired circuit board and the accuracy of the inspection.

[0009] With the advent of the Generative Adversarial Network (GAN), many researchers have applied it to defect generation, hoping to solve the dilemmas of traditional methods. However, in practical applications, the defect generation method based on GAN exposes many problems when generating circuit board defect samples with complex backgrounds. On the one hand, it performs poorly in complex backgrounds, and the quality of the generated samples is difficult to guarantee. On the other hand, this method cannot accurately control the defects to appear in reasonable positions, which will lead to misjudgment or missed judgment in actual circuit board defect detection, greatly limiting its application value in the field of circuit board defect detection. Summary of the Invention

[0010] The present invention provides a method for generating circuit board defect samples based on a two-stage edge repair model, aiming to solve the problem that the existing defect generation methods generate circuit board samples with texture blurring and other problems in complex backgrounds, resulting in insufficient quality of the training samples for defect detection algorithms.

[0011] The present invention is realized through the following technical solutions:

[0012] The object of the present invention is realized through the following technical solutions: A two-stage circuit board defect sample generation method based on edge repair, the steps include:

[0013] S1. Mask generation based on the differentiation of training and testing strategies: Generate a mask image (M) at an appropriate position, and add the mask image (M) to the circuit board image (G1) to generate a circuit board image with a mask (G2). During training, set the mask at the defect position so that the network can learn the pattern of the defect. During testing, set the mask at a suitable position to control the defect to appear at any reasonable position.

[0014] S2. Edge repair based on the LaMa large model: Input the mask image (M) and the circuit board image with a mask (G2) generated in S1 into an edge repair network based on the LaMa large model to generate an initial defect edge repair image (E2).

[0015] S3. Edge Enhancement Based on Priori Upsampling Method: Input the initial edge defect map (E2) generated in S2 into an edge enhancement network based on the priori upsampling method, and cycle through this network to obtain a high-quality defect edge repair map (E3).

[0016] S4. Defect Edge Position Information Feature Vector Extraction Module Based on the Fusion of Autoencoder and Attention: Input the high-quality defect edge repair map (E3) generated in S3 into the defect edge position information feature vector extraction network based on the fusion of autoencoder and attention, and obtain the feature vector containing defect edges and position information from it.

[0017] S5. Defect Inpainting Network Based on LKA Sampling and Fast Fourier Convolution: Input the features extracted in S4 and the circuit board image (G2) with a mask into the defect inpainting network using LKA sampling and fast Fourier convolution to obtain the final circuit board image (G3) with defects.

[0018] Preferably, in step S2, the specific process of the edge generation module based on the LaMa large model is as follows:

[0019] S21. Obtain the corresponding edge map (E1) of the circuit board sample image (G2) with a mask obtained in S1 through the canny operator. Then, combine this map with the mask image (M) and the circuit board sample image (G2) with a mask in a splicing manner to obtain a high-dimensional feature vector, and input it into an edge repair network.

[0020] S22. The edge repair network adds a spectral normalization layer and an instance normalization layer during the upsampling and downsampling processes to stabilize model training and improve the robustness of the model. At the same time, the Vision Transformer module of the LaMa pre-trained model is embedded between the network encoder and decoder, and its cross-layer attention mechanism is used to establish global feature associations. In particular, multi-scale feature fusion is performed on edge defects such as broken traces and missing solder joints in the PCB image, and finally, a high-fidelity edge repair map (E2) is output through residual connection.

[0021] Preferably, in step S3, the specific process of the edge enhancement network based on the priori upsampling method is as follows:

[0022] S31. Obtain the initial edge defect map (E2) obtained in S2.

[0023] S32. Input it into an edge enhancement network based on the prior upsampling method. This network uses the learned canny edge defect map (E2) as prior information, and uses the newly introduced E-NMS and the SSU network trained with lines to avoid the line aliasing problem of traditional methods, obtaining high-quality high-resolution lines. Finally, the initial defect edge map (E2) is upsampled to a higher resolution to obtain a higher-quality defect edge map (E3).

[0024] Preferably, in step S4, the specific process of the defect edge position information feature vector extraction module based on the fusion of the autoencoder and attention is as follows:

[0025] S41. Obtain the high-quality defect edge map (E3) of S3.

[0026] S42. Input it into a pre-trained autoencoder (AE) network to obtain the feature information of the edge map in different dimensions. In particular, this AE network adopts a network structure based on unet, and the methods of instance normalization and spectral normalization are added during the sampling process to strengthen the network's perception ability of the edge spectral information.

[0027] S43. Multiply the feature vectors obtained by upsampling each layer of the graph (E3) after passing through this network with the feature vectors obtained after passing through each ResNet Block respectively to obtain 3 fused feature vectors. Finally, these three feature vectors are fused through the attention mechanism one by one to obtain the feature vector containing the defect edge and position information.

[0028] Preferably, in step S5, the defect inpainting network based on LKA sampling and fast Fourier convolution is as follows:

[0029] S51. Obtain the circuit board image (G2) with a mask and the feature vector obtained in S4.

[0030] S52. Input the feature vector obtained in S4 into the 3-layer LKA sampling layer and the 9-layer fast Fourier convolution module (Fast Fourier Convolution block) of this network as prior information.

[0031] S53. Input the circuit board image (G2) with a mask into this network, pass through the LKA sampling and fast Fourier convolution network, and combine the prior information in S52 to improve the image repair ability of the network under complex edge information, and finally obtain the circuit board sample map (G3) with defects.

[0032] Furthermore, in step S32, the specific structures and effects of E-NMS and SSU are as follows:

[0033] E-NMS is used to process learning-based edges. After restoring the structural prior through the Transformer Structure Restorer (TSR), the uncertain edge predictions generated by the TSR are screened to filter out the edges with low credibility. Then the screened edges are binarized so that the Simple Structure Upsampler (SSU) can iteratively upsample the canny edges like processing lines. E-NMS is used to eliminate the ambiguity of the L-Edges boundary and process it into clearer and more accurate edges.

[0034] The structure upsampling module (SSU) consists of cascaded residual convolutional blocks and a sub-pixel convolutional layer. By introducing an edge-aware loss function where is the Sobel gradient operator, forcing the upsampling result to maintain the same edge sharpness as the real image. Since the lines obtained from the wireframe parser have a good discrete representation, that is, a line can be represented by the positions of two endpoints and their relationship, the SSU can utilize this feature to draw line drawings at different resolutions without ambiguity. However, when upsampling the edges, if the same training strategy as that for lines is adopted, correct results cannot be obtained due to problems such as the ambiguity of Canny edges at different image sizes. By introducing edge non-maximum suppression (E-NMS) and combining it with the SSU trained with lines, this problem can be effectively solved, significantly eliminating the blur and artifacts near the boundary and improving the performance in tasks such as high-resolution image restoration.

[0035] Furthermore, in step S51, the specific structure of the LKA sampling and FFC module is as follows: The FFC layer contains two branches: the local branch uses traditional convolution, and the global branch convolves the features after the fast Fourier transform, and then combines the two branches to obtain a larger receptive field and local invariance during the restoration process.

[0036] The LKA sampling layer decomposes the LKA with a K×K receptive field into a depthwise convolution (DW-Conv2D) with a dilation rate a (2d - 1)×(2d - 1) depthwise dilated convolution (DW-D-Conv2D), and a pointwise convolution (Conv2d 1×1). This convolution method has the characteristics of both a large receptive field and scale invariance. Compared with ordinary attention mechanisms, it can better handle high-resolution image restoration tasks.

[0037] The present invention has the following advantages and effects compared with the prior art:

[0038] Traditional sample augmentation methods can only perform simple transformations on the original image and cannot create new defective targets, resulting in serious lack of sample diversity.

[0039] Through a unique network architecture based on mask repair and edge generation, the present invention can generate a large number of high-quality circuit board defect samples, greatly enriching the sample quantity. These samples are diverse and authentic, more in line with the actual circuit board defect situation, effectively solving the restriction of scarce samples on algorithm research and development, laying a solid foundation for training a more accurate detection model, and significantly improving the recognition ability of the detection algorithm for different types of defects.

[0040] When dealing with circuit board images, traditional repair methods rely too much on simple image transformation, often resulting in problems such as blurred texture and lost details. This not only affects the quality of the repaired circuit board but also reduces the detection accuracy.

[0041] The present invention applies advanced technologies such as an edge repair module based on Fourier convolution. During the process of generating defect samples, it can effectively retain and repair the texture, avoid the phenomenon of blurred texture, significantly improve the sample quality, and thus enhance the quality of the training samples for the detection algorithm. At the same time, the GAN-based method cannot accurately control the position where defects appear, easily causing misjudgment or missed judgment.

[0042] Through a mask generation method with differentiated training and testing strategies, the present invention enables the network to learn defect patterns during training and can flexibly control the appearance of defects at any position during testing, greatly improving the accuracy and reliability of defect detection.

[0043] The edge enhancement technology based on edge non-maximum suppression of the present invention is another key advantage in improving sample quality. This technology uses the SSU upsampling module based on CNN to upsample the lines to a higher resolution. At the same time, it uses the E-NMS technology to filter and refine the edge prediction, effectively eliminating blurring and artifacts near the boundary. Through the iterative upsampling process, even in the case of large image sizes, the clarity of the lines and edges can be maintained, ensuring rich edge information can be retained at different resolutions. This series of operations significantly improves the edge quality of the generated samples, making the detection of defect edges more accurate and further enhancing the accuracy and reliability of circuit board defect detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is the flowchart of the method of the present invention,

[0045] Figure 2 is the initial defect edge repair diagram (E2) generated,

[0046] Figure 3 is the circuit board sample diagram (G2) containing the mask,

[0047] Figure 4 is the high-quality defect edge diagram (E3) generated,

[0048] Figure 5 Finally, a defective circuit board sample diagram (G3) is obtained. Specific implementation manner

[0049] As Figures 1-5 shown, the present invention discloses a method for generating circuit board defect samples based on a two-stage edge repair model; the present invention will be further described in detail below in conjunction with specific embodiments.

[0050] As Figure 1 shown, in the two-stage repair process, the first stage (S1-S3) focuses on edge generation and enhancement, and the second stage (S4-S5) completes texture reconstruction, improving the generation quality by separating edge and texture processing.

[0051] S1. Mask generation based on training and test strategy differentiation: Generate a mask diagram (M) at an appropriate position, and add the mask diagram (M) to the circuit board image (G1) to generate a circuit board image with a mask (G2) (as Figure 3 ). During training, set the mask at the defect position so that the network learns the defect pattern; during testing, set the mask at a suitable position to control the defect to appear at any reasonable position

[0052] S2. Edge repair based on the LaMa large model: Input the mask diagram (M) generated in S1 and the circuit board image with a mask (G2) into an edge repair network based on the LaMa large model to generate an initial defect edge repair diagram (E2) (as Figure 2 ).

[0053] S21. Obtain the corresponding edge diagram (E1) of the circuit board sample diagram with a mask (G2) obtained in S1 through the canny operator, and then obtain a high-dimensional feature vector by splicing this diagram with the mask diagram (M) and the circuit board sample diagram with a mask (G2), and input it into an edge repair network.

[0054] S22. The edge repair network adds a spectral normalization layer and an instance normalization layer during the upsampling and downsampling process to stabilize model training and improve the robustness of the model. At the same time, a Vision Transformer module of the LaMa pre-trained model is embedded between the network encoder and decoder, and its cross-layer attention mechanism is used to establish global feature associations, especially for multi-scale feature fusion of edge defects such as broken traces and missing solder joints in PCB images, and finally a high-fidelity edge repair diagram (E2) is output through residual connection.

[0055] S3. Edge Enhancement Based on Priori Upsampling Method: Input the initial edge defect map (E2) generated in S2 into an edge enhancement network based on the priori upsampling method, and obtain a high-quality defect edge repair map (E3) by repeatedly using this network (as shown in Figure 4 ).

[0056] S31. Obtain the initial edge defect map (E2) from S2.

[0057] S32. Input it into an edge enhancement network based on the priori upsampling method. This network uses the learned canny edge defect map (E2) as priori information, and uses the newly introduced E-NMS and the SSU network trained with lines to avoid the line aliasing problem of traditional methods, obtaining high-quality high-resolution lines. Finally, upsample the initial defect edge map (E2) to a higher resolution to obtain a higher-quality defect edge map (E3).

[0058] S4. Defect Edge Position Information Feature Vector Extraction Module Based on the Fusion of Autoencoder and Attention: Input the high-quality defect edge repair map (E3) generated in S3 into the defect edge position information feature vector extraction network based on the fusion of autoencoder and attention, and obtain the feature vector containing defect edges and position information from it.

[0059] S41. Obtain the high-quality defect edge map (E3) of S3.

[0060] S42. Input it into a pre-trained autoencoder (AE) network to obtain the feature information of the edge map in different dimensions. In particular, this AE network adopts a network structure based on unet, and adds instance normalization and spectral normalization methods during the sampling process to enhance the network's perception ability of edge spectral information.

[0061] S43. Dot-multiply the feature vectors obtained by upsampling each layer of the map (E3) after passing through this network with the feature vectors obtained after passing through each RetNet Block respectively to obtain 3 fused feature vectors. Finally, fuse these three feature vectors through a per-attention mechanism to obtain the feature vector containing defect edges and position information.

[0062] S5. Defect Inpainting Network Based on LKA Sampling and Fast Fourier Convolution: Input the features extracted in S4 and the circuit board image with a mask (G2) into the defect inpainting network using LKA sampling and fast Fourier convolution to obtain the final circuit board image with defects (G3).

[0063] S51. Obtain the circuit board image with a mask (G2) and the feature vector obtained in S4.

[0064] S52. Input the feature vectors obtained in S4 into the 3-layer LKA sampling layer and the 9-layer Fast Fourier Convolution block of the network simultaneously as prior information.

[0065] S53. Input the circuit board image (G2) with a mask into the network, and through LKA sampling and the Fast Fourier Convolution network, and combine the prior information in S52 to improve the network's image restoration ability for complex edge information, and finally obtain the circuit board sample image (G3) with defects (as Figure 5 ).

[0066] In this embodiment, the loss function of the above-mentioned edge generation network can be as follows:

[0067]

[0068] In the process of edge repair in the first stage, the L1 loss and the adversarial loss are used. The L1 loss is mainly used to measure the pixel difference between the predicted image and the real image in the unmasked area. The formula is:

[0069] Where M is a 0-1 mask, where 1 represents the masked area and 0 represents the unmasked area, which is used to specify the image area range to be considered when calculating the loss. represents the real image, which is the target image that the model expects to approximate. represents the predicted image, which is the restored image generated by the model after training. |·|1 represents the L1 norm, which is used here to calculate the sum of the absolute values of the differences between the corresponding pixels of the real image and the predicted image.

[0070] The adversarial loss consists of the discriminator loss and the generator loss. The formula is:

[0071]

[0072] The discriminator tries to distinguish between the real image and the restored image generated by the generator, and the generator tries to deceive the discriminator. This adversarial training method enables the generator to generate more realistic images. In image restoration, the adversarial loss makes the restored result generated by the model visually closer to the real image, enhancing the realism and naturalness of the image, and making the restored image look more in line with people's visual perception.

[0073] In the second stage, in addition to using the above two loss functions, the feature matching loss and the high-field perception loss are also involved.

[0074] The feature matching loss is based on the L1 loss between the discriminator features of real and fake samples. It is mainly used to stabilize GAN training and can also improve the model performance. During the image inpainting process, the feature matching loss helps the model better learn the feature representation of the image, making the inpainted image more conform to the distribution of real images at the feature level, contributing to the model's capture of the details and semantic information of the image, and thus improving the quality of the inpainted image.

[0075] The formula for the High Receptive Field (HRF) perception loss is:

[0076]

[0077] where φ hrf is the pre-trained segmentation ResNet50 with dilated convolutions. The HRF perception loss constrains the model at the perception level, making the inpainted image closer to the real image in terms of high-level semantics and structure. Through this loss function, the model can better understand the overall structure and semantic information of the image, avoiding structural distortion or semantic unreasonableness during the inpainting process, and improving the accuracy and reasonableness of image inpainting.

[0078] As described above, the present invention can be preferably implemented.

[0079] The embodiments of the present invention are not limited by the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A method for generating circuit board defect samples based on a two-stage edge repair model, characterized in that It includes the following steps: S1. Mask generation based on training and test strategy differentiation: Generate a mask image at an appropriate position, and add the mask image to the circuit board image to generate a circuit board image with a mask; S2. Edge repair based on the LaMa large model: Input the mask image and the circuit board image with a mask generated in step S1 into an edge repair network based on the LaMa large model to generate an initial defective edge repair image; S3. Edge enhancement based on the prior upsampling method: Input the initial defective edge image generated in step S2 into the edge enhancement network, and repeatedly use this network to obtain a high-quality defective edge repair image; S4. Defective edge position information feature vector extraction module based on the fusion of autoencoder and attention: Input the high-quality defective edge repair image generated in step S3 into the defective edge position information feature vector extraction network based on the fusion of autoencoder and attention to obtain a feature vector containing defective edges and position information; S5. Defective inpainting network based on LKA sampling and fast Fourier convolution: Input the features extracted in step S4 and the circuit board image with a mask into the defective inpainting network using LKA sampling and fast Fourier convolution to obtain the final circuit board image with defects.

2. The method for generating circuit board defect samples based on the two-stage edge repair model according to claim 1, wherein Step S1 based on training and testing means that during training, the mask is set at the defective position so that the network can learn the pattern of the defect; during testing, the mask is set at an appropriate position to control the defect to appear at any reasonable position.

3. The method for generating a circuit board defect sample based on a two-stage edge repair model according to claim 1, wherein In step S2, the specific process of the edge repair network based on the LaMa large model is as follows: S21. Obtain the corresponding edge image of the circuit board sample image with a mask obtained in step S1 through the canny operator, and then obtain a high-dimensional feature vector by splicing the edge image, the mask image, and the circuit board sample image with a mask, and input it into an edge repair network; S22. The edge repair network adds a spectral normalization layer and an instance normalization layer during the upsampling and downsampling processes to stabilize model training and improve the robustness of the model; at the same time, a Vision Transformer module of the LaMa pre-trained model is embedded between the network encoder and decoder to establish global feature correlations using its cross-layer attention mechanism, and multi-scale feature fusion is performed specifically for edge defects such as broken traces and missing solder joints in PCB images. Finally, a high-fidelity edge repair image is output through a residual connection.

4. The method for generating circuit board defect samples based on a two-stage edge repair model according to claim 1, wherein In step S3, the specific process of the edge enhancement network based on the prior upsampling method is as follows: S31. Obtain the initial edge defect image obtained in step S2; S32. Input the initial edge defect image into an edge enhancement network based on the prior upsampling method. The edge enhancement network uses the learned canny edge defect image as prior information, and uses the newly introduced E-NMS and the SSU network trained with lines to avoid line aliasing to obtain high-quality high-resolution lines; finally, the initial defective edge image is upsampled to a higher resolution to obtain a higher-quality defective edge image.

5. The method for generating circuit board defect samples based on the two-stage edge repair model according to claim 1, wherein In step S4, the specific process of the defective edge position information feature vector extraction module based on the fusion of autoencoder and attention is as follows: S41. Obtain the high-quality defective edge map of step S3; S42. Input the high-quality defective edge map into a pre-trained autoencoder network to obtain the feature information of the edge map in different dimensions; S43. Dot-multiply the feature vectors obtained by upsampling the high-quality defective edge map layer by layer after passing through the network with the feature vectors obtained after passing through each ResNet Block respectively to obtain three fused feature vectors; finally, fuse these three feature vectors through a per-point attention mechanism to obtain a feature vector containing defective edge and position information.

6. The method for generating a circuit board defect sample based on a two-stage edge repair model according to claim 1, wherein In step S5, the specific process of the defective inpainting network based on LKA sampling and fast Fourier convolution is as follows: S51. Obtain the circuit board image with a mask and the feature vector obtained in step S4; S52. Input the feature vector obtained in step S4 into the three-layer LKA sampling layer and the nine-layer fast Fourier convolution module of the network simultaneously as prior information; S53. Input the circuit board image with a mask into the network, pass through the LKA sampling and fast Fourier convolution network, and combine the prior information in step S52 to improve the image repair ability of the network under complex edge information, and finally obtain a circuit board sample image with defects.

7. The method for generating a circuit board defect sample based on a two-stage edge repair model according to claim 4, wherein In step S32, the process of the E-NMS method is as follows: S61. After restoring the structure prior of the initial canny edge map through the Transformer Structure Restorer, screen the uncertain edge predictions generated by the TSR to filter out the edges with low credibility; S62. Binarize the screened edges, perform iterative upsampling on the canny edges, and use E-NMS to eliminate the ambiguity of the L-Edges boundary.

8. The method for generating a circuit board defect sample based on a two-stage edge repair model according to claim 4, wherein In step S32, the process of the SSU method is as follows: S71. Obtain the lines of the edge map from the wireframe interpreter; S72. Input the lines into an upsampling network composed of cascaded residual convolutional blocks and sub-pixel convolutional layers, and introduce an edge-aware loss function to make the edge sharpness of the upsampling result consistent with the real image; S73. Introduce edge non-maximum suppression (E-NMS) to solve the ambiguity of Canny edges in different image sizes.

9. The method for generating a circuit board defect sample based on a two-stage edge repair model according to claim 6, wherein The specific structure of LKA sampling in step S51 is as follows: S81. Obtain the features extracted in S4 and the circuit board image with a mask; S82. Process the input feature vector using a depth convolution with a dilation rate d; S83. On the basis of the depth convolution, further adopt a depth dilated convolution to further increase the receptive field; S84. Finally, use a pointwise convolution to perform channel fusion and dimension adjustment on the feature maps obtained from the previous two convolution operations, linearly combine the features of different channels, and generate the final output feature map to meet the input requirements of the subsequent network layers.

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