Clock recovery device and display driving device including the same

Abstract

The invention relates to a clock recovery device and a display driving device including the same. A clock recovery apparatus according to an embodiment may include: a clock generator configured to generate a master clock signal from embedded transmission data; a delay line for generating a multi-level clock signal by delaying the master clock signal by a preset reference delay time unit based on an input frequency; and a delay controller configured to receive two clock signals delayed by a reference delay time unit among the multi-stage clock signals and detect a delay time, output a selection signal based on the delay time and the reference delay time, correct a delay time of the master clock signal to the reference delay time based on the selection signal, and output a clock signal to the master clock signal based on the corrected delay time. And outputs the master clock signal corrected to the reference delay time to the delay line; and a data recovery module configured to recover the multi-level clock signal corrected to the reference delay time by the delay line.

Description

Technical Field

[0001] This embodiment relates to a clock recovery device and a display driving device including the clock recovery device. More specifically, it relates to a clock recovery device that changes the delay time of a clock signal to be the same and a display driving device including the clock recovery device. Background Art

[0002] A display device includes a panel that displays an image through a pixel matrix, a gate driver that drives gate lines of the panel, a data driver that provides data signals to data lines of the panel, a timing controller that controls the gate driver and the data driver, etc. The data driver includes a plurality of data driving ICs (integrated circuits) that divide and drive the data lines.

[0003] The timing controller serializes parallel data and transmits it to the plurality of data driving ICs, and each of the plurality of data driving ICs can recover clock and data information from the transmitted signal and use them.

[0004] The clock recovery unit applied to the receiving unit of a conventional display device generates a clock with a delay time equal to the embedded clock frequency.

[0005] Due to the same input / output capacitance, the delay time inside the voltage-controlled delay line in the clock recovery section has a constant value. However, since the capacitance or length of the line providing the main clock signal is different from the capacitance or length inside the voltage-controlled delay line, there is an error between the first delay time and the second delay time.

[0006] Due to the above-mentioned error, a specific part for establishing or maintaining a margin during data recovery is damaged, which narrows the application range. Summary of the Invention

[0007] The purpose of this embodiment is to provide a clock recovery device and a display driving device including the clock recovery device to prevent errors in the delay time due to input / output capacitance.

[0008] To solve the above problems, the clock recovery device according to the present embodiment may include: a clock generator configured to generate a master clock signal from embedded transmission data; a delay line for generating a multi-level clock signal by delaying the master clock signal by a preset reference delay time unit based on the input frequency; a delay controller configured to receive two clock signals that are delayed by the reference delay time unit among the multi-level clock signals, detect the delay time, output a selection signal based on the delay time and the reference delay time, correct the delay time of the master clock signal to the reference delay time based on the selection signal, and output the master clock signal corrected to the reference delay time to the delay line; and a data recovery module configured to recover the multi-level clock signal corrected to the reference delay time by the delay line.

[0009] When the input frequency is a low frequency, the delay controller may increase the delay time by reducing the rise time of the clock signal via an inverter of a determined size.

[0010] The delay controller may include a first inverter of a large size and a second inverter of a small size, and the inverter of the determined size may be the first inverter.

[0011] When the input frequency is a high frequency, the delay controller may reduce the delay time by increasing the rise time of the clock signal via an inverter of a determined size.

[0012] The delay controller may include a first inverter of a large size and a second inverter of a small size, and the inverter of the determined size may be the second inverter.

[0013] The delay line includes a plurality of inverters and is capable of generating a multi-level clock signal by passing through the plurality of inverters.

[0014] In addition, to solve the above problems, a display driving device that recovers a clock signal and data from an input signal and drives a display panel using the recovered clock signal and data may include a clock recovery device, which includes: a clock generator configured to generate a master clock signal from embedded transmission data; a delay line for generating a multi-level clock signal by delaying the master clock signal by a preset reference delay time unit based on the input frequency; a delay controller configured to receive two clock signals that are delayed by the reference delay time unit among the multi-level clock signals, detect the delay time, output a selection signal based on the delay time and the reference delay time, correct the delay time of the master clock signal to the reference delay time based on the selection signal, and output the master clock signal corrected to the reference delay time to the delay line; and a data recovery module configured to recover the multi-level clock signal corrected to the reference delay time by the delay line.

[0015] The delay control unit can compare the delay time with a reference delay time and output a selection signal including "1" or "0" based on the comparison result.

[0016] The delay control unit can determine the size of an inverter for outputting a main clock signal based on the selection signal.

[0017] In addition, to solve the above problems, the clock recovery method according to the present embodiment may include the following steps: generating a main clock signal from embedded transmission data; generating a multi-level clock signal by delaying the main clock signal by a preset reference delay time unit based on the input frequency; receiving two clock signals that are delayed by the reference delay time unit among the multi-level clock signals, detecting the delay time, comparing the delay time with the reference delay time, outputting a selection signal based on the comparison result, and determining the size of an inverter for outputting the main clock signal based on the selection signal, and recovering the multi-level clock signal with the delay time corrected to the reference delay time through the inverter with the determined size.

[0018] In the step of determining the size of the inverter, when the input frequency is a low frequency, the delay time can be increased by reducing the rising time of the clock signal through the inverter with the determined size.

[0019] In the step of determining the size of the inverter, the inverter may include a first inverter with a large size and a second inverter with a small size, and the inverter with the determined size may be the first inverter.

[0020] In the step of determining the size of the inverter, when the input frequency is a high frequency, the delay time can be reduced by increasing the rising time of the clock signal through the inverter with the determined size.

[0021] In the step of determining the size of the inverter, the inverter may include a first inverter with a large size and a second inverter with a small size, and the inverter with the determined size may be the second inverter.

[0022] The step of generating a multi-level clock signal can generate a multi-level clock signal by passing through a plurality of inverters.

[0023] The present embodiment can increase the frequency range in which the clock recovery device can operate by ensuring setup or hold margins during data recovery.

[0024] In addition, the present embodiment can increase the operating range of the clock recovery device, thereby expanding the application range.

[0025] In addition, the present embodiment can improve the yield loss of the device. Brief Description of the Drawings

[0026] Figure 1It is a block diagram of a display driving device according to an embodiment and a display device including the display driving device.

[0027] Figure 2 It is a configuration diagram showing a clock recovery device provided in a display driving device according to an embodiment.

[0028] Figure 3 It is a circuit diagram showing the structure of a voltage-controlled delay line of a clock recovery device according to an embodiment.

[0029] Figure 4 It is a circuit diagram showing the structure of a delay control unit of a clock recovery device according to an embodiment.

[0030] Figure 5 It is a timing diagram showing a conventional delay time when the input frequency is a low frequency.

[0031] Figure 6 It is a timing diagram showing a delay time according to an embodiment when the input frequency is a low frequency.

[0032] Figure 7 It is a timing diagram showing a conventional delay time when the input frequency is a high frequency.

[0033] Figure 8 It is a timing diagram showing a delay time according to an embodiment when the input frequency is a high frequency.

[0034] Figure 9 It is a graph showing a first delay range according to an increase in data rate by a large-sized inverter.

[0035] Figure 10 It is a graph showing a first delay range according to an increase in data rate by a small-sized inverter.

[0036] Figure 11 It is a flowchart showing a clock recovery method according to an embodiment.

[0037] Figure 12 It is a flowchart showing a detailed process of determining the size of an inverter according to an embodiment. Detailed Embodiments

[0038] Hereinafter, embodiments will be described in detail with reference to the drawings. These embodiments can have various modifications and can adopt various styles. Therefore, specific embodiments will be shown in the drawings and described in detail in the text. However, this is not intended to limit the embodiments to the specific forms disclosed, and it should be understood that it includes all modifications, equivalent forms, or alternative forms within the spirit and technical scope of these embodiments.

[0039] Terms such as "first" and "second" may be used to describe various components, but these components should not be limited by these terms. These terms are used to distinguish components from each other. In addition, terms specifically defined in consideration of the structure and operation of the embodiment are only used to describe the embodiment and do not limit the scope of the embodiment.

[0040] In the description of the embodiment, when describing that an element is formed "on or under" each element, "on or under" includes two cases where the two elements are in direct contact with each other, or one or more other elements are indirectly located between the two elements. In addition, when expressed as "on or under", it may include not only the meaning of the upward direction based on one element, but also the downward direction.

[0041] In addition, relational terms such as "upper / above / top" and "lower / below / bottom" used hereinafter may be used to distinguish one entity or element from another entity or element, but do not necessarily require or imply any physical or logical relationship or order between these entities or elements.

[0042] The receiving unit device according to an embodiment may be configured to include a serial-to-parallel converter and a clock recovery device according to this embodiment. The serial-to-parallel converter receives transmission data (clock-embedded data: CED) in the form of a clock signal (hereinafter collectively referred to as "transmission data (CED)") sent from a timing control unit through a serial signal line, converts it into parallel data, and then sends the recovered data signal (recovered data) to the display panel; the clock recovery device extracts the embedded clock signal from the transmission data (CED) in which the clock signal is embedded between the data signals, and sends the sampling clock signal for recovering the data signal to the serial-to-parallel converter, and outputs the recovered clock signal (recovered clock) for data output.

[0043] Figure 1 is a block diagram of a display driving device according to an embodiment and a display device including the display driving device.

[0044] Referring to Figure 1 , the display device according to an embodiment may include a timing controller 10, a display driving device 20, a microcontroller 30, and a display panel 40.

[0045] The timing controller 10 receives image data and a timing signal from a host system (not shown), performs image processing such as image quality compensation on the image data, and provides a differential input signal (CEDA, CEDB) in which a clock is embedded in the data (image and control data) to the display driving device.

[0046] The display driving device 20 can recover a clock signal and data from the input signals (CEDA, CEDB), and drive the display panel 40 using the recovered clock signal and data. In addition, the display driving device 20 can detect a touch on the display panel 40 using the recovered clock signal.

[0047] The display driving device 20 may be equipped with a clock recovery device 1000 for recovering a clock.

[0048] Figure 2 is a configuration diagram showing a clock recovery device according to an embodiment.

[0049] Refer to Figure 2 , the clock recovery device 1000 according to an embodiment may include a clock generator 100, a delay control unit 200, a voltage-controlled delay line (VCDL, 300), a data recovery unit 400, a phase comparison unit 500, and a low-pass filter 600.

[0050] The clock generator 100 may receive transmission data (clock-embedded data: CED) in which a clock signal transmitted from a transmitter is embedded between data signals. The clock generator 100 may receive a multi-level clock signal (CK1, CK2,... CK2N+1) that is a delayed clock signal output from the voltage-controlled delay line 300 as an input.

[0051] The clock generator 100 may generate a main clock signal (MCLK_PRE) through the transmission data (CED) configured in the form of a clock signal input during a clock training period before generating the multi-level clock signal. At this time, the number of multi-level clock signals must be at least greater than or equal to 2N+1, where N is a natural number representing the number of data bits present between clock bits.

[0052] The delay control unit 200 according to an embodiment may receive the main clock signal (MCLK_PRE). The delay control unit 200 may correct the delay time using the multi-level clock signal output from the voltage-controlled delay line 300, and output the main clock signal (MCLK) with the corrected delay time to the voltage-controlled delay line 300. The delay control unit 200 according to an embodiment will be described in detail later.

[0053] The voltage-controlled delay line 300 may generate a multi-level clock signal by delaying the main clock signal (MCLK_PRE) by a preset reference delay time unit based on the input frequency. In addition, the voltage-controlled delay line 300 may generate a multi-level clock signal based on the main clock signal (MCLK) with the corrected delay time.

[0054] Figure 3 is a circuit diagram showing the structure of the voltage-controlled delay line of the clock recovery device according to an embodiment.

[0055] AsFigure 3 As shown, the voltage-controlled delay line 300 can be configured based only on a delay-locked loop (DLL) equipped with a plurality of delay devices capable of receiving, delaying, and outputting a main clock signal (MCLK).

[0056] A plurality of inverters 310 can be used as delay devices. The plurality of inverters 310 use two inverter pairs as one delay unit, and generate and output delayed clock signals (CK1, CK2, CK3,..., CK2N+1) while passing through the inverter pair composed of two inverters.

[0057] The above describes the voltage-controlled delay line as a delay line, but it can also be configured as a current-controlled delay line (CCDL).

[0058] Back to Figure 2 , the data recovery unit 400 can recover the remaining part of the clock signal output from the voltage-controlled delay line 300 and inserted between the data except for the edges.

[0059] The phase difference comparison unit 500 takes as inputs any two signals among the multi-stage clock signals delayed in the voltage-controlled delay line 300 based on a delay-locked loop equipped with delay devices and the input clock signal of the delay-locked loop, and can generate a rising / falling signal (UP / DN) as a delay amount control signal according to the time difference between these two signals.

[0060] When the lock signal becomes a logic high state and the delay-locked loop is locked, the phase difference comparison unit 500 takes as inputs the time difference between the main clock signal (MCLK) output from the clock generator 100 and any two clock signals among the delayed clock signals (CK1, CK2, CK3,..., CK2N+1) output from the voltage-controlled delay line 300 whose periods are the same as the period in which the clock bits are inserted. It can be configured to generate a rising / falling signal according to the time difference between these two input clock signals.

[0061] The low-pass filter 600 can remove or reduce the high-frequency components of the rising / falling signal (UP / DN) generated by the time difference between two clock signals in the phase difference comparison unit 500 to output a voltage signal (VCOUNT). The low-pass filter 600 can be composed of a combination of a charge pump unit 610 and a loop filter unit 620.

[0062] In addition, since Figure 3 the capacitance or length of the line providing the main clock signal in

[0063] is different from the capacitance or length inside the voltage-controlled delay line, the first delay time can be different from the second delay time.

[0064] Figure 4 It is a circuit diagram showing the structure of a delay control unit of a clock recovery device according to an embodiment.

[0065] Referring to Figure 4 , the delay control unit 200 according to an embodiment may include a delay detector 210 and a clock extractor 220.

[0066] The delay detector 210 may receive two clock signals (CK2, CK3) delayed by a reference delay time unit among multi-level clock signals, and detect the delay time (CK2_delay) of the clock signal CK2.

[0067] The delay detector 210 may compare the delay time (CK2_delay) with a reference delay time, and output a selection signal based on the comparison result. Here, the reference delay time may be a predetermined time. For example, the reference delay time may be 0.5UI, but the reference delay time may vary.

[0068] The clock extractor 220 may determine or change the size of an inverter that outputs a main clock signal based on the selection signal. Here, the selection signal may be "1" or "0". The clock extractor 220 may include a first inverter 221 with a large size and a second inverter 222 with a small size, but the number is not limited thereto.

[0069] For example, when the input frequency is low, the first delay time may be increased by using the first inverter 221 with a large size. On the other hand, when the input frequency is high, the first delay time may be reduced by using the second inverter 222 with a small size.

[0070] Figure 5 It is a timing diagram showing a conventional delay time when the input frequency is low.

[0071] As Figure 5 shown, when the input frequency is low, the first delay time may be less than the second delay time or the third delay time (which is 0.5UI).

[0072] Figure 6 It is a timing diagram showing the delay time according to an embodiment when the input frequency is low.

[0073] As Figure 6 shown, when the input frequency is low, if the first inverter 221 with a large size is selected by the delay control unit according to the embodiment, the rise time of the first delay time becomes shorter, and correspondingly, the first delay time may be 0.5UI, which is the same as the second delay time or the third delay time.

[0074] Figure 7 It is a timing diagram showing a conventional delay time when the input frequency is high.

[0075] As Figure 7 shown, when the input frequency is a high frequency, the first delay time can be greater than 0.5UI (which is the second delay time or the third delay time).

[0076] Figure 8 is a timing diagram showing the delay time according to an embodiment when the input frequency is a high frequency.

[0077] As Figure 8 shown, when the input frequency is a high frequency, if a small-sized second inverter is selected by the delay control unit according to the embodiment, the rise time of the first delay time increases. Accordingly, the first delay time can be 0.5UI, which is the same as the second delay time or the third delay time.

[0078] Figure 9 is a graph showing the first delay range according to the increase in data rate by a large-sized inverter.

[0079] As Figure 9 shown, the large-sized first inverter can have such specifications that as the data transfer speed (data rate) increases, the first delay time increases in the range of 0.5UI to 0.9UI. The above change range can be changed by the user according to a preset reference delay time.

[0080] Figure 10 is a graph showing the first delay range according to the increase in data rate by a small-sized inverter.

[0081] As Figure 10 shown, the small-sized second inverter can have such specifications that as the data transfer speed (data rate) increases, the first delay time increases in the range of 0.1UI to 0.5UI. The above change range can be changed by the user according to a preset reference delay time.

[0082] Figure 11 is a flowchart showing the clock recovery method according to an embodiment.

[0083] Referring Figure 11 , the clock recovery method according to an embodiment can perform the steps of generating a master clock signal (S100), generating a multi-level clock signal (S200), determining the size of the inverter for compensating the first delay time (S300), and recovering the multi-level clock signal (S400).

[0084] The clock recovery method according to an embodiment can be performed in a clock recovery device according to an embodiment.

[0085] The clock generation unit may generate a master clock signal from the embedded transmission data (S100). More specifically, the clock generation unit may receive transmission data (CED) in which a clock signal transmitted from a transmission unit is embedded between data signals. The clock generation unit may receive a multi-level clock signal (CK1, CK2... CK2N+1) output from a voltage-controlled delay line as an input. The clock generation unit may generate a master clock signal (MCLK) through the transmission data (CED) configured in the form of a clock signal input during a clock training period before generating the multi-level clock signal.

[0086] The voltage-controlled delay line may generate a multi-level clock signal by delaying the master clock signal by a preset standard delay time unit based on the input frequency (S200).

[0087] More specifically, the voltage-controlled delay line may be configured based only on a delay locked loop (DLL) equipped with a plurality of delay devices capable of receiving, delaying, and outputting the master clock signal. A plurality of inverters may be used as delay devices. The plurality of inverters use two inverter pairs as one delay unit, and generate and output delayed clock signals (CK1, CK2, CK3,... CK2N+1) while passing through the inverter pair composed of two inverters.

[0088] The delay control unit may determine the size of the inverter for correcting the first delay time (S300). The delay control unit may output the master clock signal whose delay time is corrected by passing through the inverter.

[0089] Figure 12 is a flowchart showing a detailed process of determining the size of the inverter according to an embodiment.

[0090] As Figure 12 shown, the delay control unit may receive two clock signals delayed by a reference delay time unit among the multi-level clock signals and detect the delay time (S310).

[0091] The delay control unit may compare the delay time with a preset reference delay time (S320).

[0092] The delay detector may compare the delay time with the reference delay time and output a selection signal based on the comparison result (S330). Here, the selection signal may include "1" or "0".

[0093] The delay detector may determine or change the size of the inverter that outputs the master clock signal based on the selection signal (S340).

[0094] For example, when the input frequency is low, the first delay time can be increased by using a first inverter with a large size. On the other hand, when the input frequency is high, the first delay time can be decreased by using a second inverter with a small size.

[0095] Return to Figure 11 , the data recovery unit can recover the multi-level clock signal generated based on the corrected master clock signal (S400).

[0096] Although the above has been described with reference to the accompanying drawings and embodiments, those skilled in the art will understand that these embodiments can be variously modified and changed without departing from the technical idea of the embodiments described in the patent claims.

Claims

1. A clock recovery device, the clock recovery device comprising: A clock generator configured to generate a master clock signal from embedded transmission data; A delay line for generating a multi-level clock signal by delaying the master clock signal by a preset reference delay time unit based on an input frequency; A delay controller configured to receive two clock signals delayed by a reference delay time unit among the multi-level clock signals and detect a delay time, output a selection signal based on the delay time and the reference delay time, correct the delay time of the master clock signal to the reference delay time based on the selection signal, and output the master clock signal corrected to the reference delay time to the delay line; And A data recovery module configured to recover the multi-level clock signal corrected to the reference delay time by the delay line.

2. The clock recovery device according to claim 1, wherein, The delay controller is configured to compare the delay time with the reference delay time and output the selection signal including "1" or "0" based on a comparison result.

3. The clock recovery device according to claim 1, wherein, The delay controller is configured to determine a size of an inverter for outputting the master clock signal based on the selection signal.

4. The clock recovery device according to claim 3, wherein, When the input frequency is a low frequency, the delay controller is configured to increase the delay time by reducing a rising time of the clock signal via the inverter with the determined size.

5. The clock recovery device according to claim 4, wherein The delay controller includes a first inverter and a second inverter having a size smaller than that of the first inverter, and the inverter with the determined size is the first inverter.

6. The clock recovery device according to claim 3, wherein When the input frequency is a high frequency, the delay controller is configured to reduce the delay time by increasing a rising time of the clock signal via the inverter with the determined size.

7. The clock recovery device according to claim 6, wherein, The delay controller includes a first inverter and a second inverter having a size smaller than that of the first inverter, and the inverter with the determined size is the second inverter.

8. The clock recovery device according to claim 3, wherein, The delay line is composed of a plurality of inverters, and the delay line is configured to generate the multi-level clock signal by passing through the plurality of inverters.

9. A display driving device that recovers a clock signal and data from an input signal and drives a display panel using the recovered clock signal and data, the display driving device comprising: A clock recovery device, the clock recovery device comprising: A clock generator configured to generate a master clock signal from embedded transmission data; A delay line for generating a multi-level clock signal by delaying the master clock signal by a preset reference delay time unit based on an input frequency; A delay controller configured to receive two clock signals delayed by a reference delay time unit among the multi-level clock signals and detect a delay time, output a selection signal based on the delay time and the reference delay time, correct the delay time of the master clock signal to the reference delay time based on the selection signal, and output the master clock signal corrected to the reference delay time to the delay line; and A data recovery module, the data recovery module being configured to recover the multi-level clock signal that has been corrected to the reference delay time through the delay line.

10. The display driving device according to claim 9, wherein, The delay controller is configured to compare the delay time with the reference delay time, output the selection signal including "1" or "0" based on the comparison result, and determine the size of the inverter for outputting the main clock signal based on the selection signal.

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