Driving module and display device

Abstract

The invention belongs to the field of display, and particularly relates to a driving module and a display device.The driving module comprises a power module, a power management chip, a level translator and a delay module, the power management chip is connected with the power module, the level translator is connected with the power management chip, and the power module outputs power voltage to the power management chip; the power supply management chip converts power supply voltage into working voltage required by the level converter, and the delay module is arranged between the power supply module and the level converter. When the display device is shut down and when the power supply voltage jumps reversely in the dropping process, the delay module can prevent the power supply management chip from generating the working voltage, or the delay module can prevent the generated working voltage from being output to the level translator, shutdown discharge operation interruption is avoided, liquid crystal polarization caused by in-plane charge residues is further avoided, and the display effect is improved. And display abnormity is improved or eliminated.

Description

Technical Field

[0001] This application belongs to the field of displays, and particularly relates to a driving module and a display device. Background Art

[0002] The pixel driving circuit of a liquid crystal display (LCD) includes a liquid crystal capacitor and a storage capacitor. The liquid crystal capacitor and the storage capacitor provide an electric field for driving the deflection of liquid crystal molecules to display an image. When the LCD is turned off, if the charges stored in the liquid crystal capacitor and the storage capacitor are not effectively released, the liquid crystal molecules are easily polarized, resulting in abnormal display.

[0003] Existing liquid crystal displays have a shutdown discharge function, that is, all signals of the pixel driving circuit follow a voltage to be quickly discharged to the ground. Shutdown discharge can avoid in-plane charge residue causing liquid crystal polarization, thereby eliminating display abnormalities caused by charge residue.

[0004] However, the shutdown discharge function is enabled by a level shifter (LS) recognizing a decrease in the power supply voltage during shutdown. If the power supply voltage rebounds during shutdown, the shutdown discharge operation will be interrupted. Due to the protection mechanism of the level shifter, after the shutdown discharge operation is interrupted, it cannot be triggered again within a short time, resulting in in-plane charge residue causing liquid crystal polarization, and further resulting in abnormal display. Summary of the Invention

[0005] The purpose of this application is to provide a driving module and a display device to avoid in-plane charge residue causing liquid crystal polarization, thereby improving or eliminating display abnormalities.

[0006] To achieve the above purpose, this application provides a driving module, including a power supply module and a power management chip. The power management chip is connected to the power supply module. The driving module further includes: A level shifter, connected to the power management chip; A delay module, disposed between the power supply module and the level shifter. The power management chip is used to convert the power supply voltage provided by the power supply module into the operating voltage of the level shifter. When the power supply voltage reversely jumps during the falling process, the delay module can prevent the power management chip from generating the operating voltage, or the delay module can prevent the generated operating voltage from being output to the level shifter.

[0007] Optionally, the delay module is disposed between the power management chip and the level shifter. When the power supply voltage reversely jumps during the falling process, the delay module can prevent the generated operating voltage from being output to the level shifter.

[0008] Optionally, the delay module includes a first transistor, a second transistor, a capacitor, a first resistor, and a second resistor. A first end of the first transistor is connected to the power management chip through a first node. A second end of the first transistor is connected to the level converter. The first node, the first resistor, a second node, the capacitor, and the ground terminal are connected in sequence. A control end of the second transistor is connected to the second node. A first end of the second transistor is connected to a control end of the first transistor. A second end of the second transistor is connected to the ground terminal. The second resistor is connected between the first node and the control end of the first transistor. The first transistor is a P-type field effect transistor, and the second transistor is a PNP-type triode.

[0009] Optionally, the delay module further includes a first zener diode and a third resistor. A cathode of the first zener diode is connected to the second node. An anode of the first zener diode is connected to the control end of the second transistor. The third resistor is connected between the control end of the second transistor and the ground terminal.

[0010] Optionally, the delay module includes a first transistor, a comparator, a capacitor, a first resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor. A first end of the first transistor is connected to the power management chip through a first node. A second end of the first transistor is connected to the level converter. The first node, the first resistor, a second node, the capacitor, and the ground terminal are connected in sequence. The first node, the fourth resistor, a third node, the fifth resistor, and the ground terminal are connected in sequence. A non-inverting input terminal of the comparator is connected to the third node. An inverting input terminal of the comparator is connected to the second node through the seventh resistor. A positive power supply terminal of the comparator is connected to the first node, and the positive power supply terminal of the comparator is connected to the third node through the sixth resistor. A negative power supply terminal of the comparator is connected to the ground terminal.

[0011] Optionally, the delay module further includes a second zener diode. A cathode of the second zener diode is connected to the first node. An anode of the second zener diode is connected to the second node.

[0012] Optionally, the driving module further includes a pull-down discharge module. The pull-down discharge module is disposed between the power supply module and the power management chip to prevent reverse jump of the power supply voltage during the descending process, or the pull-down discharge module is disposed between the power management chip and the level converter to prevent reverse jump of the working voltage during the descending process; and / or The driving module further includes an identification and blocking module. The level converter includes a low-voltage locking unit. The identification and blocking module is connected to the power supply module, the power management chip, and the low-voltage locking unit, and is configured to disconnect the electrical connection between the power management chip and the low-voltage locking unit when the power supply voltage is lower than a preset value.

[0013] Optionally, the driving module includes a pull-down discharge module. The pull-down discharge module includes a third transistor, a fourth transistor, an eighth resistor, and a ninth resistor. The first end of the third transistor is connected to the power supply module through the eighth resistor and the fourth node. The power management chip is connected to the fourth node. The second end of the third transistor is connected to the ground terminal. The control end of the third transistor is connected to the fourth node. The control end of the fourth transistor is connected between the eighth resistor and the third transistor. The first end of the fourth transistor is connected to the fourth node. The second end of the fourth transistor is connected to the ground terminal through the ninth resistor. The third transistor is a P-type field effect transistor, and the fourth transistor is an NPN-type triode.

[0014] Optionally, the driving module includes an identification and blocking module. The identification and blocking module includes a fifth transistor, a sixth transistor, a twelfth resistor, and a thirteenth resistor. The first end of the fifth transistor is connected to the power management chip. The second end of the fifth transistor is connected to the low-voltage locking unit. The first end of the sixth transistor is connected to the control end of the fifth transistor. The second end of the sixth transistor is connected to the ground terminal. The control end of the sixth transistor is connected to the power supply module through the twelfth resistor. The thirteenth resistor is connected between the power supply module and the first end of the sixth transistor. The fifth transistor is an N-type field effect transistor, and the sixth transistor is an NPN-type triode.

[0015] The present application further provides a display device, including: The driving module; A display panel, connected to the driving module.

[0016] The driving module and the display device disclosed in the present application have the following beneficial effects: In this application, the driving module includes a power supply module, a power management chip, a level converter, and a delay module. The power management chip is connected to the power supply module, and the level converter is connected to the power management chip. The power supply module outputs a power supply voltage to the power management chip, and the power management chip converts the power supply voltage into the working voltage required by the level converter. The delay module is disposed between the power supply module and the level converter. When the display device is turned off and the power supply voltage reversely jumps during the descending process, the delay module can prevent the power management chip from generating the working voltage, or the delay module can prevent the generated working voltage from being output to the level converter, avoiding the interruption of the shutdown discharge operation, thereby avoiding the liquid crystal polarization caused by the in-plane charge residue, and improving or eliminating the display abnormality.

[0017] Other features and advantages of the present application will become apparent from the following detailed description, or will be partly learned through the practice of the present application.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Brief Description of the Drawings

[0019] The drawings herein are incorporated into the specification and constitute a part of the specification, showing the embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0020] Figure 1 It is a schematic structural diagram of the delay module in the first embodiment of the present application.

[0021] Figure 2 It is a schematic structural diagram of the driving module in the first embodiment of the present application.

[0022] Figure 3 It is a schematic diagram of the reverse jump of the power supply voltage and the working voltage during the descending process when the device is turned off.

[0023] Figure 4 It is a schematic diagram of the delay module shielding the working voltage when the device is turned off.

[0024] Figure 5 It is a schematic diagram showing that the delay module in the embodiment of the present application includes a zener diode.

[0025] Figure 6 It is a schematic diagram showing that the delay module in the embodiment of the present application includes a comparator.

[0026] Figure 7 It is a schematic structural diagram of the pull-down discharge module in the second embodiment of the present application.

[0027] Figure 8 It is a schematic structural diagram of the identification and blocking module in Embodiment 3 of the present application.

[0028] Figure 9 It is a schematic structural diagram of the identification and blocking module in Embodiment 4 of the present application.

[0029] Description of the reference numerals: 100, driving module; 110, power supply module; 120, power management chip; 130, level converter; 131, under-voltage lockout unit; 140, delay module; 141, first transistor; 142, second transistor; 143, capacitor; 144, first resistor; 145, second resistor; 146, first zener diode; 147, third resistor; 148, second zener diode; 149, fourth resistor; 150, fifth resistor; 151, sixth resistor; 152, seventh resistor; 153, comparator; 160, timing controller; 170, source driver module; 180, pull-down discharge module; 181, third transistor; 182, fourth transistor; 183, eighth resistor; 184, ninth resistor; 185, tenth resistor; 186, eleventh resistor; 190, identification and blocking module; 191, fifth transistor; 192, sixth transistor; 193, twelfth resistor; 194, thirteenth resistor; 200, display panel. Detailed implementation manners

[0030] Now, the exemplary embodiments will be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0031] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0032] The present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation of the present application.

[0033] Embodiment 1 Refer to Figure 1 and Figure 2 As shown, in this embodiment, the driving module 100 includes a power supply module 110, a power management chip 120 (Power Management Integrated Circuit, PMIC), and a level converter 130. The power management chip 120 is connected to the power supply module 110, and the level converter 130 is connected to the power management chip 120. The power supply module 110 outputs a power supply voltage Vcc to the power management chip 120, and the power management chip 120 converts the power supply voltage Vcc into an operating voltage Vdd required by the level converter 130.

[0034] The level converter 130 can perform high and low level conversion. For example, it can perform high and low level conversion on the scan signal output by the gate driving circuit to drive the pixel driving circuit to work. The level converter 130 can recognize the decrease in the power supply voltage Vcc during shutdown to turn on the shutdown discharge function, that is, to make each signal of the pixel driving circuit follow a voltage and quickly discharge to the ground. Shutdown discharge can avoid in-plane charge residue causing liquid crystal polarization, thereby eliminating display abnormalities caused by charge residue.

[0035] The level converter 130 includes an under voltage lockout unit 131 (Under Voltage Lockout, UVLO). When the under voltage lockout unit 131 is working, the shutdown discharge operation will be interrupted. When the display device is shut down, when the power supply voltage Vcc has a reverse jump during the downward process, as Figure 3 shown, the reverse jump of the power supply voltage Vcc will cause the power management chip 120 to work, the operating voltage Vdd will be generated instantaneously, the under voltage lockout unit 131 will work, and the shutdown discharge operation will be interrupted, resulting in in-plane charge residue causing liquid crystal polarization, and further resulting in display abnormalities.

[0036] In this embodiment, the driving module 100 includes a delay module 140. Adding the delay module 140 can avoid the reverse jump of the power supply voltage Vcc during the downward process, which causes the shutdown discharge operation to be interrupted. The delay module 140 is arranged between the power supply module 110 and the level converter 130. For example, the delay module 140 is arranged between the power supply module 110 and the power management chip 120, or the delay module 140 is arranged between the power management chip 120 and the level converter 130, or the delay module 140 is integrated in the power management chip 120.

[0037] When the display device is powered off and the power supply voltage Vcc has a reverse jump during the falling process, the delay module 140 can prevent the power management chip 120 from generating the working voltage Vdd, or the delay module 140 can prevent the generated working voltage Vdd from being output to the level shifter 130. As Figure 4 shown, it will not cause the interruption of the shutdown discharge operation.

[0038] In this embodiment, the driving module 100 includes a power supply module 110, a power management chip 120, a level shifter 130, and a delay module 140. The power management chip 120 is connected to the power supply module 110, the level shifter 130 is connected to the power management chip 120. The power supply module 110 outputs the power supply voltage Vcc to the power management chip 120, and the power management chip 120 converts the power supply voltage Vcc into the working voltage Vdd required by the level shifter 130. The delay module 140 is disposed between the power supply module 110 and the level shifter 130. When the display device is powered off and the power supply voltage Vcc has a reverse jump during the falling process, the delay module 140 can prevent the power management chip 120 from generating the working voltage Vdd, or the delay module 140 can prevent the generated working voltage Vdd from being output to the level shifter 130, avoiding the interruption of the shutdown discharge operation, thereby avoiding the liquid crystal polarization caused by the in-plane charge residue, and improving or eliminating the display abnormality.

[0039] In some embodiments, the delay module 140 is disposed between the power management chip 120 and the level shifter 130. When the power supply voltage Vcc has a reverse jump during the falling process, the delay module 140 can prevent the generated working voltage Vdd from being output to the level shifter 130.

[0040] The delay module 140 is disposed between the power management chip 120 and the level shifter 130. The delay module 140 is powered by the power management chip 120, and the circuit structure of the delay module 140 is simpler.

[0041] In some embodiments, the driving module 100 further includes a timing controller 160 (Timing Controller, TCON) and a source driver module 170 (Source Driver, SD). Both the timing controller 160 and the source driver module 170 are directly connected to the power management chip 120. That is to say, the working voltage Vdd output from the power management chip 120 to the level shifter 130 is delayed by the delay module 140, and the working voltage Vdd output from the power management chip 120 to the timing controller 160 and the source driver module 170 is not delayed by the delay module 140.

[0042] It should be noted that the timing controller 160 and the source driver module 170 can be directly connected to the power management chip 120, but not limited thereto. The timing controller 160 and the source driver module 170 can also be connected to the power management chip 120 through the delay module 140, which can be determined according to the specific situation.

[0043] In some embodiments, the delay module 140 includes a first transistor 141, a second transistor 142, a capacitor 143, a first resistor 144, and a second resistor 145. A first end of the first transistor 141 is connected to the power management chip 120 through a first node A, and a second end of the first transistor 141 is connected to the level shifter 130. The first node A, the first resistor 144, a second node B, the capacitor 143, and the ground terminal are connected in sequence. A control end of the second transistor 142 is connected to the second node B, a first end of the second transistor 142 is connected to a control end of the first transistor 141, and a second end of the second transistor 142 is connected to the ground terminal. The second resistor 145 connects the first node A and the control end of the first transistor 141. The first transistor 141 is a P-type field effect transistor, and the second transistor 142 is a PNP-type triode.

[0044] When the display device is turned off, the power supply voltage Vcc drops, the working voltage Vdd generated by the power management chip 120 drops, the second transistor 142 is turned off, the connection between the control end of the first transistor 141 and the ground terminal is disconnected, and the first transistor 141 is turned off; When the display device is turned on, the power supply voltage Vcc rises, the power management chip 120 generates the working voltage Vdd, the control end of the first transistor 141 receives a high-level signal and is turned off, the second transistor 142 is turned off, the working voltage Vdd continuously charges the capacitor 143, and the voltage of the second node B rises, that is, the voltage of the control end of the second transistor 142 rises. When the voltage of the second node B rises to the point where the second transistor 142 is turned on, the control end of the first transistor 141 is connected to the ground terminal, and the first transistor 141 is turned on.

[0045] The delay time for the first transistor 141 to turn on is determined by the capacitance value of the capacitor 143. The larger the capacitance value of the capacitor 143, the longer the charging time, and the longer the delay time for the first transistor 141 to turn on. Since it takes time for the capacitor 143 to charge, when the power supply voltage Vcc undergoes a reverse jump during the descending process, the working voltage Vdd generated by the reverse jump disappears before the first transistor 141 is turned on and will not be output to the level shifter 130, thus avoiding the interruption of the shutdown discharge operation.

[0046] It should be noted that the second transistor 142 is a PNP-type triode, but not limited thereto. The second transistor 142 can also be an N-type field effect transistor, which can be determined according to the specific situation.

[0047] In some embodiments, the delay module 140 further includes a first zener diode 146 and a third resistor 147. The cathode of the first zener diode 146 is connected to the second node B, and the anode of the first zener diode 146 is connected to the control terminal of the second transistor 142, as Figure 5 shown. The third resistor 147 is connected to the control terminal of the second transistor 142 and the ground terminal.

[0048] Setting the first zener diode 146 between the second node B and the control terminal of the second transistor 142 can increase the turn-on voltage of the second transistor 142, thereby increasing the delay time of the delay module 140. Setting the third resistor 147 between the control terminal of the second transistor 142 and the ground terminal can cause the reverse leakage current of the first zener diode 146 to flow to the ground terminal, reducing or eliminating the leakage of the second transistor 142 during the charging process of the capacitor 143.

[0049] In some embodiments, the delay module 140 further includes a second zener diode 148. The cathode of the second zener diode 148 is connected to the first node A, and the anode of the second zener diode 148 is connected to the second node B.

[0050] The second zener diode 148 can be used for voltage regulation to prevent the voltage at the first node A from being too high and damaging the transistor.

[0051] In some embodiments, the delay module 140 includes a first transistor 141, a capacitor 143, a first resistor 144, a fourth resistor 149, a fifth resistor 150, a sixth resistor 151, a seventh resistor 152, and a comparator 153, as Figure 6 shown. The first end of the first transistor 141 is connected to the power management chip 120 through the first node A, and the second end of the first transistor 141 is connected to the level converter 130. The first node A, the first resistor 144, the second node B, the capacitor 143, and the ground terminal are connected in sequence. The first node A, the fourth resistor 149, the third node C, the fifth resistor 150, and the ground terminal are connected in sequence. The non-inverting input terminal of the comparator 153 is connected to the third node C, the inverting input terminal of the comparator 153 is connected to the second node B through the seventh resistor 152, the positive power supply terminal of the comparator 153 is connected to the first node A, and the positive power supply terminal of the comparator 153 is connected to the third node C through the sixth resistor 151. The negative power supply terminal of the comparator 153 is connected to the ground terminal.

[0052] When the display device is turned off, the power supply voltage Vcc drops. The voltage V+ at the non-inverting input terminal of the comparator 153 is greater than the voltage V- at the inverting input terminal of the comparator 153. The comparator 153 outputs a high-level signal, and the first transistor 141 is turned off. When the power supply voltage Vcc jumps back during the dropping process, since it takes time for the capacitor 143 to charge, the first transistor 141 remains off until the voltage V+ at the non-inverting input terminal of the comparator 153 is less than the voltage V- at the inverting input terminal of the comparator 153. Then the comparator 153 outputs a low-level signal, and the first transistor 141 is turned on.

[0053] In the embodiment where the delay module 140 uses the comparator 153, the sixth resistor 151 is a positive feedback resistor, which can effectively eliminate output jitter. When the resistance values of the first transistor 141, the fourth resistor 149, and the sixth resistor 151 are equal, the delay time t of the delay module 140 is: ; where R5 is the resistance value of the fifth resistor 150, and C is the capacitance value of the capacitor 143. is a parameter related to the off state of the voltage. According to the above formula, it can be seen that the delay time t of the delay module 140 is determined by the resistance value of the fifth resistor 150 and the capacitance value of the capacitor 143.

[0054] It should be noted that in the embodiment where the delay module 140 uses the comparator 153, the second zener diode 148 can also be set. The cathode of the second zener diode 148 is connected to the first node A, and the anode of the second zener diode 148 is connected to the second node B.

[0055] Embodiment 2 Refer to Figure 7 As shown, the driving module 100 further includes a pull-down discharge module 180. The pull-down discharge module 180 is arranged between the power supply module 110 and the power management chip 120, and is used to prevent the power supply voltage Vcc from jumping back during the dropping process. In other embodiments, the pull-down discharge module 180 can also be arranged between the power management chip 120 and the level converter 130, and is used to prevent the working voltage Vdd from jumping back during the dropping process.

[0056] By forcibly pulling down the power supply voltage Vcc or the working voltage Vdd through the pull-down discharge module 180, it is possible to avoid the interruption of the shutdown discharge operation caused by the reverse jump of the power supply voltage Vcc or the working voltage Vdd.

[0057] Taking the case where the pull-down discharge module 180 is disposed between the power supply module 110 and the power management chip 120 as an example. The pull-down discharge module 180 includes a third transistor 181, a fourth transistor 182, an eighth resistor 183, and a ninth resistor 184. The first end of the third transistor 181 is connected to the power supply module 110 through the eighth resistor 183 and the fourth node D, the power management chip 120 is connected to the fourth node D, the second end of the third transistor 181 is connected to the ground terminal, and the control end of the third transistor 181 is connected to the fourth node D. The control end of the fourth transistor 182 is connected between the eighth resistor 183 and the third transistor 181, the first end of the fourth transistor 182 is connected to the fourth node D, and the second end of the fourth transistor 182 is connected to the ground terminal through the ninth resistor 184. The third transistor 181 is a P-type field effect transistor, and the fourth transistor 182 is an NPN-type triode.

[0058] It should be noted that the fourth transistor 182 may be an NPN-type triode, but is not limited thereto. The fourth transistor 182 may also be a P-type field effect transistor, which can be determined according to specific circumstances.

[0059] When the display device displays a picture, the third transistor 181 is turned off, and the fourth transistor 182 is turned off, and no pull-down conduction will occur. When the display device is turned off, the power supply voltage Vcc drops, the third transistor 181 is turned off and then on, and the fourth transistor 182 is also turned on, so as to conduct and pull down the power supply voltage Vcc.

[0060] In some embodiments, the pull-down discharge module 180 may further include a tenth resistor 185 and an eleventh resistor 186. The tenth resistor 185 is connected to the control end of the third transistor 181 and the fourth node D, and the eleventh resistor 186 is connected to the second end of the third transistor 181 and the ground terminal.

[0061] The tenth resistor 185 and the eleventh resistor 186 can play a role in voltage stabilization and current limiting.

[0062] Embodiment 3 See Figure 8 As shown, the driving module 100 further includes an identification blocking module 190. The level converter 130 includes a low voltage locking unit 131. The identification blocking module 190 is connected to the power supply module 110, the power management chip 120, and the low voltage locking unit 131, and is used to disconnect the electrical connection between the power management chip 120 and the low voltage locking unit 131 when the power supply voltage Vcc is lower than a preset value.

[0063] When the display device is turned off, the power supply voltage Vcc drops. When the power supply voltage Vcc is lower than the preset value, the power supply of the low voltage locking unit 131 is cut off, that is, the function of the low voltage locking unit 131 is blocked. Even if the power supply voltage Vcc and the operating voltage Vdd reverse jump, it will not cause the shutdown discharge operation to be interrupted.

[0064] In some embodiments, the identification and blocking module 190 includes a fifth transistor 191, a sixth transistor 192, a twelfth resistor 193, and a thirteenth resistor 194. The first end of the fifth transistor 191 is connected to the power management chip 120, and the second end of the fifth transistor 191 is connected to the low voltage lock unit 131. The first end of the sixth transistor 192 is connected to the control end of the fifth transistor 191, the second end of the sixth transistor 192 is connected to the ground terminal, the control end of the sixth transistor 192 is connected to the power module 110 through the twelfth resistor 193, and the thirteenth resistor 194 connects the power module 110 and the first end of the sixth transistor 192. The fifth transistor 191 is an N-type field effect transistor, and the sixth transistor 192 is an NPN-type triode.

[0065] It should be noted that the sixth transistor 192 can be an NPN-type triode, but is not limited thereto. The fourth transistor 182 can also be a P-type field effect transistor, which can be determined according to specific circumstances.

[0066] When the display device is turned off, the power supply voltage Vcc drops, the sixth transistor 192 is turned on, thereby pulling down the control end voltage of the fifth transistor 191, the fifth transistor 191 is turned off, and the power supply to the low voltage lock unit 131 is cut off.

[0067] Embodiment Four Refer to Figure 9 As shown, in this embodiment, the display device includes the driving module 100 and the display panel 200 disclosed in Embodiments One to Three, and the display panel 200 is connected to the driving module 100. It should be noted that the driving module 100 can include one, any combination of two, or all three of the delay module 140, the pull-down discharge module 180, and the identification and blocking module 190.

[0068] In this embodiment, the display device includes a driving module 100. The driving module 100 includes a power supply module 110, a power management chip 120, a level converter 130, and a delay module 140. The power management chip 120 is connected to the power supply module 110, and the level converter 130 is connected to the power management chip 120. The power supply module 110 outputs a power supply voltage Vcc to the power management chip 120. The power management chip 120 converts the power supply voltage Vcc into a working voltage Vdd required by the level converter 130. The delay module 140 is disposed between the power supply module 110 and the level converter 130. When the display device is turned off, when the power supply voltage Vcc reversely jumps during the descending process, the delay module 140 can prevent the power management chip 120 from generating the working voltage Vdd, or the delay module 140 can prevent the generated working voltage Vdd from being output to the level converter 130, avoiding the interruption of the shutdown discharge operation, thereby avoiding the liquid crystal polarization caused by the in-plane charge residue, and improving or eliminating the display abnormality.

[0069] The terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0070] In the present application, unless otherwise clearly specified and limited, the terms "assembly", "connection", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0071] In the description of this specification, the description with reference to terms such as "some embodiments", "exemplarily", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0072] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the specification of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A driving module, comprising a power module and a power management chip, the power management chip being connected to the power module, characterized in that, The driving module further includes: A level converter connected to the power management chip; A delay module disposed between the power module and the level converter. The power management chip is configured to convert the power supply voltage provided by the power module into the operating voltage of the level converter. When the power supply voltage undergoes a reverse jump during the falling process, the delay module can prevent the power management chip from generating the operating voltage, or the delay module can prevent the generated operating voltage from being output to the level converter.

2. The drive module according to claim 1, wherein The delay module is disposed between the power management chip and the level converter. When the power supply voltage undergoes a reverse jump during the falling process, the delay module can prevent the generated operating voltage from being output to the level converter.

3. The drive module according to claim 2, wherein The delay module includes a first transistor, a second transistor, a capacitor, a first resistor, and a second resistor. A first end of the first transistor is connected to the power management chip through a first node. A second end of the first transistor is connected to the level converter. The first node, the first resistor, a second node, the capacitor, and the ground terminal are connected in sequence. A control terminal of the second transistor is connected to the second node. A first end of the second transistor is connected to a control terminal of the first transistor. A second end of the second transistor is connected to the ground terminal. The second resistor connects the first node and the control terminal of the first transistor. The first transistor is a P-type field effect transistor, and the second transistor is a PNP-type triode.

4. The drive module according to claim 3, characterized in that, The delay module further includes a first zener diode and a third resistor. A cathode of the first zener diode is connected to the second node. An anode of the first zener diode is connected to the control terminal of the second transistor. The third resistor connects the control terminal of the second transistor and the ground terminal.

5. The drive module according to claim 2, wherein The delay module includes a first transistor, a comparator, a capacitor, a first resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor. A first end of the first transistor is connected to the power management chip through a first node. A second end of the first transistor is connected to the level converter. The first node, the first resistor, a second node, the capacitor, and the ground terminal are connected in sequence. The first node, the fourth resistor, a third node, the fifth resistor, and the ground terminal are connected in sequence. A non-inverting input terminal of the comparator is connected to the third node. An inverting input terminal of the comparator is connected to the second node through the seventh resistor. A positive power supply terminal of the comparator is connected to the first node, and the positive power supply terminal of the comparator is connected to the third node through the sixth resistor. A negative power supply terminal of the comparator is connected to the ground terminal.

6. The drive module according to any one of claims 3 to 5, characterized in that The delay module further includes a second zener diode. A cathode of the second zener diode is connected to the first node. An anode of the second zener diode is connected to the second node.

7. The driving module according to claim 1, wherein The driving module further includes a pull-down discharge module. The pull-down discharge module is disposed between the power supply module and the power management chip and is used to prevent the reverse jump of the power supply voltage during the descending process, or the pull-down discharge module is disposed between the power management chip and the level converter and is used to prevent the reverse jump of the working voltage during the descending process; and / or The driving module further includes an identification blocking module. The level converter includes a low-voltage locking unit. The identification blocking module is connected to the power supply module, the power management chip, and the low-voltage locking unit and is used to disconnect the electrical connection between the power management chip and the low-voltage locking unit when the power supply voltage is lower than a preset value.

8. The drive module according to claim 7, wherein The driving module includes a pull-down discharge module. The pull-down discharge module includes a third transistor, a fourth transistor, an eighth resistor, and a ninth resistor. A first end of the third transistor is connected to the power supply module through the eighth resistor and a fourth node. The power management chip is connected to the fourth node. A second end of the third transistor is connected to a ground terminal. A control end of the third transistor is connected to the fourth node. A control end of the fourth transistor is connected between the eighth resistor and the third transistor. A first end of the fourth transistor is connected to the fourth node. A second end of the fourth transistor is connected to the ground terminal through the ninth resistor. The third transistor is a P-type field effect transistor, and the fourth transistor is an NPN-type triode.

9. The drive module according to claim 8, wherein, The driving module includes an identification blocking module. The identification blocking module includes a fifth transistor, a sixth transistor, a twelfth resistor, and a thirteenth resistor. A first end of the fifth transistor is connected to the power management chip. A second end of the fifth transistor is connected to the low-voltage locking unit. A first end of the sixth transistor is connected to a control end of the fifth transistor. A second end of the sixth transistor is connected to the ground terminal. A control end of the sixth transistor is connected to the power supply module through the twelfth resistor. The thirteenth resistor connects the power supply module and a first end of the sixth transistor. The fifth transistor is an N-type field effect transistor, and the sixth transistor is an NPN-type triode.

10. A display device, characterized in that, Comprising: The driving module according to any one of claims 1 to 9; A display panel, connected to the driving module.

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