Memory device, operating method thereof, and memory system

Abstract

A peripheral circuit of a memory device includes: a page buffer including a plurality of partitions each configured to receive a clock signal and output a return clock signal based on the clock signal; a first branch node connected with two of the plurality of partitions and configured to combine the return clock signals output by the two partitions to generate a first combined clock signal; two ends of the first clock path are respectively connected with the first branch node and the input / output node, and the first clock path is configured to transmit the first combined clock signal to the input / output node; a second branch node connected with the other two partitions in the plurality of partitions and configured to combine the return clock signals output by the other two partitions to generate a second combined clock signal; the two ends of the second clock path are connected with the second branch node and the input and output node respectively, and the second clock path is configured to transmit the second combined clock signal to the input and output node.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a memory device, an operation method thereof, and a memory system. Background Art

[0002] A memory device is a memory device used to store information in modern information technology. As a typical non-volatile semiconductor memory, a NAND (Not-And) flash memory has become a mainstream product in the storage market due to its high storage density, controllable production cost, appropriate programming / erasing speed, and retention characteristics.

[0003] With the continuous improvement of the processing speed of electronic devices, how to improve the data transfer rate in a memory device has become one of the technical problems that need to be solved urgently in this field at present. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory device, an operation method thereof, and a memory system to solve at least one problem existing in the prior art.

[0005] To achieve the above object, the technical solutions of the embodiments of the present disclosure are implemented as follows:

[0006] In a first aspect, embodiments of the present disclosure provide a memory device, which includes a memory array and a peripheral circuit coupled to the memory array; the peripheral circuit includes:

[0007] A page buffer, the page buffer includes a plurality of partitions, and each partition is configured to receive a clock signal and output a return clock signal based on the clock signal;

[0008] A first branch node, connected to two of the plurality of partitions, and configured to combine the return clock signals output by the two partitions to generate a first combined clock signal;

[0009] A first clock path, with both ends of the first clock path connected to the first branch node and an input / output node respectively, and configured to transmit the first combined clock signal to the input / output node;

[0010] A second branch node, connected to another two of the plurality of partitions, and configured to combine the return clock signals output by the another two partitions to generate a second combined clock signal;

[0011] A second clock path, with both ends of the second clock path connected to the second branch node and the input / output node respectively, and configured to transmit the second combined clock signal to the input / output node.

[0012] In an alternative embodiment, the peripheral circuit further includes:

[0013] A third branch node through which both the first clock path and the second clock path pass; a portion of the first clock path between the third branch node and the input / output node is arranged in parallel with a portion of the second clock path between the third branch node and the input / output node; the portion of the first clock path between the third branch node and the input / output node is configured to transmit the first combined clock signal to the input / output node; the portion of the second clock path between the third branch node and the input / output node is configured to transmit the second combined clock signal to the input / output node.

[0014] In an alternative embodiment, the first branch node is further configured to combine the data signals output from the two partitions to generate a first combined data signal; the second branch node is further configured to combine the data signals output from the other two partitions to generate a second combined data signal; the peripheral circuit further includes:

[0015] A first data path arranged in parallel with the first clock path and configured to transmit the first combined data signal to the input / output node;

[0016] A second data path arranged in parallel with the second clock path and configured to transmit the second combined data signal to the input / output node.

[0017] In an alternative embodiment, the input / output node includes:

[0018] A first matching circuit configured to match the first combined clock signal and the first combined data signal;

[0019] A second matching circuit configured to match the second combined clock signal and the second combined data signal.

[0020] In an alternative embodiment, the peripheral circuit further includes a data register and,

[0021] A third clock path with two ends respectively connected to the input / output node and the data register, and configured to transmit the first combined clock signal to the data register;

[0022] A fourth clock path with two ends respectively connected to the input / output node and the data register, and configured to transmit the second combined clock signal to the data register;

[0023] A third data path, with two ends of the third data path respectively connected to the input / output node and the data register, and configured to transmit the first merged data signal to the data register;

[0024] A fourth data path, with two ends of the fourth data path respectively connected to the input / output node and the data register, and configured to transmit the second merged data signal to the data register.

[0025] In an alternative embodiment, the data register includes a plurality of first storage areas and a plurality of second storage areas; the first storage areas and the second storage areas are arranged alternately;

[0026] The plurality of first storage areas are configured to receive a first control signal and the first merged clock signal, and receive the first merged data signal based on the first control signal and the first merged clock signal;

[0027] The plurality of second storage areas are configured to receive a second control signal and the second merged clock signal, and receive the second merged data signal based on the second control signal and the second merged clock signal.

[0028] In an alternative embodiment, the input / output node is configured to receive a first clock signal; the peripheral circuit further includes:

[0029] A fifth clock path, with two ends of the fifth clock path respectively connected to the input / output node and the third branch node, and configured to transmit the first clock signal to the third branch node; the third branch node is configured to generate a first sub-clock signal and a second sub-clock signal in parallel based on the first clock signal;

[0030] A sixth clock path, with two ends of the sixth clock path respectively connected to the third branch node and the first branch node, and configured to transmit the first sub-clock signal to the first branch node;

[0031] A seventh clock path, with two ends of the seventh clock path respectively connected to the third branch node and the second branch node, and configured to transmit the second sub-clock signal to the second branch node; the length of the sixth clock path is different from the length of the seventh clock path.

[0032] In an alternative embodiment, the input / output node is configured to receive a first data signal; the peripheral circuit further includes:

[0033] A fifth data path, which is arranged in parallel with the fifth clock path and is configured to transmit the first data signal to the third branch node; the third branch node is further configured to equally divide the first data signal into a first sub-data signal and a second sub-data signal;

[0034] A sixth data path, which is arranged in parallel with the sixth clock path and is configured to transmit the first sub-data signal to the first branch node;

[0035] A seventh data path, with two ends respectively connected to the third branch node and the second branch node, and is configured to transmit the second sub-data signal to the second branch node.

[0036] In an alternative embodiment, the bit width of the fifth data path is greater than or equal to twice the bit width of the sixth data path or twice the bit width of the seventh data path.

[0037] In an alternative embodiment, the memory device includes a pad region and a storage plane region arranged along a first direction; wherein,

[0038] The pad region includes: the input / output node and the third branch node;

[0039] The storage plane region includes: the page buffer, the first branch node, the second branch node; the two partitions are symmetrically distributed on two opposite sides of the first branch node along a second direction; the other two partitions are symmetrically distributed on two opposite sides of the second branch node along the second direction; the second direction is perpendicular to the first direction.

[0040] In an alternative embodiment, the partition includes a frequency divider, which is configured to receive the clock signal and generate the return clock signal based on the clock signal.

[0041] In an alternative embodiment, both the first branch node and the second branch node include an OR gate; the OR gate of the first branch node is configured to combine the return clock signals output by the two partitions to generate the first combined clock signal, and the OR gate of the second branch node is configured to combine the return clock signals output by the other two partitions to generate the second combined clock signal.

[0042] In an alternative embodiment, the memory device includes a three-dimensional NAND memory.

[0043] In a second aspect, an embodiment of the present disclosure provides a memory system, including:

[0044] At least one memory device according to any one of the above embodiments;

[0045] A memory controller, coupled to the at least one memory device and configured to control the memory device.

[0046] In a third aspect, an embodiment of the present disclosure provides an operation method for a memory device, the operation method including:

[0047] Partitions of a page buffer receive a clock signal and output a return clock signal based on the clock signal;

[0048] Combine return clock signals output from two of the multiple partitions to generate a first combined clock signal;

[0049] Transmit the first combined clock signal to an input / output node;

[0050] Combine return clock signals output from another two of the multiple partitions to generate a second combined clock signal;

[0051] Transmit the second combined clock signal to the input / output node.

[0052] In an alternative embodiment, the transmitting the first combined clock signal to an input / output node and the transmitting the second combined clock signal to the input / output node include:

[0053] The first combined clock signal and the second combined clock signal are transmitted to the input / output node in parallel.

[0054] In an alternative embodiment, the operation method further includes:

[0055] Combine data signals output from the two partitions to generate a first combined data signal;

[0056] Combine data signals output from the another two partitions to generate a second combined data signal;

[0057] Transmit the first combined data signal to the input / output node;

[0058] Transmit the second combined data signal to the input / output node.

[0059] In an alternative embodiment, the operation method further includes:

[0060] Match the first combined clock signal with the first combined data signal;

[0061] Match the second combined clock signal with the second combined data signal.

[0062] In an alternative embodiment, the operation method further includes:

[0063] Transmitting the first combined clock signal and the first combined data signal from the input / output node to the data register;

[0064] Transmitting the second combined clock signal and the second combined data signal from the input / output node to the data register.

[0065] In an alternative embodiment, the operation method further includes:

[0066] A plurality of first temporary storage areas of the data register receive a first control signal and the first combined clock signal, and receive the first combined data signal based on the first control signal and the first combined clock signal;

[0067] A plurality of second temporary storage areas of the data register receive a second control signal and the second combined clock signal, and receive the second combined data signal based on the second control signal and the second combined clock signal; the first temporary storage areas and the second temporary storage areas are arranged alternately.

[0068] In an alternative embodiment, before the partition of the page buffer receives a clock signal and outputs a return clock signal based on the clock signal, the method further includes:

[0069] Receiving the first clock signal;

[0070] Transmitting the first clock signal from the input / output node to a third branch node; generating a first sub-clock signal and a second sub-clock signal in parallel based on the first clock signal;

[0071] Transmitting the first sub-clock signal to a first branch node;

[0072] Transmitting the second sub-clock signal to a second branch node.

[0073] In an alternative embodiment, the method further includes:

[0074] Receiving the first data signal;

[0075] Transmitting the first data signal from the input / output node to the third branch node;

[0076] Dividing the first data signal equally into a first sub-data signal and a second sub-data signal; transmitting the first sub-data signal to the first branch node;

[0077] Transmit the second sub-data signal to the second branch node.

[0078] In the technical solution provided by the present disclosure, during the process of obtaining data from the page buffer, the first merge clock signal and the second merge clock signal do not need to be merged, and the first merge data signal and the second merge data signal do not need to be merged either. Therefore, the matching cost caused by the difference in the path lengths between the first branch node and the third branch node and between the second branch node and the third branch node can be saved, thereby improving the data transmission efficiency. In addition, between the third branch node and the input / output node, the bit width of the data signal is twice the bit width of the data path located in the memory plane area, and between the input / output node and the data register, the bit width of the data signal is also twice the bit width of the data path located in the memory plane area. That is, without changing the data path in the memory plane area, the parallelism of data transmission can be increased to transmit more data to the data register per unit time, thereby improving the data transmission rate within the memory device to enable the memory device to meet the requirements of electronic devices with higher processing speeds. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 Schematic diagram of an exemplary system with a memory system provided by an embodiment of the present disclosure;

[0080] Figure 2 Schematic diagram of an exemplary memory card with a memory system provided by an embodiment of the present disclosure;

[0081] Figure 3 Schematic diagram of an exemplary solid-state drive with a memory system provided by an embodiment of the present disclosure;

[0082] Figure 4 Schematic diagram of an exemplary memory device including a peripheral circuit provided by an embodiment of the present disclosure;

[0083] Figure 5 Schematic diagram of an exemplary memory device including a memory array and a peripheral circuit provided by an embodiment of the present disclosure;

[0084] Figure 6 Schematic of the memory device provided by an embodiment of the present disclosure Figure 1 ;

[0085] Figure 7 Schematic of the memory device provided by an embodiment of the present disclosure Figure 2 ;

[0086] Figure 8 Schematic of the memory device provided by an embodiment of the present disclosure Figure 3 ;

[0087] Figure 9 Schematic diagram of the memory device provided by the embodiment of the present disclosure Figure 4 ;

[0088] Figure 10 Timing diagram for reading data from the page buffer provided by the embodiment of the present disclosure;

[0089] Figure 11 Circuit diagram of the clock path provided by the embodiment of the present disclosure;

[0090] Figure 12 Schematic diagram of the data register provided by the embodiment of the present disclosure;

[0091] Figure 13 Schematic diagram of the memory device provided by the embodiment of the present disclosure Figure 5 ;

[0092] Figure 14 Flow schematic diagram of the operation method of the memory device provided by the embodiment of the present disclosure. Detailed implementation manners

[0093] Hereinafter, the exemplary embodiments disclosed by the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these implementation manners are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0094] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features well known to those skilled in the art are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0095] In the drawings, the same reference numerals denote the same elements throughout.

[0096] It should be understood that spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, the spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptive terms used herein are to be interpreted accordingly.

[0097] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0098] The memory system in the embodiments of the present disclosure includes, but is not limited to, a memory system including a three-dimensional NAND-type memory. For ease of understanding, a memory system including a three-dimensional NAND-type memory is taken as an example to illustrate the memory system provided by the present disclosure.

[0099] Figure 1 Schematic diagram of an exemplary system having a memory system provided for the embodiments of the present disclosure. In the embodiments of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 1As shown in FIG. 0, the system 100 may include a host device 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a Central Processing Unit (CPU), or a System on a Chip (SoC), such as an Application Processor (AP). The host device 101 may be configured to send data to or receive data from the memory system 102.

[0100] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101 and is configured to control the memory device 103. The memory controller 104 may manage the data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low-duty-cycle environment, such as in a Secure Digital card, a Compact Flash Card (CFC), a Universal Serial BUS (USB) flash drive, or in other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In other embodiments, the memory controller 104 is designed to operate in a high-duty-cycle environment, such as in a Solid State Drive or an Embedded Multi-Media Card (eMMC).

[0101] In some embodiments, the memory controller 104 and one or more memory devices 103 may be integrated into various types of storage devices, that is, the memory system 102 may be implemented and encapsulated into different types of terminal electronic products.

[0102] In an example as shown in Figure 2 FIG. 11, the memory controller 104 and a single memory device 103 may be integrated into a memory card 201. The memory card 201 may be a Compact Flash card, a Smart Media Card (SMC), a Memory Stick (MS), a Multi-Media Card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a Secure Digital card, such as a Mini SD card, a Micro SD card, an SDHC card, etc., or a Universal Flash Card. The memory card 201 may further include a connection for connecting the memory card 201 to a host device (e.g., Figure 1The memory card connector 202 coupled to the host device 101 in Figure 3 In another example as shown in Figure 1 the host device 101 in

[0103] Figure 4 FIG. is a circuit schematic diagram of an exemplary memory device 300 including a peripheral circuit provided by an embodiment of the present disclosure. The memory device 300 may be an example of the memory device 103 in Figure 1 The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. Taking the memory array 301 as a three-dimensional NAND type memory array as an example, wherein the storage unit 305 is a NAND storage unit, and the storage units 305 are provided in the form of an array of memory strings 304, and each memory string 304 extends vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of storage units 305 coupled in series and vertically stacked. Each storage unit 305 may hold a continuous analog value, e.g., voltage or charge, depending on the number of electrons trapped within the region of the storage unit 305. Each storage unit 305 may be a floating gate type storage unit including a floating gate transistor, or a charge trapping type storage unit including a charge trapping transistor.

[0104] In some embodiments, each storage unit 305 is a single level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each storage unit 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, e.g., a multi-level cell (MLC) storing two bits per cell, a triple level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0105] As in Figure 4As shown, each memory string 304 may include a bottom select transistor (BST) 307 at its source extreme and a top select transistor (TST) 306 at its drain extreme. The bottom select transistor 307 and the top select transistor 306 may be configured to activate a selected memory string 304 during read and program operations. In some embodiments, the sources of the memory strings 304 in the same memory block 303 may be coupled by a common source line (CSL) 310. In other words, all of the memory strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, and data may be read from or written to the bit line 311 via an output bus (not shown). In some embodiments, each memory string 304 is configured to apply a select voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the corresponding top select transistor 306 and / or, via one or more bottom select lines (BSL) 309, apply a select voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the corresponding bottom select transistor 307 to be selected or deselected.

[0106] As Figure 4 shown, the memory strings 304 may be organized into a plurality of memory blocks 303, each of the plurality of memory blocks 303 may have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, i.e., all of the memory cells 305 on the same memory block 303 are erased simultaneously. To erase the memory cells 305 in a selected memory block, the common source line 310 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block may be biased with an erase voltage. It should be understood that, in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 305 of adjacent memory strings 304 may be coupled by word lines 312, and the word lines 312 select which row of the memory cells 305 is affected by a read or program operation.

[0107] Return reference Figure 4, the peripheral circuit 302 can be coupled to the memory array 301 through bit lines 311, word lines 312, common source lines 310, lower select lines 309, and upper select lines 308. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuits for applying voltage signals and / or current signals to each target memory cell 305 and sensing voltage signals and / or current signals from each target memory cell 305 through the bit lines 311, word lines 312, common source lines 310, lower select lines 309, and upper select lines 308 to implement operations on the memory array 301. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor technology.

[0108] Figure 5 Some exemplary peripheral circuits are shown. The peripheral circuit 302 includes a page buffer / sense amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuits not shown in Figure 5 may also be included.

[0109] The page buffer / sense amplifier 401 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 405. In one example, the page buffer / sense amplifier 401 can store a page of programming data (write data) to be programmed to the memory array 301. In another example, the page buffer / sense amplifier 401 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cells coupled to the selected word line. In yet another example, the page buffer / sense amplifier 401 can also sense low-power signals from the bit lines representing data bits stored in the memory cells and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 402 can be configured to be controlled by the control logic 405 and select one or more memory strings by applying bit line voltages generated from the voltage generator 404.

[0110] The row decoder / word line driver 403 may be configured to be controlled by the control logic 405, and to select / deselect the memory blocks of the memory array 301 and to select / deselect the word lines of the memory blocks. The row decoder / word line driver 408 may also be configured to drive the word lines using the word line voltages generated from the voltage generator 404. In some embodiments, the row decoder / word line driver 403 may also select / deselect and drive the lower select line and the upper select line. As described in detail below, the row decoder / word line driver 403 is configured to perform a programming operation on the memory cells coupled to the selected word line(s). The voltage generator 404 may be configured to be controlled by the control logic 405, and to generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0111] The control logic 405 may be coupled to each of the peripheral circuits described above, and is configured to control the operation of each peripheral circuit. The register 406 may be coupled to the control logic 405, and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The flash memory interface 407 may be coupled to the control logic 405, and acts as a control buffer to buffer the control commands received from the host-side device (not shown) and relay them to the control logic 405, and to buffer the status information received from the control logic 405 and relay it to the memory controller. The flash memory interface 407 may also be coupled to the column decoder / bit line driver 402 via the data bus 408, and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory array 301.

[0112] As the operating speed of electronic devices continues to increase, it is necessary to adaptively increase the data transfer speed of the memory device, that is, more data needs to be transferred to the outside of the memory device per unit time. In this regard, the present disclosure proposes the following embodiments.

[0113] The present disclosure provides a memory device, Figure 6 is a partial schematic diagram of the memory device. The memory device includes a memory plane area A and a pad area B. Among them, the memory plane area A includes a plurality of memory planes P. Here, it is taken as an example that the memory plane area A includes two memory planes P. The memory planes P can be independent of each other when performing read operations, program operations, or erase operations. For example, each memory plane P can be configured to independently perform a read operation in response to a read control signal received from the control logic 405.

[0114] In some embodiments, to enable each memory plane P to operate independently, each memory plane P covers a local buffer for buffering read data and write data, and operations can be processed in parallel. Specifically, each memory plane P may include a memory array and a set of peripheral circuits. The peripheral circuits may include a page buffer / sense amplifier, a column decoder / bit line driver, a row decoder / word line driver, etc. Among them, the page buffer 501 is used to temporarily store (buffer) one or more pages of data to be read from or written to the memory array.

[0115] It should be noted that in the embodiments of the present disclosure, the schematic diagram of the memory device is a projection diagram of the memory device on the XY plane along the Z direction. The memory device may include a first semiconductor structure and a second semiconductor structure stacked in the Z direction, and a bonding interface may be included between the first semiconductor structure and the second semiconductor structure. The memory array is located in the first semiconductor structure. Figure 6 The structures shown are all located in the second semiconductor structure. That is, the memory array in the memory plane P is located in the first semiconductor structure, and a set of peripheral circuits in the memory plane P is located in the second semiconductor structure. The memory array is covered by the peripheral circuits and is not shown in the figure. Its specific structure can refer to the description of the above embodiments for Figure 4 the description.

[0116] In some embodiments, the page buffer 501 in one memory plane P may be divided into multiple partitions. Here, it is taken as an example that the page buffer 501 includes four partitions 5010, 5011, 5012, and 5013. In some embodiments, each partition may have the same size, that is, each partition may be one-fourth of the page buffer 501.

[0117] In some embodiments, the peripheral circuits further include a first branch node 502 and a second branch node 503. Two partitions 5010 and 5011 of the page buffer 501 are symmetrically distributed on opposite sides of the first branch node 502 along the second direction; the other two partitions 5012 and 5013 of the page buffer 501 are symmetrically distributed on opposite sides of the second branch node 503 along the second direction. Here, the first direction is perpendicular to the second direction. The first direction may be the Y direction, and the second direction may be the X direction.

[0118] In some specific examples, referring to Figure 6Each partition of the page buffer 501 may include three parts. Taking partition 5013 as an example, it may include a first data storage part 5013a, a second data storage part 5013b and a path setting part 5013c, wherein the first data storage part 5013a and the second data storage part 5013b may include multiple latches and are configured to buffer data. The path setting part 5013c is a setting area for the data path and the clock path inside the partition 5013. The first data storage part 5013a and the second data storage part 5013b can be connected to the second branch node 503 through the path setting part 5013c. The data signal can be transmitted between the first data storage part 5013a or the second data storage part 5013b and the second branch node 503 via the data path in the path setting part 5013c, and the clock signal can be transmitted between the first data storage part 5013a or the second data storage part 5013b and the second branch node 503 via the clock path in the path setting part 5013c.

[0119] In the embodiment of the present disclosure, the storage surface area A and the pad area B both include a path setting area, which is used to set signal transmission paths such as data paths and clock paths. The path in the storage surface area A extends along the Y direction, and the path setting area in the pad area B extends along the X direction. The path setting area includes multiple branch nodes (Branch) and relay drivers (REP), and is connected to the input and output nodes (IO_CTRL).

[0120] The pad region B also includes a data register 800 . The data buffered in the page buffer 501 can be transmitted to the input / output node 601 via the data path in the path setting region. Further, the data can be transmitted from the input / output node 601 to the data register 800 .

[0121] Figure 7 , Figure 8 and Figure 9 A schematic diagram of a memory device provided in some embodiments, including a specific setting method of a data path and a clock path and a transmission method of a data signal and a clock signal when performing a read operation; Figure 10 A timing diagram for reading data from a page buffer is provided for some specific examples; Figure 11 Circuit diagrams of clock paths are provided for some specific examples; Figure 12 Schematic diagram of data register for some specific examples. It should be noted that for the sake of simplicity, Figure 7 , Figure 8 and Figure 9 Some components including the relay driver are omitted.

[0122] In some embodiments, during a read operation, data in the memory array can be buffered in at least one partition of the page buffer 501. To transfer the data from the page buffer 501 to the data register 800, the partition of the page buffer 501 can be configured to receive a clock signal and output a return clock signal based on the clock signal, and synchronously output a data signal.

[0123] In some embodiments, as Figure 7 shown, the peripheral circuit includes: a fifth clock path 701, a sixth clock path 702, and a seventh clock path 703. Two ends of the fifth clock path 701 are respectively connected to the input / output node 601 and the third branch node 602. Two ends of the sixth clock path 702 are respectively connected to the third branch node 602 and the first branch node 502. Two ends of the seventh clock path 703 are respectively connected to the third branch node 602 and the second branch node 503.

[0124] In some embodiments, the input / output node 601 can receive a first clock signal Clk_dp. The fifth clock path 701 can be configured to transmit the first clock signal Clk_dp to the third branch node 602. The third branch node 602 can be configured to parallelly generate a first sub-clock signal Clk_dp_q01 and a second sub-clock signal Clk_dp_q23 based on the first clock signal Clk_dp. The sixth clock path 702 can be configured to transmit the first sub-clock signal Clk_dp_q01 to the first branch node 502. The seventh clock path 703 can be configured to transmit the second sub-clock signal Clk_dp_q23 to the second branch node 503.

[0125] In the embodiments of the present disclosure, the lengths of the sixth clock path 702 and the seventh clock path 703 are different. Specifically, as Figure 7 shown, the length of the sixth clock path 702 is less than the length of the seventh clock path 703. Therefore, the time for the first sub-clock signal Clk_dp_q01 to be transmitted to the first branch node 502 will be slightly later than the time for the second sub-clock signal Clk_dp_q23 to be transmitted to the second branch node 503.

[0126] In some embodiments, the first branch node 502 may be configured to divide the first sub-clock signal Clk_dp_q01 into two clock signals Clk_dp_q0 and Clk_dp_q1, and transmit the clock signal Clk_dp_q0 to partition 5010 and transmit the clock signal Clk_dp_q1 to partition 5011; the second branch node 503 may be configured to divide the second sub-clock signal Clk_dp_q23 into two clock signals Clk_dp_q2 and Clk_dp_q3, and transmit the clock signal Clk_dp_q2 to partition 5012 and transmit the clock signal Clk_dp_q3 to partition 5013.

[0127] In the embodiments of the present disclosure, with reference to Figure 7 and Figure 10 , the third branch node 602 may be configured to concurrently generate the first sub-clock signal Clk_dp_q01 and the second sub-clock signal Clk_dp_q23 based on the first clock signal Clk_dp. In the same time range, the first branch node 502 may receive the first sub-clock signal Clk_dp_q01 and generate the clock signals Clk_dp_q0 and Clk_dp_q1, and the second branch node 503 may receive the second sub-clock signal Clk_dp_q23 and generate the clock signals Clk_dp_q2 and Clk_dp_q3. Thus, partition 5010 and partition 5012 may respectively receive the clock signals Clk_dp_q0 and Clk_dp_q2 in the same time range, that is, partition 5010 and partition 5012 may be selected simultaneously. In the next time range, partition 5011 and partition 5013 may respectively receive the clock signals Clk_dp_q1 and Clk_dp_q3, that is, partition 5011 and partition 5013 may be selected simultaneously.

[0128] In some embodiments, partition 5010 may be configured to receive the clock signal Clk_dp_q0 and generate a return clock signal Clk_rtn_q0 based on the clock signal Clk_dp_q0; partition 5011 may be configured to receive the clock signal Clk_dp_q1 and generate a return clock signal Clk_rtn_q1 based on the clock signal Clk_dp_q1; partition 5012 may be configured to receive the clock signal Clk_dp_q2 and generate a return clock signal Clk_rtn_q2 based on the clock signal Clk_dp_q2; partition 5013 may be configured to receive the clock signal Clk_dp_q3 and generate a return clock signal Clk_rtn_q3 based on the clock signal Clk_dp_q3. As Figure 10As shown, the return clock signal Clk_rtn_q0 and the return clock signal Clk_rtn_q2 can be generated within the same time range, and the return clock signal Clk_rtn_q1 and the return clock signal Clk_rtn_q3 can be generated within the same time range.

[0129] In some embodiments, the first branch node 502 may be configured to combine the return clock signal Clk_rtn_q0 output from partition 5010 and the return clock signal Clk_rtn_q1 output from partition 5011 to generate a first combined clock signal Clk_rtn_q01; the second branch node 503 may be configured to combine the return clock signal Clk_rtn_q2 output from partition 5012 and the return clock signal Clk_rtn_q3 output from partition 5013 to generate a second combined clock signal Clk_rtn_q23.

[0130] In some embodiments, as Figure 8 shown, the peripheral circuit includes: a first clock path 901 and a second clock path 902. Two ends of the first clock path 901 are respectively connected to the first branch node 502 and the input / output node 601, and two ends of the second clock path 902 are respectively connected to the second branch node 503 and the input / output node 601.

[0131] In some embodiments, the first clock path 901 may be configured to transmit the first combined clock signal Clk_rtn_q01 to the input / output node 601, and the second clock path 902 may be configured to transmit the second combined clock signal Clk_rtn_q23 to the input / output node 601.

[0132] In the embodiments of the present disclosure, both the first clock path 901 and the second clock path 902 pass through the third branch node 602. The portion of the first clock path 901 between the third branch node 602 and the input / output node 601 is arranged in parallel with the portion of the second clock path 902 between the third branch node 602 and the input / output node 601. That is, while the portion of the first clock path 901 between the third branch node 602 and the input / output node 601 transmits the first combined clock signal Clk_rtn_q01 to the input / output node 601, the portion of the second clock path 902 between the third branch node 602 and the input / output node 601 can transmit the second combined clock signal Clk_rtn_q23 to the input / output node 601.

[0133] It should be noted that in the embodiments of the present disclosure, the parallel setting of paths means that two independent paths are set in the same path setting area, extend in the same direction, and their ends are connected to the same node; the parallel transmission of signals means that two independent paths transmit two independent signals respectively within the same time range.

[0134] In some embodiments, with reference to Figure 8 and Figure 9 , while the partitioned output returns the clock signal, a data signal is also output. The first branch node 502 is further configured to combine the data signals output from the partitions 5010 and 5011 to generate a first combined data signal Grd<63:0>. The second branch node 503 is further configured to combine the data signals output from the partitions 5012 and 5013 to generate a second combined clock signal Grd<127:64>. The peripheral circuit further includes: a first data path 1001 and a second data path 1002. The first data path 1001 is set in parallel with the first clock path 901 and is configured to transmit the first combined data signal Grd<63:0> to the input / output node 601 while the first clock path 901 transmits the first combined clock signal Clk_rtn_q01 to the input / output node 601. The second data path 1002 is set in parallel with the second clock path 902 and is configured to transmit the second combined data signal Grd<127:64> to the input / output node 601 while the second clock path 902 transmits the second combined clock signal Clk_rtn_q23 to the input / output node 601.

[0135] It should be noted that in the embodiments of the present disclosure, the read operation takes obtaining read data from the four partitions of the page buffer 501 simultaneously as an example, but the present disclosure is not limited thereto. In other embodiments, read data can be obtained from one, two, or three partitions of the page buffer 501 only.

[0136] In the embodiments of the present disclosure, the first combined clock signal Clk_rtn_q01 and the second combined clock signal Clk_rtn_q23 can be transmitted to the input / output node 601 within the same time range, and the first combined data signal Grd<63:0> and the second combined data signal Grd<127:64> can also be transmitted to the input / output node 601 within the same time range. Taking the bit widths of the first data path 1001 and the second data path 1002 as 64 bit as an example, the bit width of the data signal transmitted to the input / output node 601 can be 128 bit, thereby improving the parallelism of data transmission, that is, more data can be transmitted from the page buffer 501 to the input / output node 601 per unit time.

[0137] In some specific examples,Figure 11 The circuit diagram of the clock path and branch nodes in the memory device shown. With reference to Figure 8 combinedly, in Figure 8 , Figure 10 and Figure 11 , each partition of the page buffer 501 includes a frequency divider, and the frequency divider can be configured to receive a clock signal and generate a return clock signal based on the clock signal. Taking the frequency divider 1201 in the partition 5010 as an example, the frequency divider 1201 can receive the clock signal Clk_dp_q0 and generate a return clock signal Clk_rtn_q0 based on the clock signal Clk_dp_q0. Specifically, the frequency divider 1201 includes a flip-flop, and the flip-flop can be a D flip-flop (DFF). The clock input of the DFF can receive the clock signal Clk_dp_q0, the Q output of the DFF can be coupled to the D input via an inverter, and the output of the DFF can output the return clock signal Clk_rtn_q0. With reference to Figure 10 combinedly and Figure 11 , the frequency divider 1201 in the partition 5010 can double the period of the clock signal Clk_dp_q0 to output the return clock signal Clk_rtn_q0. Similarly, the frequency divider 1301 in the partition 5012 can double the period of the clock signal Clk_dp_q2 to output the return clock signal Clk_rtn_q2. It should be noted that Figure 11 the frequency dividers in the partitions 5011 and 5013 are omitted, but it can be understood that each partition includes a frequency divider that can generate a return clock signal based on the clock signal.

[0138] In some specific examples, with reference to Figure 8 , Figure 10 and Figure 11 , both the first branch node 502 and the second branch node 503 include OR gates. Specifically, the OR gate 1202 in the first branch node 502 is configured to combine the return clock signal Clk_rtn_q0 output by the partition 5010 and the return clock signal Clk_rtn_q1 output by the partition 5011 to generate a first combined clock signal Clk_rtn_q01, and the OR gate 1302 in the second branch node 503 is configured to combine the return clock signal Clk_rtn_q2 output by the partition 5012 and the return clock signal Clk_rtn_q3 output by the partition 5013 to generate a second combined clock signal Clk_rtn_q23.

[0139] In some specific examples, with reference to Figure 8 and Figure 11, the input / output node 601 includes: a first matching circuit 1203 configured to match a first combined clock signal Clk_rtn_q01 and a first combined data signal Grd<63:0>; a second matching circuit 1303 configured to match a second combined clock signal Clk_rtn_q23 and a second combined data signal Grd<127:64>. Specifically, taking the first matching circuit 1203 as an example, the first matching circuit 1203 may include a delay circuit 1204, a pulse generator 1205, and a D flip-flop 1206. The delay circuit 1204 can delay the first combined clock signal Clk_rtn_q01 to obtain a synchronized first combined clock signal Clk_rtn_q01. The pulse generator 1205 can generate a clock input for the D flip-flop 1206 based on the edge detection result of the first combined clock signal Clk_rtn_q01. At the same time, the first combined data signal Grd<63:0> is used as the data input for the D flip-flop 1206, so that a synchronized first combined data signal Grd<63:0> can be output.

[0140] In some embodiments, referring to Figure 8 and Figure 9 , the peripheral circuit further includes a data register 800, as well as a third clock path 903, a fourth clock path 904, a third data path 1003, and a fourth data path 1004. Both ends of the third clock path 903, the fourth clock path 904, the third data path 1003, and the fourth data path 1004 are respectively connected to the input / output node 601 and the data register 800.

[0141] In the embodiments of the present disclosure, the input / output node 601 can be configured to output a synchronized first combined clock signal Clk_rtn_q01 and a first combined data signal Grd<63:0>, and transmit the first combined clock signal Clk_rtn_q01 and the first combined data signal Grd<63:0> to the data register 800 via the third clock path 903 and the third data path 1003 respectively. And within the same time range, output a synchronized second combined clock signal Clk_rtn_q23 and a second combined data signal Grd<127:64>, and transmit the second combined clock signal Clk_rtn_q23 and the second combined data signal Grd<127:64> to the data register 800 via the fourth clock path 904 and the fourth data path 1004 respectively.

[0142] In some specific examples, the data register 800 includes a plurality of first temporary storage areas (FIFO_EV) 801 and a plurality of second temporary storage areas (FIFO_OD) 802, and the first temporary storage areas 801 and the second temporary storage areas 802 are arranged alternately. The plurality of first temporary storage areas 801 are configured to receive a first control signal and a first combined clock signal Clk_rtn_q01, and receive a first combined data signal Grd<63:0> based on the first control signal and the first combined clock signal Clk_rtn_q01; the plurality of second temporary storage areas 802 are configured to receive a second control signal and a second combined clock signal Clk_rtn_q23, and receive a second combined data signal Grd<127:64> based on the second control signal and the second combined clock signal Clk_rtn_q23.

[0143] In some embodiments, as Figure 12 shown, in response to the first control signal Fin_e<11:0>, the first combined data signal Grd<63:0> can be written into the plurality of first temporary storage areas 801, and during this process, the first combined clock signal Clk_rtn_q01 can be used as the write clock signal; in response to the second control signal Fin_o<11:0>, the second combined data signal Grd<127:64> can be written into the plurality of second temporary storage areas 802, and during this process, the second combined clock signal Clk_rtn_q23 can be used as the write clock signal.

[0144] It should be noted that in the embodiments of the present disclosure, the data register 800 includes 11 first temporary storage areas 801 and 11 second temporary storage areas 802 as an example, but the present disclosure is not limited thereto. In some other embodiments, the number of the first temporary storage areas 801 and the second temporary storage areas 802 can be more than 11, and the number of the first temporary storage areas 801 and the number of the second temporary storage areas 802 can be different, and the present disclosure does not limit this.

[0145] In some embodiments, continuing to refer to Figure 12 , after the first combined data signal Grd<63:0> and the second combined data signal Grd<127:64> are written into the data register 800, in response to an output control signal and an output clock signal, the data signal can be output from the data register 800 and transmitted to the outside of the memory device in a serial form via a parallel-to-serial circuit (SER) 803 to complete a read operation.

[0146] In some specific examples, the data register 800 is a first-in-first-out register (FIFO). When the data signal is output from the data register 800, the data in a first temporary storage area 801 and the data in a second temporary storage area 802 can be output alternately. That is, the data can be output in the order of FIFO_EV<0>, FIFO_OD<0>, FIFO_EV<1>, FIFO_OD<1>... FIFO_EV<10>, FIFO_OD<10>, FIFO_EV<11>, FIFO_OD<11>.

[0147] In the embodiment of the present disclosure, the first combined clock signal Clk_rtn_q01 and the second combined clock signal Clk_rtn_q23 can be used as the write clock signals of the data register 800. The writing of data into the first temporary storage area 801 and the writing of data into the second temporary storage area 802 are independent of each other. Therefore, after the first combined data signal Grd<63:0> is transmitted to the data register 800, it can be written into the first temporary storage area 801 without waiting for the second combined data signal Grd<127:64>. This can improve the data transmission efficiency and provide a suitable time window for writing data into the data register 800, avoiding the reduction of data transmission reliability caused by the difference in data writing speed due to the difference in the formation process of different temporary storage areas. In addition, the output clock signal and the write clock signal of the data register 800 are also independent of each other. Therefore, even if the first combined clock signal Clk_rtn_q01 and the second combined clock signal Clk_rtn_q23 are not synchronized, it will not affect the timing of the data signal output from the data register 800.

[0148] In an embodiment of the present disclosure, when obtaining read data from the page buffer 501, the first merged clock signal Clk_rtn_q01 and the first merged data signal Grd<63:0>, as well as the second merged clock signal Clk_rtn_q23 and the second merged data signal Grd<127:64> can be transmitted to the input / output node 601 in parallel and then transmitted from the input / output node 601 to the data register 800. On the one hand, the first merged clock signal Clk_rtn_q01 and the second merged clock signal Clk_rtn_q23 do not need to be merged, and the first merged data signal Grd<63:0> and the second merged data signal Grd<127:64> do not need to be merged either. Therefore, the matching cost caused by the difference in the path lengths between the first branch node 502 and the third branch node 602 and between the second branch node 503 and the third branch node 602 can be saved, thereby improving the data transmission efficiency. On the other hand, between the third branch node 602 and the input / output node 601, the bit width of the data signal is twice the bit width of the data path in the storage plane area A, and between the input / output node 601 and the data register 800, the bit width of the data signal is also twice the bit width of the data path in the storage plane area A. That is, without changing the bit width of the data path in the storage plane area A, the data transmission parallelism can be increased to transmit more data to the data register 800 per unit time, thereby improving the transmission efficiency of the read data in the memory device to meet the requirements of electronic devices with higher processing speeds.

[0149] In some embodiments, as Figure 13 shown, the peripheral circuit further includes: a fifth data path 1101 arranged in parallel with the fifth clock path 701, a sixth data path 1102 arranged in parallel with the sixth clock path 702, and a seventh data path 1103 arranged in parallel with the seventh clock path 703.

[0150] In an embodiment of the present disclosure, when a write operation is performed, the data to be written into the memory array can be temporarily stored in a partition of the page buffer 501 from the input / output node 601. Specifically, the fifth data path 1101 can be configured to transmit the first data signal Gwd<127:0> from the input / output node 601 to the third branch node 602. The third branch node 602 can be configured to equally divide the first data signal Gwd<127:0> into a first sub-data signal Gwd<63:0> and a second sub-data signal Gwd<127:64>. The sixth data path 1102 can be configured to transmit the first sub-data signal Gwd<63:0> from the third branch node 602 to the first branch node 502. The seventh data path 1103 can be configured to transmit the second sub-data signal Gwd<127:64> from the third branch node 602 to the second branch node 503. Further, the first branch node 502 can be configured to divide the first sub-data signal Gwd<63:0> into two data signals Gwd<31:0> and Gwd<63:32>, and transmit the data signal Gwd<31:0> to the partition 5010 and the data signal Gwd<63:32> to the partition 5011. The second branch node 503 can be configured to divide the second sub-data signal Gwd<127:64> into two data signals Gwd<95:64> and Gwd<127:96>, and transmit the data signal Gwd<95:64> to the partition 5012 and the data signal Gwd<127:96> to the partition 5013. During this process, the clock signal Clk_dp_q0 is transmitted to the partition 5010 and can be used as the write clock signal for the data signal Gwd<31:0>. The clock signal Clk_dp_q1 is transmitted to the partition 5011 and can be used as the write clock signal for the data signal Gwd<63:32>. The clock signal Clk_dp_q2 is transmitted to the partition 5012 and can be used as the write clock signal for the data signal Gwd<95:64>. The clock signal Clk_dp_q3 is transmitted to the partition 5013 and can be used as the write clock signal for the data signal Gwd<127:96>.

[0151] In some embodiments, the bit width of the fifth data path 1101 is greater than or equal to twice the bit width of the sixth data path 1102 or twice the bit width of the seventh data path 1103. The third branch node 602 can output the first sub-data signal Gwd<63:0> and the second sub-data signal Gwd<127:64> within the same time range. Therefore, without changing the bit width of the data path in the storage surface area A, the parallelism of data transmission can be increased, and more data can be transmitted from the input / output node 601 to the page buffer 501 per unit time, thereby improving the transmission efficiency of the written data in the memory device to meet the requirements of electronic devices with higher processing speeds.

[0152] In some embodiments, the memory device in the above embodiments may be a three-dimensional NAND memory, and the memory array may be a NAND memory array.

[0153] Based on a concept similar to the above memory device, the present disclosure also provides a memory system, which includes: at least one memory device in any of the foregoing embodiments; a controller coupled to at least one memory device and configured to control the memory device. For the specific composition and functional implementation of the memory system, reference may be made to the description in the foregoing text regarding Figures 1 to 5 For the sake of brevity, it will not be repeated here.

[0154] The present disclosure also provides an operation method for a memory device. Figure 14 is a schematic flowchart of the operation method for the memory device provided by the embodiments of the present disclosure. As Figure 14 shown, the operation method of the memory device includes:

[0155] Step S10: The partitions of the page buffer receive a clock signal and output a return clock signal based on the clock signal;

[0156] Step S20: Combine the return clock signals output by two of the multiple partitions to generate a first combined clock signal;

[0157] Step S30: Transmit the first combined clock signal to the input / output node;

[0158] Step S40: Combine the return clock signals output by another two of the multiple partitions to generate a second combined clock signal;

[0159] Step S50: Transmit the second combined clock signal to the input / output node.

[0160] In some embodiments, with reference to Figure 7 and Figure 10, before performing step S10, the operation method of the memory device further includes: receiving a first clock signal Clk_dp, transmitting the first clock signal Clk_dp from an input / output node 601 to a third branch node 602; generating a first sub-clock signal Clk_dp_q01 and a second sub-clock signal Clk_dp_q23 in parallel based on the first clock signal Clk_dp; transmitting the first sub-clock signal Clk_dp_q01 to a first branch node 502; and transmitting the second sub-clock signal Clk_dp_q23 to a second branch node 503.

[0161] In some embodiments, the specific process of performing step S10 may include: a partition 5010 receives a clock signal Clk_dp_q0 and generates a return clock signal Clk_rtn_q0 based on the clock signal Clk_dp_q0; a partition 5011 receives a clock signal Clk_dp_q1 and generates a return clock signal Clk_rtn_q1 based on the clock signal Clk_dp_q1; a partition 5012 receives a clock signal Clk_dp_q2 and generates a return clock signal Clk_rtn_q2 based on the clock signal Clk_dp_q2; a partition 5013 receives a clock signal Clk_dp_q3 and generates a return clock signal Clk_rtn_q3 based on the clock signal Clk_dp_q3. As Figure 10 shown, the return clock signal Clk_rtn_q0 and the return clock signal Clk_rtn_q2 can be generated within the same time range, and the return clock signal Clk_rtn_q1 and the return clock signal Clk_rtn_q3 can be generated within the same time range.

[0162] It should be noted that Figure 14 the steps of the memory operation method in Figure 8 and Figure 10 are not sorted in the order of time. In some embodiments, with reference to

[0163] Steps S20 and S40 can be executed in parallel, and steps S30 and S50 can also be executed in parallel.

[0164] In some embodiments, the specific processes of performing step S30 and step S50 may include: transmitting the first combined clock signal Clk_rtn_q01 and the second combined clock signal Clk_rtn_q23 in parallel to the input / output node 601.

[0165] In some embodiments, referring to Figure 9 , the operation method of the memory device further includes: combining the data signals output from partition 5010 and partition 5011 to generate a first combined data signal Grd<63:0>; combining the data signals output from partition 5012 and partition 5013 to generate a second combined data signal Grd<127:64>; transmitting the first combined data signal Grd<63:0> to the input / output node 601; transmitting the second combined data signal Grd<127:64> to the input / output node 601.

[0166] In some embodiments, the operation method of the memory device further includes: matching the first combined clock signal Clk_rtn_q01 with the first combined data signal Grd<63:0>; matching the second combined clock signal Clk_rtn_q23 with the second combined data signal Grd<127:64>.

[0167] In some embodiments, the operation method of the memory device further includes: transmitting the first combined clock signal Clk_rtn_q01 and the first combined data signal Grd<63:0> from the input / output node 601 to the data register 800; transmitting the second combined clock signal Clk_rtn_q23 and the second combined data signal Grd<127:64> from the input / output node 601 to the data register 800.

[0168] In some embodiments, in combination with reference to Figure 8 , Figure 9 and Figure 12 , the operation method of the memory device further includes: a plurality of first temporary storage areas 801 of the data register 800 receive the first control signal Fin_e<11:0> and the first combined clock signal Clk_rtn_q01, and receive the first combined data signal Grd<63:0> based on the first control signal Fin_e<11:0> and the first combined clock signal Clk_rtn_q01; a plurality of second temporary storage areas 802 of the data register 800 receive the second control signal Fin_o<11:0> and the second combined clock signal Clk_rtn_q23, and receive the second combined data signal Grd<127:64> based on the second control signal Fin_o<11:0> and the second combined clock signal Clk_rtn_q23; the first temporary storage areas 801 and the second temporary storage areas 802 are arranged alternately.

[0169] In some embodiments, with reference to Figure 13 , the method for operating a memory device further includes: when performing a write operation, receiving a first clock signal Clk_dp; transmitting the first clock signal Clk_dp from an input / output node 601 to a third branch node 602; generating a first sub-clock signal Clk_dp_q01 and a second sub-clock signal Clk_dp_q23 in parallel based on the first clock signal Clk_dp; transmitting the first sub-clock signal Clk_dp_q01 to a first branch node 502; and transmitting the second sub-clock signal Clk_dp_q23 to a second branch node 503. While receiving the first clock signal Clk_dp, receiving a first data signal Gwd<127:0>; transmitting the first data signal Gwd<127:0> from the input / output node 601 to the third branch node 602, and equally dividing the first data signal Gwd<127:0> into a first sub-data signal Gwd<63:0> and a second sub-data signal Gwd<127:64>; transmitting the first sub-data signal Gwd<63:0> to the first branch node 502; and transmitting the second sub-data signal Gwd<127:64> to the second branch node 503.

[0170] In the embodiments of the present disclosure, when performing a read operation, a first merged clock signal Clk_rtn_q01 and a first merged data signal Grd<63:0>, and a second merged clock signal Clk_rtn_q23 and a second merged data signal Grd<127:64> can be transmitted to the input / output node 601 in parallel and then transmitted from the input / output node 601 to a data register 800. The first merged clock signal Clk_rtn_q01 and the second merged clock signal Clk_rtn_q23 do not need to be merged, and the first merged data signal Grd<63:0> and the second merged data signal Grd<127:64> do not need to be merged either. Therefore, the matching cost caused by the difference in the path lengths between the first branch node 502 and the third branch node 602 and between the second branch node 503 and the third branch node 602 can be saved, thereby improving the transmission efficiency of the read data to enable the memory device to meet the requirements of electronic devices with higher processing speeds. When performing a write operation, the first sub-data signal Gwd<63:0> and the second sub-data signal Gwd<127:64> can be transmitted in parallel, and more data can be transmitted from the input / output node 601 to a page buffer 501 per unit time, thereby improving the transmission efficiency of the written data in the memory device to enable the memory device to meet the requirements of electronic devices with higher processing speeds.

[0171] The features disclosed in the several device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new device embodiments.

[0172] In the several method embodiments provided by the present disclosure, the disclosed methods can be arbitrarily combined without conflict to obtain new method embodiments.

[0173] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure.

Claims

1. A memory device, characterized in that, The memory device includes a memory array and a peripheral circuit coupled to the memory array; The peripheral circuit includes: A page buffer, the page buffer including a plurality of partitions, each partition being configured to receive a clock signal and output a return clock signal based on the clock signal; A first branch node, connected to two of the plurality of partitions, and configured to combine the return clock signals output by the two partitions to generate a first combined clock signal; A first clock path, with two ends of the first clock path respectively connected to the first branch node and an input / output node, and configured to transmit the first combined clock signal to the input / output node; A second branch node, connected to another two of the plurality of partitions, and configured to combine the return clock signals output by the another two partitions to generate a second combined clock signal; A second clock path, with two ends of the second clock path respectively connected to the second branch node and the input / output node, and configured to transmit the second combined clock signal to the input / output node.

2. The memory device according to claim 1, wherein The peripheral circuit further includes: A third branch node, both the first clock path and the second clock path pass through the third branch node; a portion of the first clock path between the third branch node and the input / output node is arranged in parallel with a portion of the second clock path between the third branch node and the input / output node; the portion of the first clock path between the third branch node and the input / output node is configured to transmit the first combined clock signal to the input / output node; the portion of the second clock path between the third branch node and the input / output node is configured to transmit the second combined clock signal to the input / output node.

3. The memory device according to claim 1, wherein The first branch node is further configured to combine the data signals output by the two partitions to generate a first combined data signal; the second branch node is further configured to combine the data signals output by the another two partitions to generate a second combined data signal; The peripheral circuit further includes: A first data path, arranged in parallel with the first clock path, and configured to transmit the first combined data signal to the input / output node; A second data path, arranged in parallel with the second clock path, and configured to transmit the second combined data signal to the input / output node.

4. The memory device according to claim 3, wherein The input / output node includes: A first matching circuit, configured to match the first combined clock signal and the first combined data signal; A second matching circuit, configured to match the second combined clock signal and the second combined data signal.

5. The memory device according to claim 4, wherein, The peripheral circuit further includes a data register and, A third clock path, with two ends of the third clock path respectively connected to the input / output node and the data register, and configured to transmit the first combined clock signal to the data register; A fourth clock path, with two ends of the fourth clock path respectively connected to the input / output node and the data register, and configured to transmit the second combined clock signal to the data register; A third data path, with two ends of the third data path respectively connected to the input / output node and the data register, and configured to transmit the first combined data signal to the data register; A fourth data path, with two ends of the fourth data path respectively connected to the input / output node and the data register, and configured to transmit the second combined data signal to the data register.

6. The memory device according to claim 5, wherein The data register includes a plurality of first storage areas and a plurality of second storage areas; the first storage areas and the second storage areas are arranged alternately; The plurality of first storage areas are configured to receive a first control signal and the first combined clock signal, and receive the first combined data signal based on the first control signal and the first combined clock signal; The plurality of second storage areas are configured to receive a second control signal and the second combined clock signal, and receive the second combined data signal based on the second control signal and the second combined clock signal.

7. The memory device according to claim 2, wherein The input / output node is configured to receive a first clock signal; the peripheral circuit further includes: A fifth clock path, with two ends of the fifth clock path respectively connected to the input / output node and the third branch node, and configured to transmit the first clock signal to the third branch node; the third branch node is configured to generate a first sub-clock signal and a second sub-clock signal in parallel based on the first clock signal; A sixth clock path, with two ends of the sixth clock path respectively connected to the third branch node and the first branch node, and configured to transmit the first sub-clock signal to the first branch node; A seventh clock path, with two ends of the seventh clock path respectively connected to the third branch node and the second branch node, and configured to transmit the second sub-clock signal to the second branch node; the length of the sixth clock path is different from the length of the seventh clock path.

8. The memory device according to claim 7, wherein, The input / output node is configured to receive a first data signal; the peripheral circuit further includes: A fifth data path, arranged in parallel with the fifth clock path, and configured to transmit the first data signal to the third branch node; the third branch node is further configured to equally divide the first data signal into a first sub-data signal and a second sub-data signal; A sixth data path, arranged in parallel with the sixth clock path, and configured to transmit the first sub-data signal to the first branch node; A seventh data path, with two ends of the seventh data path respectively connected to the third branch node and the second branch node, and configured to transmit the second sub-data signal to the second branch node.

9. The memory device according to claim 8, wherein The bit width of the fifth data path is greater than or equal to twice the bit width of the sixth data path or twice the bit width of the seventh data path.

10. The memory device according to claim 2, wherein, The memory device includes a pad region and a storage plane region arranged in a first direction; wherein, the pad region includes: the input / output node and the third branch node; the storage plane region includes: the page buffer, the first branch node, and the second branch node; the two partitions are symmetrically distributed on opposite sides of the first branch node along a second direction; the other two partitions are symmetrically distributed on opposite sides of the second branch node along the second direction; the second direction is perpendicular to the first direction.

11. The memory device according to claim 1, wherein, The partition includes a frequency divider configured to receive the clock signal and generate the return clock signal based on the clock signal.

12. The memory device according to claim 1, wherein Both the first branch node and the second branch node include an OR gate; the OR gate of the first branch node is configured to combine the return clock signals output by the two partitions to generate the first combined clock signal, and the OR gate of the second branch node is configured to combine the return clock signals output by the other two partitions to generate the second combined clock signal.

13. The memory device according to claim 1, wherein, The memory device includes a 3D NAND memory.

14. A memory system, characterized in that, Including: at least one memory device according to any one of claims 1 to 13; a memory controller coupled to the at least one memory device and configured to control the memory device.

15. A method for operating a memory device, characterized in that, The operation method includes: The partitions of the page buffer receive the clock signal and output the return clock signal based on the clock signal; combining the return clock signals output by two of the multiple partitions to generate a first combined clock signal; transmitting the first combined clock signal to the input / output node; combining the return clock signals output by the other two of the multiple partitions to generate a second combined clock signal; transmitting the second combined clock signal to the input / output node.

16. The method for operating a memory device according to claim 15, wherein The transmitting the first combined clock signal to the input / output node and the transmitting the second combined clock signal to the input / output node include: transmitting the first combined clock signal and the second combined clock signal to the input / output node in parallel.

17. The method for operating a memory device according to claim 15, wherein The operation method further includes: combining the data signals output by the two partitions to generate a first combined data signal; combining the data signals output by the other two partitions to generate a second combined data signal; transmitting the first combined data signal to the input / output node; transmitting the second combined data signal to the input / output node.

18. The method for operating a memory device according to claim 17, wherein, The operation method further includes: matching the first combined clock signal with the first combined data signal; matching the second combined clock signal with the second combined data signal.

19. The method for operating a memory device according to claim 18, characterized in that, The operation method further includes: transmitting the first combined clock signal and the first combined data signal from the input / output node to the data register; transmitting the second combined clock signal and the second combined data signal from the input / output node to the data register.

20. The method for operating a memory device according to claim 19, wherein, The operation method further includes: A plurality of first temporary storage areas of the data register receive a first control signal and the first merged clock signal, and receive the first merged data signal based on the first control signal and the first merged clock signal; A plurality of second temporary storage areas of the data register receive a second control signal and the second merged clock signal, and receive the second merged data signal based on the second control signal and the second merged clock signal; the first temporary storage areas and the second temporary storage areas are arranged alternately.

21. The method for operating a memory device according to claim 16, wherein, Before the partition of the page buffer receives a clock signal and outputs a return clock signal based on the clock signal, the method further includes: Receiving a first clock signal; Transmitting the first clock signal from the input / output node to a third branch node; generating a first sub-clock signal and a second sub-clock signal in parallel based on the first clock signal; Transmitting the first sub-clock signal to a first branch node; Transmitting the second sub-clock signal to a second branch node.

22. The operation method of the memory device according to claim 21, characterized in that, The method further includes: Receiving a first data signal; Transmitting the first data signal from the input / output node to the third branch node; Dividing the first data signal equally into a first sub-data signal and a second sub-data signal; transmitting the first sub-data signal to the first branch node; Transmitting the second sub-data signal to the second branch node.

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