Semiconductor memory device

Abstract

The embodiment of the invention provides a high-quality semiconductor memory device. According to one embodiment, a semiconductor memory device includes: a first cell region including a plurality of memory cells; a second cell region including a plurality of memory cells; a connection region sandwiched between the first cell region and the second cell region; and a row decoder that transmits a voltage to the word lines of the first and second cell regions via the connection region.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application. The parent application of this divisional application is a patent application for invention with the application date of February 14, 2020, application number 202010105340.6, and invention title "Semiconductor Memory Device".

[0003] [Related Application]

[0004] This application claims the priority based on Japanese Patent Application No. 2019-171693 (filing date: September 20, 2019). This application incorporates all the contents of the base application by reference to the base application. Technical Field

[0005] The embodiment relates to a semiconductor memory device. Background Art

[0006] A NAND (Not and) type flash memory capable of storing data non-volatilely is known. Summary of the Invention

[0007] The embodiment provides a high-quality semiconductor memory device.

[0008] The semiconductor memory device of the embodiment includes a first unit region, a second unit region, and a first connection region. The first unit region includes a plurality of first conductor layers laminated at intervals in a first direction, and a first semiconductor layer extending in the first direction within the plurality of first conductor layers, and intersections of the plurality of first conductor layers and the first semiconductor layer respectively form memory cells. The second unit region includes a plurality of second conductor layers laminated at intervals in the first direction, and a second semiconductor layer extending in the first direction within the plurality of second conductor layers, and intersections of the plurality of second conductor layers and the second semiconductor layer respectively form memory cells. The first connection region is disposed between the first unit region and the second unit region in a second direction intersecting the first direction, and includes a first bridging region and a first stepped region. In the first bridging region, a plurality of third conductor layers laminated at intervals in the first direction are respectively electrically connected to one layer of the plurality of first conductor layers and one layer of the plurality of second conductor layers. In the first stepped region, the plurality of third conductor layers respectively include steps for providing first contact plugs.

[0009] The first stepped region may also be connected to the first bridging region in a third direction intersecting the first direction and the second direction.

[0010] The first connection region may further include a first sub-channel region, which is adjacent to the first bridging region and the first stepped region in the second direction, and is provided with second contact plugs extending in the first direction in a plurality of third conductor layers.

[0011] In the first sub-channel region, one layer of the plurality of first conductor layers and one layer of the plurality of second conductor layers may be electrically connected to each other in the plurality of third conductor layers.

[0012] The semiconductor memory device may further include a first slit, a third cell region, a fourth cell region, and a second connection region including a second sub-channel region. The first slit is adjacent to the first cell region, the first connection region, and the second cell region in the third direction. The third cell region is adjacent to the first cell region with the first slit interposed therebetween in the third direction, and includes a plurality of fourth conductor layers stacked at intervals in the first direction and a third semiconductor layer extending in the first direction in the plurality of fourth conductor layers. Intersections of the plurality of fourth conductor layers and the third semiconductor layer respectively form memory cells. The fourth cell region is adjacent to the second cell region with the first slit interposed therebetween in the third direction, and includes a plurality of fifth conductor layers stacked at intervals in the first direction and a fourth semiconductor layer extending in the first direction in the plurality of fifth conductor layers. Intersections of the plurality of fifth conductor layers and the fourth semiconductor layer respectively form memory cells. The second sub-channel region is disposed between the third cell region and the fourth cell region in the second direction, and is provided with a second bridging region, a second stepped region, and a fourth contact plug. In the second bridging region, one layer of the plurality of fourth conductor layers and one layer of the plurality of fifth conductor layers are electrically connected to each other by a plurality of sixth conductor layers stacked at intervals in the first direction. In the second stepped region, the plurality of sixth conductor layers each include a step for providing a third contact plug and are connected to the second bridging region in the third direction. The fourth contact plug is adjacent to the second bridging region and the second stepped region in the second direction and extends in the first direction in the plurality of sixth conductor layers.

[0013] The first bridging region and the first stepped region may be adjacent to the second sub-channel region with the first slit interposed therebetween in the third direction, and the second bridging region and the second stepped region may be adjacent to the first sub-channel region with the first slit interposed therebetween in the third direction.

[0014] A first row decoder related to the first unit region and the second unit region may also be provided below the first bridging region, the first stepped region, and the first sub-channel region in the first direction. The first unit region and the second unit region are connected to the first row decoder via a fourth contact plug, a first contact plug, the first stepped region, and the first bridging region. A second row decoder related to the third unit region and the fourth unit region may also be provided below the second bridging region, the second stepped region, and the first sub-channel region in the first direction. The third unit region and the fourth unit region are connected to the second row decoder via a third contact plug, a second contact plug, the second stepped region, and the second bridging region.

[0015] The semiconductor memory device may further include: a first wiring connecting the fourth contact plug and the first contact plug; and a second wiring connecting the third contact plug and the second contact plug.

[0016] The first to third conductor layers may also be the same conductor layer.

[0017] The first to third conductor layers may also be word lines or select gate lines.

[0018] The fourth to sixth conductor layers may also be the same conductor layer.

[0019] The fourth to sixth conductor layers may also be word lines or select gate lines.

[0020] The semiconductor memory device may further include a third stepped region, a third connection region, a fourth stepped region, and a fourth connection region. The third stepped region is separated from the first connection region by the first unit region in the second direction, and each of a plurality of seventh conductor layers stacked with intervals in the first direction has a step for setting a fifth contact plug. The third connection region includes a first contact region adjacent to the third stepped region in the second direction and having a sixth contact plug extending in the first direction among the plurality of seventh conductor layers. The fourth stepped region is separated from the second connection region by the third unit region in the second direction, and each of a plurality of eighth conductor layers stacked with intervals in the first direction has a step for setting a seventh contact plug. The fourth connection region includes a second contact region adjacent to the fourth stepped region in the second direction and having an eighth contact plug extending in the first direction among the plurality of eighth conductor layers.

[0021] The third stepped region may also be adjacent to the second contact region with a first slit interposed therebetween in the third direction, and the fourth stepped region may also be adjacent to the first contact region with a first slit interposed therebetween in the third direction.

[0022] Below the 3rd step region and below the 1st direction of the 2nd contact region, a 3rd row decoder related to the 1st unit region is provided, and the 1st unit region is connected to the 3rd row decoder via the 5th contact plug, the 8th contact plug, and the 3rd step region. Below the 4th step region and below the 1st direction of the 1st contact region, a 4th row decoder related to the 3rd unit region is provided, and the 3rd unit region is connected to the 4th row decoder via the 6th contact plug, the 7th contact plug, and the 4th step region.

[0023] The semiconductor memory device may further include: a 3rd wiring connecting the 5th contact plug and the 8th contact plug; and a 4th wiring connecting the 6th contact plug and the 7th contact plug.

[0024] The 1st to 3rd, and 7th conductive layers may also be the same conductive layer.

[0025] The 1st to 3rd, and 7th conductive layers may also be word lines or select gate lines.

[0026] The 4th to 6th, and 8th conductive layers may also be the same conductive layer.

[0027] A semiconductor memory device according to another embodiment includes a 1st unit region, a 2nd unit region, a connection region, and a row decoder. The 1st unit region includes a plurality of 1st conductive layers stacked in the 1st direction and a plurality of memory cells. The plurality of memory cells extend in the 1st direction within the plurality of 1st conductive layers, include a 1st semiconductor layer, and intersections of the plurality of 1st conductive layers and the 1st semiconductor layer respectively form memory cells. The 2nd unit region is a region arranged in the 2nd direction intersecting the 1st direction of the 1st unit region, and includes a plurality of 2nd conductive layers stacked in the 1st direction and a plurality of memory cells. The plurality of memory cells extend in the 1st direction within the plurality of 2nd conductive layers, include a 2nd semiconductor layer, and intersections of the plurality of 1st conductive layers and the 2nd semiconductor layer respectively form memory cells. The connection region is a region arranged between the 1st unit region and the 2nd unit region, and is sandwiched between a plurality of 3rd conductive layers stacked in the 1st direction and respectively electrically connecting one layer of the plurality of 1st conductive layers and one layer of the plurality of 2nd conductive layers, and a 1st contact plug electrically insulated from the plurality of 3rd conductive layers and extending in the 1st direction. The row decoder is arranged below the connection region, and transmits a voltage to the word lines of the 1st and 2nd unit regions via the connection region electrically connected to the 1st contact plug of the connection region.

[0028] According to the embodiment, a high-quality semiconductor memory device can be provided. Description of the Drawings

[0029] Figure 1 It is a block diagram showing a configuration example of the semiconductor memory device according to the 1st embodiment.

[0030] Figure 2 It is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment.

[0031] Figure 3 It is a bird's-eye view simply shown for easily understanding the layout in the Z direction of the semiconductor memory device.

[0032] Figure 4 It is a diagram showing an example of the planar layout of the memory cell array.

[0033] Figure 5 It is a diagram showing an example of the layout related to the lower layer of the memory cell array.

[0034] Figure 6 It is a diagram showing an example of the layout related to the upper layer of the memory cell array.

[0035] Figure 7 It is a diagram showing the relationship between the lower layer and the upper layer.

[0036] Figure 8 It is a diagram showing an example of the layout of the connection region (lower) and the cell region (lower) separated by the connection region (lower).

[0037] Figure 9 It is a diagram showing an example of the layout of the connection region (lower) in the first lower layer.

[0038] Figure 10 It is a diagram showing an example of the layout of the connection region (lower) in the second lower layer.

[0039] Figure 11 It is a diagram showing an example of the layout of the connection region (upper) and the cell region (upper) separated by the connection region (upper).

[0040] Figure 12 It is a diagram showing an example of the layout of the connection region (upper) in the first upper layer.

[0041] Figure 13 It is a diagram showing an example of the layout of the connection region (upper) in the second upper layer.

[0042] Figure 14 It is a block diagram showing the connection of each component in the first lower layer.

[0043] Figure 15 It is a block diagram showing the connection of each component in the second lower layer.

[0044] Figure 16 It is a block diagram showing the connection of each component in the first upper layer.

[0045] Figure 17It is a block diagram showing the connections of the components in the second upper layer.

[0046] Figure 18 It is a diagram showing the relationship between the connection area (lower) and the connection area (upper).

[0047] Figure 19 It is a diagram showing an example of the planar layout of the circuit area.

[0048] Figure 20 It is a diagram showing an example of the layout of a part of the row decoder module and a part of the sense amplifier module.

[0049] Figure 21 It is a diagram showing the relationship between the row decoder module in the circuit area and the connection area in the memory cell array.

[0050] Figure 22 It is a diagram showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the first embodiment.

[0051] Figure 23 It is a diagram showing an example of the detailed planar layout of the memory cell array in the cell area of the semiconductor memory device of the first embodiment.

[0052] Figure 24 It is along Figure 23 A cross-sectional view taken along the C-C line, and it is a diagram showing an example of the cross-sectional structure in the cell area of the memory cell array included in the semiconductor memory device of the first embodiment.

[0053] Figure 25 It is along Figure 24 A cross-sectional view taken along the D-D line, and it is a diagram showing an example of the cross-sectional structure of the memory pillar in the semiconductor memory device of the first embodiment.

[0054] Figure 26 It is an example of the detailed planar layout of the connection area of the semiconductor memory device of the first embodiment, and it is a diagram showing two adjacent connection areas ([[]] Figure 22 B) selected in the Y direction.

[0055] Figure 27 It is along Figure 26 A cross-sectional view taken along the E-E line, and it is a diagram showing an example of the cross-sectional structure of the sub-channel connection area and the stepped area.

[0056] Figure 28 It is along Figure 26 A cross-sectional view taken along the F-F line, and it is a diagram showing an example of the cross-sectional structure of the sub-channel connection area and the stepped area.

[0057] Figure 29 It is along Figure 26A cross-sectional view of the G-G line, and it is a figure showing an example of the cross-sectional structure of the sub-channel connection area and the stepped area.

[0058] Figure 30 It is a cross-sectional view along Figure 26 the H-H line, and it is a figure showing an example of the cross-sectional structure of the lower bridging area and the lower sub-channel connection area.

[0059] Figure 31 It is a cross-sectional view along Figure 26 the J-J line, and it is a figure showing an example of the cross-sectional structure of the first lower connectable area.

[0060] Figure 32 It is a cross-sectional view along Figure 26 the K-K line, and it is a figure showing an example of the cross-sectional structure of the lower bridging area and the lower sub-channel connection area.

[0061] Figure 33 It is a cross-sectional view along Figure 26 the L-L line, and it is a figure showing an example of the cross-sectional structure of the first upper connectable area.

[0062] Figure 34 It is a cross-sectional view along Figure 26 the M-M line, and it is a figure showing an example of the cross-sectional structure of the sub-channel connection area.

[0063] Figure 35 It is a figure showing the transmission direction of the voltage of the comparative example to the cell area.

[0064] Figure 36 It is a figure showing the transmission direction of the voltage of the comparative example to the cell area.

[0065] Figure 37 It is a figure showing the transmission direction of the voltage of the comparative example to the cell area.

[0066] Figure 38 It is a figure showing the transmission direction of the voltage of the embodiment to the cell area.

[0067] Figure 39 It is a figure showing the transmission direction of the voltage of the embodiment to the cell area.

[0068] Figure 40 It is a figure showing an example of the layout of the connection area and the cell areas separated by the connection area.

[0069] Figure 41 It is a figure showing the layout of the circuit area and the memory cell array of the semiconductor memory device of the first embodiment.

[0070] Figure 42It is a diagram showing the layout of the circuit area CTA and the memory cell array 10 of the semiconductor memory device 1 which represents a modification example 2 of the first embodiment.

[0071] Figure 43 It is a diagram showing the layout of the circuit area CTA and the memory cell array 10 of the semiconductor memory device 1 which represents a modification example 2 of the first embodiment.

[0072] Figure 44 It is a diagram showing a planar layout example of the circuit area.

[0073] Figure 45 It is a diagram showing a planar layout example of the memory cell array.

[0074] Figure 46 It is a diagram showing the transmission direction of voltage to the cell area of the second embodiment.

[0075] Figure 47 It is a diagram showing the transmission direction of voltage to the cell area of the second embodiment.

[0076] Figure 48 It is a diagram showing a planar layout example of the circuit area.

[0077] Figure 49 It is a diagram showing a planar layout example of the memory cell array.

[0078] Figure 50 It is a diagram showing a layout example of the connection area and the cell area adjacent to the connection area.

[0079] Figure 51 It is a diagram showing a layout example of the connection area and the cell area adjacent to the connection area.

[0080] Figure 52 It is a diagram showing the layout of the circuit area and the memory cell array of the semiconductor memory device of the third embodiment.

[0081] Figure 53 It is a diagram showing the layout of the circuit area and the memory cell array of the semiconductor memory device of the third embodiment.

[0082] Figure 54 It is a diagram showing the layout of the circuit area and the memory cell array of the semiconductor memory device of the third embodiment.

[0083] Figure 55 It is a diagram showing the layout of the circuit area and the memory cell array of the semiconductor memory device of the third embodiment.

[0084] Figure 56 It is a diagram showing an overview of the stepped area.

[0085] Figure 57This is a diagram showing an overview of the stepped area.

[0086] Figure 58 This is an example of the detailed planar layout of the stepped area of the semiconductor memory device according to the fourth embodiment, and is a diagram showing two stepped areas adjacent in the Y direction selected by lottery.

[0087] Figure 59 This is along Figure 58 The cross-sectional view of the N-N line, and is a diagram showing an example of the cross-sectional structure of the stepped area. Detailed implementation manners

[0088] Hereinafter, embodiments will be described with reference to the drawings. Each embodiment illustrates a device or method for embodying the technical idea of the invention. The drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as the actual situation. The technical idea of the present invention is not specified by the shape, structure, configuration, etc. of the constituent elements.

[0089] In addition, in the following description, constituent elements having substantially the same functions and configurations are denoted by the same reference numerals. The numbers after the characters of the reference symbols are referred to by the reference symbols including the same characters, and are used to distinguish the elements having the same configuration from each other. When it is not necessary to distinguish the elements denoted by the reference symbols including the same characters from each other, these elements are referred to by the reference symbols including only the characters.

[0090] <1> First embodiment

[0091] Hereinafter, the semiconductor memory device 1 according to the first embodiment will be described.

[0092] <1-1> Overall configuration of the semiconductor memory device 1

[0093] <1-1-1> Configuration example

[0094] Figure 1 A configuration example of the semiconductor memory device 1 according to the first embodiment is shown. The semiconductor memory device 1 is a NAND-type flash memory that can store data non-volatilely and is controlled by an external memory controller 2. The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard.

[0095] As Figure 1 shown, the semiconductor memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0096] The memory cell array 10 includes a plurality of blocks BLK(0) to BLK(n) (n is an integer of 1 or more). The block BLK is a set of a plurality of memory cells capable of non-volatile data storage and is used, for example, as a data deletion unit. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described below.

[0097] The command register 11 stores the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes, for example, commands for causing the sequencer 13 to perform read operations, write operations, delete operations, etc.

[0098] The address register 12 stores the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BAdd, a page address PAdd, and a column address CAdd. For example, the block address BA, the page address PAdd, and the column address CAdd are used for selecting the block BLK, the word line, and the bit line, respectively.

[0099] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, based on the command CMD stored in the command register 11, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc., to perform read operations, write operations, delete operations, etc.

[0100] The driver module 14 generates the voltages used in read operations, write operations, delete operations, etc. Moreover, the driver module 14 applies the generated voltage, for example, to the signal line corresponding to the word line selected based on the page address PAdd stored in the address register 12.

[0101] The row decoder module 15 includes a plurality of row decoders RD. The row decoder RD selects one block BLK in the corresponding memory cell array 1v based on the block address BAdd stored in the address register 12. Moreover, the row decoder RD transmits, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0102] In the write operation, the sense amplifier module 16 applies the required voltage to each bit line according to the write data DAT received from the memory controller 2. In addition, in the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and then reads out the determination result and transmits it to the memory controller 2 in the form of data DAT.

[0103] The semiconductor memory device 1 and the memory controller 2 described above may also be combined to form one semiconductor device. As such a semiconductor device, for example, an SD is listed.TM a memory card of the card, or an SSD (solid state drive), etc.

[0104] <1-1-2>Circuit Configuration of Memory Cell Array

[0105] Figure 2 An example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment is shown, and one block BLK is selected from among the plurality of blocks BLK included in the memory cell array 10. As Figure 2 shown, the block BLK includes a plurality of string components SU(0) to SU(k) (k is an integer of 1 or more).

[0106] Each string component SU includes a plurality of NAND strings NS respectively associated with bit lines BL(0) to BL(m) (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT(0) to MT(15), and selection transistors ST(1) and ST(2). The memory cell transistor MT includes a control gate and a charge accumulation layer, and stores data non-volatilely. The selection transistors ST(1) and ST(2) are respectively used for selection of the string component SU during various operations.

[0107] In each NAND string NS, the memory cell transistors MT(0) to MT(15) are connected in series. The drain of the selection transistor ST(1) is connected to the bit line BL associated therewith, and the source of the selection transistor ST(1) is connected to one end of the series-connected memory cell transistors MT(0) to MT(15). The drain of the selection transistor ST(2) is connected to the other end of the series-connected memory cell transistors MT(0) to MT(15). The source of the selection transistor ST(2) is connected to the source line SL.

[0108] In the same block BLK, the control gates of the memory cell transistors MT(0) to MT(15) are commonly connected to word lines WL(0) to WL(7) respectively. The gates of the selection transistors ST(1) in the string components SU(0) to SU(k) are commonly connected to selection gate lines SGD(0) to SGD(k) respectively. The gate of the selection transistor ST(2) is commonly connected to the selection gate line SGS.

[0109] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by the NAND strings NS assigned the same column address in each string component SU. The source line SL is shared, for example, by a plurality of blocks BLKj.

[0110] A set of multiple memory cell transistors MT connected to a common word line WL within one string component SU is, for example, called a cell component CU. For example, the storage capacity of a cell component CU containing memory cell transistors MT that each store 1-bit data is defined as "1 page of data". The cell component CU can have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored in the memory cell transistors MT.

[0111] In addition, the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment is not limited to the circuit configuration described above. For example, the number of memory cell transistors MT and selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to be any number respectively. The number of string components SU included in each block BLK can be designed to be any number.

[0112] <1-2>Layout of the semiconductor memory device

[0113] Hereinafter, the layout of the semiconductor memory device 1 will be described.

[0114] In addition, in the drawings referred to below, the Y direction corresponds to the extending direction of the bit line BL, the X direction corresponds to the extending direction of the word line WL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate 20 forming the semiconductor memory device 1. In the plan view, hatching is appropriately added for easy viewing of the figure. The hatching added to the plan view is not necessarily related to the raw materials or characteristics of the elements to which the hatching is added.

[0115] <1-2-1>Outline of the layout of the semiconductor memory device

[0116] Use Figure 3 , the outline of the layout of the semiconductor memory device 1 will be described. Figure 3 is a bird's-eye view simply shown to easily understand the layout of the semiconductor memory device 1 in the Z direction.

[0117] As Figure 3As shown in the figure, the semiconductor memory device 1 includes a circuit area CTA having a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16, and a memory cell array 10 disposed on the circuit area CTA in the Z direction. The memory cell array 10 includes a lower layer LL and an upper layer UL disposed on the lower layer LL in the Z direction. In addition, the lower layer LL includes a first lower layer LL1 and a second lower layer LL2 disposed on the first lower layer LL1 in the Z direction. Similarly, the upper layer UL includes a first upper layer UL1 and a second upper layer UL2 disposed on the first upper layer UL1 in the Z direction. Details of the first lower layer LL1, the second lower layer LL2, the first upper layer UL1, and the second upper layer UL2 will be described below.

[0118] <1-2-2>Layout of Memory Cell Array

[0119] <1-2-2-1>Overview

[0120] Next, the layout of the memory cell array 10 in a plane including the X direction and the Y direction will be described.

[0121] Figure 4 An example of the planar layout of the memory cell array 10 is shown. In Figure 4 For simplicity, a schematic layout including the first lower layer LL1, the second lower layer LL2, the first upper layer UL1, and the second upper layer UL2 is shown.

[0122] As Figure 4 shown, the memory cell array 10 generally includes a plurality of cell regions 100 and a plurality of connection regions 101. The cell region 100 is a region having the above-described plurality of blocks BLK. The connection region 101 connects the blocks BLK of the cell regions 100 separated by the connection region 101, or transfers a voltage from the row decoder module 15 to the selection gate line or word line of the block BLK.

[0123] As Figure 4 shown, there are a plurality of cell regions 100, which are roughly divided into the left and right sides with respect to Figure 4 the paper surface. Moreover, the connection region 101 is located between the cell regions 100 on the left side and the cell regions 100 on the right side. That is to say, the connection region 101 is located in the center of the memory cell array 10 in the X direction. The cell regions 100 on the left side, the cell regions 100 on the right side, and the connection region 101 sandwiched therebetween as Figure 4 shown can be collectively referred to as a "layer". For example, the semiconductor memory device 1 may include a plurality of layers, and each layer can be controlled independently or in parallel.

[0124] Hereinafter, a layout example of the unit region 100 and the connection region 101 will be described.

[0125] Specifically, on the paper surface of Figure 4 , the unit region 100 is located in four parts, namely the upper left, upper right, lower left, and lower right. The expressions of upper left, upper right, lower left, and lower right are based on the paper surface of Figure 4 .

[0126] For convenience, the unit regions 100 located in the upper left, upper right, lower left, and lower right in the memory cell array 10 are respectively denoted as unit region (upper left) 100-FP, unit region (upper right) 100-GP, unit region (lower left) 100-FD, and unit region (lower right) 100-GD. Additionally, when not differentiating the four unit regions, it is simply denoted as unit region 100.

[0127] The unit region (upper left) 100-FP and the unit region (lower left) 100-FD can also share the bit line BL. Similarly, the unit region (upper right) 100-GP and the unit region (lower right) 100-GD can also share the bit line BL.

[0128] In addition, as Figure 4 shows, there are two connection regions 101. The first connection region 101 is provided between the unit region (upper left) 100-FP and the unit region (upper right) 100-GP to connect (short-circuit) the respective unit regions. The second connection region 101 is provided between the unit region (lower left) 100-FD and the unit region (lower right) 100-GD to connect (short-circuit) the respective unit regions.

[0129] For convenience, the connection region 101 provided between the unit region (upper left) 100-FP and the unit region (upper right) 100-GP is denoted as connection region (upper) 101-P. Additionally, the connection region 101 provided between the unit region (lower left) 100-FD and the unit region (lower right) 100-GD is denoted as connection region (lower) 101-D. Moreover, when not differentiating the two connection regions, it is simply denoted as connection region 101.

[0130] <1-2-2-2> Outline of the layout related to the lower layer LL

[0131] Next, using Figure 5 , an outline of the layout related to the lower layer LL of the memory cell array 10 will be described. Figure 5 Shows a layout example related to the lower layer LL of the memory cell array 10.

[0132] As Figure 5As shown, the lower layer LL generally includes a cell region 100 and a connection region 101. Hereinafter, when referring to the cell region 100 in the lower layer LL, it may sometimes be referred to as the cell region (lower). In addition, when referring to the connection region 101 in the lower layer LL, it may sometimes be referred to as the connection region (lower) 101.

[0133] Specifically, on the paper surface of Figure 5 , the cell region (lower) 100 is located at four positions, namely the upper left, upper right, lower left, and lower right. The so-called upper left, upper right, lower left, and lower right expressions when referring to the cell region (lower) 100 are expressions based on the paper surface of Figure 5 .

[0134] For convenience, the cell regions (lower) 100 located in the upper left, upper right, lower left, and lower right in the lower layer LL are respectively referred to as the cell region (lower & upper left) 100-LFP, the cell region (lower & upper right) 100-LGP, the cell region (lower & lower left) 100-LFD, and the cell region (lower & lower right) 100-LGD.

[0135] In addition, as Figure 5 shown, there are two connection regions (lower) 101. The first connection region (lower) 101 is provided between the cell region (lower & upper left) 100-LFP and the cell region (lower & upper right) 100-LGP to connect (short-circuit) the respective cell regions. The second connection region (lower) 101 is provided between the cell region (lower & lower left) 100-LFD and the cell region (lower & lower right) 100-LGD to connect (short-circuit) the respective cell regions.

[0136] For convenience, the connection region (lower) 101 provided between the cell region (lower & upper left) 100-LFP and the cell region (lower & upper right) 100-LGP is referred to as the connection region (lower & upper) 101-LP. In addition, the connection region (lower) 101 provided between the cell region (lower & lower left) 100-LFD and the cell region (lower & lower right) 100-LGD is referred to as the connection region (lower & lower) 101-LD.

[0137] <1-2-2-3> Summary of the layout related to the upper layer UL

[0138] Next, using Figure 6 , a summary of the layout related to the upper layer UL of the memory cell array 10 will be described. Figure 6 Shows a layout example related to the upper layer UL of the memory cell array 10.

[0139] As Figure 6As shown, the upper layer UL generally includes a cell region 100 and a connection region (upper) 101. Hereinafter, when referring to the cell region 100 in the upper layer UL, it may sometimes be referred to as the cell region (upper). In addition, when referring to the connection region 101 in the upper layer UL, it may sometimes be referred to as the connection region (upper) 101.

[0140] Specifically, on the Figure 6 paper surface, the cell region (upper) 100 is located at four positions, namely the upper left, upper right, lower left, and lower right. The expressions such as upper left, upper right, lower left, and lower right when referring to the cell region (upper) 100 are expressions based on the Figure 6 paper surface.

[0141] For convenience, the cell regions (upper) 100 located in the upper left, upper right, lower left, and lower right in the upper layer UL are respectively referred to as the cell region (upper & upper left) 100 - UFP, the cell region (upper & upper right) 100 - UGP, the cell region (upper & lower left) 100 - UFD, and the cell region (upper & lower right) 100 - UGD.

[0142] The cell region (upper & upper left) 100 - UFP and the cell region (upper & lower left) 100 - UFD can also share the bit line BL. Similarly, the cell region (upper & upper right) 100 - UGP and the cell region (upper & lower right) 100 - UGD can also share the bit line BL.

[0143] In addition, as Figure 6 shown, there are two connection regions (upper) 101. The first connection region (upper) 101 is provided between the cell region (upper & upper left) 100 - UFP and the cell region (upper & upper right) 100 - UGP to connect (short - circuit) the respective cell regions. The second connection region (upper) 101 is provided between the cell region (upper & lower left) 100 - UFD and the cell region (upper & lower right) 100 - UGD to connect (short - circuit) the respective cell regions.

[0144] For convenience, the connection region (upper) 101 provided between the cell region (upper & upper left) 100 - UFP and the cell region (upper & upper right) 100 - UGP is referred to as the connection region (upper & upper) 101 - UP. In addition, the connection region (upper) 101 provided between the cell region (upper & lower left) 100 - UFD and the cell region (upper & lower right) 100 - UGD is referred to as the connection region (upper & lower) 101 - LD.

[0145] <1 - 2 - 2 - 4>Relationship between the lower layer LL and the upper layer UL

[0146] Here, as Figure 7 shown, the relationship between the lower layer LL and the upper layer UL will be described. Figure 7Illustrates the relationship between the lower layer LL and the upper layer UL.

[0147] As Figure 7 shown, in the Z direction, the unit area (upper & lower left) 100 - UFD is set above the unit area (lower & lower left) 100 - LFD, and the respective unit areas are connected. The unit area (lower & lower left) 100 - LFD and the unit area (upper & lower left) 100 - UFD form the unit area (lower left) 100 - FD.

[0148] In addition, in the Z direction, the unit area (upper & lower right) 100 - UGD is set above the unit area (lower & lower right) 100 - LGD, and the respective unit areas are connected. The unit area (lower & lower right) 100 - LGD and the unit area (upper & lower right) 100 - UGD form the unit area (lower right) 100 - GD.

[0149] In addition, in the Z direction, the connection area (upper & lower) 101 - UD is located above the connection area (lower & lower) 101 - LD. The connection area (lower & lower) 101 - LD and the connection area (upper & lower) 101 - UD form the connection area (lower) 101 - D.

[0150] Furthermore, in the Z direction, the unit area (upper & upper left) 100 - UFP is set above the unit area (lower & upper left) 100 - LFP, and the respective unit areas are connected. The unit area (lower & upper left) 100 - LFP and the unit area (upper & upper left) 100 - UFP form the unit area (upper left) 100 - FP.

[0151] In addition, in the Z direction, the unit area (upper & upper right) 100 - UGP is set above the unit area (lower & upper right) 100 - LGP, and the respective unit areas are connected. The unit area (lower & upper right) 100 - LGP and the unit area (upper & upper right) 100 - UGP form the unit area (upper right) 100 - GP.

[0152] In addition, in the Z direction, the connection area (upper & upper) 101 - UP is located above the connection area (lower & upper) 101 - LP. The connection area (lower & upper) 101 - LP and the connection area (upper & upper) 101 - UP form the connection area (upper) 101 - P.

[0153] As described above, the connection area (upper) 101 is located above the connection area (lower) 101. This means that the connection area 101 is located at the center of the memory cell array 10 in the X direction.

[0154] <1 - 2 - 2 - 5> Summary of the unit area (lower) and the connection area (lower)

[0155] Next, useFigure 8 , the general layout of the connection region (lower) 101 and the unit region (lower) 100 separated by the connection region (lower) 101 will be described. Figure 8 A layout example of the connection region (lower) 101 and the unit region (lower) 100 separated by the connection region (lower) 101 is shown.

[0156] In Figure 8 , a part of the unit region (lower & upper left) 100-LFP, the unit region (lower & upper right) 100-LGP, and the lower connection region (lower & upper) 101-LP is specifically shown.

[0157] As Figure 8 shown, the unit region (lower & upper left) 100-LFP and the unit region (lower & upper right) 100-LGP each contain a plurality of blocks BLK. Moreover, in the Y direction, the plurality of blocks BLK are respectively divided by slits SLT extending in the X direction.

[0158] For convenience, for the block BLK(v) (v: any integer) belonging to the unit region (lower & upper left) 100-LFP, it is denoted as the block (lower & upper left) BLK(v)-LFP. In addition, for the block BLK(v) belonging to the unit region (lower & upper right) 100-LGP, it is denoted as the block (lower & upper right) BLK(v)-LGP.

[0159] In addition, as Figure 8 shown, the connection region (lower & upper) 101-LP has a set of a stepped region (lower) SSA-L and a sub-channel region (lower) SBA-L for each block.

[0160] In the stepped region (lower) SSA-L, the ends of the select gate line SGS and the word lines WL(0) to WL(7) are set in a stepped shape that forms a step difference in the X direction in sequence. In other words, in the stepped region (lower) SSA-L, the select gate line SGS and the word lines WL(0) to WL(7) each have a stepped portion (in addition, it is also denoted as a step, a stepped portion, an extraction portion, a step, or a stepped part) that does not overlap with the lower wiring layer (conductor layer) at the end. Contact plugs CC (not shown) are formed on each stepped portion. Such a stepped region can also be denoted as an extraction region.

[0161] The sub-channel region (lower) SBA-L is roughly divided into two functions.

[0162] The first is the function of connecting the stepped region (lower) SSA-L to the row decoder module 15. Specifically, in the sub-channel region (lower) SBA-L, a contact plug C4 (not shown) is formed to connect the row decoder module 15 formed below the connection region (lower) 101 in the Z direction to the contact plug CC. However, this contact plug C4 penetrates through the sub-channel region (upper) SBA-U provided on the sub-channel region (lower) SBA-L in the Z direction and is exposed on the sub-channel region (upper) SBA-U. Therefore, in order to connect this contact plug C4 to the contact plug CC, the contact plug CC must be connected to the contact plug C4 exposed on the sub-channel region (upper) SBA-U provided on the sub-channel region (lower) SBA-L. The contact plugs CC and C4 contain a conductive material, and for example, a metal material such as tungsten (W) or titanium nitride (TiN) can also be used.

[0163] The second is the function of connecting the blocks BLK adjacent in the X direction. Specifically, the block (lower & upper left) BLK(n - 1)-LFP of the unit region (lower & upper left) 100-LFP and the block (lower & upper right) BLK(n - 1)-LGP of the unit region (lower & upper right) 100-LGP are connected through the stepped region (lower) SSA-L and the sub-channel region (lower) SBA-L provided between the respective unit regions. Thereby, the block (lower & upper left) BLK(n - 1)-LFP of the unit region (lower & upper left) 100-LFP and the block (lower & upper right) BLK(n - 1)-LGP of the unit region (lower & upper right) 100-LGP can be controlled simultaneously respectively.

[0164] In Figure 8 the unit region (lower & upper left) 100-LFP, the unit region (lower & upper right) 100-LGP, and the connection region (lower & upper) 101-LP are specifically described, and the same applies to the unit region (lower & lower left) 100-LFD, the unit region (lower & lower right) 100-LGD, and the connection region (lower & lower) 101-LD.

[0165] <1-2-2-6>Connection region in the lower layer

[0166] Next, Figure 9 and Figure 10 are used to describe the connection region (lower) 101 in the lower layer LL. In Figure 9 and Figure 10 the block (lower & upper left) BLK(n)-LFP, the block (lower & upper right) BLK(n)-LGP, and the stepped region (lower) SSA-L and the sub-channel region (lower) SBA-L related to the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP are shown.

[0167] For convenience, the stepped area (lower) SSA-L in the first lower layer LL1 is denoted as the stepped area (first lower) SSA-L1. Similarly, the sub-channel area (lower) SBA-L in the first lower layer LL1 is denoted as the sub-channel area (first lower) SBA-L1.

[0168] In addition, for convenience, the stepped area (lower) SSA-L in the second lower layer LL2 is denoted as the stepped area (second lower) SSA-L2. Similarly, the sub-channel area (lower) SBA-L in the second lower layer LL2 is denoted as the sub-channel area (second lower) SBA-L2.

[0169] As Figure 9 shown, in the first lower layer LL1, the stepped area (first lower) SSA-L1 includes a lower bridging area LBBA and a lower sub-channel connection area LBCA.

[0170] The lower bridging area LBBA is provided with wirings that connect (or are also denoted as short-circuited) the select gate lines SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP.

[0171] The sub-channel area (first lower) SBA-L1 connects the select gate lines SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP via the lower bridging area LBBA.

[0172] The lower sub-channel connection area LBCA includes, for example, stepped portions related to the select gate line SGS and word lines WL(0) to WL(4), and contact plugs CC (not shown) are provided in each stepped portion.

[0173] As Figure 10 shown, the second lower layer LL2 does not include the lower bridging area LBBA.

[0174] In the second lower layer LL2, the stepped area (second lower) SSA-L2 includes a first lower connectable area LCA1 and a second lower connectable area LCA2.

[0175] The first lower connectable area LCA1 includes, for example, stepped portions related to the word lines WL(5) to WL(7) of the block (lower & upper left) BLK(n)-LFP, and contact plugs CC (not shown) are provided in each stepped portion.

[0176] The second lower connectable region LCA2 has, for example, a stepped portion related to word lines WL(5) to WL(7) of the block (lower & upper right) BLK(n)-LGP. Further, contact plugs CB are provided respectively in the stepped portions of the first lower connectable region LCA1 and the second lower connectable region LCA2. Further, on the contact plugs CB, wirings LCL are provided which connect the word lines WL(5) to WL(7) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP respectively.

[0177] <1-2-2-7> Outline of unit region (upper) and connection region (upper)

[0178] Next, a general layout of the connection region (upper) 101 and the unit region (upper) 100 separated by the connection region (upper) 101 will be described.

[0179] In Figure 11 a part of the unit region (upper & upper left) 100-UFP, the unit region (upper & upper right) 100-UGP, and the connection region (upper & upper) 101-UP are specifically shown.

[0180] As Figure 11 shown, the unit region (upper & upper left) 100-UFP and the unit region (upper & upper right) 100-UGP each contain a plurality of blocks BLK. Further, in the Y direction, the plurality of blocks BLK are each divided by a slit SLT extending in the X direction.

[0181] In addition, for convenience, the block BLK(v) belonging to the unit region (upper & upper left) 100-UFP is denoted as the block (upper & upper left) BLK(v)-UFP. The block BLK(v) belonging to the unit region (upper & upper right) 100-UGP is denoted as the block (upper & upper right) BLK(v)-UGP.

[0182] In addition, as Figure 11 shown, the connection region (upper & upper) 101-UP has a set of a stepped region (upper) SSA-U and a sub-channel region (upper) SBA-U for each block.

[0183] In the stepped region (upper) SSA-U, the ends of the word lines WL(8) to WL(15) and the select gate line SGD are each set in a stepped shape having a step difference successively formed in the X direction. In other words, in the stepped region (upper) SSA-U, the word lines WL(8) to WL(15) and the select gate line SGD each have a stepped portion at the end that does not overlap with the lower wiring layer (conductor layer). Contact plugs CC (not shown) are formed on each stepped portion.

[0184] The sub-channel region (upper) SBA-U generally has two functions. The first is the function of connecting the stepped region (upper) SSA-U to the row decoder module 15. Specifically, in the sub-channel region (upper) SBA-U, a contact plug C4 (not shown) is formed to connect the row decoder module 15 formed below the Z direction in the connection region (lower) 101 to the contact plug CC. The upper ends of the contact plug CC and the contact plug C4 are connected through a wiring layer. The contact plugs CC and C4 contain a conductive material, and for example, a metal material such as tungsten (W) or titanium nitride (TiN) can also be used. The second is the function of connecting the blocks BLK adjacent in the X direction.

[0185] Specifically, the block BLK(n-1)-UFP in the cell region (upper & upper left) 100-UFP and the block BLK(n-1)-UGP in the cell region (upper & upper right) 100-UGP are connected through the stepped region (upper) SSA-U and the sub-channel region (upper) SBA-U provided between the respective cell regions. Thus, the block BLK(n-1)-UFP in the cell region (upper & upper left) 100-UFP and the block BLK(n-1)-UGP in the cell region (upper & upper right) 100-UGP can be controlled simultaneously respectively.

[0186] In addition, Figure 8 and Figure 11 the shown block BLK is located at the same coordinates in the plane including the X direction and the Y direction. That is, Figure 11 the shown block BLK(n-1) is located Figure 8 above the shown block BLK(n-1) in the Z direction. The same applies to other blocks BLK.

[0187] In addition, Figure 8 the shown stepped region (lower) SSA-L and Figure 11 the shown stepped region (upper) SSA-U are located at the same coordinates in the plane including the X direction and the Y direction. That is, Figure 11 the shown stepped region (upper) SSA-U is located Figure 8 above the shown stepped region (lower) SSA-L in the Z direction. The same applies to other stepped regions (lower) SSA-L and stepped regions (upper) SSA-U. Sometimes, for simplicity, the stepped region (lower) SSA-L and the stepped region (upper) SSA-U are collectively referred to as the stepped region SSA.

[0188] In addition, Figure 8 the shown sub-channel region (lower) SBA-L and Figure 11 the shown sub-channel region (upper) SBA-U are located at the same coordinates in the plane including the X direction and the Y direction. That is, Figure 11The secondary channel region (upper) SBA-U shown is located Figure 8 above the secondary channel region (lower) SBA-L in the Z direction. The same applies to the other secondary channel regions (lower) SBA-L and the secondary channel region (upper) SBA-U. Sometimes, for simplicity, the secondary channel region (lower) SBA-L and the secondary channel region (upper) SBA-U are collectively referred to as the secondary channel region SBA.

[0189] In Figure 11 specifically, the unit region (upper & upper left) 100-UFP, the unit region (upper & upper right) 100-UGP, and the connection region (upper & upper) 101-UP are described. The same applies to the unit region (upper & lower left) 100-UFD, the unit region (upper & lower right) 100-UGD, and the connection region (upper & lower) 101-UD.

[0190] <1-2-2-8>The connection region in the upper layer

[0191] Next, use Figure 12 and Figure 13 to describe the connection region (upper) 101. In Figure 12 and Figure 13 the block (upper & upper left) BLK(n)-UFP, the block (upper & upper right) BLK(n)-UGP, the stepped region (upper) SSA-U related to the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP, and the secondary channel region (upper) SBA-U are shown.

[0192] For convenience, the stepped region (upper) SSA-U in the first upper layer UL1 is denoted as the stepped region (first upper) SSA-U1. Similarly, the secondary channel region (upper) SBA-U in the first upper layer UL1 is denoted as the secondary channel region (first upper) SBA-U1.

[0193] In addition, for convenience, the stepped region (upper) SSA-U in the second upper layer UL2 is denoted as the stepped region (second upper) SSA-U2. Similarly, the secondary channel region (upper) SBA-U in the second upper layer UL2 is denoted as the secondary channel region (second upper) SBA-U2.

[0194] As Figure 12 shown, in the first upper layer UL1, the stepped region (first upper) SSA-U1 includes the upper bridging region UBBA and the upper secondary channel connection region UBCA.

[0195] The upper bridging region UBBA is provided with wirings connecting the word lines WL(8) to WL(12) in the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP.

[0196] The sub-channel region (upper 1st), SBA-U1, connects the word lines WL(8) to WL(12) in the block (upper & upper left), BLK(n)-UFP and the block (upper & upper right), BLK(n)-UGP via the upper bridging region, UBBA.

[0197] The upper sub-channel connection region, UBCA, has, for example, stepped portions related to the word lines WL(8) to WL(12), and contact plugs CC (not shown) are provided in each stepped portion.

[0198] As Figure 13 shown, the second upper layer, UL2, does not include the upper bridging region, UBBA.

[0199] In the second upper layer, UL2, the stepped region (upper 2nd), SSA-U2, includes the first upper connectable region, UCA1, and the second upper connectable region, UCA2.

[0200] The first upper connectable region, UCA1, has, for example, stepped portions related to the word lines WL(13) to WL(15) of the block (upper & upper left), BLK(n)-UFP and the select gate line, SGD, and contact plugs CC (not shown) are provided in each stepped portion.

[0201] The second upper connectable region, UCA2, has, for example, stepped portions related to the word lines WL(13) to WL(15) of the block (upper & upper right), BLK(n)-UGP and the select gate line, SGD. Further, contact plugs CB are provided in the stepped portions of the first upper connectable region, UCA1, and the stepped portions of the second upper connectable region, UCA2, respectively. Further, wirings UCL that connect the word lines WL(13) to WL(15) and the select gate line, SGD, in the block (upper & upper left), BLK(n)-UFP and the block (upper & upper right), BLK(n)-UGP are provided on the above contact plugs CB.

[0202] <1-2-2-9>Connection relationships in the lower layer

[0203] As described above, in the first lower layer, LL1, and the second lower layer, LL2, the connection methods of the block (lower & lower left), BLK(n)-LFP and the block (lower & lower right), BLK(n)-LGP are different. Therefore, the connection methods of the block (lower & lower left), BLK(n)-LFP and the block (lower & lower right), BLK(n)-LGP, the connection method of the block (lower & lower left), BLK(n)-LFP and the row decoder, RD, of the row decoder module 15, and the connection method of the block (lower & lower right), BLK(n)-LGP and the row decoder, RD, of the row decoder module 15 in the first lower layer, LL1, and the second lower layer, LL2 are schematically described.

[0204] Figure 14 It is a block diagram showing the connection of each component in the first lower layer LL1. As Figure 14 shown, in the first lower layer LL1, the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP are connected via the lower bridging area LBBA and the sub-channel area (lower) SBA-L.

[0205] In addition, the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP are connected to the row decoder RD related to the block BLK(n) via the lower sub-channel connection area LBCA, the first contact wiring CL1 connecting the lower sub-channel connection area LBCA and the contact plug C4, and the contact plug C4. Hereinafter, the row decoder RD related to the block BLK(v) is denoted as RD(BLK(v)).

[0206] In addition, the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper right) BLK(n)-LGP are connected to the row decoder RD(BLK(n)) related to the block BLK(n) via the sub-channel area (lower) SBA-L, the lower bridging area LBBA, the lower sub-channel connection area LBCA, the first contact wiring CL1, and the contact plug C4.

[0207] Figure 15 It is a block diagram showing the connection of each component in the second lower layer LL2. Next, as Figure 15 shown, in the second lower layer LL2, the word lines WL(5) to WL(7) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP are connected via the first lower connectable area LCA1, the lower connection wiring LCL connecting the first lower connectable area LCA1 and the second lower connectable area LCA2, and the second lower connectable area LCA2.

[0208] In addition, the word lines WL(5) to WL(7) in the block (lower & upper left) BLK(n)-LFP are connected to the row decoder RD(BLK(n)) related to the block BLK(n) via the first lower connectable area LCA1, the second contact wiring CL2 connecting the first lower connectable area LCA1 and the contact plug C4, and the contact plug C4.

[0209] In addition, word lines WL(5) to WL(7) in block (lower & upper right) BLK(n)-LGP are connected to row decoder RD(BLK(n)) related to block BLK(n) via sub-channel region (lower) SBA-L, second lower connectable region LCA2, lower connection wiring LCL, first lower connectable region LCA1, second contact wiring CL2, and contact plug C4.

[0210] <1-2-2-10>Connection relationship in the upper layer

[0211] As described above, in the first upper layer UL1 and the second upper layer UL2, the connection methods of block (upper & upper left) BLK(n)-UFP and block (upper & upper right) BLK(n)-UGP are different. Therefore, the connections of each component in the first upper layer UL1 and the second upper layer UL2 are schematically described.

[0212] Figure 16 It is a block diagram showing the connections of each component in the first upper layer UL1. As Figure 16 shown, in the first upper layer UL1, word lines WL(8) to WL(12) in block (upper & upper left) BLK(n)-UFP and block (upper & upper right) BLK(n)-UGP are connected via upper bridging region UBBA and sub-channel region (upper) SBA-U.

[0213] In addition, word lines WL(8) to WL(12) in block (upper & upper left) BLK(n)-UFP are connected to row decoder RD(BLK(n)) related to block BLK(n) via upper sub-channel connection region UBCA, third contact wiring CL3 connecting upper sub-channel connection region UBCA and contact plug C4, and contact plug C4.

[0214] In addition, word lines WL(8) to WL(12) in block (upper & upper right) BLK(n)-UGP are connected to row decoder RD(BLK(n)) related to block BLK(n) via sub-channel region (upper) SBA-U, upper bridging region UBBA, upper sub-channel connection region UBCA, third contact wiring CL3, and contact plug C4.

[0215] Figure 17 It is a block diagram showing the connections of each component in the second upper layer UL2. Next, as Figure 17As shown, in the second upper layer UL2, the word lines WL(13) to WL(15) and the select gate line SGD in the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP are connected via the first upper connectable region UCA1, the upper connection wiring UCL connecting the first upper connectable region UCA1 and the second upper connectable region UCA2, and the second upper connectable region UCA2.

[0216] In addition, the word lines WL(13) to WL(15) and the select gate line SGD in the block (upper & upper left) BLK(n)-UFP are connected to the row decoder RD(BLK(n)) related to the block BLK(n) via the first upper connectable region UCA1, the fourth contact wiring CL4 connecting the first upper connectable region UCA1 and the contact plug C4, and the contact plug C4.

[0217] In addition, the word lines WL(13) to WL(15) and the select gate line SGD in the block (upper & upper right) BLK(n)-UGP are connected to the row decoder RD(BLK(n)) related to the block BLK(n) via the sub-channel region (upper) SBA-U, the second upper connectable region UCA2, the upper connection wiring UCL, the first upper connectable region UCA1, the fourth contact wiring CL4, and the contact plug C4.

[0218] In addition, without distinguishing the first contact wiring CL1, the second contact wiring CL2, the third contact wiring CL3, and the fourth contact wiring CL4, they are simply recorded as the contact wiring CL.

[0219] <1-2-2-11>The relationship between the connection region (lower) and the connection region (upper)

[0220] Here, use Figure 18 , to illustrate the relationship between the connection region (lower) 101 and the connection region (upper) 101. In Figure 18 , the block (lower & upper left) BLK(n)-UFP, the block (lower & upper right) BLK(n)-UGP, the stepped region (lower) SSA-L and the sub-channel region (lower) SBA-L related to the block (lower & upper left) BLK(n)-UFP and the block (lower & upper right) BLK(n)-UGP, and the block (upper & upper left) BLK(n)-UFP, the block (upper & upper right) BLK(n)-UGP, the stepped region (upper) SSA-U and the sub-channel region (upper) SBA-U related to the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP are shown.

[0221] As Figure 18As shown, the lower sub-channel connection area LBCA of the first lower layer LL1 includes areas LBCA1 and LBCA2. Area LBCA1 is covered by the first lower connectable area LCA1 in the Z direction. On the other hand, area LBCA2 is not covered by the first lower connectable area LCA1 in the Z direction. Therefore, a step for setting a contact plug CC (not shown) is formed in area LBCA2.

[0222] The first lower connectable area LCA1 of the second lower layer LL2 includes areas LCA11 and LCA12. Area LCA11 is covered by the upper sub-channel connection area UBCA in the Z direction. On the other hand, area LCA12 is not covered by the upper sub-channel connection area UBCA in the Z direction. Therefore, a step for setting a contact plug CC is formed in area LCA12.

[0223] The second lower connectable area LCA2 of the second lower layer LL2 includes areas LCA21 and LCA22. Area LCA21 is covered by the second upper connectable area UCA2 in the Z direction. On the other hand, area LCA22 is not covered by the second upper connectable area UCA2 in the Z direction. Therefore, a step for setting a contact plug CC is formed in area LCA22.

[0224] In addition, the upper sub-channel connection area UBCA of the first upper layer UL1 includes areas UBCA1 and UBCA2. Area UBCA1 is covered by the first upper connectable area UCA1 in the Z direction. On the other hand, area UBCA2 is not covered by the first upper connectable area UCA1 in the Z direction. Therefore, a step for setting a contact plug CC is formed in area UBCA2.

[0225] In this way, a part of the upper sub-channel connection area UBCA has the first upper connectable area UCA1 set above it in the Z direction, and the first upper connectable area UCA1 is not set above other parts. Therefore, wiring can be connected from the upper sub-channel connection area UBCA to the sub-channel area.

[0226] In addition, a part of the first lower connectable area LCA1 has the upper sub-channel connection area UBCA set above it in the Z direction, and the upper sub-channel connection area UBCA is not set above other parts. Therefore, wiring can be connected from the first lower connectable area LCA1 to the sub-channel area.

[0227] In addition, a part of the lower sub-channel connection area LBCA has the first lower connectable area LCA1 set above it in the Z direction, and the first lower connectable area LCA1 is not set above other parts. Therefore, wiring can be connected from the lower sub-channel connection area LBCA to the sub-channel area.

[0228] In addition, a second upper connectable region UCA2 is provided above a part of the second lower connectable region LCA2 in the Z direction, and the second upper connectable region UCA2 is not provided above other parts. Therefore, wiring can be connected from the second lower connectable region LCA2 to the sub-channel region.

[0229] <1-2-3>Layout of the Circuit Region

[0230] <1-2-3-1>Overview

[0231] Usage Figure 19 , the layout of the plane including the X direction and the Y direction of the circuit region CTA will be described.

[0232] As Figure 19 shown, in the circuit region CTA, the sense amplifier module 16 is divided into four.

[0233] Specifically, on the paper surface of Figure 19 , the sense amplifier module 16 is located at four positions: upper left, upper right, lower left, and lower right. The expressions of upper left, upper right, lower left, and lower right are based on the paper surface of Figure 19 .

[0234] For convenience, the sense amplifier modules 16 located in the upper left, upper right, lower left, and lower right in the circuit region CTA are respectively denoted as sense amplifier module (upper left) 16-FP, sense amplifier module (upper right) 16-GP, sense amplifier module (lower left) 16-FD, and sense amplifier module (lower right) 16-GD. In addition, when not distinguishing the four sense amplifier modules, it is simply denoted as sense amplifier module 16.

[0235] In addition, as Figure 19 shown, in the Z direction, the sense amplifier module (upper left) 16-FP is provided below the cell region (upper & upper left) 100-UFP and the cell region (lower & upper left) 100-LFP. Moreover, the sense amplifier module (upper left) 16-FP is connected to the bit line BL associated with the cell region (upper & upper left) 100-UFP and the cell region (lower & upper left) 100-LFP via the second peripheral circuit (upper left) 18-FP provided on one side of the sense amplifier module (upper left) 16-FP.

[0236] In addition, as Figure 19As shown, in the Z direction, the sense amplifier module (upper right) 16-GP is disposed below the cell regions (upper & upper right) 100-UGP and (lower & upper right) 100-LGP. Moreover, the sense amplifier module (upper right) 16-GP is connected to the bit lines BL associated with the cell regions (upper & upper right) 100-UGP and (lower & upper right) 100-LGP via the second peripheral circuit (upper right) 18-GP disposed on one side of the sense amplifier module (upper right) 16-GP.

[0237] In addition, as Figure 19 shown, in the Z direction, the sense amplifier module (lower left) 16-FD is disposed below the cell regions (upper & lower left) 100-UFD and (lower & lower left) 100-LFD. Moreover, the sense amplifier module (lower left) 16-FD is connected to the bit lines BL associated with the cell regions (upper & lower left) 100-UFD and (lower & lower left) 100-LFD via the second peripheral circuit (lower left) 18-FD disposed on one side of the sense amplifier module (lower left) 16-FD.

[0238] In addition, as Figure 19 shown, in the Z direction, the sense amplifier module (lower right) 16-GD is disposed below the cell regions (upper & lower right) 100-UGD and (lower & lower right) 100-LGD. Moreover, the sense amplifier module (lower right) 16-GD is connected to the bit lines BL associated with the cell regions (upper & lower right) 10-UGD and (lower & lower right) 100-LGD via the second peripheral circuit (upper right) 18-GD disposed on one side of the sense amplifier module (lower right) 16-GD.

[0239] As Figure 19 shown, the row decoder module (upper) 15-P is sandwiched between the sense amplifier module (upper left) 16-FP and the sense amplifier module (upper right) 16-GP in the X direction. In addition, the row decoder module (lower) 15-D is sandwiched between the sense amplifier module (lower left) 16-FD and the sense amplifier module (lower right) 16-GD in the X direction.

[0240] In addition, as Figure 19 shown, the first peripheral circuit 17 is disposed on one side of the circuit area CTA.

[0241] The first peripheral circuit 17 and the second peripheral circuit 18 suitably include a command register 11, an address register 12, a sequencer 13, and a driver module 14.

[0242] <1-2-3-2>Relationship between row decoder and block

[0243] Next, useFigure 20 , the relationship between the row decoder and the block is described.

[0244] In Figure 20 , a part of the row decoder module 15 and a part of the sense amplifier module 16 in the circuit area CTA are shown. In particular, in Figure 20 , a part of the sense amplifier module (upper left) 16-FP, the sense amplifier module (upper right) 16-GP, and the row decoder module (upper) 15-P are shown.

[0245] As Figure 20 shown, the row decoder module 15 has a row decoder RD for each block BLK. As Figure 20 shown, two row decoders RD are arranged along the X direction, and a plurality of row decoders RD are arranged along the Y direction.

[0246] <1-2-3-3> Relationship between the row decoder module and the connection area in the memory cell array

[0247] Next, using Figure 21 , the relationship between the row decoder module 15 in the circuit area CTA and the connection area 101 in the memory cell array 10 is described.

[0248] In Figure 21 , the same content as Figure 20 is shown for the circuit area CTA. In addition, in Figure 21 , for the memory cell array 10, for simplicity, the lower layer LL and the upper layer UL are shown without distinction.

[0249] As Figure 21 shown, the connection area 101 is arranged above the row decoder module 15 in the Z direction. More specifically, a step area and a sub-channel area related to the block BLK(n-1) are arranged above the row decoder RD(BLK(n-1)) related to the block BLK(n-1) in the Z direction. The row decoder RD(BLK(n-1)) related to the block BLK(n-1) is connected to the block BLK(n-1) of the memory cell array 10 via the step area and the sub-channel area related to the block BLK(n-1).

[0250] The other row decoder modules 15, as well as the step area and the sub-channel area, are also arranged corresponding to the block BLK of the memory cell array 10.

[0251] <1-2-4> Detailed structure of the memory cell array

[0252] <1-2-4-1> Planar layout of the memory cell array

[0253] Using Figure 22, an example of the planar layout of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment will be described.

[0254] Figure 22 This is an example of the planar layout of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment, and a region corresponding to two blocks BLK (i.e., string components SU0 to SU3) is selectively shown.

[0255] As Figure 22 shown, in the planar layout of the memory cell array 10, for example, two cell regions 100 are connected via a connection region 101 in the X direction. In addition, the memory cell array 10 includes a plurality of slits SLT ( Figure 22 SLT0 to SLT2 in this case), and a plurality of slits SHE (SHE0 and SHE1).

[0256] The plurality of slits SLT are respectively arranged along the X direction and arranged in the Y direction. The slits SLT cross the cell region 100 and the connection region 101 in the X direction.

[0257] For example, one slit SHE is located between each adjacent slit SLTj. The slit SHE is arranged along the X direction and crosses the cell region 100 in the X direction.

[0258] Specifically, the slit SLT, for example, divides a plurality of wiring layers corresponding to the word lines WL(0) to WL(15), the selection gate line SGD, and the selection gate line SGS. The slit SHE divides the wiring layer corresponding to the selection gate line SGD.

[0259] The slit SLT and the slit SHE each have a structure in which an insulating member is buried inside the groove.

[0260] In the planar layout of the memory cell array 10 described above, the regions separated by the slits SLT and SHE in the cell region 100 respectively correspond to one string component SU. That is, in this example, the string components SU0 to SU3 extending in the X direction are arranged in the Y direction.

[0261] Specifically, a plurality of NAND strings NS in the region disposed between the slit SLT0 and the slit SHE0 in the Y direction are defined as the string component SU0. Further, a plurality of NAND strings NS in the region disposed between the slit SHE0 and the slit SLT1 in the Y direction are defined as the string component SU1. Moreover, the string components SU0 and SU1 in the region disposed between the slit SLT0 and the slit SLT1 are described as the block BLK, for example. Similarly, a plurality of NAND strings NS in the region disposed between the slit SLT1 and the slit SHE1 in the Y direction are defined as the string component SU2. Further, a plurality of NAND strings NS in the region disposed between the slit SHE1 and the slit SLT2 in the Y direction are defined as the string component SU3. Moreover, the string components SU2 and SU3 in the region disposed between the slit SLT1 and the slit SLT2 are described as the block BLK.

[0262] In addition, in the planar layout of the memory cell array 10 described above, the number of slits SHE located adjacent to the slit SLTj can be designed to be any number. The number of string components SU of two adjacent slits SLTj varies based on the number of slits SHE located between the two adjacent slits SLT.

[0263] Structure of the memory cell array 10 in the unit region CA of the <1-2-4-2> cell

[0264] Next, a detailed planar layout of the memory cell array 10 in the unit region 100 of the semiconductor memory device 1 according to the first embodiment will be described.

[0265] Figure 23 FIG. is an example of a detailed planar layout of the memory cell array 10 in the unit region 100 of the semiconductor memory device 1 according to the first embodiment, and an area corresponding to the string components SU0 and SU1 ( Figure 22 is shown as A).

[0266] As Figure 23 shown, in the unit region 100, the memory cell array 10 further includes a plurality of memory pillars MP, a plurality of contact plugs CP, and a plurality of bit lines BL.

[0267] Each of the memory pillars MP functions as, for example, one NAND string NS.

[0268] The plurality of memory pillars MP are arranged along a plurality of "columns" and "rows".

[0269] The "columns" in which the plurality of memory pillars MP are arranged extend in the Y direction and generally include even columns Ce and odd columns Co. The even columns Ce and the odd columns Co are alternately arranged in the X direction along the X direction.

[0270] For example, as Figure 23As shown, in the slits SLTj in the string components SU0 and SU1, four memory pillars MP are provided in the even columns Ce, and five memory pillars MP are provided in the odd columns Co. Additionally, the number of these memory pillars MP is not limited to this.

[0271] The "rows" in which a plurality of memory pillars MP are arranged extend in the X direction, and multiple rows (for example, nine rows in this example) are provided in the Y direction between the slits SLT.

[0272] In each row, a memory pillar MP is provided corresponding to either the even column Ce or the odd column Co.

[0273] Additionally, a plurality of memory pillars MP provided in adjacent even columns Ce and odd columns Co can be described as being arranged in a staggered configuration in the Y direction.

[0274] Furthermore, the memory pillar MP located at the position overlapping with the slit SHE does not function as a NAND string NS but is treated as a dummy NAND string NS.

[0275] Multiple bit lines BL extend in the Y direction and are arranged in the X direction. Each bit line BL is provided so as to overlap with at least one memory pillar MP in each string component SU. In this example, two bit lines BL are provided to overlap with each memory pillar MP. A contact plug CP is provided between one of the multiple bit lines BL overlapping with the memory pillar MP and the memory pillar MP. Each memory pillar MP is electrically connected to the corresponding bit line BL via the contact plug CP.

[0276] Additionally, as described above, the memory pillar MP overlapping with the slit SHE is a dummy. Therefore, the contact plug CP between the memory pillar MP overlapping with the slit SHE and the bit line BL is omitted. The number and layout of the memory pillars MP or slits SHE, etc. between adjacent slits SLT are not limited to the configuration described Figure 23 and can be changed appropriately.

[0277] <1-2-4-3>Cross-sectional structure in the cell region of the memory cell array

[0278] Next, an example of the cross-sectional structure in the cell region 100 of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment will be described using Figure 24 .

[0279] Figure 24 is a cross-sectional view along the Figure 23 C-C line, showing an example of the cross-sectional structure in the cell region 100 of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment. As Figure 24As shown, the memory cell array 10 further includes conductor layers 21 to 25. The conductor layers 21 to 25 are disposed above the semiconductor substrate 20.

[0280] Specifically, above the semiconductor substrate 20, the insulator layer 40 is interposed to dispose the conductor layer 21. Circuits corresponding to, for example, the row decoder module 15 or the sense amplifier module 16 may also be disposed in the insulator layer 40 between the semiconductor substrate 20 and the conductor layer 21. The conductor layer 21 is formed, for example, in a plate shape extending along the XY plane and is used as the source line SL. The conductor layer 21 contains, for example, silicon (Si).

[0281] Above the conductor layer 21, the insulator layer 41 is interposed to dispose the conductor layer 22. The conductor layer 22 is formed, for example, in a plate shape extending along the XY plane and is used as the select gate line SGS. The conductor layer 22 contains, for example, silicon.

[0282] Above the conductor layer 22, the insulator layer 42 and the conductor layer 23 are alternately stacked. The conductor layer 23 is formed, for example, in a plate shape extending along the XY plane. For example, the stacked plurality of conductor layers 23 respectively correspond to the word lines WL(0) to WL(15) in order from the semiconductor substrate 20 side. The conductor layer 23 contains, for example, tungsten (W).

[0283] Above the uppermost conductor layer 23, the insulator layer 42 is interposed to stack the conductor layer 24. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane. For example, the conductor layer 24 corresponds to the select gate line SGD. The conductor layer 24 contains, for example, tungsten.

[0284] Above the uppermost conductor layer 24, the conductor layer 25 is disposed with the insulator layer 43 interposed therebetween. The conductor layer 25 is formed, for example, in a linear shape extending along the Y direction and is used as the bit line BL. The conductor layer 25 contains, for example, copper (Cu).

[0285] In addition, the plurality of conductor layers 23 may also be described as a stacked body.

[0286] The memory posts MP are respectively disposed to extend along the Z direction and penetrate the conductor layers 22 to 24. The memory posts MP are respectively formed inside the memory holes MH.

[0287] The memory holes MH penetrate the conductor layers 22 to 24 and the bottom thereof is in contact with the conductor layer 21.

[0288] In addition, the memory posts MP respectively contain, for example, the core member 30, the semiconductor layer 31, and the stacked film 32.

[0289] Specifically, the core member 30 is provided to extend along the Z direction. For example, the upper end of the core member 30 is included in a layer above the uppermost conductive layer 24, and the lower end of the core member 30 is included in the layer where the conductive layer 21 is provided. The semiconductor layer 31 has, for example, a portion covering the side surface and the bottom surface of the core member 30, and a columnar portion extending in the Z direction at the bottom of the core member 30. For example, the bottom of the columnar portion of the semiconductor layer 31 is included in the layer where the conductive layer 21 is provided. The laminated film 32 covers the side surface and the bottom surface of the semiconductor layer 31 except for the portion where the columnar portion of the semiconductor layer 31 is provided. For example, the bottom of the columnar portion of the laminated film 32 is included in the layer where the conductive layer 21 is provided. The core member 30 includes, for example, an insulator such as silicon dioxide (SiO2). The semiconductor layer 31 includes, for example, silicon.

[0290] Columnar contact plugs CP are provided on the upper surface of the semiconductor layer 31 in the memory pillar MP. In the illustrated region, the contact plugs CP corresponding to two of the five memory pillars MP are shown. For the memory pillars MP in this region that do not overlap with the slit SHE and are not connected to the contact plugs CP, the contact plugs CP are connected in a region not shown.

[0291] One conductive layer 25, that is, one bit line BL, contacts the upper surface of the contact plug CP. In each of the spaces (string components) separated by the slits SLT and SHE and the memory pillars MP in contact with the slit SHE, one contact plug CP is connected to one conductive layer 25.

[0292] The slit SLT is formed, for example, in a plate shape extending along the XZ plane and cuts off the conductive layers 22 to 24. The upper end of the slit SLT is included in the layer between the uppermost conductive layer 24 and the conductive layer 25. The lower end of the slit SLT is included, for example, in the layer where the conductive layer 21 is provided. The slit SLT includes, for example, an insulator such as silicon dioxide.

[0293] The slit SHE is formed, for example, in a plate shape extending along the XZ plane and cuts off the laminated conductive layer 24. The upper end of the slit SHE is included in the layer between the conductive layer 24 and the conductive layer 25. The lower end of the slit SHE is included, for example, in the layer between the uppermost conductive layer 23 and the conductive layer 24. The slit SHE includes, for example, an insulator such as silicon dioxide. For example, the upper end of the slit SHE is aligned with the upper end of the memory pillar MP. However, it is not limited thereto, and the upper ends of the memory pillar MP and the slits SLT and SHE may not be aligned.

[0294] In addition, in the present embodiment, the portion from the source line SL to the word line WL(7) is defined as the lower layer LL. In addition, the portion from the word line WL(8) to the select gate line SGD is defined as the upper layer UL.

[0295] Cross-sectional structure of the memory cell column MP of the memory cell array 10

[0296] Figure 25 is a cross-sectional view along the Figure 24 D-D line, showing an example of the cross-sectional structure of the memory cell column MP in the semiconductor memory device 1 of the first embodiment. More specifically, Figure 25 shows the cross-sectional structure of the memory cell column MP in a layer parallel to the surface of the semiconductor substrate 20 and including the conductor layer 23.

[0297] As Figure 21 shown, in the layer including the conductor layer 23, the core member 30 is disposed, for example, at the center of the memory cell column MP. The semiconductor layer 31 surrounds the side surface of the core member 30. The stacked film 32 surrounds the side surface of the semiconductor layer 31. The stacked film 32 includes, for example, a tunnel insulating film 33, an insulating film 34, and a barrier insulating film 35.

[0298] The tunnel insulating film 33 surrounds the side surface of the semiconductor layer 31. The insulating film 34 surrounds the side surface of the tunnel insulating film 33. The barrier insulating film 35 surrounds the side surface of the insulating film 34. The conductor layer 23 surrounds the side surface of the barrier insulating film 35. The tunnel insulating film 33 and the barrier insulating film 35 each include, for example, silicon oxide. The insulating film 34 includes, for example, silicon nitride (SiN).

[0299] In the structure of the memory cell column MP described above, the portion where the memory cell column MP intersects the conductor layer 22 functions as the selection transistor ST2. The portion where the memory cell column MP intersects the conductor layer 23 functions as the memory cell transistor MT. The portion where the memory cell column MP intersects the conductor layer 24 functions as the selection transistor ST1.

[0300] That is, the semiconductor layer 31 is used as the channel of each of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 34 is used as the charge accumulation layer of the memory cell transistor MT. Thus, each memory cell column MP functions as one NAND string NS.

[0301] <1-2-4-5>Structure of the connection region

[0302] Next, the structure of the connection region 101 of the semiconductor memory device 1 of the first embodiment will be described.

[0303] Figure 26 is an example of a detailed planar layout of the connection region 101 of the semiconductor memory device 1 of the first embodiment, showing two adjacent connection regions 101 ([[]]END]] Figure 22 in the B direction) selected in the Y direction. More specifically, Figure 26 shows the setting in Figure 8 orFigure 11 The stepped area and the sub-channel area between the block BLK(n) and the block BLK(n-1) shown in

[0304] Figure 27 is along Figure 26 A cross-sectional view along the E-E line of shows an example of the cross-sectional structure of the sub-channel connection area and the stepped area. More specifically, Figure 27 shows the contact plug CC provided in the stepped area.

[0305] Figure 28 is along Figure 26 A cross-sectional view along the F-F line of shows an example of the cross-sectional structure of the sub-channel connection area and the stepped area. More specifically, Figure 28 shows the contact plug CB provided in the stepped area.

[0306] Figure 29 is along Figure 26 A cross-sectional view along the G-G line of shows an example of the cross-sectional structure of the sub-channel connection area and the stepped area. More specifically, Figure 29 shows the lower bridging area LBBA, the upper bridging area UBBA, and the sub-channel area.

[0307] Figure 30 is along Figure 26 A cross-sectional view along the H-H line of shows an example of the cross-sectional structure of the lower bridging area LBBA and the lower sub-channel connection area LBCA. More specifically, Figure 30 shows an example of the stepped portion related to the select gate lines SGS of the block BLK(n) and the block BLK(n-1), and the cross-sectional structure of the lower bridging area LBBA related to the select gate lines SGS.

[0308] Figure 31 is along Figure 26 A cross-sectional view along the J-J line of shows an example of the cross-sectional structure of the first lower connectable area LCA1. More specifically, Figure 31 shows the stepped portion related to the word lines WL(5) of the block BLK(n) and the block BLK(n-1), and the contact plugs CC and CB provided in the stepped portion.

[0309] Figure 32 is along Figure 26 A cross-sectional view along the K-K line of shows an example of the cross-sectional structure of the lower bridging area LBBA and the lower sub-channel connection area LBCA. More specifically, Figure 32 shows an example of the stepped portion related to the word lines WL(8) of the block BLK(n) and the block BLK(n-1), and the cross-sectional structure of the upper bridging area UBBA related to the word lines WL(8).

[0310] Figure 33 is a cross-sectional view along the L-L line of Figure 26 , showing an example of the cross-sectional structure of the first upper connectable region UCA1. More specifically, Figure 26 it shows a stepped portion related to the word lines WL(14) of the block BLK(n) and the block BLK(n - 1), and contact plugs CC and CB provided in the stepped portion. Figure 33

[0311] Figure 34 is a cross-sectional view along the M-M line of Figure 26 , showing an example of the cross-sectional structure of the sub-channel connection region. More specifically, Figure 26 it shows the contact plug C4 provided in the sub-channel connection region. Figure 34

[0312] As shown in Figure 26 , Figure 27 , and Figure 34 , the contact plug CC is, for example, located on the same straight line in the X direction. In addition, the contact plug C4 penetrates through the sub-channel region (lower) SBA-L and the sub-channel region (upper) SBA-U and is connected to the row decoder RD.

[0313] Similarly, as shown in Figure 26 and Figure 28 , the contact plug CB is, for example, located on the same straight line in the X direction. In particular, as shown in Figure 28 , the positions (heights from the semiconductor substrate (not shown)) of the first lower connectable region LCA1 and the second lower connectable region LCA2 in the Z direction are the same respectively.

[0314] As shown in Figure 29 , the select gate line SGS, the word lines WL(0) to WL(4) are connected to the lower sub-channel connection region LBCA via the lower bridging region LBBA. Similarly, the word lines WL(8) to WL(13) are connected to the upper sub-channel connection region UBCA via the upper bridging region UBBA. On the other hand, the lower bridging region LBBA is not provided for the word lines WL(5) to WL(7). In addition, the upper bridging region UBBA is not provided for the word lines WL(14), WL(15), and the select gate line SGD.

[0315] As shown in Figure 30 , the select gate line SGS is connected to the lower bridging region LBBA via the lower sub-channel connection region LBCA. The same applies to the word lines WL(0) to WL(4). Thus, the select gate lines SGS, the word lines WL(0) to WL(4) of the two blocks BLK(n) across the connection region 101 are connected to each other. Similarly, the select gate lines SGS, the word lines WL(0) to WL(4) of the two blocks BLK(n - 1) across the connection region 101 are connected to each other.​​

[0316] As shown Figure 31 in Figure 31 , the lower bridging area LBBA is not provided for the word line WL(5). Therefore, a contact plug CB is provided at the step portion of the first lower connectable area LCA1, and is connected to the contact plug CB of the second lower connectable area LCA2 via a lower connection wiring LCL (not shown) (see Figure 26 ). Thus, the word lines WL(5) to WL(7) of two blocks BLK(n) across the connection area 101 are connected to each other. Similarly, the word lines WL(5) to WL(7) of two blocks BLK(n - 1) across the connection area 101 are connected to each other.

[0317] As shown Figure 32 in Figure 32 , the word line WL(8) is connected to the upper bridging area UBBA via the upper sub-channel connection area UBCA. The same applies to the word lines WL(9) to WL(13). Thus, the word lines WL(8) to WL(13) of two blocks BLK(n) across the connection area 101 are connected to each other. Similarly, the word lines WL(8) to WL(13) of two blocks BLK(n - 1) across the connection area 101 are connected to each other.

[0318] As shown Figure 33 in Figure 33 , the upper bridging area UBBA is not provided for the word line WL(14). Therefore, a contact plug CB is provided at the step portion of the first upper connectable area UCA1, and is connected to the contact plug CB of the second upper connectable area UCA2 via an upper connection wiring UCL (not shown) (see Figure 26 ). Thus, the word lines WL(14), WL(15), and the selection gate line SGD of two blocks BLK(n) across the connection area 101 are connected to each other. Similarly, the word lines WL(14), WL(15), and the selection gate line SGD of two blocks BLK(n - 1) across the connection area 101 are connected to each other.

[0319] <1 - 3> Effect

[0320] According to the above-described embodiment, a lead-out area for applying voltage to the selection gate line and the word line is provided at the center of the memory cell array 10. Moreover, the lead-out area shorts the selection gate line and the word line of two cell areas across the lead-out area. Therefore, the selection gate line and the word line of two cell areas across the lead-out area are supplied with voltage via the lead-out area.

[0321] To illustrate the effect of this embodiment, a comparative example will be described. In Figure 35 , a part of the cell area in the comparative example and the lead-out area for applying voltage to the selection gate line and the word line are shown.

[0322] For example, in the comparative example, lead-out regions are provided at both ends in the X direction of the cell region. The Figure 35 lead-out region provided on the left side of the paper surface is denoted as lead-out region (left), and the lead-out region provided on the right side is denoted as lead-out region (right).

[0323] In the comparative example, for example, even-numbered blocks BLK (BLK(n), BLK(n + 2)…) are connected to the lead-out region (left), and odd-numbered blocks BLK (BLK(n - 1), BLK(n + 1)…) are connected to the lead-out region (right). That is, the selection gate lines and word lines of each block BLK are supplied with voltage from a single-sided lead-out region (refer to the arrows in the figure).

[0324] In addition, in recent years, the miniaturization and large capacity of memory cell transistors have been continuously developed, and improvement in the write performance and read performance of memory cell transistors has been required. In particular, sometimes the wiring resistance increases along with the reduction in the wiring widths of the selection gate lines and word lines.

[0325] In the case of the comparative example, voltage is applied from a single side of the selection gate lines and word lines. Therefore, sometimes the voltage transfer speed becomes slow due to the wiring resistance. As a result, there is a possibility that the write performance and read performance of the memory cell transistors are reduced.

[0326] In contrast, it is considered to provide a lead-out region at the center of the cell region. For example, as Figure 36 shown, the cell region is divided into left and right two parts with respect to the Figure 36 paper surface. Moreover, a lead-out region is provided between the left cell region (left) and the right cell region (right). This lead-out region includes a lead-out region (center & left) related to the left cell region (left) and a lead-out region (center & right) related to the right cell region (right). In this case, it is necessary to prepare, as Figure 37 shown, a row decoder module (center & left) related to the cell region (left) and a row decoder module (center & right) related to the cell region (right).

[0327] On the other hand, as Figure 38 shown, in the present embodiment, a connection region 101 is provided between two cell regions 100. This connection region 101 connects the two cell regions 100, so that the same voltage can be supplied to the two cell regions 100 simultaneously. Therefore, as Figure 39As shown, for two cell regions 100, there is a common row decoder module. Therefore, it is possible to halve the wiring lengths of the selection gate lines and the word lines while suppressing the area of the row decoder module as described in the comparative example. As a result, it is possible to suppress an increase in the area of the row decoder module while suppressing an increase in the resistance in the selection gate lines and the word lines. Therefore, the voltage transfer speed becomes faster compared to the comparative example. As a result, in the semiconductor memory device of the present embodiment, it is possible to improve the write performance and read performance of the memory cell transistors.

[0328] <1-4>Variation 1

[0329] Variation 1 of the first embodiment will be described. As Variation 1 of the first embodiment, Figure 40 is used to describe the connection between the sub-channel region SBA and the stepped region SSA.

[0330] In Figure 40 , the directions of the first contact wiring CL1, the second contact wiring CL2, the third contact wiring CL3, and the fourth contact wiring CL4 (hereinafter referred to as contact wiring CL) that connect the contact plug CC provided in the stepped region SSA to the contact plug C4 provided in the sub-channel region, and the position of the row decoder RD in the Z direction provided below the connection region (refer to the dotted line) are shown. In Figure 40 , a part of the cell region (upper left) 100-FP, the cell region (upper right) 100-GP, and the connection region (upper) 101-P are specifically shown.

[0331] In addition, the contact wiring CL related to the block BLK(v) is denoted as CL(BLK(v)). Further, the block BLK(v) belonging to the cell region 100-FP is denoted as BLK(v)-FP. Furthermore, the block BLK(v) belonging to the cell region 100-GP is denoted as BLK(v)-GP. In addition, the contact plug C4 related to the block BLK(v) is denoted as C4(BLK(v)). In addition, the contact plug CC related to the block BLK(v) is denoted as CC(BLK(v)). In addition, the stepped region SSA related to the block BLK(v) is denoted as SSA(BLK(v)). In addition, the sub-channel region SBA related to the block BLK(v) is denoted as SBA(BLK(v)).

[0332] As Figure 40 shows, the row decoder RD(BLK(n-1)) related to the block BLK(n-1) is provided below the stepped region SSA related to the block BLK(n-1) and the sub-channel region SBA related to the block BLK(n) in the Z direction.

[0333] As described above, a contact plug CC (not shown) is provided in the stepped region SSA. Further, in the sub-channel region SSA, a contact plug C4 (not shown) is provided which penetrates the sub-channel region SSA and is connected to a row decoder RD provided below the sub-channel region SSA in the Z direction.

[0334] As described above, the sub-channel region SSA has two functions, i.e., a function of connecting blocks BLK adjacent in the X direction, and a function of connecting the selection gate lines SGS, word lines WL0 to WL15, and selection gate line SGD of the block BLK to a row decoder RD provided below the sub-channel region SSA.

[0335] In this modification example, the sub-channel region SSA (BLK(v)) sandwiched between two blocks BLK(v) in the X direction connects the two blocks BLK(v) adjacent in the X direction. Further, the sub-channel region SSA (BLK(v)) includes a contact plug C4 (BLK(v±1)) which connects the selection gate line SGS, word lines WL0 to WL15, and selection gate line SGD of a block BLK(v±1) adjacent to the block BLK(v) in the Y direction to a row decoder RD (BLK(v±1)) associated with the block BLK(v±1). The contact plug C4 (BLK(v±1)) is connected to a contact plug CC (BLK(v±1)) provided in the stepped region SSA (BLK(v±1)) associated with the block BLK(v±1) via a wiring CL (BLK(v±1)) extending in the Y direction. As a result, the sub-channel region SSA (BLK(v)) can connect the selection gate line SGS, word lines WL0 to WL15, and selection gate line SGD of the block BLK(v±1) to the row decoder RD (BLK(v±1)) associated with the block BLK(v±1).

[0336] Specifically, the selection gate line SGS, word lines WL0 to WL15, and selection gate line SGD of the block BLK(n - 1) are connected to a row decoder RD (BLK(n - 1)) associated with the block BLK(n - 1) via the stepped region SSA (BLK(n - 1)), a contact plug CC (BLK(n - 1)) provided in the stepped region SSA (BLK(n - 1)), a contact plug C4 (BLK(n - 1)) associated with the block BLK(n - 1) which penetrates the sub-channel region SBA (BLK(n)) associated with the block BLK(n), and a wiring CL (BLK(n - 1)) connecting the contact plug CC (BLK(n - 1)) and the contact plug C4 (BLK(n - 1)).

[0337] In addition, the select gate line SGS, word lines WL0 to WL15, and select gate line SGD of block BLK(n) are connected to the row decoder RD(BLK(n)) associated with block BLK(n) via the stepped region SSA(BLK(n)), the contact plug CC(BLK(n)) provided in the stepped region SSA(BLK(n)), the contact plug C4(BLK(n)) associated with block BLK(n) that penetrates the sub-channel region SBA(BLK(n - 1)) associated with block BLK(n - 1)), and the wiring CL(BLK(n)) that connects the contact plug CC(BLK(n)) and the contact plug C4(BLK(n)).

[0338] Similarly, the select gate line SGS, word lines WL0 to WL15, and select gate line SGD of block BLK(n + 1) are connected to the row decoder RD(BLK(n + 1)) associated with block BLK(n + 1) via the stepped region SSA(BLK(n + 1)), the contact plug CC(BLK(n + 1)) provided in the stepped region SSA(BLK(n + 1)), the contact plug C4(BLK(n + 1)) associated with block BLK(n + 1) that penetrates the sub-channel region SBA(BLK(n + 2)) associated with block BLK(n + 2)), and the wiring CL(BLK(n + 1)) that connects the contact plug CC(BLK(n + 1)) and the contact plug C4(BLK(n + 1)).

[0339] In addition, the select gate line SGS, word lines WL0 to WL15, and select gate line SGD of block BLK(n + 2) are connected to the row decoder RD(BLK(n + 2)) associated with block BLK(n + 2) via the stepped region SSA(BLK(n + 2)), the contact plug CC(BLK(n + 2)) provided in the stepped region SSA(BLK(n + 2)), the contact plug C4(BLK(n + 2)) associated with block BLK(n + 2) that penetrates the sub-channel region SBA(BLK(n + 1)) associated with block BLK(n + 1)), and the wiring CL(BLK(n + 2)) that connects the contact plug CC(BLK(n + 2)) and the contact plug C4(BLK(n + 2)).

[0340] Similarly, the select gate lines SGS, word lines WL0 to WL15, and select gate line SGD of block BLK(n + 3) are connected to the row decoder RD(BLK(n + 3)) associated with block BLK(n + 3) via the stepped region SSA(BLK(n + 3)), the contact plug CC(BLK(n + 3)) provided in the stepped region SSA(BLK(n + 3)), the contact plug C4(BLK(n + 3)) associated with block BLK(n + 3) that penetrates the sub-channel region SBA(BLK(n + 4)) associated with block BLK(n + 4), and the wiring CL(BLK(n + 3)) that connects the contact plug CC(BLK(n + 3)) and the contact plug C4(BLK(n + 3)).

[0341] In addition, the select gate lines SGS, word lines WL0 to WL15, and select gate line SGD of block BLK(n + 4) are connected to the row decoder RD(BLK(n + 4)) associated with block BLK(n + 4) via the stepped region SSA(BLK(n + 4)), the contact plug CC(BLK(n + 4)) provided in the stepped region SSA(BLK(n + 4)), the contact plug C4(BLK(n + 4)) associated with block BLK(n + 4) that penetrates the sub-channel region SBA(BLK(n + 3)) associated with block BLK(n + 3), and the wiring CL(BLK(n + 4)) that connects the contact plug CC(BLK(n + 4)) and the contact plug C4(BLK(n + 4)).

[0342] <1-5>Variant 2

[0343] Variant 2 of the first embodiment will be described. In Variant 2 of the first embodiment, different examples of the connection region will be described. Figure 41 The layout of the circuit region CTA of the semiconductor memory device 1 and the memory cell array 10 of the first embodiment is shown. Figure 42 The layout of the circuit region CTA of the semiconductor memory device 1 and the memory cell array 10 of Variant 2 of the first embodiment is shown. Figure 43 The layout of the circuit region CTA of the semiconductor memory device 1 and the memory cell array 10 of Variant 2 of the first embodiment is shown.

[0344] As Figure 41 shown, in the first embodiment, the connection region (lower & upper) 101-LP in the first lower layer LL1 includes the stepped region (first lower) SSA-L1 and the sub-channel region (first lower) SBA-L1. In addition, the connection region (lower & upper) 101-LP in the second lower layer LL2 includes the stepped region (second lower) SSA-L2 and the sub-channel region (second lower) SBA-L2.

[0345] However, it is also possible that Figure 42 as shown, the connection region (lower & upper) 101-LP in the second lower layer LL2 does not include the stepped region (second lower) SSA-L2 but includes a stepped region having the same structure as the stepped region (first lower) SSA-L1 (for convenience, denoted as SSA-L1 in the drawings).

[0346] In addition, as Figure 41 shown, in the first embodiment, the connection region (upper & upper) 101-UP in the first upper layer UL1 includes the stepped region (first upper) SSA-U1 and the sub-channel region (first upper) SBA-U1. In addition, the connection region (upper & upper) 101-UP in the second upper layer UL2 includes the stepped region (second upper) SSA-U2 and the sub-channel region (second upper) SBA-U2.

[0347] However, it is also possible that Figure 43 as shown, the connection region (upper & upper) 101-UP in the second upper layer UL2 does not include the stepped region (second upper) SSA-U2 but includes a stepped region having the same structure as the stepped region (first upper) SSA-U1 (for convenience, denoted as SSA-U1 in the drawings).

[0348] In addition, it is also possible to combine the Figure 42 layout described in Figure 43 with the layout described in

[0349] <2> Second Embodiment

[0350] The second embodiment will be described. In the second embodiment, a case where the row decoder related to the select gate line SGD is arranged at a position different from the row decoder related to the select gate lines SGS and word lines WL0 to WL15 will be described.

[0351] <2-1> Layout of Circuit Region

[0352] The layout of the plane including the X direction and the Y direction of the circuit region CTA will be described.

[0353] As Figure 44 shown, compared with the circuit region CTA described in Figure 19 a row decoder module related to the select gate line SGD is further provided at the end of the sense amplifier module 16. Hereinafter, the row decoder module 15 related to the select gate line SGD will be denoted as the row decoder module (SGD) 15, etc.

[0354] Specifically, the row decoder module related to the select gate line SGD is located Figure 44On the left side of the sense amplifier module (upper left) 16-FP on the paper surface. The row decoder module is described as the row decoder module (SGD & upper left) 15-LU. In this way, the sense amplifier module (upper left) 16-FP is sandwiched in the X direction between the row decoder module (upper) 15-P and the row decoder module (SGD & upper left) 15-LU. In addition, the row decoder module (upper) 15-P, similar to the first embodiment, includes a row decoder related to the select gate line SGD.

[0355] In addition, the row decoder module related to the select gate line SGD is located Figure 44 On the right side of the sense amplifier module (upper right) 16-GP on the paper surface. The row decoder module is described as the row decoder module (SGD & upper right) 15-RU. In this way, the sense amplifier module (upper right) 16-GP is sandwiched in the X direction between the row decoder module (upper) 15-P and the row decoder module (SGD & upper right) 15-RU.

[0356] In addition, the row decoder module related to the select gate line SGD is located Figure 44 On the left side of the sense amplifier module (lower left) 16-FD on the paper surface. The row decoder module is described as the row decoder module (SGD & lower left) 15-LD. In this way, the sense amplifier module (lower left) 16-FD is sandwiched in the x direction between the row decoder module (lower) 15-D and the row decoder module (SGD & lower left) 15-LD. In addition, the row decoder module (lower) 15-D, similar to the first embodiment, includes a row decoder related to the select gate line SGD.

[0357] In addition, the row decoder module related to the select gate line SGD is located Figure 44 On the right side of the sense amplifier module (lower right) 16-GD on the paper surface. The row decoder module is described as the row decoder module (SGD & lower right) 15-RD. In this way, the sense amplifier module (lower right) 16-GD is sandwiched in the X direction between the row decoder module (lower) 15-D and the row decoder module (SGD & lower right) 15-RD.

[0358] In addition, the regions for setting the row decoder module (SGD & upper left) 15-LU and the row decoder module (SGD & lower left) 15-LD are also described as the "left end portion". In addition, the regions for setting the row decoder module (SGD & upper right) 15-RU and the row decoder module (SGD & lower right) 15-RD are also described as the "right end portion".

[0359] <2-2> Layout of the memory cell array

[0360] Next, an explanation will be given of the layout of the storage cell array 10 with respect to a plane including the X direction and the Y direction.

[0361] Figure 45 FIG. shows an example of the planar layout of the storage cell array 10. In Figure 45 for simplicity, a schematic layout including the first lower layer LL1, the second lower layer LL2, the first upper layer UL1, and the second upper layer UL2 is shown.

[0362] As Figure 45 shown, compared with the storage cell array 10 described in Figure 4 a connection region 101 for connecting the select gate line SGD to the row decoder module (SGD) 15 is further provided at the end of the cell region 100. Hereinafter, the connection region 101 related to the select gate line SGD will be referred to as the connection region (SGD) 101 and the like.

[0363] Specifically, the connection region related to the select gate line SGD is located on the left side of the cell region (upper left) 100-FP on the paper surface of Figure 45 . This connection region is denoted as the connection region (SGD & upper left) 101-LU. In this way, the cell region (upper left) 100-FP is sandwiched in the X direction between the connection region (upper) 101-P and the connection region (SGD & upper left) 101-LU. In addition, similar to the first embodiment, the connection region (upper) 101-P includes a connection region related to the select gate line SGD.

[0364] In addition, the connection region related to the select gate line SGD is located on the right side of the cell region (upper right) 100-GP on the paper surface of Figure 45 . This connection region is denoted as the connection region (SGD & upper right) 101-RU. In this way, the cell region (upper right) 100-GP is sandwiched in the X direction between the connection region (upper) 101-P and the connection region (SGD & upper right) 101-RU.

[0365] In addition, the connection region related to the select gate line SGD is located on the left side of the cell region (lower left) 100-FD on the paper surface of Figure 45 . This connection region is denoted as the connection region (SGD & lower left) 101-LD. In this way, the cell region (lower left) 100-FD is sandwiched in the X direction between the connection region (lower) 101-D and the connection region (SGD & lower left) 101-LD. In addition, similar to the first embodiment, the connection region (lower) 101-D includes a connection region related to the select gate line SGD.

[0366] In addition, the connection region related to the select gate line SGD is located on the left side of the cell region (lower left) 100-FD on the paper surface of Figure 45On the right side of the unit area (lower right) 100-GD on the paper surface. This connection area is denoted as the connection area (SGD & lower right) 101-RD. In this way, the unit area (lower right) 100-GD is sandwiched between the connection area (lower) 101-D and the connection area (SGD & lower right) 101-RD in the X direction.

[0367] In addition, the area for setting the connection area (SGD & upper left) 101-LU and the connection area (SGD & lower left) 101-LD is also denoted as the "left end portion". Further, the area for setting the connection area (SGD & upper right) 101-RU and the connection area (SGD & lower right) 101-RD is also denoted as the "right end portion".

[0368] The row decoder module (SGD & upper left) 15-LU is located below the connection area (SGD & upper left) 101-LU in the Z direction. The row decoder module (SGD & upper right) 15-RU is located below the connection area (SGD & upper right) 101-RU in the Z direction. The row decoder module (SGD & lower left) 15-LD is located below the connection area (SGD & lower left) 101-LD in the Z direction. The row decoder module (SGD & lower right) 15-RD is located below the connection area (SGD & lower right) 101-RD in the Z direction.

[0369] <2-3> Effect

[0370] According to the above-described embodiment, compared with the configuration of the first embodiment, it is configured that the voltage is transmitted to the selection gate line SGD not only from the center of the memory cell array 10 but also from both ends (the left end portion and the right end portion).

[0371] The selection gate line SGD is divided by the slit SHE or the like, so the width of the wiring may become narrow. In this case, there is a possibility that the resistance value of the wiring of the selection gate line SGD becomes high. Therefore, for the selection gate line SGD, as Figure 46 and Figure 47 shown, it is configured to transmit the voltage not only from the center of the memory cell array 10 but also from both ends. Therefore, even when the resistance value of the wiring of the selection gate line SGD becomes high, the effects described in the first embodiment can be obtained.

[0372] In addition, in the second embodiment, the variation example 2 of the first embodiment can also be applied.

[0373] <3> Third Embodiment

[0374] A description will be given of the third embodiment. In the third embodiment, a case will be described where the row decoder modules 15 related to the lower layer LL are arranged at the center in the X direction, and the row decoder modules 15 related to the upper layer UL are arranged at the left and right ends in the X direction.

[0375] <3-1>Layout of the circuit region

[0376] A description will be given of the layout of the plane including the X direction and the Y direction of the circuit region CTA.

[0377] As Figure 48 shown, compared with the circuit region CTA described in Figure 19 , the row decoder modules 15-P and 15-D respectively become the row decoder modules related to the lower layer LL. In addition, a row decoder module (upper) related to the upper layer UL is further provided at the end of the sense amplifier module 16.

[0378] As Figure 48 shown, the row decoder module (upper) 15-P and the row decoder module (lower) 15-D in Figure 19 are respectively described as the row decoder module (lower & upper) 15-LP and the row decoder module (lower & lower) 15-LD.

[0379] The row decoder module related to the upper layer UL is located Figure 48 on the left side of the sense amplifier module (upper left) 16-FP on the paper surface of

[0380] . This row decoder module is described as the row decoder module (upper & upper left) 15-UFP. In this way, the sense amplifier module (upper left) 16-FP is sandwiched in the X direction between the row decoder module (lower & upper) 15-LP and the row decoder module (upper & upper left) 15-UFP. Figure 48 In addition, the row decoder module related to the upper layer UL is located

[0381] on the right side of the sense amplifier module (upper right) 16-GP on the paper surface of Figure 48 . This row decoder module is described as the row decoder module (upper & upper right) 15-UGP. In this way, the sense amplifier module (upper right) 16-GP is sandwiched in the X direction between the row decoder module (lower & upper) 15-LP and the row decoder module (upper & upper right) 15-UGP.

[0382] In addition, the row decoder module related to the upper layer UL is located Figure 48 to the right of the sense amplifier module (lower right) 16-GD on the paper surface of

[0383] This row decoder module is denoted as the row decoder module (upper & lower right) 15-UGD. In this way, the sense amplifier module (lower right) 16-GD is sandwiched in the X direction between the row decoder module (lower & lower) 15-LD and the row decoder module (upper & lower right) 15-UGD.

[0384] <3-2> Layout of the memory cell array

[0385] Next, an explanation will be given regarding the layout of the plane of the memory cell array 10 including the X direction and the Y direction.

[0386] Figure 49 A planar layout example of the memory cell array 10 is shown. In Figure 49 for simplicity, a rough layout including the first lower layer LL1, the second lower layer LL2, the first upper layer UL1, and the second upper layer UL2 is shown.

[0387] As Figure 49 shown, compared with the memory cell array 10 described in Figure 4 a connection region (upper) 101 for connecting the upper layer UL to the row decoder module (upper) 15 is further provided at the end of the cell region 100.

[0388] As Figure 49 shown, the connection region (upper) 101-P and the connection region (lower) 101-D in Figure 19 are respectively denoted as the connection region (lower & upper) 101-LP and the connection region (lower & lower) 101-LD. In the present embodiment, the connection region (upper) 101 is not included in the connection region (upper) 101-P and the connection region (lower) 101-D.

[0389] The connection region (upper) 101 is located Figure 49 to the left of the cell region (upper left) 100-FP on the paper surface of

[0390] In addition, the connection area (upper) 101 is located Figure 49 The unit region (upper right) 100-GP on the paper is on the right side. The connection region (upper) 101 is recorded as the connection region (upper & upper right) 101-UGP. In this way, the unit region (upper right) 100-GP is sandwiched between the connection region (lower & upper) 101-LP and the connection region (upper & upper right) 101-UGP in the X direction.

[0391] In addition, the connection area (upper) 101 is located Figure 49 The unit region (lower left) 100-FD on the paper is on the left side. The connection region (upper) 101 is recorded as the connection region (upper & lower left) 101-UFD. In this way, the unit region (lower left) 100-FD is sandwiched between the connection region (lower & lower) 101-LD and the connection region (upper & lower left) 101-UFD in the X direction.

[0392] In addition, the connection area (upper) 101 is located Figure 49 The unit region (lower right) 100-GD on the paper is on the right side. The connection region (upper) 101 is recorded as the connection region (upper & lower right) 101-UGD. In this way, the unit region (lower right) 100-GD is sandwiched between the connection region (lower & lower) 101-LD and the connection region (upper & lower right) 101-UGD in the X direction.

[0393] In addition, the area for setting the connection area (upper & upper left) 101-UFP and the connection area (upper & lower left) 101-UFD is also recorded as the "left end". In addition, the area for setting the connection area (upper & upper right) 101-UGP and the connection area (upper & lower right) 101-UGD is also recorded as the "right end".

[0394] The row decoder module (upper & upper left) 15-UFP is located below the connection area (upper & upper left) 101-UFP in the Z direction. The row decoder module (upper & upper right) 15-UGP is located below the connection area (upper & upper right) 101-UGP in the Z direction. The row decoder module (upper & lower left) 15-UFD is located below the connection area (upper & lower left) 101-UFD in the Z direction. The row decoder module (upper & lower right) 15-UGD is located below the connection area (upper & lower right) 101-UGD in the Z direction.

[0395] Here, the connection region (upper) 101 will be described.

[0396] use Figure 50 , the relationship between the connection area (upper) 101 and the XY plane of the row decoder module (upper) 15 is described. Figure 50Specifically shown therein are a unit region (upper & upper left) 100-UFP, a connection region (upper & upper left) 101-UFP, and a part of a row decoder module (upper & upper left) 15-UFP. In Figure 50 the row decoder RD included in the row decoder module (upper & upper left) 15-UFP is indicated by a dashed line.

[0397] For convenience, the row decoder RD related to the block (upper & upper left) BLK(v)-UFP is denoted as RD(BLK(v)-UFP). In addition, the second contact wiring CL2 related to the block (upper & upper left) BLK(v)-UFP is denoted as CL2(BLK(v)-UFP). The contact plug area CPA related to the block (upper & upper left) BLK(v)-UFP is denoted as CPA(BLK(v)-UFP).

[0398] As ​ shown, the connection region (upper & upper left) 101-UFP has a set of a stepped region (upper) SSA-U and a contact plug area CPA for each block. Since the stepped region (upper) SSA-U is the same as the stepped region (upper) SSA-U described in the first embodiment, the description thereof is omitted. The contact plug area CPA is a region for connecting the stepped region (upper) SSA-U to the row decoder RD. Specifically, in the contact plug area CPA, a contact plug C4 (not shown) for connecting the row decoder DC formed below the connection region (upper & upper left) 101-UFP in the Z direction to the contact plug CC is formed. The upper ends of the contact plug CC and the contact plug C4 are connected by the second contact wiring CL2. The second contact wiring CL2 extends in the Y direction.

[0399] In the present embodiment, the contact plug area CPA(BLK(v)) includes a contact plug C4(BLK(v±1)-UFP) that connects the word lines WL8 to WL15 and the select gate line SGD of the block BLK(v±1)-UFP adjacent to the block BLK(v)-UFP in the Y direction to the row decoder RD(BLK(v±1)-UFP) associated with the block BLK(v±1)-UFP. The contact plug C4(BLK(v±1)-UFP) is connected via a second contact wiring CL2(BLK(v±1)-UFP) extending in the Y direction to a contact plug CC(BLK(v±1)-UFP) provided in a stepped area SSA(BLK(v±1)-UFP) associated with the block BLK(v±1)-UFP. As a result, the sub-channel area SSA(BLK(v)-UFP) can connect the word lines WL8 to WL15 and the select gate line SGD of the block BLK(v±1)-UFP to the row decoder RD(BLK(v±1)-UFP) associated with the block BLK(v±1)-UFP.

[0400] Specifically, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n-1)-UFP are connected to the row decoder RD(BLK(n-1)-UFP) associated with the block BLK(n-1)-UFP via a stepped area SSA(BLK(n-1)-UFP), a contact plug CC(BLK(n-1)-UFP) provided in the stepped area SSA(BLK(n-1)-UFP), a contact plug C4(BLK(n-1)-UFP) associated with the block BLK(n-1)-UFP that penetrates a sub-channel area SBA(BLK(n)-UFP) associated with the block BLK(n)-UFP, and a second contact wiring CL2(BLK(n-1)-UFP) connecting the contact plug CC(BLK(n-1)-UFP) and the contact plug C4(BLK(n-1)-UFP).

[0401] In addition, word lines WL8 to WL15 of block BLK(n)-UFP and the select gate line SGD are connected to the row decoder RD(BLK(n)-UFP) associated with block BLK(n)-UFP via the stepped region SSA(BLK(n)-UFP), the contact plug CC(BLK(n)-UFP) provided in the stepped region SSA(BLK(n)-UFP), the contact plug C4(BLK(n)-UFP) associated with block BLK(n)-UFP that penetrates the sub-channel region SBA(BLK(n - 1)-UFP) associated with block BLK(n - 1)-UFP, and the second contact wiring CL2(BLK(n)-UFP) that connects the contact plug CC(BLK(n)-UFP) and the contact plug C4(BLK(n)-UFP).

[0402] Similarly, word lines WL8 to WL15 of block BLK(n + 1)-UFP and the select gate line SGD are connected to the row decoder RD(BLK(n + 1)-UFP) associated with block BLK(n + 1)-UFP via the stepped region SSA(BLK(n + 1)-UFP), the contact plug CC(BLK(n + 1)-UFP) provided in the stepped region SSA(BLK(n + 1)-UFP), the contact plug C4(BLK(n + 1)-UFP) associated with block BLK(n + 1)-UFP that penetrates the sub-channel region SBA(BLK(n + 2)-UFP) associated with block BLK(n + 2)-UFP, and the wiring CL(BLK(n + 1)-UFP) that connects the contact plug CC(BLK(n + 1)-UFP) and the contact plug C4(BLK(n + 1)-UFP).

[0403] In addition, word lines WL8 to WL15 of block BLK(n + 2)-UFP and the select gate line SGD are connected to the row decoder RD(BLK(n + 2)-UFP) associated with block BLK(n + 2)-UFP via the stepped region SSA(BLK(n + 2)-UFP), the contact plug CC(BLK(n + 2)-UFP) provided in the stepped region SSA(BLK(n + 2)-UFP), the contact plug C4(BLK(n + 2)-UFP) associated with block BLK(n + 2)-UFP that penetrates the sub-channel region SBA(BLK(n + 1)-UFP) associated with block BLK(n + 1)-UFP, and the second contact wiring CL2(BLK(n + 2)-UFP) that connects the contact plug CC(BLK(n + 2)-UFP) and the contact plug C4(BLK(n + 2)-UFP).

[0404] Similarly, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n + 3)-UFP are connected to the row decoder RD(BLK(n + 3)-UFP) associated with the block BLK(n + 3)-UFP via the step region SSA(BLK(n + 3)-UFP), the contact plug CC(BLK(n + 3)-UFP) provided in the step region SSA(BLK(n + 3)-UFP), the contact plug C4(BLK(n + 3)-UFP) associated with the block BLK(n + 3)-UFP that penetrates the sub-channel region SBA(BLK(n + 4)-UFP) associated with the block BLK(n + 4)-UFP, and the second contact wiring CL2(BLK(n + 3)-UFP) that connects the contact plug CC(BLK(n + 3)-UFP) and the contact plug C4(BLK(n + 3)-UFP).

[0405] In addition, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n + 4)-UFP are connected to the row decoder RD(BLK(n + 4)-UFP) associated with the block BLK(n + 4)-UFP via the step region SSA(BLK(n + 4)-UFP), the contact plug CC(BLK(n + 4)-UFP) provided in the step region SSA(BLK(n + 4)-UFP), the contact plug C4(BLK(n + 4)-UFP) associated with the block BLK(n + 4)-UFP that penetrates the sub-channel region SBA(BLK(n + 3)-UFP) associated with the block BLK(n + 3)-UFP, and the second contact wiring CL2(BLK(n + 4)-UFP) that connects the contact plug CC(BLK(n + 4)-UFP) and the contact plug C4(BLK(n + 4)-UFP). In addition, use ​ , the relationship between the connection region (upper) 101 and the row decoder module (upper) 15 in the X-Y plane will be described. In ​ , a part of the cell region (upper & upper right) 100-UGP, the connection region (upper & upper right) 101-UGP, and the row decoder module (upper & upper right) 15-UGP is specifically shown. In ​ , the row decoder RD included in the row decoder module (upper & upper right) 15-UGP is indicated by a dashed line.

[0406] For convenience, the row decoder RD related to the block (upper & upper right) BLK(v)-UGP is denoted as RD(BLK(v)-UGP). In addition, the second contact wiring CL2 related to the block (upper & upper right) BLK(v)-UGP is denoted as CL2(BLK(v)-UGP). The contact plug area CPA related to the block (upper & upper right) BLK(v)-UGP is denoted as CPA(BLK(v)-UGP).

[0407] As ​ shown, the connection area (upper & upper right) 101-UGP has a set of a stepped area (upper) SSA-U and a contact plug area CPA for each block. Since the stepped area (upper) SSA-U is the same as the stepped area (upper) SSA-U described in the first embodiment, the description thereof is omitted. The contact plug area CPA is an area for connecting the stepped area (upper) SSA-U to the row decoder RD. Specifically, in the contact plug area CPA, a contact plug C4 (not shown) for connecting the row decoder DC formed below the connection area (upper & upper right) 101-UGP in the Z direction to the contact plug CC is formed. The upper ends of the contact plug CC and the contact plug C4 are connected by the second contact wiring CL2. The second contact wiring CL2 extends in the Y direction.

[0408] In the present embodiment, the contact plug area CPA(BLK(v)) includes the contact plug C4(BLK(v±1)-UGP) for connecting the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(v±1)-UGP adjacent to the block BLK(v)-UGP in the Y direction to the row decoder RD(BLK(v±1)-UGP) related to the block BLK(v±1)-UGP. The contact plug C4(BLK(v±1)-UGP) is connected to the contact plug CC(BLK(v±1)-UGP) provided in the stepped area SSA(BLK(v±1)-UGP) related to the block BLK(v±1)-UGP via the second contact wiring CL2(BLK(v±1)-UGP) extending in the Y direction. As a result, the sub-channel area SSA(BLK(v)-UGP) can connect the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(v±1)-UGP to the row decoder RD(BLK(v±1)-UGP) related to the block BLK(v±1)-UGP.

[0409] Specifically, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n - 1)-UGP are connected to the row decoder RD(BLK(n - 1)-UGP) associated with the block BLK(n - 1)-UGP via the step region SSA(BLK(n - 1)-UGP), the contact plug CC(BLK(n - 1)-UGP) provided in the step region SSA(BLK(n - 1)-UGP), the contact plug C4(BLK(n - 1)-UGP) associated with the block BLK(n - 1)-UGP that penetrates the sub-channel region SBA(BLK(n - 1)-UGP) associated with the block BLK(n)-UGP, and the second contact wiring CL2(BLK(n - 1)-UGP) that connects the contact plug CC(BLK(n - 1)-UGP) and the contact plug C4(BLK(n - 1)-UGP).

[0410] In addition, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n)-UGP are connected to the row decoder RD(BLK(n)-UGP) associated with the block BLK(n)-UGP via the step region SSA(BLK(n)-UGP), the contact plug CC(BLK(n)-UGP) provided in the step region SSA(BLK(n)-UGP), the contact plug C4(BLK(n)-UGP) associated with the block BLK(n)-UGP that penetrates the sub-channel region SBA(BLK(n - 1)-UGP) associated with the block BLK(n - 1)-UGP, and the second contact wiring CL2(BLK(n)-UGP) that connects the contact plug CC(BLK(n)-UGP) and the contact plug C4(BLK(n)-UGP).

[0411] Similarly, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n + 1)-UGP are connected to the row decoder RD(BLK(n + 1)-UGP) associated with the block BLK(n + 1)-UGP via the step region SSA(BLK(n + 1)-UGP), the contact plug CC(BLK(n + 1)-UGP) provided in the step region SSA(BLK(n + 1)-UGP), the contact plug C4(BLK(n + 1)-UGP) associated with the block BLK(n + 1)-UGP that penetrates the sub-channel region SBA(BLK(n + 2)-UGP) associated with the block BLK(n + 2)-UGP, and the wiring CL(BLK(n + 1)-UGP) that connects the contact plug CC(BLK(n + 1)-UGP) and the contact plug C4(BLK(n + 1)-UGP).

[0412] In addition, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n+2)-UGP are connected to the row decoder RD(BLK(n+2)-UGP) associated with the block BLK(n+2)-UGP via the stepped region SSA(BLK(n+2)-UGP), the contact plug CC(BLK(n+2)-UGP) provided in the stepped region SSA(BLK(n+2)-UGP), the contact plug C4(BLK(n+2)-UGP) associated with the block BLK(n+2)-UGP that penetrates the sub-channel region SBA(BLK(n+1)-UGP) associated with the block BLK(n+1)-UGP), and the second contact wiring CL2(BLK(n+2)-UGP) that connects the contact plug CC(BLK(n+2)-UGP) and the contact plug C4(BLK(n+2)-UGP).

[0413] Similarly, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n+3)-UGP are connected to the row decoder RD(BLK(n+3)-UGP) associated with the block BLK(n+3)-UGP via the stepped region SSA(BLK(n+3)-UGP), the contact plug CC(BLK(n+3)-UGP) provided in the stepped region SSA(BLK(n+3)-UGP), the contact plug C4(BLK(n+3)-UGP) associated with the block BLK(n+3)-UGP that penetrates the sub-channel region SBA(BLK(n+4)-UGP) associated with the block BLK(n+4)-UGP, and the second contact wiring CL2(BLK(n+3)-UGP) that connects the contact plug CC(BLK(n+3)-UGP) and the contact plug C4(BLK(n+3)-UGP).

[0414] In addition, the word lines WL8 to WL15 and the select gate line SGD of the block BLK(n+4)-UGP are connected to the row decoder RD(BLK(n+4)-UGP) associated with the block BLK(n+4)-UGP via the stepped region SSA(BLK(n+4)-UGP), the contact plug CC(BLK(n+4)-UGP) provided in the stepped region SSA(BLK(n+4)-UGP), the contact plug C4(BLK(n+4)-UGP) associated with the block BLK(n+4)-UGP that penetrates the sub-channel region SBA(BLK(n+3)-UGP) associated with the block BLK(n+3)-UGP, and the second contact wiring CL2(BLK(n+4)-UGP) that connects the contact plug CC(BLK(n+4)-UGP) and the contact plug C4(BLK(n+4)-UGP).

[0415] <3-3> Circuit Region and Layout of Memory Cell Array

[0416] Next, use ​ to illustrate the layout of the semiconductor memory device 1 as observed from a cross-section parallel to the X-Z plane.

[0417] In ​ , a cross-sectional view of the circuit region CTA and the memory cell array 10 is shown. Specifically, in ​ , the row decoder module (upper & upper left) 15-UFP, the row decoder module (upper & upper right) 15-UGP, the row decoder module (lower & upper) 15-LP, the sense amplifier module (upper left) 16-FP, and the sense amplifier module (upper right) 16-GP are shown as the circuit region CTA. In addition, in ​ , the cell region (lower & upper left) 100-LFP, the cell region (lower & upper right) 100-LGP, and the connection region (lower & upper) 101-LP are shown as the lower layer LL of the memory cell array 10. In addition, in ​ , the cell region (upper & upper left) 100-UFP, the cell region (upper & upper right) 100-UGP, the connection region (upper & upper left) 101-UFP, and the connection region (upper & upper right) 101-UGP are shown as the upper layer UL of the memory cell array 10.

[0418] As ​ shows, the cell region (lower & upper left) 100-LFP and the cell region (upper & upper left) 100-UFP are provided above the sense amplifier module (upper left) 16-FP in the Z direction. The sense amplifier module (upper left) 16-FP is connected to the cell region (lower & upper left) 100-LFP and the cell region (upper & upper left) 100-UFP through wirings (not shown).

[0419] Moreover, the connection region (lower & upper) 101-LP is provided above the row decoder module (lower & upper) 15-LP in the Z direction. The row decoder module (lower & upper) 15-LP is connected to the connection region (lower & upper) 101-LP through wirings (not shown).

[0420] In addition, the connection region (upper & upper left) 101-UFP is provided above the row decoder module (upper & upper left) 15-UFP in the Z direction. The row decoder module (upper & upper left) 15-UFP is connected to the connection region (upper & upper left) 101-UFP through wirings (not shown).

[0421] Furthermore, a connection region (upper & upper right) 101-UGP is provided above the row decoder module (upper & upper right) 15-UGP in the Z direction. The row decoder module (upper & upper right) 15-UGP and the connection region (upper & upper right) 101-UGP are connected by wiring (not shown).

[0422] That is to say, as ​ shown, the cell region (lower & upper left) 100-LFP and the cell region (lower & upper right) 100-LGP receive voltage from the row decoder module (lower & upper) 15-LP via the connection region (lower & upper) 101-LP.

[0423] In addition, the cell region (upper & upper left) 100-UFP receives voltage from the row decoder module (upper & upper left) 15-UFP via the connection region (upper & upper left) 101-UFP.

[0424] In addition, the cell region (upper & upper right) 100-UGP receives voltage from the row decoder module (upper & upper right) 15-UGP via the connection region (upper & upper right) 101-UGP.

[0425] Furthermore, as ​ shown, in the third embodiment, the connection region (lower & upper) 101-LP in the first lower layer LL1 includes a stepped region (first lower) SSA-L1 and a sub-channel region (first lower) SBA-L1. In addition, the connection region (lower & upper) 101-LP in the second lower layer LL2 includes a stepped region (second lower) SSA-L2 and a sub-channel region (second lower) SBA-L2.

[0426] However, it is also possible that, as ​ shown, the connection region (lower & upper) 101-LP in the second lower layer LL2 does not include the stepped region (second lower) SSA-L2 but includes a stepped region having the same structure as the stepped region (first lower) SSA-L1 (for convenience, denoted as SSA-L1 in the drawings).

[0427] In addition, it is also possible that, as ​ shown, the connection region (lower & upper) 101-LP in the first lower layer LL1 does not include the stepped region (first lower) SSA-L1 but includes a stepped region having the same structure as the stepped region (second lower) SSA-L2 (for convenience, denoted as SSA-L2 in the drawings).

[0428] <4> Fourth Embodiment

[0429] The fourth embodiment will be described. In the fourth embodiment, another structure of the stepped region will be described.

[0430] <4-1> Outline

[0431] In the above-described embodiments, as ​ shown, a step (descending step) that descends in the Z direction toward the selection gate line SGD, word lines WL15 to WL0, and selection gate line SGS is provided in the stepped region SSA. However, in the above-described embodiments, it is also possible to, as ​ shown, provide a step (descending step) that descends in the Z direction toward the selection gate line SGD, word lines WL15 to WL0, and selection gate line SGS, and a step (ascending step) that ascends upward in the Z direction in the stepped region SSA. This ascending step may be a dummy step without a contact plug provided, or a contact plug may be provided.

[0432] Here, the descending step refers to a step in the direction from the cell region 100 toward the direction in which the semiconductor substrate is provided in the direction of the sub-channel region SBA. In addition, the ascending step refers to a step in the direction from the cell region 100 toward the direction opposite to the direction in which the semiconductor substrate is provided in the direction of the sub-channel region SBA.

[0433] <4-2> Specific Example

[0434] Hereinafter, a specific example of the stepped region SSA of the present embodiment will be described.

[0435] ​ is an example of a detailed planar layout of the stepped region SSA of the semiconductor memory device 1 of the fourth embodiment, and two stepped regions SSA adjacent in the Y direction are selected and shown. More specifically, ​ shows the stepped region provided between ​ or ​ the block BLK(n) and the block BLK(n-1) shown in.

[0436] ​ is a cross-sectional view along the ​ N-N line, showing an example of the cross-sectional structure of the stepped region.

[0437] As ​ and ​ shown, the stepped region (lower) SSA-L and the stepped region (upper) SSA-U are respectively descending steps. Moreover, a dummy stepped region DBCA is provided between the stepped region (lower) SSA-L and the stepped region (upper) SSA-U. This dummy stepped region DBCA is an ascending step.

[0438] The dummy stepped region DBCA is provided between the stepped region (lower) SSA-L and the stepped region (upper) SSA-U, but can be provided at any position. For example, the dummy stepped region DBCA is included in the stepped region (lower) SSA-L or the stepped region (upper) SSA-U. In addition, the dummy stepped region DBCA can be connected to the lower bridging region LBBA or the upper bridging region UBBA adjacent in the Y direction. In this case, the dummy stepped region DBCA can be connected to each block via the lower bridging region LBBA or the upper bridging region UBBA. Therefore, contact plugs can also be provided in the dummy stepped region DBCA.

[0439] In addition, the number of steps of the dummy stepped region DBCA can be appropriately changed. In addition, the number of dummy stepped regions DBCA can also be appropriately changed.

[0440] <5>Other variations etc.

[0441] In the above-described embodiment, the case where the structure between two adjacent slits SLT corresponds to one string component SU is illustrated, but it is not limited thereto. For example, multiple string components SU can also be formed between two adjacent slits SLT by providing a slit that divides the selection gate line SGD between the two adjacent slits SLT. The number of string components SU between adjacent slits SLT varies based on the number of slits that divide the selection gate line SGD.

[0442] In the above-described embodiment, the storage pillar MP, and the contact plugs CP, CV, V0, V1, and V2 can each have a tapered shape or an inverted tapered shape, and can also have a shape with a protruding middle portion. Similarly, the slit SLT can have a tapered shape or an inverted tapered shape, and can also have a shape with a protruding middle portion. In addition, the case where the cross-sectional structure of the storage pillar MP or the transistor TR is circular is illustrated, but their cross-sectional structures can also be elliptical and can be designed in any shape.

[0443] In the above-described embodiment, the case where the stacked wiring such as the word line WL forms a stepped structure having a step in the X direction in the connection region is illustrated, but it is not limited thereto. For example, the ends of the stacked word lines WL, and the selection gate lines SGD and SGS can also form a step in the Y direction. The ends of the stacked word lines WL, and the selection gate lines SGD and SGS in the connection region can be designed in a stepped shape with any number of columns. The formed stepped structure can also be different between the selection gate line SGS, the word line WL, and the selection gate line SGD.

[0444] As used in this specification, "connection" means electrical connection, and cases where other elements are interposed therebetween are not excluded. "Electrical connection" may also be through an insulator as long as it can operate in the same manner as an electrical connection. "Columnar" means a structure provided in a hole formed in the manufacturing process of the semiconductor memory device 1.

[0445] Some embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents.

[0446] [Description of Reference Signs]

[0447] 1 Semiconductor memory device

[0448] 2 Memory controller

[0449] 10 Memory cell array

[0450] 10 - UGD (lower right)

[0451] 11 Command register

[0452] 12 Address register

[0453] 13 Sequencer

[0454] 14 Driver module

[0455] 15 Row decoder module

[0456] 16 Sense amplifier module

[0457] 17 Peripheral circuit

[0458] 18 Peripheral circuit

[0459] 20 Semiconductor substrate

[0460] 21 - 25 Conductor layers

[0461] 30 Core member

[0462] 31 Semiconductor layer

[0463] 32 Stacked film

[0464] 33 Tunnel insulating film

[0465] 34 Insulating film

[0466] 35 Barrier insulating film

[0467] 40 - 43 Insulating layer

[0468] 100 Unit area

[0469] 101 Connection area

Claims

1. A semiconductor memory device comprising: A first cell region including a plurality of first conductor layers laminated at intervals in a first direction and a first semiconductor layer extending in the first direction within the plurality of first conductor layers, and intersections of the plurality of first conductor layers and the first semiconductor layer respectively form memory cells; A second cell region including a plurality of second conductor layers laminated at intervals in the first direction and a second semiconductor layer extending in the first direction within the plurality of second conductor layers, and intersections of the plurality of second conductor layers and the second semiconductor layer respectively form memory cells; and A first connection region disposed between the first cell region and the second cell region in a second direction intersecting the first direction, and including a first bridging region and a first stepped region. In the first bridging region, one layer of the plurality of first conductor layers and one layer of the plurality of second conductor layers are respectively electrically connected by a plurality of third conductor layers laminated at intervals in the first direction. In the first stepped region, the plurality of third conductor layers respectively have steps for providing first contact plugs.

2. The semiconductor memory device according to claim 1, wherein The first stepped region is connected to the first bridging region in a third direction intersecting the first direction and the second direction.

3. The semiconductor memory device according to claim 2, wherein The first connection region further includes a first sub-channel region adjacent to the first bridging region and the first stepped region in the second direction, and second contact plugs extending in the first direction within the plurality of third conductor layers are provided.

4. The semiconductor memory device according to claim 3, wherein In the first sub-channel region, one layer of the plurality of first conductor layers and one layer of the plurality of second conductor layers are respectively electrically connected by the plurality of third conductor layers.

5. The semiconductor memory device according to claim 4, comprising: A first slit adjacent to the first cell region, the first connection region, and the second cell region in the third direction; A third cell region adjacent to the first cell region with the first slit interposed therebetween in the third direction, and including a plurality of fourth conductor layers laminated at intervals in the first direction and a third semiconductor layer extending in the first direction within the plurality of fourth conductor layers, and intersections of the plurality of fourth conductor layers and the third semiconductor layer respectively form memory cells; A fourth cell region adjacent to the second cell region with the first slit interposed therebetween in the third direction, and including a plurality of fifth conductor layers laminated at intervals in the first direction and a fourth semiconductor layer extending in the first direction within the plurality of fifth conductor layers, and intersections of the plurality of fifth conductor layers and the fourth semiconductor layer respectively form memory cells; and A second connection region is disposed between the third unit region and the fourth unit region in the second direction, and includes a second bridging region, a second stepped region, and a second sub-channel region. In the second bridging region, a plurality of sixth conductor layers stacked at intervals in the first direction are respectively electrically connected to one layer of the plurality of fourth conductor layers and one layer of the plurality of fifth conductor layers. In the second stepped region, the plurality of sixth conductor layers respectively have steps for providing third contact plugs, and the second stepped region is connected to the second bridging region in the third direction. The second sub-channel region is adjacent to the second bridging region and the second stepped region in the second direction, and fourth contact plugs extending in the first direction are provided in the plurality of sixth conductor layers.

6. The semiconductor memory device according to claim 5, wherein the first bridging region and the first stepped region are adjacent to the second sub-channel region with the first slit interposed therebetween in the third direction, and the second bridging region and the second stepped region are adjacent to the first sub-channel region with the first slit interposed therebetween in the third direction.

7. The semiconductor memory device according to claim 6, wherein a first row decoder related to the first unit region and the second unit region is provided below the first bridging region, the first stepped region, and the second sub-channel region in the first direction, the first unit region and the second unit region are connected to the first row decoder via the fourth contact plug, the first contact plug, the first stepped region, and the first bridging region, a second row decoder related to the third unit region and the fourth unit region is provided below the second bridging region, the second stepped region, and the first sub-channel region in the first direction, and the third unit region and the fourth unit region are connected to the second row decoder via the third contact plug, the second contact plug, the second stepped region, and the second bridging region.

8. The semiconductor memory device according to claim 7, further comprising: a first wiring connecting the fourth contact plug and the first contact plug; and a second wiring connecting the third contact plug and the second contact plug.

9. The semiconductor memory device according to any one of claims 1 to 8, wherein the first to third conductor layers are the same conductor layer.

10. The semiconductor memory device according to any one of claims 1 to 8, wherein the first to third conductor layers are word lines or select gate lines.

11. The semiconductor memory device according to any one of claims 5 to 8, wherein the fourth to sixth conductor layers are the same conductor layer.

12. The semiconductor memory device according to any one of claims 5 to 8, wherein the fourth to sixth conductor layers are word lines or select gate lines.

13. The semiconductor memory device according to any one of claims 5 to 8, further comprising: A third stepped region, in the second direction, separated from the first connection region by the first unit region, and a plurality of seventh conductor layers stacked at intervals along the first direction each have a step for providing a fifth contact plug; A third connection region, having a first contact region adjacent to the third stepped region in the second direction and provided with a sixth contact plug extending in the first direction among the plurality of seventh conductor layers; A fourth stepped region, in the second direction, separated from the second connection region by the third unit region, and a plurality of eighth conductor layers stacked at intervals along the first direction each have a step for providing a seventh contact plug; and A fourth connection region, having a second contact region adjacent to the fourth stepped region in the second direction and provided with an eighth contact plug extending in the first direction among the plurality of eighth conductor layers.

14. The semiconductor memory device according to claim 13, wherein the third stepped region is adjacent to the second contact region with the first slit interposed therebetween in the third direction, and the fourth stepped region is adjacent to the first contact region with the first slit interposed therebetween in the third direction.

15. The semiconductor memory device according to claim 14, wherein a third row decoder related to the first unit region is provided below the third stepped region and the second contact region in the first direction, the first unit region is connected to the third row decoder via the fifth contact plug, the eighth contact plug, and the third stepped region, a fourth row decoder related to the third unit region is provided below the fourth stepped region and the first contact region in the first direction, and the third unit region is connected to the fourth row decoder via the sixth contact plug, the seventh contact plug, and the fourth stepped region.

16. The semiconductor memory device according to claim 15, further comprising: a third wiring connecting the fifth contact plug and the eighth contact plug; and a fourth wiring connecting the sixth contact plug and the seventh contact plug.

17. The semiconductor memory device according to claim 13, wherein the first to third, and seventh conductor layers are the same conductor layer.

18. The semiconductor memory device according to claim 13, wherein the first to third, and seventh conductor layers are word lines or selection gate lines.

19. The semiconductor memory device according to claim 13, wherein the fourth to sixth, and eighth conductor layers are the same conductor layer.

20. A semiconductor memory device, comprising: a first unit region, including a plurality of first conductor layers stacked in a first direction, and a plurality of memory cells, the plurality of memory cells extending in the first direction among the plurality of first conductor layers, including a first semiconductor layer, and intersections of the plurality of first conductor layers and the first semiconductor layer respectively form memory cells; The second unit region, which is a region arranged in a second direction intersecting the first direction of the first unit region, and includes a plurality of second conductor layers stacked in the first direction and a plurality of memory cells. The plurality of memory cells extend in the first direction within the plurality of second conductor layers, include a second semiconductor layer, and intersections of the plurality of first conductor layers and the second semiconductor layer respectively form memory cells; The connection region, which is a region arranged between the first unit region and the second unit region, and is sandwiched between a plurality of third conductor layers stacked in the first direction and respectively electrically connecting one of the plurality of first conductor layers and one of the plurality of second conductor layers, and a first contact plug that is electrically insulated from the plurality of third conductor layers and extends in the first direction; And A row decoder, arranged below the connection region, and transmits a voltage to word lines of the first and second unit regions via the connection region electrically connected to the first contact plug of the connection region.

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