DRAM (Dynamic Random Access Memory) regulation and control method, control device and regulation and control equipment

Abstract

The invention discloses a regulation and control method, a control device and regulation and control equipment of a DRAM (Dynamic Random Access Memory), and relates to the technical field of the DRAM. The DRAM comprises a plurality of storage units, and the method comprises the following steps: carrying out quality grade classification on the plurality of storage units in the DRAM, and confirming the number and physical addresses of the plurality of storage units with different quality grades; determining the quality level of the DRAM based on the storage unit with the lowest quality level in the plurality of storage units; and based on the target quality level required to be improved by the DRAM, removing the storage unit with the quality level lower than the target quality level, and remapping the physical address of the storage unit with the quality level higher than or equal to the target quality level, so as to obtain the DRAM required by the target quality level. The invention aims to improve the quality grade of the DRAM.

Description

Technical Field

[0001] The present invention relates to the technical field of DRAM, and particularly relates to a regulation method, a control device and a regulation device for DRAM. Background Art

[0002] DRAM (Dynamic Random Access Memory) is a semiconductor memory. The main principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. There are certain distribution differences in the quality and reliability of the cell units inside DRAM. This distribution is jointly caused by various factors such as the randomness of the manufacturing process, material defects, thermal stress, and design tolerances. This leads to various products with different quality levels in the production and manufacturing of DRAM. There are DRAMs with high quality levels, DRAMs with low quality levels, and DRAMs that cannot be used due to failures of some cell units. Summary of the Invention

[0003] The main object of the present invention is to provide a regulation method, a control device and a regulation device for DRAM, aiming to improve the quality level of DRAM.

[0004] To achieve the above object, a regulation method for DRAM provided by the present invention, the DRAM includes a plurality of storage units, and the method includes: Classify the quality levels of a plurality of storage units in the DRAM, and confirm the quantity and physical addresses of the storage units with multiple different quality levels; Based on the storage units with the lowest quality level among the plurality of storage units, confirm the quality level of the DRAM; Based on the target quality level required to be improved for the DRAM, remove the storage units with quality levels lower than the target quality level, and remap the physical addresses of the storage units with quality levels higher than or equal to the target quality level, so as to obtain a DRAM that meets the requirements of the target quality level.

[0005] In an embodiment, the method for classifying the quality levels of a plurality of storage units in the DRAM and confirming the quantity and physical addresses of the storage units with multiple different quality levels specifically includes: Conduct quality level tests on a plurality of storage units in the DRAM to obtain the quality parameters of the plurality of storage units; Based on the quality parameters of the plurality of storage units, confirm the quality levels of the corresponding storage units, and classify and count the quantity and corresponding physical addresses of the storage units in each quality level.

[0006] In one embodiment, the method for performing a quality level test on multiple memory cells in a DRAM to obtain quality parameters of the multiple memory cells, and confirming the quality level of the corresponding memory cells based on the quality parameters of the multiple memory cells specifically includes: Perform a function test, a charge retention duration test, and a leakage current test on multiple memory cells in a DRAM to obtain function parameters, charge retention duration parameters, and leakage current parameters of the multiple memory cells; Based on the comparison results of the function parameters, charge retention duration parameters, and leakage current parameters of the multiple memory cells with corresponding preset parameters, confirm the quality level of the corresponding memory cells.

[0007] In one embodiment, the method for confirming the quality level of the corresponding memory cells based on the comparison results of the function parameters, charge retention duration parameters, and leakage current parameters of the multiple memory cells with corresponding preset parameters specifically includes: Memory cells with function parameters within a preset function parameter range, charge retention duration parameters greater than a first preset parameter, and leakage current parameters less than a second preset parameter are of a first quality level; Memory cells with function parameters within a preset function parameter range, charge retention duration parameters less than a first preset parameter, and leakage current parameters less than a second preset parameter are of a second quality level; Memory cells with function parameters within a preset function parameter range, charge retention duration parameters less than a first preset parameter, and leakage current parameters greater than a second preset parameter are of a third quality level; Memory cells with function parameters outside the preset function parameter range are faulty memory cells.

[0008] In one embodiment, the method for classifying and counting the number of memory cells of each quality level and the corresponding physical addresses specifically includes: Confirm the number of memory cells of the first quality level, and identify the physical addresses of the memory cells of the first quality level; Confirm the number of memory cells of the second quality level, and identify the physical addresses of the memory cells of the second quality level; Confirm the number of memory cells of the third quality level, and identify the physical addresses of the memory cells of the third quality level; Confirm the number of faulty memory cells, and identify the physical addresses of the faulty memory cells.

[0009] In one embodiment, the method for confirming the quality level of the DRAM based on the memory cells with the lowest quality level among the multiple memory cells is specifically: When the number of the fault storage units is not zero, the DRAM is a faulty DRAM; When the number of the storage units of the third quality level is not zero and the number of the fault storage units is zero, the DRAM is a DRAM of the third quality level; When the number of the storage units of the second quality level is not zero and the numbers of the storage units of the third quality level and the fault storage units are zero, the DRAM is a DRAM of the second quality level; When the number of the storage units of the first quality level is not zero and the numbers of the storage units of the second quality level, the third quality level and the fault storage units are zero, the DRAM is a DRAM of the first quality level.

[0010] In one embodiment, the method for removing the storage units with a quality level lower than the target quality level based on the target quality level to be improved for the DRAM specifically includes: When the target quality level to be improved for the DRAM is the first quality level, remove the storage units of the second quality level, the third quality level and the fault storage units in the DRAM; When the target quality level to be improved for the DRAM is the second quality level, remove the storage units of the third quality level and the fault storage units in the DRAM; When the target quality level to be improved for the DRAM is the third quality level, remove the fault storage units in the DRAM.

[0011] In one embodiment, the method for remapping the physical addresses of the storage units with a quality level higher than or equal to the target quality level specifically includes: Continuously remap the physical addresses of the storage units of the first quality level to a first physical address segment; Continuously remap the physical addresses of the storage units of the second quality level to a second physical address segment; Continuously remap the physical addresses of the storage units of the third quality level to a third physical address segment; Wherein, the first physical address segment, the second physical address segment and the third physical address segment are consecutive in sequence.

[0012] The present invention also provides a control device, which includes: a memory, a processor, and a control program of a DRAM regulation method stored on the memory and running on the processor. The control program of the DRAM regulation method is configured to implement the steps of the DRAM regulation method as described in any one of the above.

[0013] The present invention also provides a regulation device, which includes the control device as described above.

[0014] Through the technical solution of the present invention, by adopting a DRAM regulation method, the quality level of the DRAM can be effectively improved to meet the diverse needs of users. Among them, the DRAM regulation method first needs to classify the quality levels of multiple memory cells in the DRAM, so as to confirm which quality level memory cells exist in the DRAM, and confirm the quantity and physical addresses of these quality level memory cells. Secondly, it is necessary to confirm the quality level of the DRAM by using the memory cells with the lowest quality level among the multiple memory cells in the DRAM. For example, the DRAM includes memory cells of the first quality level, memory cells of the second quality level, and memory cells of the third quality level, and the first quality level is greater than the second quality level, and the second quality level is greater than the third quality level. At this time, the quality level of the DRAM is the third quality level. After confirming the current quality level of the DRAM to be regulated, it is necessary to further confirm the target quality level that the DRAM needs to be improved to. For example, it needs to be improved from the third quality level to the second quality level. At this time, it is necessary to remove the memory cells of the third quality level in the DRAM, retain the memory cells of the second quality level, and remap the physical addresses of the retained memory cells, so as to obtain a DRAM of the second quality level. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0016] Figure 1 It is a flowchart of the DRAM regulation method of the present invention; Figure 2 It is a flowchart of an embodiment of the DRAM regulation method of the present invention; Figure 3 It is a flowchart of another embodiment of the DRAM regulation method of the present invention; Figure 4Schematic flowchart of another embodiment of the regulation method for the DRAM of the present invention; Figure 5 Schematic flowchart of still another embodiment of the regulation method for the DRAM of the present invention; Figure 6 Schematic flowchart of another embodiment of the regulation method for the DRAM of the present invention; Figure 7 Schematic flowchart of the second another embodiment of the regulation method for the DRAM of the present invention; Figure 8 Schematic flowchart of the third another embodiment of the regulation method for the DRAM of the present invention; Figure 9 Schematic structural diagram of an embodiment of multiple memory cells in the regulation method for the DRAM of the present invention; Figure 10 Schematic structural diagram of another embodiment of multiple memory cells in the regulation method for the DRAM of the present invention; Figure 11 Schematic structural diagram of still another embodiment of multiple memory cells in the regulation method for the DRAM of the present invention; Figure 12 Schematic structural diagram of yet another embodiment of multiple memory cells in the regulation method for the DRAM of the present invention; Figure 13 Schematic structural diagram of another embodiment of multiple memory cells in the regulation method for the DRAM of the present invention.

[0017] The realization of the object, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0019] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0020] In addition, the descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or unable to be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0021] DRAM (Dynamic Random Access Memory) is a type of semiconductor memory. The main principle of operation is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. There are certain distribution differences in the quality and reliability of the cell units inside DRAM. This distribution is jointly caused by various factors such as the randomness of the manufacturing process, material defects, thermal stress, and design tolerances. This results in various products with different quality grades in the production and manufacturing of DRAM. There are DRAMs with high quality grades, DRAMs with low quality grades, and also DRAMs that cannot be used due to faults in some cell units.

[0022] It should be noted that in the technical solution of the present application, the storage units of the first quality grade are labeled as A, the storage units of the second quality grade are labeled as B, the storage units of the third quality grade are labeled as C, and the faulty storage units are labeled as F.

[0023] Therefore, referring to Figure 1 , Figures 9 to 13 The present invention provides a method, where the DRAM includes a plurality of storage units, and the method includes: Step S100: Classify the quality grades of the plurality of storage units in the DRAM, and confirm the quantity and physical addresses of the storage units with multiple different quality grades; Step S200: Based on the storage units with the lowest quality grade among the plurality of storage units, confirm the quality grade of the DRAM; Step S300: Based on the target quality grade required to be improved for the DRAM, perform a removal process on the storage units with quality grades lower than the target quality grade, and remap the physical addresses of the storage units with quality grades higher than or equal to the target quality grade, so as to obtain a DRAM that meets the target quality grade requirements.

[0024] It should be understood that the basic storage unit of DRAM consists of a transistor and a capacitor, which enables DRAM to have a higher density compared to SRAM. Each storage unit is used to store one bit of data, that is, 0 or 1, which is represented by charging or discharging the capacitor. Among them, the cell units of DRAM will exhibit the characteristics of Gaussian distribution or long-tail distribution during the production process, that is, the performance of most storage units is concentrated in the middle region, such as the retention time within a certain range, but there are a small number of storage units with poor or excellent performance at both ends; or a very small number of storage units may exhibit extremely poor retention time or high leakage current. It can be understood that in the production and manufacturing of DRAM, there are many factors that will cause quality defects in DRAM. For example, the raw material of DRAM is a silicon wafer, and as the basic material of semiconductors, the characteristics such as its purity and crystal structure integrity directly affect the performance of the final product, and any impurities or defects may affect the formation and working performance of transistors and capacitors. In addition, lithography is a key step in the manufacturing process for defining circuit patterns. Insufficient accuracy of the lithography process will lead to feature size deviation, which in turn affects the consistency and reliability of storage units. For example, poor line width control may cause electrical property variations. Also, in order to adjust the conductivity of semiconductors, specific types of impurities (i.e., doping) are usually introduced into silicon. If the doping concentration or distribution is uneven, it will cause differences in the transistor characteristics of different regions, such as threshold voltage changes. Therefore, there may be problems with inconsistent quality among the multiple storage units in DRAM.

[0025] In this embodiment, it is necessary to perform performance tests on multiple storage units in DRAM through corresponding test equipment to confirm the quality levels of the multiple storage units. Among them, the corresponding test equipment can be specialized semiconductor test equipment, and such equipment usually includes automatic test equipment, which can perform a series of predefined electrical tests on DRAM to detect the functionality and performance of each storage unit in DRAM by applying voltage, current, and measuring the response. It can be understood that corresponding parameter ranges are preset in the test equipment, so that while detecting the functionality and performance of each storage unit in DRAM, the quality levels of each storage unit in DRAM are classified according to the preset parameter ranges. For example, each storage unit in DRAM is classified into Class A, Class B, Class C, etc. according to the corresponding parameter ranges. In addition, while confirming the corresponding quality levels according to the functionality and performance of each storage unit, it is also necessary to count the number and physical addresses of storage units with different quality levels, so as to facilitate subsequent confirmation of the storage space size of DRAM after reaching the target quality level, and the re-mapping of the physical addresses of each storage unit in the corresponding DRAM.

[0026] It is understandable that in different application environments, the performance requirements for DRAM are different. According to the nature of the application device, DRAM can be divided into computer (DDR), mobile (LPDDR), and graphics memory DRAM (GDDR). According to the application type, DDR can be further divided into the PC side, the server side, and the consumer side, with memory density and transmission rate as the core parameters; LPDDR is mainly applied to the mobile phone side, and the power consumption index is crucial; for the server side and the mobile phone side, etc., there are relatively high requirements for the high quality and reliability of DRAM. However, in actual use, it needs to be considered that all storage units in DRAM will be in use. Therefore, the storage units with the lowest quality level in DRAM will become the quality level of DRAM. For example, there are storage units with different quality levels such as A level, B level, and C level in DRAM, and the A level quality is higher than the B level quality, and the B level quality is higher than the C level quality. At this time, this DRAM is a DRAM of C level quality. Therefore, in an application environment where DRAM of A level quality is required, DRAM of B level quality cannot be used for substitution, even if there are only a small number of storage units in this DRAM that are lower than the A level quality.

[0027] In this embodiment, after confirming the current quality level of the DRAM, it is necessary to further confirm the target quality level that the DRAM needs to improve. It should be understood that the target quality level that the DRAM can improve cannot be higher than the quality level of the memory cells in the DRAM. For example, in a DRAM, only memory cells with a quality level of B and memory cells with a quality level of C exist in its internal memory cells. At this time, the DRAM is a DRAM with a quality level of C, and its target quality level can only be a quality level of B. Another example is that in a DRAM, memory cells with a quality level of A, memory cells with a quality level of B, and memory cells with a quality level of C exist in its internal memory cells. At this time, the DRAM is a DRAM with a quality level of C, and its target quality level can be a quality level of A or a quality level of B. Further, to ensure that the quality level of the DRAM is effectively improved, it is necessary to remove the memory cells in the DRAM whose quality level is lower than the target quality level, so as to avoid the memory cells with a quality level lower than the target quality level from affecting the performance of the DRAM. It can be understood that removing the memory cells in the DRAM whose quality level is lower than the target quality level can be to mark the memory cells with a quality level lower than the target quality level as unused memory cells by means of marking. Furthermore, it should be understood that in a DRAM, the physical address of a memory cell is mainly used to uniquely identify and access the location of each memory cell. The physical address allows the system to accurately locate a specific memory cell. Since the memory cells in the DRAM are organized in a two-dimensional matrix form (rows and columns), the physical address is usually decomposed into a row address (Row Address) and a column address (Column Address) to facilitate accessing a specific memory cell. To perform a data read or write operation, the processor or memory controller needs to know the exact location to be accessed. By providing the correct physical address, the system can accurately find the target memory cell and perform the corresponding operation. Therefore, in this embodiment, by remapping the physical addresses of the memory cells in the DRAM whose quality level is higher than or equal to the target quality level, the DRAM can accurately locate those memory cells with a quality level higher than or equal to the target quality level through the remapped physical address when in use.

[0028] It can be understood that by removing the storage units with a quality level lower than the target quality level and remapping the physical addresses of the storage units with a quality level higher than or equal to the target quality level, a DRAM meeting the requirements of the target quality level can be obtained. This method will inevitably result in a reduction in the available storage units in the DRAM, that is, a decrease in the storage space of the DRAM. For example, in a DRAM with a storage capacity of N, it contains a storage units of grade A quality, b storage units of grade B quality, and c storage units of grade C quality. Then the storage capacity N is the sum of the storage capacities included in a storage units of grade A quality, b storage units of grade B quality, and c storage units of grade C quality. At this time, the quality level of the DRAM is grade C. When the quality level of the DRAM needs to be upgraded to grade B, then c storage units of grade C quality need to be removed. At this time, the storage capacity of the DRAM is reduced by the storage capacity brought by c storage units of grade C quality.

[0029] By adopting a DRAM regulation method, the quality level of the DRAM can be effectively improved to meet the diverse needs of users. Among them, the DRAM regulation method first needs to classify the quality levels of multiple storage units in the DRAM, so as to confirm which quality-level storage units exist in the DRAM, and confirm the quantity and physical addresses of these quality-level storage units. Secondly, it is necessary to determine the quality level of the DRAM by means of the storage units with the lowest quality level among the multiple storage units in the DRAM. For example, the DRAM includes storage units of the first quality level, storage units of the second quality level, and storage units of the third quality level, and the first quality level is greater than the second quality level, and the second quality level is greater than the third quality level. At this time, the quality level of the DRAM is the third quality level. After confirming the current quality level of the DRAM to be regulated, it is necessary to further confirm the target quality level that the DRAM needs to be upgraded to. For example, it needs to be upgraded from the third quality level to the second quality level. At this time, it is necessary to remove the storage units of the third quality level in the DRAM, retain the storage units of the second quality level, and remap the physical addresses of the retained storage units, so as to obtain a DRAM of the second quality level.

[0030] Reference Figure 2 In an embodiment of the present invention, the method for classifying the quality levels of multiple storage units in the DRAM and confirming the quantity and physical addresses of multiple storage units with different quality levels specifically includes: Step S110: Perform a quality level test on multiple storage units in the DRAM to obtain quality parameters of the multiple storage units; Step S120: Based on the quality parameters of the multiple storage units, confirm the quality levels of the corresponding storage units, and classify and count the number of storage units in each quality level and their corresponding physical addresses.

[0031] In this embodiment, there are multiple factors affecting the quality levels of the storage units in the DRAM. Therefore, to determine the quality level of a storage unit, it is necessary to perform quality level tests on multiple aspects of the storage unit to obtain multiple corresponding quality parameters. It can be understood that the storage units in the DRAM are the basic building blocks of the storage system, and their main function is to store one bit of binary data. Each storage unit usually consists of a transistor and a capacitor, and this design is called 1T1C, that is, the structure of one transistor and one capacitor. Among them, the capacitor is used to actually store data. If the capacitor is charged to a certain voltage level, it means that a binary number "1" is stored; if the capacitor is not charged or discharged to another voltage level, it means that a binary number "0" is stored. When it is necessary to read the data stored in the cell, the transistor controlling the storage unit is activated, so that the capacitor is connected to the corresponding bit line, thereby allowing the sense amplifier to detect the voltage state on the capacitor and convert it into a logic level. When writing data to the storage unit, the required voltage is applied to the capacitor through the bit line to change its charge state. Then, the control transistor is turned off to keep the capacitor in the new charge state. Therefore, in actual tests, the functionality of each storage unit can be confirmed by performing a functional test on the storage unit. Further, there are multiple storage units in the DRAM. Therefore, in actual tests, quality parameters of multiple storage units will be obtained. Among them, the quality parameters of multiple storage units can be various and are not limited to the quality parameters of the functional test.

[0032] In this embodiment, by obtaining the quality parameters corresponding to each storage unit in the DRAM, the quality levels of the storage units can be effectively confirmed.

[0033] Reference Figure 3 Optionally, the method of performing quality level tests on multiple storage units in the DRAM to obtain the quality parameters of the multiple storage units, and confirming the quality levels of the corresponding storage units based on the quality parameters of the multiple storage units specifically includes: Step S111: Perform functional tests, charge retention duration tests, and leakage current tests on multiple storage units in the DRAM to obtain the function parameters, charge retention duration parameters, and leakage current parameters of the multiple storage units; Step S121: Based on the comparison results of the function parameters, charge retention duration parameters, and leakage current parameters of the multiple storage units with the corresponding preset parameters, confirm the quality levels of the corresponding storage units.

[0034] In this embodiment, first, by performing read and write operation tests, it can be verified whether the storage unit can correctly store and retrieve data. If a certain storage unit fails to correctly execute these basic operations, then it is determined to have a fault. Secondly, by testing the length of time that the storage unit can maintain its charge state without refreshing, the quality level of the storage unit can be judged. It can be understood that a shorter retention time may indicate leakage or other problems in the capacitor, thus affecting the persistence of data storage. Finally, in an ideally completely isolated state, the situation where current flows from the power supply of the storage unit to the ground or an adjacent circuit, a larger leakage current may be due to poor insulation caused by manufacturing defects or material aging, which will cause the charge to leak faster, thus shortening the charge retention time and possibly resulting in data loss or errors. Therefore, by obtaining the functional parameter, charge retention duration parameter, and leakage current parameter of each storage unit, and comparing the functional parameter, charge retention duration parameter, and leakage current parameter of each storage unit with the corresponding preset parameters, the quality level of the corresponding storage unit can be judged. For example, when comparing the functional parameter of a certain storage unit with the preset functional parameter and finding that its functional parameter is outside the preset functional parameter range, it can be judged as a faulty storage unit.

[0035] Reference Figure 4 , optionally, the method for confirming the quality level of the corresponding storage unit based on the comparison results of the functional parameter, charge retention duration parameter, and leakage current parameter of the multiple storage units with the corresponding preset parameters specifically includes: Step S1211: The storage unit with the functional parameter within the preset functional parameter range, the charge retention duration parameter greater than the first preset parameter, and the leakage current parameter less than the second preset parameter is of the first quality level; Step S1212: The storage unit with the functional parameter within the preset functional parameter range, the charge retention duration parameter less than the first preset parameter, and the leakage current parameter less than the second preset parameter is of the second quality level; Step S1213: The storage unit with the functional parameter within the preset functional parameter range, the charge retention duration parameter less than the first preset parameter, and the leakage current parameter greater than the second preset parameter is of the third quality level; Step S1214: The storage unit with the functional parameter outside the preset functional parameter range is a faulty storage unit.

[0036] In this embodiment, by obtaining the comparison results of the functional parameters, charge retention duration parameters, and leakage current parameters of the storage unit with the corresponding preset parameters, the quality grade of the storage unit is determined. Among them, a storage unit whose functional parameters are outside the preset functional parameter range is a faulty storage unit. The first preset parameter is the charge retention duration preset parameter, and the second preset parameter is the leakage current preset parameter. The first preset parameter and the second preset parameter can be set correspondingly according to actual needs, and multiple groups of the first preset parameter and the second preset parameter can also be set, so as to divide the quality grade of the storage unit into multiple groups. For example, in this embodiment, one group of the first preset parameter and the second preset parameter are both set, so as to divide the quality grade of the storage unit into three different quality grades of storage units, namely the first quality grade, the second quality grade, and the third quality grade.

[0037] Reference Figure 5 and Figure 10 , optionally, the method for classifying and counting the number of storage units of each quality grade and the corresponding physical addresses specifically includes: Step S122: Confirm the number of storage units of the first quality grade and identify the physical addresses of the storage units of the first quality grade; Step S123: Confirm the number of storage units of the second quality grade and identify the physical addresses of the storage units of the second quality grade; Step S124: Confirm the number of storage units of the third quality grade and identify the physical addresses of the storage units of the third quality grade; Step S125: Confirm the number of faulty storage units and identify the physical addresses of the faulty storage units.

[0038] In this embodiment, the quality grade of the corresponding memory cell is confirmed by comparing the functional parameters, charge retention duration parameters, and leakage current parameters of multiple memory cells with the corresponding preset parameters. To improve the quality grade of the DRAM, it is necessary to identify the memory cells whose quality grades have been confirmed. Among them, the number of memory cells with different quality grades is confirmed to finally confirm the storage capacity after the quality grade of the DRAM is improved to the target quality grade. The physical addresses of memory cells with different quality grades are distinguished and identified to remap the physical addresses of memory cells with the same quality grade uniformly later. For example, when the number of memory cells of the first quality grade is confirmed to be K, the physical address of the memory cells of the first quality grade is labeled as A; when the number of memory cells of the second quality grade is confirmed to be J, the physical address of the memory cells of the first quality grade is labeled as B; when the number of memory cells of the first quality grade is confirmed to be L, the physical address of the memory cells of the first quality grade is labeled as C; when the number of memory cells of the first quality grade is confirmed to be M, the physical address of the memory cells of the first quality grade is labeled as F. If the target quality grade of the DRAM is A, its storage capacity is equal to the storage capacity corresponding to K memory cells; if the target quality grade of the DRAM is B, its storage capacity is equal to the storage capacity corresponding to K + J memory cells. In addition, by distinguishing and identifying the physical addresses of memory cells with different quality grades, the quality of the DRAM can be improved after the physical address remapping in the later stage, and the interference of memory cells corresponding to the target quality grade can be avoided.

[0039] Reference Figure 6 , in an embodiment of the present invention, the method for confirming the quality grade of the DRAM based on the memory cells with the lowest quality grade among the multiple memory cells is specifically as follows: Step S210: When the number of the faulty memory cells is not zero, the DRAM is a faulty DRAM; Step S220: When the number of the memory cells of the third quality grade is not zero and the number of the faulty memory cells is zero, the DRAM is a DRAM of the third quality grade; Step S230: When the number of the memory cells of the second quality grade is not zero and the number of the memory cells of the third quality grade and the number of the faulty memory cells are zero, the DRAM is a DRAM of the second quality grade; Step S240: When the number of the memory cells of the first quality grade is not zero and the number of the memory cells of the second quality grade, the number of the memory cells of the third quality grade, and the number of the faulty memory cells are zero, the DRAM is a DRAM of the first quality grade.

[0040] It can be understood that, in order to confirm the stability of DRAM operation, the lowest quality level in its memory cells is the current quality level of the DRAM. Specifically, when there are faulty memory cells in the DRAM, the DRAM is a faulty DRAM; when the number of memory cells of the third quality level in the DRAM is not zero and the number of the faulty memory cells is zero, the DRAM is a DRAM of the third quality level. Therefore, when there are a small number of memory cells of the third quality level in the DRAM, it will result in the DRAM having a quality level of the third quality level. However, most of the memory cells in the DRAM are memory cells of the first quality level, which is the reason for the relatively small number of high-quality DRAMs in production. Among them, in this embodiment, the first quality level is higher than the second quality level, and the second quality level is higher than the third quality level.

[0041] Reference Figure 7 、 Figures 11 to 13 , in an embodiment of the present invention, the method for removing memory cells with a quality level lower than the target quality level based on the target quality level that the DRAM needs to be improved specifically includes: Step S310: When the target quality level that the DRAM needs to be improved is the first quality level, remove the memory cells of the second quality level, the memory cells of the third quality level, and the faulty memory cells in the DRAM; Step S320: When the target quality level that the DRAM needs to be improved is the second quality level, remove the memory cells of the third quality level and the faulty memory cells in the DRAM; Step S330: When the target quality level that the DRAM needs to be improved is the third quality level, remove the faulty memory cells in the DRAM.

[0042] As can be seen from the above, the current quality level of the DRAM will be determined by the memory cell with the lowest quality level in the DRAM, and the target quality level that the DRAM needs to improve can be the quality level of the memory cell with the highest quality level in the DRAM. For example, if there are memory cells of the first quality level, the second quality level, and the third quality level in the DRAM, at this time, the current quality level of the DRAM is the third quality level, but the target quality level of the DRAM can be the first quality level or the second quality level. Among them, when the target quality level that the DRAM needs to improve is the first quality level, the memory cells of the second quality level, the third quality level, and the faulty memory cells in the DRAM are removed. Among them, removing the memory cells with a quality level lower than the target quality level in the DRAM can be achieved by marking the memory cells with a quality level lower than the target quality level as unused memory cells. At this time, the DRAM improves the overall quality level of the DRAM by reducing its own capacity.

[0043] Reference Figure 8 、 Figures 11 to 13 Optionally, the method for remapping the physical addresses of the memory cells with a quality level higher than or equal to the target quality level specifically includes: Step S340: Continuously remap the physical addresses of the memory cells of the first quality level to the first physical address segment; Step S350: Continuously remap the physical addresses of the memory cells of the second quality level to the second physical address segment; Step S360: Continuously remap the physical addresses of the memory cells of the third quality level to the third physical address segment; Wherein, the first physical address segment, the second physical address segment, and the third physical address segment are consecutive in sequence.

[0044] In this embodiment, by confirming the quality levels of multiple memory cells in the DRAM, and confirming their quantities and physical addresses, and identifying the memory cells with the same quality level, different quality-level memory cells are effectively screened out. To improve the quality level of the DRAM, it is necessary to remap the physical addresses of the memory cells with the same quality level and map them to a certain fixed physical address segment, so that the subsequent control of the DRAM to the memory cells to work can directly read and write data according to this physical address segment. For example, the memory cells of the first quality level are identified as A, the memory cells of the second quality level are identified as B, the memory cells of the third quality level are identified as C, and the faulty memory cells are identified as F. By continuously remapping the memory cells of the first quality level to the first physical address segment, continuously remapping the memory cells of the second quality level to the second physical address segment, continuously remapping the memory cells of the third quality level to the third physical address segment, and continuously remapping the faulty memory cells to the fourth physical address segment. When the target quality level of the DRAM is the first quality level, only the memory cells in the first physical address segment need to be read and written; when the target quality level of the DRAM is the second quality level, only the memory cells in the first physical address segment and the second physical address segment need to be read and written; when the target quality level of the DRAM is the third quality level, only the memory cells in the first physical address segment, the second physical address segment, and the third physical address segment need to be read and written.

[0045] The present invention also provides a control device, which includes: a memory, a processor, and a control program of the DRAM regulation method stored on the memory and running on the processor. The control program of the DRAM regulation method is configured to implement the steps of the DRAM regulation method as described in any one of the above. It should be noted that since the control device of the present invention is based on the above DRAM regulation method, the embodiments of the control device of the present invention include all the technical solutions of all the embodiments of the above DRAM regulation method, and the achieved technical effects are also exactly the same, so they will not be elaborated here.

[0046] The present invention also provides a regulation device, which includes the control device as described above. It should be noted that since the regulation device of the present invention is based on the above control device, the embodiments of the regulation device of the present invention include all the technical solutions of all the embodiments of the above control device, and the achieved technical effects are also exactly the same, so they will not be elaborated here.

[0047] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural transformation made by using the description and drawings of the present invention under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A control method for DRAM, characterized in that The DRAM includes a plurality of memory cells, and the method includes: Classifying the quality levels of a plurality of memory cells in the DRAM, and confirming the quantity and physical addresses of the memory cells with a plurality of different quality levels; Based on the memory cells with the lowest quality level among the plurality of memory cells, confirming the quality level of the DRAM; Based on the target quality level that the DRAM needs to be improved, performing a removal process on the memory cells with a quality level lower than the target quality level, and remapping the physical addresses of the memory cells with a quality level higher than or equal to the target quality level, so as to obtain a DRAM that meets the requirements of the target quality level.

2. The method for regulating a DRAM according to claim 1, wherein The method for classifying the quality levels of a plurality of memory cells in the DRAM and confirming the quantity and physical addresses of the memory cells with a plurality of different quality levels specifically includes: Performing a quality level test on a plurality of memory cells in the DRAM to obtain the quality parameters of the plurality of memory cells; Based on the quality parameters of the plurality of memory cells, confirming the quality levels of the corresponding memory cells, and classifying and counting the quantity and corresponding physical addresses of the memory cells with each quality level.

3. The control method of the DRAM according to claim 2, wherein, Performing a quality level test on a plurality of memory cells in the DRAM to obtain the quality parameters of the plurality of memory cells; The method for confirming the quality levels of the corresponding memory cells based on the quality parameters of the plurality of memory cells specifically includes: Performing a function test, a charge retention duration test, and a leakage current test on a plurality of memory cells in the DRAM to obtain the function parameters, charge retention duration parameters, and leakage current parameters of the plurality of memory cells; Based on the comparison results between the function parameters, charge retention duration parameters, and leakage current parameters of the plurality of memory cells and the corresponding preset parameters, confirming the quality levels of the corresponding memory cells.

4. The control method of the DRAM according to claim 3, characterized in that, The method for confirming the quality levels of the corresponding memory cells based on the comparison results between the function parameters, charge retention duration parameters, and leakage current parameters of the plurality of memory cells and the corresponding preset parameters specifically includes: The memory cells with the function parameters within the preset function parameter range, the charge retention duration parameter greater than the first preset parameter, and the leakage current parameter less than the second preset parameter are of the first quality level; The memory cells with the function parameters within the preset function parameter range, the charge retention duration parameter less than the first preset parameter, and the leakage current parameter less than the second preset parameter are of the second quality level; The memory cells with the function parameters within the preset function parameter range, the charge retention duration parameter less than the first preset parameter, and the leakage current parameter greater than the second preset parameter are of the third quality level; The memory cells with the function parameters outside the preset function parameter range are faulty memory cells.

5. The control method of the DRAM according to claim 4, wherein, The method for classifying and counting the quantity and corresponding physical addresses of the memory cells with each quality level specifically includes: Confirming the quantity of the memory cells of the first quality level, and identifying the physical addresses of the memory cells of the first quality level; Confirming the quantity of the memory cells of the second quality level, and identifying the physical addresses of the memory cells of the second quality level; Confirm the number of memory cells of the third quality level, and identify the physical addresses of the memory cells of the third quality level; Confirm the number of faulty memory cells, and identify the physical addresses of the faulty memory cells.

6. The control method of the DRAM according to claim 4, wherein, The method for confirming the quality level of the DRAM based on the memory cells of the lowest quality level among the multiple memory cells is specifically as follows: When the number of faulty memory cells is not zero, the DRAM is a faulty DRAM; When the number of memory cells of the third quality level is not zero and the number of faulty memory cells is zero, the DRAM is a DRAM of the third quality level; When the number of memory cells of the second quality level is not zero and the number of memory cells of the third quality level and the number of faulty memory cells are zero, the DRAM is a DRAM of the second quality level; When the number of memory cells of the first quality level is not zero and the number of memory cells of the second quality level, the number of memory cells of the third quality level, and the number of faulty memory cells are zero, the DRAM is a DRAM of the first quality level.

7. The control method of the DRAM according to claim 6, wherein The method for removing memory cells with a quality level lower than the target quality level based on the target quality level to be improved for the DRAM specifically includes: When the target quality level to be improved for the DRAM is the first quality level, remove the memory cells of the second quality level, the memory cells of the third quality level, and the faulty memory cells in the DRAM; When the target quality level to be improved for the DRAM is the second quality level, remove the memory cells of the third quality level and the faulty memory cells in the DRAM; When the target quality level to be improved for the DRAM is the third quality level, remove the faulty memory cells in the DRAM.

8. The control method of the DRAM according to claim 7, wherein The method for remapping the physical addresses of memory cells with a quality level higher than or equal to the target quality level specifically includes: Continuously remap the physical addresses of the memory cells of the first quality level to the first physical address segment; Continuously remap the physical addresses of the memory cells of the second quality level to the second physical address segment; Continuously remap the physical addresses of the memory cells of the third quality level to the third physical address segment; Wherein, the first physical address segment, the second physical address segment, and the third physical address segment are consecutive in sequence.

9. A control device, characterized in that, The control device includes: a memory, a processor, and a control program for the regulation method of the DRAM stored on the memory and running on the processor, and the control program for the regulation method of the DRAM is configured to implement the steps of the regulation method of the DRAM according to any one of claims 1 to 8.

10. A control device, characterized in that, The regulation device includes the control device according to claim 9.

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