Testing method and control device of three-dimensional integrated storage chip

Abstract

The invention relates to a testing method of a three-dimensional integrated chip and a control device. The test method comprises the following steps: sending a chip selection signal to an Mth storage layer of the three-dimensional integrated storage chip to select the Mth storage layer, then performing read-write operation on the Mth storage layer through an IO interface of a logic circuit layer, and disconnecting a data transmission path between a global read-out amplification circuit for receiving write-in data of the Mth storage layer and a corresponding storage array, data written by the read-write operation is isolated in the global read-out amplification circuit, then read out and returned to the logic circuit layer, whether the read data is consistent with the written data or not is judged, if yes, a chip interconnection path between the logic circuit layer and the Mth storage layer has no fault, and if not, a fault exists. According to the test method, the influence of the storage array fault on the test result is eliminated, the accuracy of the test result is improved, and the improvement of the manufacturing process is facilitated. The control device can execute the test method.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a test method for a three-dimensional integrated chip and a control device. Background Art

[0002] A three-dimensional integrated chip includes two or more vertically interconnected chips, which has the advantages of high integration, short response time, low energy consumption, etc. Taking a three-dimensional integrated memory chip as an example, it includes at least two memory dies (such as dram dies) stacked in sequence on a logic die. The logic die forms a logic circuit layer in the three-dimensional integrated memory chip, and each memory die forms a memory layer. The logic circuit layer and each memory layer are vertically interconnected through chip interconnection paths. When the three-dimensional integrated memory chip works, a power supply signal, a control signal, and data are transmitted through the above chip interconnection paths.

[0003] The failure ratio of the chip interconnection paths directly affects the yield of the three-dimensional integrated chip. Therefore, it is particularly important to detect whether there are faults in the chip interconnection paths and locate the fault positions for the improvement of the manufacturing process. However, currently, the faults detected through data read / write tests may be faults in the chip interconnection paths or faults in the memory arrays inside the memory layers, and the fault positions cannot be located, and the fault and fault position information of the chip interconnection paths cannot be determined. Summary of the Invention

[0004] In order to achieve the fault detection of the chip interconnection paths and facilitate the determination of the fault positions, the present invention provides a test method for a three-dimensional integrated memory chip and a control device.

[0005] On the one hand, the present invention provides a test method for a three-dimensional integrated memory chip. The three-dimensional integrated memory chip includes a logic circuit layer and a first memory layer to an Nth memory layer stacked in sequence on one side of the logic circuit layer, where N is an integer greater than 1. The logic circuit layer and each memory layer are vertically interconnected through at least one chip interconnection path. Each memory layer includes a global sense amplifier circuit connected to the logic circuit layer through the corresponding chip interconnection path and a memory array that obtains data through the global sense amplifier circuit. The test method includes: Step 1, sending a chip select signal from the logic circuit layer to the Mth memory layer to select the Mth memory layer, where M is an integer and 1 ≤ M ≤ N, and the remaining memory layers are masked by the chip select signal; Step 2: Perform read and write operations on the M-th storage layer through the IO interface of the logic circuit layer, and disconnect the data transmission path between the global sense amplifier for receiving written data in the M-th storage layer and the corresponding memory array, so that the data written in the read and write operations is isolated in the global sense amplifier and then read out and returned to the logic circuit layer; Step 3: Determine whether the read data is consistent with the written data. If it is consistent, the chip interconnection path between the logic circuit layer and the M-th storage layer is fault-free. If it is inconsistent, the chip interconnection path between the logic circuit layer and the M-th storage layer has a fault.

[0006] Optionally, the N global sense amplifiers respectively provided in the 1st storage layer to the N-th storage layer are connected to the logic circuit layer through a shared chip interconnection path, and the read and write test data is written and read through the chip interconnection path between the M-th storage layer and the logic circuit layer.

[0007] Optionally, the test method includes: Set M to gradually increase from 1 or gradually decrease from N, and loop through Steps 1 to 3 to determine one by one whether there is a fault in the chip interconnection path between the logic circuit layer and the M-th storage layer.

[0008] Optionally, when M is greater than 1 and the chip interconnection path between the logic circuit layer and the (M - 1)-th storage layer is fault-free but the chip interconnection path between the logic circuit layer and the M-th storage layer has a fault, locate the fault in the chip interconnection path between the (M - 1)-th storage layer and the M-th storage layer.

[0009] Optionally, among the 1st storage layer to the N-th storage layer, the first number of global sense amplifiers respectively provided in the first number of storage layers are commonly connected to the first chip interconnection path of the logic circuit layer, and the second number of global sense amplifiers respectively provided in the second number of storage layers are commonly connected to the second chip interconnection path of the logic circuit layer.

[0010] Optionally, the test method includes: Select the memory layers connected by the first chip interconnection path in sequence in a direction from near to far or from far to near relative to the logic circuit layer, and execute the above step 1 to step 3 to determine whether there is a fault in the first chip interconnection path between the logic circuit layer and the corresponding memory layer. When a fault exists, locate the fault in the chip interconnection path between the last two detected memory layers; and, select the memory layers connected by the second chip interconnection path in sequence in a direction from near to far or from far to near relative to the logic circuit layer, and execute the above step 1 to step 3 in the order of moving away from the logic circuit layer to determine whether there is a fault in the second chip interconnection path between the logic circuit layer and the corresponding memory layer. When a fault exists, locate the fault in the second chip interconnection path between the last two detected memory layers.

[0011] Optionally, the global sense amplifier circuit includes a latch. Wherein, in step 2, the data written to the Mth memory layer is temporarily stored in the latch of the corresponding global sense amplifier circuit.

[0012] Optionally, in step 2, when performing read and write tests on the Mth memory layer, the frequency of the test clock used is less than the frequency of the working clock used in the working mode of the three-dimensional integrated memory chip.

[0013] Optionally, the frequency of the working clock is 400 MHz, and the frequency of the test clock is between 40 MHz and 60 MHz.

[0014] Optionally, the chip interconnection path includes TSVs disposed in the logic circuit layer and the 1st to (N - 1)th memory layers to connect the front and back structures of the corresponding layers, and also includes a metal structure for connecting the logic circuit layer and the first memory layer and a metal structure for connecting adjacent two memory layers.

[0015] On the other hand, the present invention provides a control device for controlling a three-dimensional integrated memory chip. When testing whether there is a fault in the chip interconnection path in the three-dimensional integrated memory chip, the control device executes the above test method.

[0016] Optionally, when testing whether there is a fault in the chip interconnection path in the three-dimensional integrated memory chip, the control device sets the three-dimensional integrated memory chip to enter the test mode of the chip interconnection path; and, in response to entering the test mode of the chip interconnection path, the data transmission path between the global sense amplifier circuit for receiving write data and the corresponding memory array in the N memory layers is disconnected, and / or, each memory layer includes P memory cells, where P is an integer greater than 1, and in response to entering the test mode of the chip interconnection path, the data transmission paths between the N*P global sense amplifier circuits and the corresponding memory arrays in the N memory layers are all disconnected.

[0017] In the test method and control device of the three-dimensional integrated memory chip provided by the present invention, in order to determine whether there is a fault in the chip interconnection path, a chip select signal is sent to select the Mth memory layer, and then the Mth memory layer is read and written through the IO interface of the logic circuit layer, and it is judged whether the read data is consistent with the written data. Since the fault on the chip interconnection path between the Mth memory layer and the logic circuit layer will affect data transmission, making the read data different from the written data, and at the same time, since the data transmission path between the global sense amplifier circuit of the Mth memory layer and the corresponding memory array is disconnected, when the read data is inconsistent with the written data, it is determined that there is a fault in the chip interconnection path between the logic circuit layer and the Mth memory layer. In addition, the above test method or control device can also be used to test more than two memory layers sharing the chip interconnection path one by one to locate the fault position of the chip interconnection path. Since the written data is stored in the global sense amplifier circuit of the Mth memory layer and not written into the memory array, the influence of the memory array fault on the test result is excluded, the accuracy of the test result is improved, and it helps to improve the manufacturing process of the three-dimensional integrated memory chip. Brief Description of the Drawings

[0018] Figure 1 is a schematic cross-sectional view of a three-dimensional integrated memory chip in an embodiment of the present invention.

[0019] Figure 2 is a schematic cross-sectional view of a three-dimensional integrated memory chip in another embodiment of the present invention.

[0020] Figure 3 is a schematic diagram of storing data in a three-dimensional integrated memory chip in the working mode in an embodiment of the present invention.

[0021] Figure 4 is a schematic flowchart of a test method for a three-dimensional integrated memory chip according to an embodiment of the present invention.

[0022] Figure 5 is Figure 3Schematic diagram showing that the data transmission path between the global sense amplifier circuit in the M-th memory layer and the corresponding memory array in the second step of the three-dimensional integrated memory chip is disconnected.

[0023] Figure 6 It is a timing diagram of multiple signals during the test of the three-dimensional integrated memory chip in an embodiment of the present invention. Detailed implementation manners

[0024] The following further details the test method and control device of the three-dimensional integrated memory chip of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0025] For ease of understanding, the three-dimensional integrated memory chip involved in the embodiments of the present invention will be described first below.

[0026] Refer to Figure 1 , the three-dimensional integrated memory chip 100 includes a logic circuit layer D0 and the first memory layer D1 to the N-th memory layer DN stacked in sequence on one side of the logic circuit layer D0, where N is an integer greater than 1. Figure 1 Taking N = 4 as an example, the first memory layer D1, the second memory layer D2, the third memory layer, and the fourth memory layer D4 are shown as examples. In the three-dimensional integrated memory chip 100, the logic circuit layer D0 and the first memory layer D1 to the N-th memory layer are respectively bare chips (dies), for example. The front sides of the bare chips where the devices are formed face the same direction, and the back sides face the same direction. The first memory layer D1 to the N-th memory layer DN are stacked on the back side of the logic circuit layer D0, for example.

[0027] The first memory layer D1 to the N-th memory layer DN are used to store data. Each memory layer includes P memory cells (such as Figure 1 the DU shown, the positions and quantities of DU shown in the figure are only examples) to store data, where P is an integer greater than 1. Each memory cell DU is, for example, a "BANK", which includes a memory array (array) having, for example, 16K word lines and 16K bit lines, and the memory array can store 128M bit (i.e., 32M byte) data; however, it is not limited thereto. The number of word lines and bit lines of the memory array is not necessarily equal. For example, a "BANK" can also include a memory array having 2K word lines and 16K bit lines, so that it can store 32M bit (i.e., 4M byte) data.

[0028] The logic circuit layer D0 is formed with logic circuits. When controlling the operation of the memory layer or testing the performance of the memory layer, signals are usually input / output from the IO ports on the side of the logic circuit layer D0 facing away from the first memory layer D1. There are more than one of these IO ports. According to specific settings, these IO ports can be used to transmit power supply signals, control signals, data, etc. For example, independent chip select signals can be sent from the logic circuit layer D0 to each memory layer through specified IO ports.

[0029] As Figure 1 shown, in the three-dimensional integrated memory chip 100, the logic circuit layer D0 and each memory layer are vertically interconnected through at least one chip interconnection path 10 to form a total circuit system. The chip interconnection path 10 may include TSVs disposed in the logic circuit layer D0 and the first to the (N - 1)th memory layers to connect the front and back structures of the corresponding layers. Figure 1 In the embodiment shown, the Nth memory layer DN is, for example, the fourth memory layer D4, that is, N = 4. In addition, the logic circuit layer D0 and the first memory layer D1 are bonded to each other, and adjacent memory layers are also bonded to each other, such as by micro - bump (μBump) connection or hybrid bonding (HB) connection. The chip interconnection path 10 also includes a metal structure for connecting the logic circuit layer D0 and the first memory layer D1 and metal structures for adjacent memory layers. In the following embodiments, hybrid bonding is used between the logic circuit layer D0 and the first memory layer D1 and between adjacent memory layers. The hybrid bonding regions are as Figure 1 shown as "HB" in

[0030] Each memory layer also has an IO interface (as Figure 1 marked as "IO" in the first to the fourth memory layers D1 to D4 in

[0031] Referring to Figure 1 , in one embodiment, the stacked structure of the logic circuit layer D0, the first to the Nth memory layers D1 to DN (for example, N = 4) has a chip interconnection path 10 passing through it. The first to the Nth memory layers D1 to DN are connected to the logic circuit layer D0 through the shared chip interconnection path 10.

[0032] The present invention is not limited to this. In the three - dimensional integrated memory chip of the present invention, the chip interconnection paths connecting to the logic circuit layer may not be shared by all the memory layers. Referring to Figure 2, in another embodiment, the 3D integrated memory chip 101 includes a logic circuit layer D0 and a first memory layer D1 to an Nth memory layer DN stacked in sequence on one side (e.g., the back side) of the logic circuit layer D0, where N is an integer greater than 1, and Figure 1 different from the 3D integrated memory chip 100 shown in Figure 1 , in the 3D integrated memory chip 101, some memory layers (such as the first memory layer D1 and the second memory layer D2) share a first chip interconnection path 11 to connect to the logic circuit layer D0, and another part of the memory layers (such as the third memory layer D3 and the fourth memory layer D4) share a second chip interconnection path 12 to connect to the logic circuit layer D0. Compared with Figure 2 the 3D integrated memory chip 100 in the shown embodiment, in the 3D integrated memory chip 101, signals can be transmitted to the above two parts of the memory layers simultaneously from the logic circuit layer D0 through the first chip interconnection path 11 and the second chip interconnection path 12 respectively, which can increase the bandwidth. Figure 1 For example, the bandwidth of the 3D integrated memory chip 101 including the first chip interconnection path 11 and the second chip interconnection path 12 shown in

[0033] is twice that of the 3D integrated memory chip 100 including only the chip interconnection path 10 shown in Figure 3 . To write data into each memory cell DU of each memory layer or read data from the memory cell DU, corresponding circuits may be provided in each memory layer of the above 3D integrated memory chip 100 or 3D integrated memory chip 101 to form a data transmission path. As an example, referring to Figure 3As shown, a COLEN low-pass high-lock signal can be input from the clock module side to write data into the global sense amplifier circuit, and the RDQS signal is used to read out data. The present invention is not limited thereto, and specific circuit designs for performing read and write tests can also adopt known technologies. For the specific structures of the write controller, global sense amplifier circuit, row decoder, column decoder, and clock module, as well as the process of writing data into the storage unit DU or reading data from the storage unit DU, reference can be made to known technologies. As an example, after the chip is powered on, in order to write data into the storage unit DU, the data is transmitted through the logic circuit layer D0 and the above-mentioned chip interconnection path to the specified storage unit in the specified storage layer, and is first written into the global sense amplifier circuit through the write controller of the specified storage unit via the data channel, and then according to the address of the storage array selected by the row decoder and column decoder, the data is written into the corresponding storage array through the data transmission path between the global sense amplifier circuit and the storage array.

[0034] The following further introduces the test method of the three-dimensional integrated memory chip according to the embodiments of the present invention. As described above, the three-dimensional integrated memory chip includes a logic circuit layer D0 and the first storage layer D1 to the Nth storage layer DN stacked in sequence on one side of the logic circuit layer D0, where N is an integer greater than 1. The logic circuit layer D0 and each storage layer are vertically interconnected through a chip interconnection path. Each storage layer includes a global sense amplifier circuit (global SA or SSA for short) connected to the logic circuit layer D0 through the corresponding chip interconnection path and a storage array that obtains data through the global sense amplifier circuit. Referring to Figure 3 , the test method of the three-dimensional integrated memory chip according to the embodiments of the present invention may include the following steps: Step 1 (S1), send a chip select signal CS from the above-mentioned logic circuit layer D0 to the Mth storage layer to select the Mth storage layer, where M is an integer and 1 ≤ M ≤ N, and the remaining storage layers in the three-dimensional integrated memory chip are shielded by the chip select signal CS; Step 2 (S2), perform read and write operations on the Mth storage layer through the IO interface of the logic circuit layer D0, and disconnect the data transmission path between the global read and write amplifier circuit that receives the written data in the Mth storage layer and the corresponding storage array, so that the data written by the read and write operations is isolated in the global read and write amplifier circuit and then read out and returned to the logic circuit layer D0; Step 3 (S3), determine whether the read data is consistent with the written data. If it is consistent, there is no fault in the chip interconnection path between the logic circuit layer D0 and the Mth storage layer. If it is inconsistent, there is a fault in the chip interconnection path between the logic circuit layer D0 and the Mth storage layer.

[0035] Referring to Figure 1, taking M = 1 as an example, when performing the above test method, in step one, a chip select signal is sent to the first storage layer D1 to select the first storage layer D1; in step two, read and write operations are performed on the selected first storage layer D1 through the IO interface of the logic circuit layer D0, and, by sending corresponding control signals through the logic circuit layer D0, the data transmission path between the global read amplifier circuit that receives the written data and the corresponding storage array during the read and write operations can be disconnected for the first storage layer D1 (if necessary, the data transmission paths between all the global read amplifier circuits of the first storage layer D1 and the corresponding storage arrays can also be disconnected; or, if necessary, the data transmission paths between all the global read amplifier circuits of all N storage layers D1 to DN and the corresponding storage arrays can be disconnected). The purpose is to prevent the written data from being written into any storage array to avoid the influence of the storage array on the test results. In this way, during the read and write operations, the written data will be isolated in the global read amplifier circuit that receives the data. After the read and write operations write data, a read operation is also performed, so that the data isolated in the global read amplifier circuit is read out and returned to the logic circuit layer D0 through the corresponding data channel and the chip interconnection path. It can be seen that if there is a fault in the chip interconnection path 10 between the first storage layer D1 and the logic circuit layer D0, the written data and the read data will be inconsistent. Since the written data does not pass through the storage array of the first storage layer D1, the influence of the storage array on the test results is excluded. When the read data is different from the written data, the possibility of a fault in the storage array is excluded, and the comparison result of the read data and the written data can reflect whether there is a fault in the chip interconnection path between the logic circuit layer D0 and the first storage layer. Step three can be executed in the logic circuit layer D0 or through an external processing device of the chip to determine whether the data read out in the read and write operations in step two is consistent with the written data. If it is consistent, there is no fault in the chip interconnection path 10 between the logic circuit layer D0 and the first storage layer D1; if it is inconsistent, there is a fault in the chip interconnection path 10 between the logic circuit layer D0 and the first storage layer D1.

[0036] It should be noted that in the above test method for the three-dimensional integrated memory chip, step three is executed only on the basis that the operations of sending the chip select signal described in step one and writing and reading data described in step two are all effective. Since the transmission of the chip select signal and the data both pass through the chip interconnection path, if the chip select signal is invalid, the written data is invalid, or the read data is invalid, it can be directly concluded that there is a fault in the corresponding chip interconnection path or there is a problem with the test settings, and the test can be ended or further confirmation can be made.

[0037] The value of M can be set as needed and the above steps 1 to 3 can be performed to obtain information on whether there is a fault in the chip interconnection path between the logic circuit layer D0 and the corresponding M-th memory layer. When M>1 and after the above steps, it is found that there is a fault in the chip interconnection path between the logic circuit layer D0 and the M-th memory layer. Since this chip interconnection path also connects the logic circuit layer D0 and the memory layers between the logic circuit layer D0 and the M-th memory layer, in order to further locate where the fault occurs in this chip interconnection path, it is also necessary to determine whether there is a fault in the chip interconnection path between the memory layer below the M-th memory layer and the logic circuit layer D0.

[0038] Refer to Figure 1 , in an embodiment, in the three-dimensional integrated memory chip 100, the N global sense amplifier circuits respectively disposed in the first memory layer D1 to the N-th memory layer DN are connected to the logic circuit layer D0 through a shared chip interconnection path 10. In order to detect faults on the chip interconnection path 10 and locate the specific position of the fault, in the test method, M is set to gradually increase from 1 (the maximum value is N) or gradually decrease from N (the minimum value is 1), and the above steps 1 to 3 are repeatedly executed to successively determine whether there is a fault in the chip interconnection path 10 between the logic circuit layer D0 and the M-th memory layer. Optionally, when M>1 and there is no fault in the chip interconnection path 10 between the logic circuit layer D0 and the (M-1)-th memory layer but there is a fault in the chip interconnection path 10 between the logic circuit layer D0 and the M-th memory layer, it is located that the fault is in the chip interconnection path 10 between the (M-1)-th memory layer and the M-th memory layer.

[0039] Refer to Figure 2, in another embodiment, in the three-dimensional integrated memory chip 101, the first number of global sense amplifier circuits respectively disposed in the first number of memory layers (such as the first memory layer D1 and the second memory layer D2) are commonly connected to the first chip interconnection path 11 of the logic circuit layer D0, and the second number of global sense amplifier circuits respectively disposed in the second number of memory layers (such as the third memory layer D3 and the fourth memory layer D4) are commonly connected to the second chip interconnection path 12 of the logic circuit layer D0. At this time, it is necessary to test and locate the fault positions for the first chip interconnection path 11 and the second chip interconnection path 12 respectively. The specific process may include the following: Along the direction from near to far or from far to near with respect to the logic circuit layer D0, sequentially select the memory layers connected to the first chip interconnection path 11 to execute the above-mentioned steps 1 to 3 to determine whether there is a fault in the first chip interconnection path 11 between the logic circuit layer D0 and the corresponding memory layer. When a fault exists, locate the fault in the first chip interconnection path 11 between the last two detected memory layers; and, also along the direction from near to far or from far to near with respect to the logic circuit layer D0, sequentially select the memory layers connected to the second chip interconnection path 12, and repeatedly execute the above-mentioned steps 1 to 3 to determine whether there is a fault in the second chip interconnection path 12 between the logic circuit layer D0 and the corresponding memory layer. When a fault exists, locate the fault in the second chip interconnection path 12 between the last two detected memory layers. The above-mentioned fault detection for the first chip interconnection path 11 and the first chip interconnection path 11 can be carried out independently of each other.

[0040] In the above test method, in step 2, by disconnecting the data transmission path between the global sense amplifier circuit that receives the written data in the Mth memory layer and the corresponding memory array, the data written by the read-write operation is isolated in the global sense amplifier circuit and will not be written into the memory array of the Mth memory layer where it is located, which can eliminate the influence of the memory array on the test result. Figure 5 shows Figure 3 Schematic diagram of the data transmission path between the global sense amplifier circuit (SSA) in the Mth memory layer and the corresponding memory array of the three-dimensional integrated memory chip shown in step 2 being disconnected. As Figure 5 shown, in this embodiment, in order to eliminate the possibility that the read data and the written data are different and there may also be a fault in the memory array, before writing the data, disconnect the data transmission path between the global sense amplifier circuit that receives the written data in the Mth memory layer and the corresponding memory array. It can be achieved by cutting off the connection between the row decoder and the global sense amplifier circuit and the data channel ( Figure 5The cross in it indicates the cutting position), disconnecting the data transmission path between the corresponding global sense amplifier circuit and the corresponding memory array. In this way, during the read and write operations in step two, data is only transmitted to the global sense amplifier circuit through the chip interconnection path and the circuit on the Mth memory layer, and will not be written into the corresponding memory array. The global sense amplifier circuit includes, for example, a latch. In step two, the data written to the Mth memory layer is temporarily stored in the latch of the corresponding global sense amplifier circuit.

[0041] In addition, in order to rule out the risk of misjudging a fault in the chip interconnection path due to read and write errors caused by circuit timing, which may lead to inconsistent data detected in step three between the read data and the written data, compared with the frequency of the working clock used in the working mode of the three-dimensional integrated memory chip, the period of the test clock used when performing read and write operations on the Mth memory layer through the IO interface of the logic circuit layer D0 can be relaxed, which can reduce the possibility of read and write errors caused by circuit timing. In one embodiment, when performing read and write tests on the Mth memory layer in step two above, the frequency of the test clock used is less than the frequency of the working clock used in the working mode of the three-dimensional integrated chip (such as during normal read and write). For example, the frequency of the working clock is 400 MHz, and the frequency of the test clock is between 40 MHz and 60 MHz, such as 50 MHz.

[0042] To execute the above test method, the three-dimensional integrated memory chip to be tested can be connected to a test motherboard, and then the read and write mode can be configured, such as setting the timing, address mapping mode, and clock signal for read and write operations, and then data can be written and read through a programmer or the debug interface on the test motherboard. Figure 6 Schematically shows the timing of multiple signals when testing the three-dimensional integrated memory chip. Refer to Figure 6 , as an example, when performing step one, based on the clock signal CLK (such as a test clock with a frequency lower than the working clock), control the chip select signal DU0_CS corresponding to the Mth memory layer to change from low level to high level, and the Mth memory layer is selected; when performing step two, first make the write enable signal DU0_WE high level to write data to the Mth memory layer, and during the period when the write enable signal DU0_WE is high level, also control DU0_COLEN to write data to the latch of the above global sense amplifier circuit from low to high and lock it, Figure 6 where MC0_SSA represents the state of the latch; then, the write enable signal DU0_WE becomes low level, the read enable signal DU0_RE is high level, and the pulse falling edge of the DU0_RDQS signal reads the data in the latch to the corresponding IO port (such as the DIO (digital IO) port) of the logic circuit layer D0. Figure 6 where DU0_DIO represents the data state of the DIO port.

[0043] Using the test method of the three-dimensional integrated memory chip described in the above embodiments, it is possible to detect whether there is a fault in the chip interconnection path between the Mth memory layer and the logic circuit layer D0, and eliminate the influence of the fault of the memory array on the test result, improving the test accuracy. By testing for continuous M values in a loop, the fault location can also be determined. The test result obtained by using the above test method helps to improve the manufacturing process of the three-dimensional integrated memory chip.

[0044] An embodiment of the present invention also relates to a control device, which is used to control, for example, a three-dimensional integrated memory chip. When testing whether there is a fault in the chip interconnection path in the three-dimensional integrated memory chip, the control device executes the test method of the three-dimensional integrated memory chip described in the above embodiments. The concept of the test method can be referred to the description of the above embodiments.

[0045] When testing whether there is a fault in the chip interconnection path in the three-dimensional integrated memory chip, the control device can, through parameter settings, make the three-dimensional integrated memory chip enter the test mode of the chip interconnection path. In one embodiment, in response to entering the test mode of the chip interconnection path (TSV / HB test mode), the data transmission path between the global sense amplifier circuit for receiving write data and the corresponding memory array in the N memory layers of the three-dimensional integrated memory chip is disconnected. In another embodiment, each memory layer of the three-dimensional integrated memory chip further includes P memory cells DU (P is an integer greater than 1). In response to entering the test mode of the chip interconnection path (TSV / HB test mode), the data transmission paths between the N*P global sense amplifier circuits in the N memory layers and the corresponding memory arrays are all disconnected. In some embodiments, by configuring the parameters of the mode register (Mode Register, MR) in the three-dimensional integrated memory chip, the entire three-dimensional integrated memory chip can enter the test mode of the chip interconnection path (TSV / HB test mode).

[0046] The control device may include a processor and a storage medium. The storage medium stores executable instructions corresponding to the test method. When the processor executes the executable instructions, the above test method is executed.

[0047] The control device according to the embodiment of the present invention can execute the above test method, can achieve the fault detection of the chip interconnection path and facilitate the determination of the fault location, and can be used to improve the manufacturing process of the three-dimensional integrated memory chip.

[0048] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A test method for a three-dimensional integrated memory chip, characterized in that The three-dimensional integrated memory chip includes a logic circuit layer and a first memory layer to an Nth memory layer stacked in sequence on one side of the logic circuit layer, where N is an integer greater than 1. The logic circuit layer and each memory layer are vertically interconnected through at least one chip interconnection path. Each memory layer includes a global sense amplifier circuit connected to the logic circuit layer through the corresponding chip interconnection path and a memory array that obtains data through the global sense amplifier circuit. The test method includes: Step 1: Send a chip select signal from the logic circuit layer to the Mth memory layer to select the Mth memory layer, where M is an integer and 1 ≤ M ≤ N, and the remaining memory layers are masked by the chip select signal. Step 2: Perform read and write operations on the Mth memory layer through the IO interface of the logic circuit layer, and disconnect the data transmission path between the global sense amplifier circuit that receives the written data in the Mth memory layer and the corresponding memory array, so that the data written in the read and write operations is isolated in the global sense amplifier circuit and then read out and returned to the logic circuit layer. Step 3: Determine whether the read data is consistent with the written data. If it is consistent, there is no fault in the chip interconnection path between the logic circuit layer and the Mth memory layer; if it is inconsistent, there is a fault in the chip interconnection path between the logic circuit layer and the Mth memory layer.

2. The test method according to claim 1, characterized in that, The N global sense amplifier circuits respectively provided in the first memory layer to the Nth memory layer are connected to the logic circuit layer through a shared chip interconnection path, and the read and write test data is written and read through the chip interconnection path between the Mth memory layer and the logic circuit layer.

3. The testing method according to claim 2, wherein Including: Set M to gradually increase from 1 or gradually decrease from N, and loop through Steps 1 to 3 to determine one by one whether there is a fault in the chip interconnection path between the logic circuit layer and the Mth memory layer.

4. The test method according to claim 3, characterized in that When M is greater than 1 and there is no fault in the chip interconnection path between the logic circuit layer and the (M - 1)th memory layer but there is a fault in the chip interconnection path between the logic circuit layer and the Mth memory layer, locate that the fault is in the chip interconnection path between the (M - 1)th memory layer and the Mth memory layer.

5. The testing method according to claim 1, characterized in that, Among the first memory layer to the Nth memory layer, the first number of global sense amplifier circuits respectively provided in the first number of memory layers are commonly connected to the first chip interconnection path of the logic circuit layer, and the second number of global sense amplifier circuits respectively provided in the second number of memory layers are commonly connected to the second chip interconnection path of the logic circuit layer.

6. The test method according to claim 5, characterized in that, Select the memory layers connected by the first chip interconnection path in sequence in the direction from near to far or from far to near relative to the logic circuit layer, and perform Steps 1 to 3 to determine whether there is a fault in the first chip interconnection path between the logic circuit layer and the corresponding memory layer. When there is a fault, locate that the fault is in the chip interconnection path between the last two detected memory layers. Moreover, along the direction from near to far or from far to near relative to the logic circuit layer, in the order of moving away from the logic circuit layer, the storage layers connected by the second chip interconnection paths are sequentially selected to execute the first to third steps to determine whether there are faults in the second chip interconnection paths between the logic circuit layer and the corresponding storage layers. When a fault exists, the fault is located in the second chip interconnection path between the two storage layers detected last.

7. The test method according to claim 1, characterized in that, The global sense amplifier circuit includes a latch. Among them, in the second step, the data written to the Mth storage layer is temporarily stored in the latch of the corresponding global sense amplifier circuit.

8. The test method according to claim 1, characterized in that In the second step, when performing read and write tests on the Mth storage layer, the frequency of the test clock used is less than the frequency of the working clock used in the working mode of the three-dimensional integrated memory chip.

9. The testing method according to claim 8, characterized in that, The frequency of the working clock is 400 MHz, and the frequency of the test clock is between 40 MHz and 60 MHz.

10. The test method according to any one of claims 1 to 9, characterized in that, The chip interconnection path includes TSVs provided in the logic circuit layer and the first to (N - 1)th storage layers to connect the front and back structures of the corresponding layers, and also includes a metal structure for connecting the logic circuit layer and the first storage layer and a metal structure for connecting adjacent two storage layers.

11. A control device, characterized in that, It is used to control a three-dimensional integrated memory chip. Among them, when testing whether there are faults in the chip interconnection paths in the three-dimensional integrated memory chip, the control device executes the test method according to any one of claims 1 to 10.

12. The control device according to claim 11, wherein When testing whether there are faults in the chip interconnection paths in the three-dimensional integrated memory chip, the control device sets the three-dimensional integrated memory chip to enter the test mode of the chip interconnection paths; and, in response to entering the test mode of the chip interconnection paths, the data transmission paths between the global sense amplifier circuits for receiving written data and the corresponding memory arrays in the N storage layers are disconnected, and / or, each storage layer includes P memory cells, where P is an integer greater than 1. In response to entering the test mode of the chip interconnection paths, the data transmission paths between the N*P global sense amplifier circuits and the corresponding memory arrays in the N storage layers are all disconnected.

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