Self-repairing system, method and equipment suitable for SRAM (Static Random Access Memory) and medium
By instantiating the built-in self-test controller and logical design repair module in the sram_wrapper layer of SRAM, the problem of limited application of BISR technology in SRAM is solved, and the repair function in MBIST mode is realized, reducing hardware resource consumption and chip cost.
Patent Information
- Application Number
- CN202510425605.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2025-07-08
AI Technical Summary
In the prior art, the built-in self-repair (BISR) technology of SRAM is limited in application, resulting in increased hardware resource consumption and increased design and manufacturing complexity, and MBIST logic cannot implement repair functions in SRAM.
By instantiating the built-in self-test controller and memory interface in the sram_wrapper layer of SRAM, combining the logically designed SRAM repair module, a repair-related signal is generated to realize the repair function of SRAM in MBIST mode.
It realizes that SRAM has repair functions in MBIST mode, reduces hardware resource consumption, optimizes redundant resource usage, saves chip area and power consumption, and facilitates post-debugging and maintenance.
Smart Images
Figure CN120279973A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and particularly to a self-repair system, method, device and medium applicable to SRAM. Background Art
[0002] In the prior art, when a fault occurs in a memory, the memory built-in self-repair (MBIST) module records the specific location of the memory fault and transfers the relevant information to the built-in self-repair (BISR) module. The built-in self-repair technology is adopted to determine the repair strategy according to the fault type and location and automatically execute the repair operation. However, the BISR technology is usually used for the repair of vulnerable memories such as DRAM, especially to replace the faulty unit with a redundant unit when a fault occurs. For SRAM, due to its different structure and working principle, the application of BISR is relatively limited. First, the SRAM storage cell is composed of multiple transistors, and each storage cell has its own stable data retention ability. Compared with the single-transistor + capacitor structure of DRAM, SRAM is less likely to have unit-level faults. Second, the probability of faults occurring during the operation of SRAM is lower than that of DRAM, especially during the manufacturing process, and its failure rate is usually lower than that of DRAM. Therefore, SRAM generally does not need to rely on redundant units and repair mechanisms as much as DRAM.
[0003] In the application scenario of SRAM, if the BISR technology is used, additional circuits are required to perform functions such as fault detection, repair control, and address mapping, which will cause unnecessary consumption of hardware resources. This will increase the complexity of design and manufacturing, resulting in additional R & D costs and production costs. If the BISR hardware repair technology is not adopted and the SRAM repair module is written in a logic language, information such as repair signals and the positions of redundant replacement units will be generated. Combining with the existing MBIST technology, there is a problem: the MBIST logic generated by the design for testability (DFT) tool will be inserted between the SRAM control unit and the memory interface (memory_interface), which is usually called the sram_wrapper layer. The automatically generated MBIST-related logic does not contain the signals related to the repair function required by SRAM. The SRAM cannot access the registers related to the repair function after being gated by MBIST, that is, it does not have the repair function. Summary of the Invention
[0004] In view of this, the purpose of the present invention is to provide a self-repair system, method, device and medium applicable to SRAM, which adopts logic to implement the SRAM repair function, thereby avoiding unnecessary resource consumption by the BISR hardware repair circuit. Combining with the MBIST logic generated by the DFT tool, the SRAM can also access the registers related to the repair in the MBIST working mode and has the repair function.
[0005] According to one aspect of the present invention, there is provided a self - repair system applicable to SRAM, including:
[0006] A built - in self - test controller and an SRAM repair module connected through a memory interface;
[0007] The built - in self - test controller is used to perform a fault test on the SRAM;
[0008] The SRAM repair module is used to generate repair - related signals and apply the repair - related signals to the SRAM under test.
[0009] Optionally, the built - in self - test controller, the memory interface, and the SRAM repair module are all instantiated in the sram_wrapper layer.
[0010] Optionally, it further includes extracting the built - in self - test controller and the memory interface from the sram_sub_top layer and then instantiating them in the sram_wrapper layer.
[0011] Optionally, the built - in self - test controller includes a state machine and a comparison module. The state machine is used to perform specific Pattern read - write tests on the SRAM under test; the comparison module is used to compare the read - write values of the SRAM. If they are different, it marks the fault information; the SRAM repair module includes a judgment module and a remapping module. The judgment module is used to formulate a repair strategy according to the fault information and generate the coordinates of redundant units for replacing the faulty location; the remapping module is used to complete the mapping of the current test address and the coordinates of the redundant units, and when mbist_en is turned on, the SRAM repair module generates repair - related signals and transmits them to the SRAM under test to complete the repair.
[0012] Optionally, the SRAM repair module is written in a logic language so that it can read the fault information obtained from the specific Pattern read - write test.
[0013] Optionally, it further includes a three - to - one multiplexer, which is used to select one of the input signals in the SRAM repair module. When the memory interface is selected, it generates repair - related signals and applies the repair - related signals to the SRAM under test.
[0014] Optionally, the SRAM under test includes two large - block SRAMs, which store high - address data and low - address data respectively
[0015] According to another aspect of the present invention, a self - repair method applicable to SRAM is further provided. When mbist_en is turned on, the state machine of the built - in self - test controller is started to perform specific Pattern read - write tests on the SRAM under test; the read - write values of the SRAM are compared in the comparison module. If they are different, fault information is marked and passed to the judgment module; in the judgment module, a repair strategy is formulated based on the fault information to generate the coordinates of redundant cells for replacing the faulty positions. Then, in the remapping module, the current test address and the coordinates of the redundant cells are mapped. When mbist_en is turned on, the SRAM repair module generates repair - related signals and passes them to the SRAM under test to complete the repair.
[0016] According to another aspect of the present invention, a computer device is further provided, including: a processor and a memory storing computer program instructions; the memory includes at least one SRAM, and the processor reads and executes the computer program instructions to implement the self - repair method according to any embodiment of the present invention.
[0017] According to another aspect of the present invention, a computer - readable storage medium is further provided. Computer program instructions are stored on the computer - readable storage medium, and when the computer program instructions are executed by a processor, the self - repair method according to any embodiment of the present invention is implemented.
[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: For SRAM, an MBIST logic modification scheme is provided, which can be compatible with SRAM with or without a repair function, and can complete the insertion of its MBIST logic, which is helpful for later testing; a solution for inserting MBIST for multiple SRAMs with a repair function is provided; the repair_ip designed logically collaborates with the MBIST logic generated by the DFT tool. When an SRAM fault is detected, based on redundant resources and logical mapping, a repair strategy can be generated in a timely manner at a lower cost to repair the SRAM, which can be better optimized for specific design requirements, precisely control the use of redundant resources, further save chip area and power consumption, and is also convenient for later debugging and maintenance. Description of the Drawings
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0020] Figure 1 It is a block diagram of the relationship between TMB, memory_interface and SRAM in the prior art;
[0021] Figure 2 This is the logic block diagram of the digital system of the SRAM MBIST of the present invention;
[0022] Figure 3 This is the block diagram of the MBIST system without repair function;
[0023] Figure 4 This is the block diagram of the MBIST system with repair function;
[0024] Figure 5 This is the block diagram of the relationship between TMB and the repair module. Specific implementation manners
[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0026] In the related art, the built-in self-test controller is a part of the MBIST, which is responsible for generating, managing, and executing test patterns, control sequences, and data streams to comprehensively test and verify the SRAM; in this embodiment, the built-in self-test controller TMB (Tessent Memory BIST Controller) in the Tessent tool of Siemens Corporation is taken as an example; the memory interface memory_Interface provides a channel for connection and interaction to realize the communication between the TMB and the SRAM to be tested. The specific relationship diagram is as Figure 1 shown, the TMB and the memory_interface are instantiated in the sram_sub_top layer where the SRAM is located. When the Tessent tool automatically generates the MBIST-related logic and selects the MBIST path, it does not have the repair function.
[0027] The embodiment of the present invention provides a self-repair system for SRAM. Specifically, an SRAM repair module is applied to repair the SRAM when the MBIST detects an error in the SRAM. This function can be applied to two large blocks of SRAM, which respectively store high-address data and low-address data, named u_sram_l and u_sram_h. Figure 2Shows the connection relationship between the SRAM MBIST logic and the original design. Among them, in the simulation top layer (testbench), there are a digital circuit part (digital) and an analog circuit (analog) part. The common_wrapper part in digital contains mbist_controller_no_repair, mbist_bap_tdr, and mbist_controller_sib, which control the mbist_controller. Among them, mbist_controller_no_repair is the controller for SRAM without repair function; the mbist_controller in sram_wrapper controls the SRAM with repair function.
[0028] In this embodiment, TMB (mbist_controller) and memory_iterface are extracted from the sram_sub_top layer and moved to the sram_wrapper layer. The mbist_interface serves as a bridge to connect the mbist_controller and the SRAM repair module (repair_ip), and interacts with the SRAM, so that the SRAM has a repair function.
[0029] As Figure 3 shown, in this scheme, when the Tessent MBIST branch is selected, the repair-related signals of the repair_ip cannot act on the SRAM, so the repair function cannot take effect. And in this embodiment, as Figure 4 shown, whether the Tessent MBIST or the function branch is selected, the repair-related signals of the repair_ip can act on the SRAM, so the repair function can always take effect.
[0030] Furthermore, as Figure 2 shown, a multiplexer (MUX) for input signals is made in the SRAM repair module (repair_ip), so that when the MBIST is strobed, the corresponding repair signal can be selected for output, enabling the SRAM to have a repair function.
[0031] Further, in repair_ip, a three - way MUX is implemented to select one path from the Tessent interface, the sram function interface, and the debug interface to connect to u_sram_l and u_sram_h. Among them, the Tessent interface is the memory_interface, which is the interface for controlling the SRAM through the mbist_controller; the function interface is the interface for normal access to the SRAM; the debug interface is a channel for writing a specific value through a register and then reading it for SRAM debugging. Each group of interfaces includes signals such as chip select, read / write, and address of the SRAM.
[0032] Further, the SRAM repair module is written in a logic language so that it can read the fault information obtained from the read - write test based on a specific Pattern. Therefore, the repair_ip designed with logic collaborates with the MBIST logic generated by the Tessent tool. When an SRAM fault is detected, based on redundant resources and logical mapping, a repair strategy can be generated in a timely manner at a lower cost to repair the SRAM. It can be better optimized for specific design requirements, precisely control the use of redundant resources, avoid using the automatically instantiated repair circuit of Tessent for repair, thereby further saving chip area and power consumption, and facilitating later debugging and maintenance.
[0033] An embodiment of the present invention also provides a self - repair method for SRAM. When mbist_en is turned on, the MBIST state machine (FSM) is started to perform a specific Pattern read - write test on the SRAM under test; in the Compare module, the read - write values of the SRAM are compared. If they are different, the fault information is marked and passed to the next module; in the Judge module, a repair strategy is formulated according to the fault information to generate the coordinates repair_addr of the redundant unit used to replace the faulty location; in the Remapping module, the mapping of the current test address function_addr and repair_addr is completed, and when mbist_en is turned on, the Repair module generates the signals required for repair and passes them to the SRAM under test to complete the repair.
[0034] An embodiment of the present invention also provides a computer device, including: a processor and a memory storing computer program instructions; the memory includes at least one SRAM, and the processor reads and executes the computer program instructions to implement the self - repair method according to any embodiment of the present invention.
[0035] An embodiment of the present invention further provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the self-repair method described in any embodiment of the present invention is implemented.
[0036] It should be clear that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, the detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order between steps after understanding the spirit of this application.
[0037] The functional blocks shown in the above block diagrams can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium or transmitted via a data signal carried in a carrier wave on a transmission medium or a communication link. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable read-only memory (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical discs, hard disks, fiber optic media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.
[0038] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. That is, the steps can be executed in the order mentioned in the embodiments, or different from the order in the embodiments, or several steps can be executed simultaneously.
[0039] Aspects of the present disclosure have been described above with reference to the flowchart and / or block diagram of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block in the flowchart and / or block diagram, and the combinations of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing apparatus enable the implementation of the functions / acts specified in one or more blocks of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It is also understood that each block in the block diagram and / or flowchart, and the combinations of blocks in the block diagram and / or flowchart, can also be implemented by dedicated hardware performing the specified functions or acts, or by a combination of dedicated hardware and computer instructions.
[0040] It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and these modifications or substitutions should all be covered within the scope of protection of the present application.
Claims
1. A self - repair system applicable to SRAM, characterized in that, Comprising: A built-in self-test controller and an SRAM repair module connected through a memory interface; The built-in self-test controller is used to perform a fault test on the SRAM; The SRAM repair module is used to generate repair-related signals and apply the repair-related signals to the SRAM under test.
2. The self-healing system according to claim 1, wherein The built-in self-test controller, the memory interface, and the SRAM repair module are all instantiated in the sram_wrapper layer.
3. The self-healing system according to claim 2, wherein The instantiation in the sram_wrapper layer includes extracting the built-in self-test controller and the memory interface from the sram_sub_top layer and then instantiating them in the sram_wrapper layer.
4. The self-repair system according to claim 1, wherein The built-in self-test controller includes a state machine and a comparison module. The state machine is used to perform a specific Pattern read / write test on the SRAM under test when mbist_en is turned on; the comparison module is used to compare the read / write values of the SRAM under test. If they are different, fault information is marked; The SRAM repair module includes a judgment module and a remapping module. The judgment module is used to formulate a repair strategy based on the fault information and generate the coordinates of redundant cells for replacing the faulty location; the remapping module is used to complete the mapping of the current test address and the coordinates of the redundant cells, and when mbist_en is turned on, the SRAM repair module generates repair-related signals and transmits them to the SRAM under test to complete the repair.
5. The self-healing system according to claim 4, wherein The SRAM repair module is written in a logic language so that it can read the fault information obtained from the specific Pattern read / write test.
6. The self-healing system according to claim 1, characterized in that It further includes a three-way multiplexer for selecting one of three input signals in the SRAM repair module. When the memory interface is selected, repair-related signals are generated and applied to the SRAM under test.
7. The self-healing system according to claim 1, wherein, The SRAM under test includes two large blocks of SRAM, which store high-address data and low-address data respectively.
8. A self - repair method using the self - repair system applicable to SRAM as described in any one of claims 1 - 7, characterized in that, Comprising: When mbist_en is turned on, start the state machine of the built-in self-test controller to perform a specific Pattern read / write test on the SRAM under test; compare the read / write values of the SRAM under test in the comparison module. If they are different, mark the fault information and transmit it to the judgment module; formulate a repair strategy based on the fault information in the judgment module to generate the coordinates of redundant cells for replacing the faulty location, then complete the mapping of the current test address and the coordinates of the redundant cells in the remapping module, and when mbist_en is turned on, the SRAM repair module generates repair-related signals and transmits them to the SRAM under test to complete the repair.
9. A computer device, characterized in that, The computer device includes: a processor and a memory storing computer program instructions; the memory includes at least one SRAM, and the processor reads and executes the computer program instructions to implement the self-repair method according to claim 8.
10. A computer-readable storage medium, characterized in that, Computer program instructions are stored on the computer-readable storage medium, and when the computer program instructions are executed by the processor, the self-repair method according to claim 8 is implemented.