A test optimization method and system for large capacity 3D flash memory

Abstract

The application relates to a large-capacity 3D flash memory test optimization method and system, which comprises the following steps: based on a reference temperature and a target temperature, performing multiple reliability tests on random storage units in a target flash memory chip through grouping; collecting test data of the target chip under the reference temperature and the target temperature for reliability test respectively, and constructing a data sample set according to the test data; based on the data sample set and a few-sample training method, training a discriminator model for judging whether a flash memory chip is faulty; obtaining test data of the target flash memory chip under the target temperature for reliability test, and inputting the test data into the discriminator model to obtain a test result of the target flash memory chip. The application optimizes the large-capacity 3D flash memory chip test process by selecting characteristic storage units and predicting the test result under the target temperature through the discriminator, a small amount of test data analysis obtains the test result, and the test time is greatly shortened and the test efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of flash memory reliability testing, and particularly relates to a test optimization method and system for large-capacity 3D flash memory, and particularly relates to a flash memory reliability multi-temperature test method and system for long-time storage. BACKGROUND

[0002] With the rapid development of big data, cloud computing, Internet of Things and other technologies, the amount of information that needs to be stored and analyzed is growing explosively, and the demand for storage capacity is increasing. In order to obtain greater storage capacity and higher storage density, flash memory manufacturers and users have shifted their focus from planar architecture to 3D architecture. Under long-term use and different environmental conditions, flash memory may have problems such as data loss or damage, and needs to be tested for reliability to discover and solve potential problems in advance. Therefore, 3D NAND flash memory reliability testing is crucial for mining its reliability characteristics, improving product quality, ensuring data security, and promoting its widespread application in various fields.

[0003] In order to obtain error characteristics at different temperatures, the traditional test method needs to design experiments for different temperatures to obtain a large amount of data. However, this process consumes a lot of flash memory particle life, resulting in very high test costs. SUMMARY

[0004] In order to reduce the test cost of flash memory and improve the test accuracy, in a first aspect of the present application, a test optimization method for large-capacity 3D flash memory is provided, comprising: based on a reference temperature and a target temperature, performing multiple reliability tests on random storage units in a target flash memory chip through grouping; collecting test data of the target chip at the reference temperature and the target temperature for reliability testing, and constructing a data sample set according to the test data; the test data includes storage location, read / write times, read / write time and abnormal information; based on the data sample set and a few sample training method, training a discriminator model for judging whether a flash memory chip has failed; obtaining test data of the target flash memory chip under the target temperature for reliability testing, and inputting the test data into the discriminator model to obtain the test result of the target flash memory chip.

[0005] In some embodiments of the present application, the multiple reliability tests on random storage units in the target flash memory chip through grouping based on the reference temperature and the target temperature include: randomly sampling from a plurality of target chips, and dividing the sampled target chips into two groups based on the reference temperature and the target temperature; based on the reference temperature and the target temperature, performing programming, erasing and reading cycle tests on the two groups of target chips, respectively.

[0006] Further, the programming, erasing and reading cycle test on the two groups of target chips comprises: in each cycle test, sequentially performing erasing, writing, programming and reading operations on the target chips, and marking the failed operation; judging whether the tested target chip has a fault, and determining whether to end the cycle test according to the judgment result.

[0007] In some embodiments of the present application, the training of the discriminator model for judging whether the flash memory chip has a fault based on the data sample set and the few-sample training method comprises: taking the test data of the target chip in N times of reliability tests at the reference temperature and the target temperature as samples, where n≥1000; taking the test data of n times of reliability tests at the reference temperature and the target temperature as samples, and taking the result of m times of reliability tests at the target temperature as a label, where m>n; and training the discriminator model for judging whether the flash memory chip has a fault based on the samples and the label through the few-sample training method.

[0008] Further, .

[0009] In the above embodiments, the discriminator model is a neural network.

[0010] In a second aspect of the present application, a test optimization system for large-capacity 3D flash memory is provided, comprising: a test module for performing multiple reliability tests on random storage units in a target flash memory chip based on a reference temperature and a target temperature through grouping; a construction module for respectively collecting test data of the target chip in reliability tests at the reference temperature and the target temperature, and constructing a data sample set according to the test data; the test data comprises storage location, read / write times, read / write time and abnormal information; a training module for training a discriminator model for judging whether the flash memory chip has a fault based on the data sample set and a few-sample training method; and a judgment module for obtaining test data of the target flash memory chip in a reliability test at the target temperature, and inputting the test data into the discriminator model to obtain a test result of the target flash memory chip.

[0011] Further, the test module comprises: a sampling unit for randomly sampling from a plurality of target chips, and dividing the sampled target chips into two groups based on the reference temperature and the target temperature; and a test unit for performing programming, erasing and reading cycle tests on the two groups of target chips based on the reference temperature and the target temperature.

[0012] In a third aspect of the present application, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the test optimization method for large-capacity 3D flash memory provided in the first aspect of the present application.

[0013] In a fourth aspect, the present application provides a computer readable medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the method for testing optimization of large-capacity 3D flash memory provided in the first aspect of the present application.

[0014] The present application has the following beneficial effects:

[0015] The present application designs an optimization method for multi-temperature testing of flash memory reliability for long-term storage. The reliability testing method is designed based on the 3D NAND flash memory reliability mechanism, which can accurately simulate and predict the reliability decline process of flash memory chips at different temperatures during data retention. The modeling method establishes a model based on test data at room temperature, and uses a small amount of data in multi-temperature testing to train the model, thereby obtaining accurate prediction results at a lower testing cost and improving the universality of the model. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A basic flowchart of the method for testing optimization of large-capacity 3D flash memory in some embodiments of the present application;

[0017] Figure 2 A specific flowchart of the method for testing optimization of large-capacity 3D flash memory in some embodiments of the present application;

[0018] Figure 3 A flowchart of the room temperature programming / erasing / reading cycle test in some embodiments of the present application;

[0019] Figure 4 A flowchart of the programming / erasing / reading test at the target temperature in some embodiments of the present application;

[0020] Figure 5 A flowchart of establishing a discriminator mathematical model in some embodiments of the present application;

[0021] Figure 6 A structure diagram of the discriminator model in some embodiments of the present application;

[0022] Figure 7 A specific structure diagram of the large-capacity 3D flash memory testing optimization system in some embodiments of the present application;

[0023] Figure 8 A structure diagram of the large-capacity 3D flash memory testing optimization device in some embodiments of the present application;

[0024] Figure 9 A structure diagram of the electronic device in some embodiments of the present application. DETAILED DESCRIPTION

[0025] The principles and features of the present application are described below in conjunction with the accompanying drawings, in which the examples are used to explain the present application and are not intended to limit the scope of the present application.

[0026] Reference Figures 1 to 3 In a first aspect of the present application, a test optimization method for large-capacity 3D flash memory is provided, comprising: S100. Based on the reference temperature and the target temperature, multiple reliability tests are performed on random storage units in the target flash chip by grouping; S200. Test data of the target chip at the reference temperature and the target temperature are collected respectively, and a data sample set is constructed according to the test data; the test data includes storage location, read / write times, read / write time and abnormal information; S300. Based on the data sample set and the few-sample training method, a discriminator model for judging whether the flash chip has failed is trained; S400. Obtain the test data of the target flash chip under the reliability test at the target temperature, and input the test data into the discriminator model to obtain the test result of the target flash chip.

[0027] In step S100 of some embodiments of the present application, the multiple reliability tests on random storage units in the target flash chip based on the reference temperature and the target temperature include: randomly sampling from multiple target chips, and dividing the sampled target chips into two groups based on the reference temperature and the target temperature; based on the reference temperature and the target temperature, programming, erasing and reading cycle tests are performed on the two groups of target chips respectively.

[0028] Specifically, the multi-pole unit 3D NAND flash (TLC NAND flash) product under a certain manufacturing process is taken as the failure prediction object. First, the storage units in the flash chip are sampled, and the same number of odd and even block numbers of storage blocks are randomly selected, and it is ensured that the selected storage blocks are uniformly distributed in the entire address range of the chip. For each selected storage block, a plurality of continuous boundary physical address word lines in the block are selected, and a middle physical address word line is randomly selected for testing. The test data used in the flash test is pseudo-random test data, the erase / program / read cycle number Cpe is 1000, and the temperature K takes the value of-40, 0, 55 and 80 degrees Celsius.

[0029] Further, the programming, erasing and reading cycle test on the two groups of target chips includes: in each cycle test, the target chip is erased, written, programmed and read in turn, and the failed operation is marked; it is judged whether the measured target chip has failed, and whether the cycle test is ended is determined according to the judgment result.

[0030] The specific test steps are as follows: 1. The test equipment performs an erase operation on the storage block to be tested; 2. The chip erase operation success flag is checked, if the erase operation is successful, step 3 is executed, otherwise, it returns to step 1, when the number of repeated steps 1 exceeds 5, the storage block to be tested is marked as a bad block and a new storage block to be tested is selected; 3. The test equipment writes test data to the storage block to be tested; 4. The chip programming operation success flag is checked, if the programming operation is successful, step 5 is executed, otherwise, it returns to step 3, when the number of repeated steps 3 exceeds 5, the storage block to be tested is marked as a bad block and a new storage block to be tested is selected; 5. Wait for 1 minute, the test equipment performs a read operation on the storage block to be tested and collects chip parameters; 6. Determine whether the tested chip has failed, if it has failed, end the normal temperature cycle test. 7. Determine whether the number of erase / program / read cycles experienced by the storage block to be tested is less than 1000, if the program / erase / read cycle is less than 1000, repeat steps 1 to 6.

[0031] In step S200 of some embodiments of the present application, test data of the target chip performing reliability test at the reference temperature and the target temperature are collected respectively, and a data sample set is constructed according to the test data; the test data includes storage location, read / write times, read / write time and abnormal information;

[0032] Reference Figure 4 , which shows a flowchart of the program / erase / read test at the target temperature. The flash memory chip is placed in the test equipment, the oven is adjusted to the target temperature, one erase / program / read operation is performed, the chip parameters are collected, and the detector determines whether the tested chip has failed; the above steps are repeated by changing the value of the target temperature K until all values of K are traversed.

[0033] It should be noted that the reference temperature is normal temperature, i.e. the ambient temperature 25°C: for industrial-grade chips, the working temperature range is usually -40℃~85℃. The working temperature range of commercial-grade chips (also known as consumer-grade or civilian-grade) is usually 0℃~+70℃. Therefore, for commercial-grade chips, normal temperature can also be considered as 25°C.

[0034] Reference Figure 5 In step S300 of some embodiments of the present application, the discriminator model for judging whether the flash memory chip has failed is trained based on the data sample set and the few-sample training method, which includes: taking the test data of the target chip performing n times of reliability test at the reference temperature and the target temperature as samples, where n≥1000; taking the test data of n times of reliability test at the reference temperature and the target temperature as samples, and taking the result of m times of reliability test at the target temperature appearing failure as a label, m>n; based on the samples and the label, the discriminator model for judging whether the flash memory chip has failed is trained by the few-sample training method.

[0035] Specifically, the target model chip is sampled, and the sampled flash memory chip is divided into two groups A and B. The flash memory chip in group A is selected to perform the normal temperature erase / program / read cycle test according to the method. Figure 3 The flash memory chip in group B is tested at the target temperature according to the method. Figure 4 The flash memory chip in group B is tested at the target temperature according to the method.

[0036] The chip parameters obtained by the normal temperature test of group A and the chip parameters obtained by n times of erase / program / read cycle test at the target temperature K of group B are taken as the input of the discriminator, and whether a fault occurs after m times of erase / program / read cycle at the target temperature K of group B is taken as the output of the discriminator; the relationship between the input chip parameters and the output discrimination result is calculated, and a discriminator mathematical model is established. The calculation method of the relationship between the input chip parameters and the output discrimination result is any calculation method that can accurately establish the relationship between variables.

[0037] Referring to Figure 6 , the artificial neural network comprises an input layer, a hidden layer, a softmax layer and an output layer. The number of hidden layers is 10, the number of units in each layer is 50, and the activation function is sigmoid. The model input is: the original error bit number of the selected storage unit, the block number to which the storage unit belongs, the word line position to which the storage unit belongs, the number of programming / erase cycles experienced by the storage unit, the test temperature of the storage unit, the erase operation time of the storage unit, the programming operation time of the storage unit, the read operation time of the storage unit, the read-retry error bit number and the read-retry delay. The model output is: whether a fault occurs after the target erase / program / read cycle. The discriminator model modeling steps are as follows:

[0038] 1. Initialize the training algorithm; 2. Input the chip data of group A into the artificial neural network, and the training algorithm calculates the error between the output of the artificial neural network and the actual value; 3. The training algorithm adjusts the weight of the artificial neural network; 4. Determine whether the epoch number reaches 100, if yes, stop training, otherwise return to step 2. 5. The program outputs the discriminator model. For the trained discriminator model, reset the parameters of the model input layer, the softmax layer and the output layer, that is, restore the parameters of the specified neural network layer to the values before the cycle. The training algorithm adjusts the parameters of the discriminator model after resetting the input layer, the softmax layer and the output layer, and the specific steps are as follows: 1. The test data of the flash memory chip in group B is input into the discriminator model as training data; 2. The training algorithm calculates the error between the output of the artificial neural network and the actual value, and adjusts the weight of the artificial neural network; 3. Determine whether the error is reduced or the epoch number reaches 1000, if one of the conditions is met, stop training; 4. The program outputs the discriminator model.

[0039] Example 2

[0040] Reference Figure 8 In a second aspect of the present application, a test optimization system 1 for large-capacity 3D flash memory is provided, comprising: a test module 11 configured to perform multiple reliability tests on random storage units in a target flash chip by grouping based on a reference temperature and a target temperature; a construction module 12 configured to collect test data of the target chip at the reference temperature and the target temperature for reliability testing, respectively, and construct a data sample set according to the test data; the test data includes storage location, read / write times, read / write time and abnormal information; a training module 13 configured to train a discriminator model for judging whether a flash chip has failed based on the data sample set and a few-shot training method; a judgment module 14 configured to obtain test data of a target flash chip at a target temperature under reliability testing, and input the test data into the discriminator model to obtain a test result of the target flash chip.

[0041] Further, the test module 11 comprises: a sampling unit configured to randomly sample from a plurality of target chips, and divide the sampled target chips into two groups based on the reference temperature and the target temperature; a test unit configured to perform programming, erasing and reading cycle tests on the two groups of target chips based on the reference temperature and the target temperature, respectively.

[0042] Reference Figure 7 In an embodiment of the application, the test optimization system for large-capacity 3D flash memory comprises a storage unit selection module for selecting feature storage units in the chip under test. An operation configuration module generates test scripts corresponding to different target temperatures K. A chip parameter acquisition module acquires chip parameters under test based on the data of the storage unit selection module and the operation configuration module, and transmits the obtained data to a data storage module. A discriminator module judges based on the input data provided by the data storage module, and transmits the results to a result statistics module, thereby generating a test report of the chip.

[0043] Embodiment 3

[0044] Reference Figure 9 In a third aspect of the present application, an electronic device is provided, comprising: one or more processors; a storage device configured to store one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the test optimization method for large-capacity 3D flash memory in the first aspect of the present application.

[0045] The electronic device 500 can include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 501 that can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 502 or loaded into a random access memory (RAM) 503 from a storage device 508. Various programs and data required for the operation of the electronic device 500 are also stored in the RAM 503. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0046] In general, the following devices can be connected to the I / O interface 505: input devices 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 508 including, for example, a hard disk, etc.; and communication devices 509. The communication devices 509 can allow the electronic device 500 to communicate wirelessly or wired with other devices to exchange data. Although Figure 9 The electronic device 500 is shown with various devices, but it should be understood that all of the shown devices are not required to be implemented or present. More or fewer devices can alternatively be implemented or present. Figure 9 Each block shown in the flowchart of FIG. 6 can represent one device, or a plurality of devices, as necessary.

[0047] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for executing the methods illustrated by the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by the communication device 509, or installed from the storage device 508, or installed from the ROM 502. When the computer program is executed by the processing device 501, the above-mentioned functions defined in the methods of embodiments of the present disclosure are executed. It should be noted that the computer readable medium described in embodiments of the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In embodiments of the present disclosure, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, device or apparatus. In embodiments of the present disclosure, the computer readable signal medium can include a data signal carried in a baseband or as part of a carrier wave, in which the computer readable program code is carried. Such a propagated data signal can take a variety of forms, including but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate or transport a program for use by or in connection with an instruction execution system, device or apparatus. The program code contained on the computer readable medium can be transmitted by any suitable medium, including but not limited to, wire, cable, RF (radio frequency), or the like, or any suitable combination of the above.

[0048] The computer readable medium described above can be included in the electronic device described above; or can exist separately from the electronic device and be not assembled into the electronic device. The computer readable medium described above carries one or more computer programs, which, when executed by the electronic device, cause the electronic device to:

[0049] Computer program code for carrying out operations of embodiments of the present disclosure can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++, Python, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0050] The computer program instructions can also be loaded onto a computer or other programmable information processing apparatus to cause a series of operations to be performed on the computer or other programmable information processing apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable information processing apparatus implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0051] The foregoing is merely illustrative of the principles of the application, and the application should not be limited to such detail. Rather, the application should be limited only by the following claims.

Claims

1. A method for testing optimization of mass 3D flash memory, characterized in that, The method comprises the following steps: Based on the reference temperature and the target temperature, multiple reliability tests are performed on random storage units in the target flash memory chip by grouping; Test data of the target chip under the reference temperature and the target temperature are collected respectively, and a data sample set is constructed according to the test data; The test data includes storage location, read-write times, read-write time and abnormal information; wherein the test data at least includes: the original error bit number of the selected storage unit, the programming / erasing cycle number of the storage unit, the erasing operation time of the storage unit, the programming operation time of the storage unit, the read operation time of the storage unit, and one or more of read-retry error bit number and read-retry delay; Based on the data sample set and the few-sample training method, a discriminator model for judging whether the flash memory chip has failed is trained: the test data of the target chip under the reference temperature and the target temperature are n times of reliability test as samples, wherein n≥1000; the test data of the target chip under the reference temperature and the target temperature are n times of reliability test as samples, and the result of the target chip under the target temperature in m times of reliability test is taken as a label, m>n; based on the samples and the label, a few-sample training method is used to train a discriminator model for judging whether the flash memory chip has failed; The test data of the target flash memory chip under the target temperature are obtained, and the test data are input into the discriminator model to obtain the test result of the target flash memory chip.

2. The method of claim 1, wherein, The method comprises the following steps: Randomly sample from a plurality of target chips, and divide the sampled target chips into two groups based on the reference temperature and the target temperature; Based on the reference temperature and the target temperature, programming, erasing and reading cycle tests are respectively performed on the two groups of target chips.

3. The method of claim 2, wherein, The programming, erasing and reading cycle tests on the two groups of target chips comprise the following steps: In each cycle test, the target chip is sequentially erased, written, programmed and read, and the failed operation is marked; Determine whether the tested target chip has failed, and determine whether to end the cycle test according to the determination result.

4. The method of claim 1, wherein, m>1000×n.

5. The method of claim 1, wherein, The discriminator model is a neural network.

6. A test optimization system for mass 3D flash memory, characterized by, The method comprises the following steps: A test module is used to perform multiple reliability tests on random storage units in the target flash memory chip by grouping based on the reference temperature and the target temperature; A construction module is used to collect test data of the target chip under the reference temperature and the target temperature respectively, and construct a data sample set according to the test data; The test data includes storage location, read-write times, read-write time and abnormal information; wherein the test data at least includes: the original error bit number of the selected storage unit, the programming / erasing cycle number of the storage unit, the erasing operation time of the storage unit, the programming operation time of the storage unit, the read operation time of the storage unit, and one or more of read-retry error bit number and read-retry delay; The training module is configured to train a discriminator model for judging whether a flash memory chip is faulty based on the data sample set and a few-shot training method; test data of the target chip subjected to n times of reliability tests at a reference temperature and a target temperature are taken as samples, where n is greater than or equal to 1000; test data of the target chip subjected to n times of reliability tests at the reference temperature and the target temperature are taken as samples, and results of m times of reliability tests at the target temperature are taken as labels, where m is greater than n; and the discriminator model for judging whether the flash memory chip is faulty is trained based on the samples and the labels by using the few-shot training method. The judging module is configured to obtain test data of a target flash memory chip subjected to reliability tests at a target temperature, and input the test data into the discriminator model to obtain a test result of the target flash memory chip.

7. The test optimization system for mass 3D flash memory of claim 6, wherein, The test module comprises: a sampling unit configured to randomly sample target chips from a plurality of target chips, and divide the sampled target chips into two groups based on a reference temperature and a target temperature; a test unit configured to perform programming, erasing and reading cycle tests on the two groups of target chips based on the reference temperature and the target temperature, respectively.

8. An electronic device comprising: one or more processors; a storage device configured to store one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the test optimization method for a large-capacity 3D flash memory according to any one of claims 1 to 5.

9. A computer readable medium having stored thereon a computer program, wherein, The computer program, when executed by a processor, implements the test optimization method for a large-capacity 3D flash memory according to any one of claims 1 to 5.

Images