Method for preparing semiconductor structure and semiconductor structure

Abstract

The present application discloses a method for fabricating a semiconductor structure and a semiconductor structure. The method comprises: etching a substrate using an etching process to form a high-aspect-ratio etched structure on the substrate; after each predetermined number of periodic cycles of the etching process are completed, using a treatment process different from the etching process to remove a portion of the thickness of a passivation layer deposited on the sidewalls of an intermediate structure formed before the high-aspect-ratio etched structure is formed, and removing at least a portion of a protrusion on the sidewall that is exposed from the remaining passivation layer surface. The present application organically combines the etching process with sidewall treatment technology, alternating cycles to balance the etching rate and sidewall quality, and can achieve deep silicon etching with higher aspect ratios and smaller nanometer-scale dimensions.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Deep Silicon Etching (DSE) is an advanced process for fabricating high aspect ratio (high depth, narrow linewidth) microstructures on silicon substrates. It is widely used in:

[0003] (1) MEMS devices: such as accelerometers, gyroscopes, pressure sensors, etc.

[0004] (2) 3D integration and packaging: such as through-silicon via (TSV) preparation, chip stacking, etc.

[0005] (3) Optical devices: such as optical waveguides, diffraction gratings, etc.

[0006] (4) Power devices: such as insulated gate bipolar transistors (IGBTs) and trench structures of power metal-oxide semiconductor field-effect transistors (MOSFETs).

[0007] The core technology of deep silicon etching includes an existing etching process, the main steps of which are: alternating cycles of passivation and etching to achieve overall anisotropic etching in the depth direction.

[0008] With technological advancements, the demand for higher-density interconnects in advanced packaging is driving deep silicon etching (DSI) processes to achieve nanometer-scale linewidths (less than 50nm) and higher aspect ratios (greater than 100:1). Existing etching processes, subject to physical limitations such as ion shadowing and reactive gas transport efficiency, struggle to meet these extreme aspect ratio requirements. Furthermore, nanometer-scale linewidths are particularly sensitive to thickness fluctuations in sidewall passivation layers (such as CF polymers). Large variations in sidewall passivation thickness can easily lead to linewidth deviations and etch tilt (3D through-silicon vias and memory stacks require an etch verticality error of less than ±0.2°). Furthermore, existing etching processes face challenges such as plasma chemical residue and localized roughness peaks (Ra > 5nm) caused by random deposition of CF polymers on the sidewalls. These factors significantly impact the achievement of higher aspect ratios and nanometer-scale DSI etching. Therefore, it is necessary to develop a process that can significantly improve these issues. Summary of the Invention

[0009] The purpose of this application is to overcome the above-mentioned problems existing in the prior art and to provide a method for preparing a semiconductor structure and a semiconductor structure to solve the shortcomings of the existing etching process in deep silicon etching, which is difficult to achieve deep silicon etching with higher aspect ratio and nanometer-scale size due to the corresponding physical limitations, large fluctuations in the thickness of the sidewall passivation layer, and rough sidewalls.

[0010] To achieve the above objectives, the technical solutions of this application are as follows:

[0011] According to a first aspect of the present application, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0012] providing a substrate;

[0013] Etching the substrate using an etching process to form an etched structure with a high aspect ratio on the substrate;

[0014] The etching process includes a plurality of periodic cycles of deposition and etching steps. After each predetermined number of periodic cycles, a treatment process different from the etching process is used to perform the following treatment on the intermediate structure formed before the high aspect ratio etched structure is formed:

[0015] removing a portion of the thickness of the passivation layer deposited on the sidewalls and removing at least a portion of the protrusions present on the sidewalls and exposed from the remaining surface of the passivation layer;

[0016] The treatment process includes:

[0017] Using plasma of a first gas to perform adsorption and reaction on the sidewalls to remove a portion of the passivation layer and react with the substrate material on the exposed surface of the protrusion to generate a volatile reaction product layer on the exposed surface of the protrusion;

[0018] The reaction product layer is removed by bombardment using plasma of a second gas.

[0019] In some embodiments, the high aspect ratio etched structure is obtained by performing the last treatment on the last intermediate structure formed before the high aspect ratio etched structure is formed.

[0020] In some embodiments, after the reaction product layer is generated, it is first purged using a third gas, and then the reaction product layer is removed.

[0021] In some embodiments, the substrate material includes silicon, the first gas includes chlorine gas, and the reaction product layer includes a tetrachlorosilane layer.

[0022] In some embodiments, the second gas includes a rare gas, or the second gas includes a mixed gas of a rare gas and a fluorine-based gas.

[0023] In some embodiments, the third gas includes a noble gas or nitrogen.

[0024] In some embodiments, when the plasma of the first gas is used for adsorption and reaction, the temperature is 60°C to 100°C, the pressure is 30mTorr to 2Torr, the source power is 500W to 5000W, and the flow rate of the first gas is 20sccm to 500sccm.

[0025] In some embodiments, when the reaction product layer is removed using the plasma of the second gas, the temperature is 60°C to 100°C, the pressure is 5mTorr to 50mTorr, the source power is 300W to 2000W, the bias power is 50W to 300W, the pulse frequency includes 1KHz, and the duty cycle is 10% to 90%.

[0026] In some embodiments, when the third gas is used for purging, the flow rate of the third gas is 1000 sccm to 3000 sccm.

[0027] In some embodiments, the preset number of times is n times, and the total number of the periodic cycle steps is m, 1<n<m.

[0028] In some embodiments, m / n≧10.

[0029] In some embodiments, the n is 2 to 5 times.

[0030] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure, which is obtained using the preparation method of the semiconductor structure provided by any embodiment of the first aspect above.

[0031] The embodiments of the present application may or at least have the following advantages:

[0032] (1) By performing a treatment on the formed intermediate structure each time a preset number of periodic cycle steps are completed during the etching process of the substrate, a portion of the thickness of the passivation layer deposited on the sidewall is removed, and at least a portion of the protrusions existing and exposed on the sidewall are removed, the thickness uniformity of the passivation layer on the sidewall can be adjusted, and the surface of the sidewall can be smoothed. By performing a periodic cycle of the etching process and an alternating cycle between the treatment process, the etching rate and the sidewall quality can be balanced, thereby achieving a high etching rate and high etching quality of the high aspect ratio etching structure. Precision (atomic level precision), and can increase the diffusion coefficient, improve the reaction gas transmission efficiency, solve the problems of plasma chemical residue (polymer thickness fluctuation has a great influence on the control of nanoscale line width) and ion shadow effect (nanoscale involves atomic size level), thereby effectively improving the uniformity and roughness of local CF polymer, and solving the line width offset (titling) problem, achieving higher verticality (90°±0.2°), and achieving better uniformity (uniform size of the upper, middle and lower positions of the high aspect ratio etched structure), and better sidewall smoothness.

[0033] (2) By embedding the above-mentioned treatment process in the periodic cycle steps of the etching process, the by-products generated in the intermediate structure (deep hole or groove) during the etching process can be removed in time to prevent the polymer from being too thick and accumulating. At the same time, the side wall roughness is improved to avoid the etch stop phenomenon (etch stop) after etching to a certain depth, or the bottom angle tilting inward (high verticality is difficult to achieve), and the by-products generated are difficult to be removed from the deep hole or groove in time, resulting in limited process adjustment and difficulty in achieving more refined structures.

[0034] (3) By adopting a cyclical method of embedded etching process and embedded treatment process, fine etching and surface treatment of internal structures can be carried out. In the same processing chamber, while gradually deepening the high aspect ratio etching structure to be completed, side wall treatment and by-product treatment can be carried out, thus laying a good foundation for achieving deep silicon etching with higher aspect ratio (for example, greater than 100:1) and nanometer size (for example, less than 50nm) (the current mainstream width size is more than 140nm, and the aspect ratio is about 50:1).

[0035] Other advantages of the present application will be described in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a flow chart of a method for preparing a semiconductor structure according to a preferred embodiment of the present application.

[0037] Figure 2A schematic diagram of a structure after a mask pattern is formed on a substrate is provided in a preferred embodiment of the present application.

[0038] Figure 3 A schematic diagram of a structure after a first trench intermediate structure is formed on a substrate is provided in a preferred embodiment of the present application.

[0039] Figure 4 This is a schematic diagram of the principle of processing the sidewall provided in a preferred embodiment of the present application. Figure 4 (a) is adsorption and reaction, Figure 4 (b) Desorption.

[0040] Figure 5 A schematic diagram of the structure after processing the intermediate structure of the first groove is provided in a preferred embodiment of the present application.

[0041] Figure 6 A schematic diagram of a structure after forming a second trench intermediate structure is provided in a preferred embodiment of the present application.

[0042] Figure 7 A schematic diagram of the structure after processing the middle structure of the second groove is provided in a preferred embodiment of the present application.

[0043] Figure 8 A schematic diagram of a complete structure after deep trenches are formed on a substrate is provided in a preferred embodiment of the present application.

[0044] Figure 9 A schematic diagram of a structure after removing the mask pattern is provided in a preferred embodiment of the present application.

[0045] In the figure, 10. substrate; 11. opening; 12. mask pattern; 13. protective film; 14. deep trench; 141. first trench intermediate structure; 142. second trench intermediate structure; 15. scalloped stripes; 16. raised portion; 17. recessed portion. DETAILED DESCRIPTION

[0046] The purpose of the embodiments of the present application is to solve the shortcomings of existing etching processes in deep silicon etching, such as the difficulty in achieving deep silicon etching structures with higher aspect ratios and nanometer-scale dimensions due to corresponding physical limitations, large fluctuations in the thickness of the sidewall passivation layer, and rough sidewalls.

[0047] In order to solve the above problems, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0048] providing a substrate;

[0049] Etching the substrate using an etching process to form an etched structure with a high aspect ratio on the substrate;

[0050] The etching process includes a plurality of periodic cycles of deposition and etching steps. After each predetermined number of periodic cycles, a treatment process different from the etching process is used to perform the following treatment on the intermediate structure formed before the high aspect ratio etched structure is formed:

[0051] removing a portion of the thickness of the passivation layer deposited on the sidewalls and removing at least a portion of the protrusions present on the sidewalls and exposed from the remaining surface of the passivation layer;

[0052] The treatment process includes:

[0053] Using plasma of a first gas to perform adsorption and reaction on the sidewalls to remove a portion of the passivation layer and react with the substrate material on the exposed surface of the protrusion to generate a volatile reaction product layer on the exposed surface of the protrusion;

[0054] The reaction product layer is removed by bombardment using plasma of a second gas.

[0055] The embodiment of the present application provides the above-mentioned novel high aspect ratio etching method for etching structures, organically combines the etching process with the sidewall processing technology, and alternately cycles to balance the etching rate and sidewall quality, thereby achieving a high etching rate and high etching accuracy for high aspect ratio etching structures, increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residue and ion shadow effect, and effectively improving the uniformity and roughness of local CF polymers, so as to ultimately achieve deep silicon etching of nanometer-scale dimensions with a higher aspect ratio.

[0056] An embodiment of the present application also provides a semiconductor structure obtained using the above-mentioned method for preparing the semiconductor structure.

[0057] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0058] refer to Figure 1 The present invention provides a method for preparing a semiconductor structure, which includes the following steps in sequence:

[0059] Step S11: providing a substrate.

[0060] refer to Figure 2 In some embodiments, the material of the substrate 10 includes silicon (ie, a silicon substrate).

[0061] In some embodiments, a silicon wafer may be used as the substrate 10 to further form a desired high aspect ratio etched structure on the substrate 10 .

[0062] In some embodiments, the high aspect ratio etched structure includes a deep trench, a deep via, or a through via, etc. The following takes forming a deep trench as a high aspect ratio etched structure on the substrate 10 as an example to describe the embodiments of the present application in detail.

[0063] In some embodiments, the silicon wafer may be doped to provide the substrate 10 with desired electrical properties.

[0064] In some embodiments, integrated circuits, such as transistor structures, may be fabricated on the substrate 10 , so that after forming deep trenches (high aspect ratio etched structures), the required vertical interconnections are achieved by filling the deep trenches with conductive materials.

[0065] Step S12: forming a plurality of mask patterns on the surface of the substrate.

[0066] refer to Figure 2 In some embodiments, a mask layer is formed on the upper surface of the substrate 10 and patterned to form a plurality of mask patterns 12 on the upper surface of the substrate 10. An opening 11 serving as an etching window is provided between any two adjacent mask patterns 12, and the surface of the substrate 10 located between the two adjacent mask patterns 12 is exposed at the bottom of the opening 11.

[0067] It should be noted that Figure 2 The figure schematically shows a case where two mask patterns 12 are formed on the upper surface of the substrate 10. However, it is understood that more mask patterns may be formed on the upper surface of the substrate 10, for example, three mask patterns, four mask patterns, ten mask patterns, etc., and the number is not limited thereto.

[0068] In some embodiments, the mask pattern 12 includes an organic mask pattern, which is obtained by patterning an organic mask layer.

[0069] In some embodiments, the organic material includes photoresist, that is, the organic material mask layer includes a photoresist layer.

[0070] In some embodiments, a spin coating process is used to form a photoresist layer on the upper surface of the substrate 10. Then, a photolithography process is used to photolithography the photoresist layer, thereby forming a plurality of photoresist patterns, namely, mask patterns 12, on the upper surface of the substrate 10.

[0071] In some embodiments, before etching substrate 10, a plasma of a fourth gas is first used to bombard the upper surface of substrate 10, forming a protective film 13 at the interface between the bottom of mask pattern 12 and the upper surface of substrate 10 (i.e., at the inner bottom corner of opening 11). The plasma of the fourth gas is generated by ionizing the fourth gas introduced into the process chamber.

[0072] Due to the mask edge effect, the passivation layer will be insufficiently deposited in the edge area during the subsequent main etching process, thereby exacerbating the etching behavior at the top. Ion bombardment is more concentrated at the top, and lateral etching in this area is intensified during etching, resulting in deeper and rougher sidewall ripples at the top of the deep trench. Therefore, by pre-forming a protective film 13 at the junction of the bottom of the mask pattern 12 and the upper surface of the substrate 10, the top morphology of the etched area can be effectively protected during the subsequent etching process of the substrate 10, preventing abnormal excessive lateral etching behavior at the top, and ensuring dimensional uniformity at different depths at the top, middle, and bottom during subsequent high-aspect-ratio etching.

[0073] In some embodiments, the fourth gas includes a rare gas. The protective film 13 includes a carbon-based protective film.

[0074] In this embodiment, argon is used as the fourth gas, and the photoresist material of the mask pattern 12 and the upper surface of the substrate 10 are bombarded by the formed argon plasma (plasma of the fourth gas), thereby forming a carbon-based protective film (a protective film 13 of a carbon-based material containing C, N, and O) at the junction of the bottom of the mask pattern 12 and the upper surface of the substrate 10.

[0075] In some embodiments, the temperature during the process of bombarding the protective film 13 with argon gas is between -20°C and 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, or any value between any two of the aforementioned temperature values.

[0076] In some embodiments, the pressure of argon gas bombardment to form the protective film 13 is 5 to 50 mTorr. For example, the pressure may be 5 mTorr, 10 mTorr, 20 mTorr, 30 mTorr, 40 mTorr, or 50 mTorr, or any value between any two of the aforementioned pressure values.

[0077] In some embodiments, when argon gas is used for bombardment to form the protective film 13 , the source power is 100 W to 1000 W. For example, the source power can be 100 W, 200 W, 300 W, 400 W, 500 W, 600 W, 700 W, 800 W, 900 W, or 1000 W, or any value between any two of the aforementioned source power values.

[0078] In some embodiments, during the process of forming the protective film 13 by bombarding with argon gas, the bias power is 10 W to 100 W. For example, the bias power can be 10 W, 20 W, 30 W, 40 W, 50 W, 60 W, 70 W, 80 W, 90 W, or 100 W, or any value between any two of the aforementioned bias power values.

[0079] In some embodiments, the process of bombarding the protective film 13 with argon gas lasts for 5 to 20 seconds. For example, the time may be 5 seconds, 10 seconds, 15 seconds, or 20 seconds, or any value between any two of the aforementioned time values.

[0080] Step S13: using an etching process to perform a preset number of periodic cycle etching on the substrate to form a first trench intermediate structure on the substrate, and processing the sidewalls of the first trench intermediate structure.

[0081] refer to Figure 3 In some embodiments, an etching process is used, and the mask pattern 12 is used as a mask to perform a predetermined number of periodic cyclic etchings on the upper surface of the substrate 10 exposed at the bottom of the opening 11, thereby first forming a first trench intermediate structure 141 on the substrate 10, with the goal of ultimately forming a deep trench completed structure on the substrate 10 (refer to FIG. Figure 8 ).

[0082] In some embodiments, the etching process includes multiple (or more) periodic cycles of passivation layer deposition and etching steps. The etching steps can be further divided into a first etching step and a second etching step. The passivation layer deposition step forms a passivation layer on the sidewalls to protect them during etching; the first etching step removes the passivation layer from the bottom, allowing for further etching downwards in the second etching step. By performing multiple periodic cycles, deep trenches are formed in substrate 10.

[0083] However, existing etching processes have difficulty meeting the extreme aspect ratio requirements of nanometer-scale line widths (less than 50nm) and higher aspect ratios (greater than 100:1). This is because existing etching processes are subject to corresponding physical limitations (such as ion shadowing and reaction gas transmission efficiency). Nanometer-scale line widths are more sensitive to thickness fluctuations of sidewall passivation layers (such as CF polymer), which can easily lead to line width offset and increased verticality errors.

[0084] At the same time, due to the characteristics of the existing etching process, multiple regular scallop-shaped stripes 15 will be formed on the side wall during multiple periodic etching cycles. Among them, the bottom of each scallop-shaped stripe 15 has a recessed portion 17, and the junction of two scallop-shaped stripes 15 has a raised portion 16, which makes the side wall have a rough surface morphology. In addition, there are problems such as plasma chemical residues and local rough peaks (Ra>5nm) caused by random deposition of CF polymers on the side walls. The existence of the above factors will cause the etching to stop after a certain depth is etched, or the bottom angle will tilt inward (high verticality is difficult to achieve), and the by-products produced will be difficult to be removed from the deep holes or grooves in time, resulting in limited process adjustment and difficulty in achieving more refined structures. Therefore, the embodiments of the present application promptly remove excess polymer on the sidewalls to prevent uneven etching caused by an excessively thick passivation layer, and reduce the roughness of the sidewalls through processing to improve the smoothness of the sidewalls, thereby increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residues and ion shadow effects, and effectively improving the uniformity and roughness of local CF polymers, thereby enabling deep silicon etching of nanoscale sizes with higher aspect ratios.

[0085] In some embodiments, when etching the substrate 10 using an etching process, after each predetermined number of periodic cycles are completed and an intermediate structure before deep trenches (high aspect ratio etched structures) are formed on the substrate 10, a step of treating the intermediate structure is embedded. Specifically, after each predetermined number of periodic cycles are completed, a special treatment process different from the etching process is used to perform the following treatment on the intermediate structure formed before the deep trench formation: removing a portion of the thickness of the passivation layer deposited on the sidewalls, and removing at least a portion of the protrusion 16 on the sidewalls that is exposed from the remaining passivation layer surface.

[0086] In some embodiments, an etching process is used to etch the substrate 10 using the mask pattern 12 as a mask, and a predetermined number of periodic cycles are completed to form a first trench intermediate structure 141 on the substrate 10 as the first intermediate structure before the deep trench is formed. Figure 3 As shown in FIG. The first trench intermediate structure 141 is an intermediate structure before a deep trench of the desired depth is formed. That is, the depth of the first trench intermediate structure 141 is less than the total depth of the deep trench. The sidewalls of the first trench intermediate structure 141 are then processed using the processing techniques of the embodiments of the present application.

[0087] Due to the presence of the protective film 13, when etching to form the first trench intermediate structure 141, the top is prevented from being excessively etched laterally, so that the size of the first trench intermediate structure 141 is relatively uniform, thereby laying a good foundation for ensuring the uniform size of different positions at the top, middle and bottom of the entire deep trench.

[0088] In some embodiments, when etching the substrate 10 using an etching process, the process gas used in the deposition step includes a mixture of C4F8 and Ar. The process gas used in the etching step includes a mixture of SF6 and Ar. Vertical deep trenches are formed by alternating between depositing a passivation layer using C4F8 and etching using SF6.

[0089] In some embodiments, when etching the substrate 10 using an etching process (until the entire deep trench is etched), the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, or any value between any two of the foregoing temperature values.

[0090] In some embodiments, when etching the substrate 10 using an etching process, the pressure is 10 mTorr to 200 mTorr. For example, the pressure can be 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 130 mTorr, 150 mTorr, 190 mTorr, or 200 mTorr, or any value between any two of the aforementioned pressure values.

[0091] In some embodiments, when etching the substrate 10 using an etching process, the source power is 1000 W to 4000 W. For example, the source power can be 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, or 4000 W, or any value between any two of the foregoing source power values.

[0092] In some embodiments, when etching the substrate 10 using an etching process, the bias power is 10 W to 200 W. For example, the bias power can be 10 W, 20 W, 50 W, 70 W, 100 W, 130 W, 160 W, 180 W, or 200 W, or any value between any two of the foregoing bias power values.

[0093] In some embodiments, assuming that the preset number of times is n and the total number of periodic cycle steps is m, then: 1<n<m.

[0094] In some embodiments, m / n≧10, that is, m / n is the number of treatments. During the process of etching to form deep trenches, the sidewalls need to be treated at least 10 times, and at least one treatment needs to be performed on the upper, middle, and lower positions of the deep trenches respectively.

[0095] In some embodiments, the total number of times (m / n) the sidewalls are treated may be 3 or more, 5 or more, 10 or more, 20 or more, 50 or more, 100 or more, 200 or more, 500 or more, or 1000 or more, or any number between any two of the foregoing numbers, but is not limited thereto.

[0096] In some embodiments, the preset number n is 2 to 5. For example, the preset number n can be 2, 3, 4 or 5 times.

[0097] In some embodiments, the preset number n may be 2 to 10. For example, the preset number n may be 2, 3, 4, 5, 6, 7, 8, 9 or 10 times, or more than 10 times.

[0098] In this embodiment, the preset number n is set to 3 times. The first groove intermediate structure 141 formed is as follows Figure 3 After three periodic cycles, three scalloped stripes 15 are formed on the sidewalls of the first trench intermediate structure 141. Each scalloped stripe 15 has a concave portion 17 at its bottom, and a convex portion 16 at the junction of two adjacent scalloped stripes 15. This results in a rough surface topography on the sidewalls of the first trench intermediate structure 141. The following treatment method is required to treat the sidewalls of the first trench intermediate structure 141 to improve the rough surface topography.

[0099] In some embodiments, when processing the sidewalls of the first trench intermediate structure 141, a reactive gas is used to react with the passivation layer on the sidewalls, removing a portion of the passivation layer to adjust the thickness uniformity of the passivation layer on the sidewalls. As the thickness of the passivation layer gradually decreases, the protrusions 16 on the sidewalls gradually become exposed from the surface of the passivation layer. During this process, the reactive gas reacts with the substrate 10 material on the surface of the exposed protrusions 16 to generate volatiles, thereby removing at least a portion of the protrusions 16 and smoothing the sidewalls.

[0100] For deep silicon etching with nanometer-scale line widths and higher aspect ratios, due to the influence of the process characteristics of the etching process itself, the deposition rate will gradually exceed the etching rate. This will make the polymer (passivation layer) easily accumulate on the bottom and affect the timely removal of by-products, thus causing problems such as etching stopping after reaching a certain depth. The embodiment of the present application removes part of the thickness of the passivation layer deposited on the sidewall after each preset number of periodic cycle steps. This can avoid the formation of an excessively thick passivation layer on the sidewall after repeated deposition of the passivation layer, which affects the uniformity of etching and the timely removal of by-products. At the same time, by utilizing the fact that the thickness of the passivation layer on the protrusion 16 is thinner than that of the passivation layer on the recessed portion 17, when removing the excessively thick passivation layer on the sidewall, the top of the protrusion 16 can be exposed from the surface of the passivation layer remaining after removing part of the thickness. Therefore, by reacting and removing this part of the protrusion 16, the sidewall surface becomes smoother. It can also reduce the accumulation of the passivation layer and facilitate the timely removal of by-products. In addition, the smooth sidewalls are beneficial for providing vertical guidance during downward etching, thereby achieving higher verticality and improving the electrical performance after deep trench filling.

[0101] In some embodiments, when treating the sidewalls of the first trench intermediate structure 141 using a treatment process, a first gas plasma (reactive gas) is first adsorbed and reacted on the sidewall surfaces of the first trench intermediate structure 141 to remove a portion of the passivation layer, thereby reducing the thickness of the passivation layer and maintaining uniform thickness across the upper and lower portions of the sidewalls. The first gas plasma then reacts with the substrate 10 material on the surface of the protrusion 16 exposed from the remaining passivation layer, forming a layer of volatile reaction products on the sidewall surfaces of the first trench intermediate structure 141. The first gas plasma is generated by ionizing the first gas (reactive gas) introduced into the process chamber.

[0102] In some embodiments, the first gas includes chlorine gas, and argon gas may be used as a diluent gas. The chlorine gas introduced into the process chamber is ionized to form a chlorine plasma (first gas plasma). The chlorine plasma is used as a reactive gas to perform the aforementioned treatment on the sidewalls of the first trench intermediate structure 141.

[0103] The passivation layer is deposited during the passivation layer deposition step to protect the sidewalls during the etching step. Due to the influence of the scalloped streaks 15 on the sidewalls, the thickness of the passivation layer deposited on the sidewalls is non-uniform. Furthermore, the random deposition of CF polymer on the sidewalls can cause localized roughness peaks, exacerbating the roughness of the sidewalls. As the dimensions of the deep trenches reach the nanometer scale, the already small channels within the trenches become even more difficult to remove byproducts due to the influence of the scalloped streaks 15, the random deposition of CF polymer, ion shadowing, reaction gas transport efficiency, and plasma chemical residues. This can easily lead to polymer accumulation in the trenches, resulting in line width deviation, poor verticality, and uneven etching depth. Therefore, before the deep trench etching is completed, the intermediate structures of the deep trenches being formed need to be gradually processed. This is because, after the deep trenches are etched to their final depth using the etching process, the effects of these factors have already been established (for example, the sidewall roughness and overall morphology have been determined), making them difficult to modify through post-processing. Moreover, the polymers produced on the sidewalls by the existing etching methods will increase with the increase of etching depth, and will eventually lead to the "etching stop" problem due to excessive accumulation of polymers, thereby hindering higher aspect ratio vertical etching in the nanometer lateral dimension, and the final etching depth at the nanometer scale is also limited.

[0104] In the embodiment of the present application, chlorine plasma is used to process the sidewall of the first trench intermediate structure 141. After the chlorine plasma enters the first trench intermediate structure 141, the chloride ions (Cl + ) will remove the by-products and the like present in the first trench intermediate structure 141, and react with the polymer material of the passivation layer on the side wall to remove a portion of the thickness of the passivation layer on the side wall to avoid accumulation due to excessive thickness of the passivation layer. In the process of removing a portion of the thickness of the passivation layer, the top of the protrusion 16 will gradually be exposed from the surface of the passivation layer remaining after removing the portion of the thickness. At this time, the chloride ions will continue to be adsorbed on the surface of the exposed protrusion 16, and react with the silicon (Si) material of the substrate 10 to generate a layer of tetrachlorosilane (SiCl4) as a reaction product layer on the surface of the exposed protrusion 16. Among them, the chloride ions can penetrate into the exposed protrusion 16 from multiple directions, such as Figure 4 As shown in (a), the chlorine ions react with the silicon material to form a tetrachlorosilane layer, causing the silicon material interface to gradually retreat toward the outside of the sidewall; and the recessed portion 17 is still covered by the passivation layer, which blocks the chloride ions from reacting with the silicon material below it, so that the new interface of the silicon material formed after the reaction (i.e., the new sidewall surface to be formed later, refer to Figure 4(b)) becomes more gentle. Therefore, the raised portion 16 that reacts to form a tetrachlorosilane layer can be removed, so that the new sidewall surface formed after the removal (i.e., the interface of the silicon material on the sidewall) becomes smoother.

[0105] It's worth noting that the adsorption and reaction of chloride ions on the silicon surface of the sidewalls is a self-limiting reaction. Therefore, once a layer of tetrachlorosilane forms and adsorbs on the sidewall surface, it will no longer react, preventing excessive etching of the silicon material on the sidewall surface at the raised portion 16, achieving atomic-level precision etching. Once the raised portion 16 is fully removed, resulting in a smoother sidewall surface, the passivation layer deposited again in subsequent cycles can protect the treated upper sidewalls, thereby preventing loss of width. Furthermore, by embedding a separate treatment process within the etching cycle, chlorine gas can be used to partially replace the etching gas SF6 used in the etching process, providing a more controllable etch-passivation cycle. After each passivation layer deposition step in the etching process, chlorine gas is used to remove excess fluorocarbon polymer (C4F8 polymer), preventing uneven etching caused by excessive passivation layer thickness.

[0106] In some embodiments, when chlorine plasma is used for adsorption and reaction, the temperature is 60° C. to 100° C. For example, the temperature can be 60° C., 65° C., 70° C., 75° C., 80° C., 85° C., 90° C., or 100° C., or any value between any two of the foregoing temperature values.

[0107] In some embodiments, when chlorine plasma is used for adsorption and reaction, the pressure is 30 mTorr to 2000 mTorr. For example, the pressure can be 30 mTorr, 50 mTorr, 100 mTorr, 200 mTorr, 500 mTorr, 1000 mTorr, 1500 mTorr, 1900 mTorr, or 2000 mTorr, or any value between any two of the foregoing pressure values.

[0108] In some embodiments, when chlorine plasma is used for adsorption and reaction, the source power is 500 W to 5000 W. For example, the source power can be 500 W, 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, 4000 W, 4500 W, or 5000 W, or any value between any two of the foregoing source power values.

[0109] In some embodiments, when chlorine plasma is used for adsorption and reaction, the flow rate of chlorine gas is 20 sccm to 500 sccm. For example, the flow rate can be 20 sccm, 50 sccm, 100 sccm, 200 sccm, 300 sccm, 400 sccm, or 500 sccm, or any value between any two of the aforementioned flow rates.

[0110] Next, the inner wall surface of the first trench intermediate structure 141 is purged with a third gas to remove excess chlorine gas (chlorine plasma) that has not participated in the reaction in the first trench intermediate structure 141 .

[0111] In some embodiments, the third gas includes a rare gas or nitrogen, and the rare gas may be, for example, argon.

[0112] In some embodiments, when the third gas is used for purging, the flow rate of the third gas is 1000 sccm to 3000 sccm. For example, the flow rate can be 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, or 3000 sccm, or any value between any two of the aforementioned flow rates, so as to purge excess chlorine gas in the first trench intermediate structure 141.

[0113] Afterwards, the sidewall surface of the first trench intermediate structure 141 is bombarded with plasma of the second gas to remove the tetrachlorosilane layer as a reaction product layer. The plasma of the second gas is obtained by ionizing the second gas introduced into the process chamber.

[0114] In some embodiments, the second gas includes a rare gas, such as argon.

[0115] In some embodiments, the second gas includes a mixture of a rare gas and a fluorine-based gas, such as a mixture of argon and CF 4 , but is not limited thereto.

[0116] In this embodiment, low energy argon ions (Ar + ), bombarding the sidewall surface of the first trench intermediate structure 141 to desorb tetrachlorosilane and remove it from the sidewall, forming a relatively smooth new sidewall.

[0117] In some embodiments, when the reaction product layer is removed using the plasma of the second gas, the temperature is 60° C. to 100° C. For example, the temperature can be 60° C., 65° C., 70° C., 75° C., 80° C., 85° C., 90° C., or 100° C., or any value between any two of the foregoing temperature values.

[0118] In some embodiments, when the reaction product layer is removed using the plasma of the second gas, the pressure is 5 mTorr to 50 mTorr. For example, the pressure can be 5 mTorr, 10 mTorr, 15 mTorr, 20 mTorr, 25 mTorr, 30 mTorr, 35 mTorr, 40 mTorr, 45 mTorr, or 50 mTorr, or any value between any two of the foregoing pressure values.

[0119] In some embodiments, when the reaction product layer is removed using the plasma of the second gas, the source power is 300 W to 2000 W. For example, the source power can be 300 W, 500 W, 800 W, 1000 W, 1500 W, 1800 W, or 2000 W, or any value between any two of the foregoing source power values.

[0120] In some embodiments, when the reaction product layer is removed using the plasma of the second gas, the bias power is 50 W to 300 W. For example, the bias power can be 50 W, 80 W, 100 W, 150 W, 200 W, 250 W, or 300 W, or any value between any two of the foregoing bias power values.

[0121] In some embodiments, when the reaction product layer is removed using a plasma of the second gas, the pulse frequency is 1 kHz and the duty cycle is 10% to 90%. For example, the duty cycle can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%, or any value between any two of the foregoing duty cycle values.

[0122] After the tetrachlorosilane layer is removed by the plasma of the second gas, the newly formed sidewall surface becomes smooth, thereby reducing the roughness of the sidewall surface. Figure 4 (b) shows the sidewall morphology of the first trench intermediate structure 141 after processing. Figure 5 As shown. Figure 3 In comparison, it can be seen that the sidewalls are significantly smoothed, resulting in a significant reduction in sidewall roughness. This allows the passivation layer deposited in subsequent cycles to more evenly cover the smooth upper sidewall surface after treatment, eliminating the need for a very thick deposition thickness to provide good sidewall protection and effectively avoiding local roughness peaks (Ra > 5nm) caused by random deposition of CF polymer on the sidewalls.

[0123] Afterwards, the substrate 10 below the first trench intermediate structure 141 may be further etched using the aforementioned etching process based on the processed first trench intermediate structure 141 to form a deeper trench.

[0124] Step S14: using an etching process, the substrate below the first trench middle structure is continuously periodically etched for a preset number of times to form a second trench middle structure below the first trench middle structure, and the sidewalls of the second trench middle structure are processed.

[0125] refer to Figure 6 In some embodiments, the same method as that used to form the first trench intermediate structure 141 is used, that is, an etching process is used, and the mask pattern 12 is used as a mask to perform a predetermined number of periodic cycle etchings on the substrate 10 below the bottom of the first trench intermediate structure 141, and a second trench intermediate structure 142 is subsequently formed below the first trench intermediate structure 141 (for ease of understanding, Figure 6 The arc-shaped dotted line indicates the original bottom of the first trench intermediate structure 141. The second trench intermediate structure 142 and the first trench intermediate structure 141 together constitute an intermediate structure formed before the deep trench is formed.

[0126] In this embodiment, the preset number n is also set to 3 times (only for example). The second groove intermediate structure 142 formed is as follows: Figure 6 After three more periodic cycles, three scallop-shaped stripes 15 will also be formed on the sidewalls of the newly formed second trench intermediate structure 142 etched below the first trench intermediate structure 141 whose sidewalls have been processed (refer to Figure 3 The bottom of each scallop-shaped stripe 15 also has a concave portion 17, and the junction of two adjacent scallop-shaped stripes 15 also has a convex portion 16, so that the sidewall of the second groove intermediate structure 142 has a rough surface morphology ( Figure 6 The vertical dotted line in the figure shows that the protrusion 16 on the sidewall of the second trench intermediate structure 142 is more protruding than the sidewall of the first trench intermediate structure 141 after treatment, for the sake of comparison. Therefore, it is also necessary to use the same treatment method as in the previous step to treat the sidewall of the second trench intermediate structure 142 to remove the excessively thick passivation layer on the sidewall and improve the rough morphology of the sidewall surface. The morphology of the sidewall of the second trench intermediate structure 142 after treatment is shown in FIG. Figure 7 As shown. You can see, Figure 6 The three scallop-shaped stripes 15 on the sidewall of the second groove intermediate structure 142 are shown. After the treatment, the protrusion has been significantly reduced, so that Figure 7 The overall sidewall morphology of the processed second trench intermediate structure 142 is smoother and is close to the smooth sidewall morphology of the processed first trench intermediate structure 141 ( Figure 7The vertical dotted line in the figure shows that the sidewalls of the second trench intermediate structure 142 after treatment have the same degree of undulation as the sidewalls of the first trench intermediate structure 141 for easy comparison), so that the overall roughness of the sidewalls is significantly reduced. For the specific treatment process of the sidewalls of the second trench intermediate structure 142, please refer to the corresponding description of step S13 and combine it with the following steps: Figure 4 Please understand it and I will not elaborate on it.

[0127] Step S15: Repeat step S14 until a deep trench with a target depth is formed on the substrate.

[0128] In some embodiments, the method of step S13 and step S14 can be used to continue etching the substrate 10 in the depth direction, that is, the method of forming the first trench intermediate structure 141 and the second trench intermediate structure 142 is used, and the etching process is used. With the mask pattern 12 as a mask, the substrate 10 below the bottom of the second trench intermediate structure 142 is again periodically etched for a preset number of times, thereby further forming a third trench intermediate structure (not shown) below the second trench intermediate structure 142, and obtaining a new intermediate structure with a deeper depth before the deep trench is formed. And the same processing method as mentioned above is used to process the sidewalls of the third trench intermediate structure to remove the excessively thick passivation layer on the sidewalls and improve the rough morphology of the sidewall surface. And so on, until a deep trench 14 with a target depth and processed sidewalls is formed on the substrate 10, as shown in FIG. Figure 8 shown.

[0129] Each adsorption and reaction, purging, and removal of the reaction product layer in the aforementioned treatment process is considered a treatment cycle. At least one treatment cycle is inserted after every two to five periodic cycles of the etching process. After the final treatment of the last intermediate structure (the m / nth trench intermediate structure) formed before the formation of deep trench 14, a finished deep trench 14 with smooth sidewalls and high verticality is obtained.

[0130] In some embodiments, the preset number of etching passes may vary from large to small as the etching depth increases. For example, the preset number of etching passes (e.g., 5 passes) used to form the first intermediate structure (the first trench intermediate structure) on the substrate may be greater than the preset number of etching passes (e.g., 2 passes) used to form the last intermediate structure (the m / nth trench intermediate structure) on the substrate. The preset number of etching passes used to form other intermediate structures between these two intermediate structures may be gradually reduced (e.g., from 5 passes to 2 passes).

[0131] In some embodiments, as the etch depth increases and the aspect ratio becomes larger, it becomes increasingly difficult for the etching reactants generated during the etching process to diffuse upward from the bottom and evaporate. This results in a phenomenon where the deeper the etch depth, the more polymer remains at the bottom. Therefore, as the etch depth increases, the deposition step in the etching process cycle can be shortened, thereby correspondingly reducing the amount of polymer generated during the deposition step. This can maintain a consistent level of polymer residue from the top to the bottom of the sidewall, thereby facilitating the control and optimization of the three steps of adsorption and reaction, purging, and removal of the reaction product layer in the treatment process, particularly the control and optimization of the reaction time for polymer removal in the treatment process.

[0132] In some embodiments, as the etching depth increases, the reaction time for removing the polymer in the treatment process may remain unchanged or be slightly lengthened to facilitate the full volatilization of volatiles generated by the reaction.

[0133] In some embodiments, as the etching depth continues to increase, the temperature during the etching process can be gradually increased to increase the etching effect on the bottom of the deep trench, which is beneficial to adjust the uniformity of the upper, middle and lower dimensions of the deep trench and improve the verticality of the deep trench sidewalls.

[0134] In some embodiments, the critical dimension of the deep trench 14 may be less than 50 nm, and the aspect ratio of the deep trench 14 may be greater than or equal to 100:1.

[0135] Afterwards, the following step S16 may be performed.

[0136] Step S16: removing the mask pattern.

[0137] In some embodiments, after forming the deep trench 14, the surface of the substrate 10 is bombarded with a plasma of a fifth gas to remove the mask pattern 12 and the protective film 13 on the surface of the substrate 10. The plasma of the fifth gas is obtained by ionizing the fifth gas introduced into the process chamber. The structure after removing the mask pattern 12 and the protective film 13 is as follows: Figure 9 shown.

[0138] In some embodiments, the fifth gas includes an oxidizing gas for removing the mask pattern 12 of the photoresist material and the carbon-based protective film 13 .

[0139] In some embodiments, the fifth gas includes oxygen, and nitrogen may be introduced simultaneously as a diluent gas.

[0140] In some embodiments, when the surface of the substrate 10 is bombarded with plasma of the fifth gas, the temperature is 200° C. to 300° C. For example, the temperature can be 200° C., 210° C., 220° C., 230° C., 240° C., 250° C., 260° C., 270° C., 280° C., 290° C., or 300° C., or any value between any two of the foregoing temperature values.

[0141] In a second aspect, an embodiment of the present application further provides a semiconductor structure, which is obtained using a method for preparing a semiconductor structure as provided in any one of the embodiments of the first aspect above.

[0142] refer to Figure 9 In some embodiments, the semiconductor structure includes a substrate 10 and a deep trench 14 formed on the substrate 10 using the method for preparing the semiconductor structure according to the above embodiments.

[0143] In some embodiments, the semiconductor structure can be applied to MEMS devices (such as accelerometers, gyroscopes, pressure sensors, etc.), 3D integration and packaging (such as through-silicon via (TSV) preparation, chip stacking, etc.), optical devices (such as optical waveguides, diffraction gratings, etc.), power devices (such as insulated gate bipolar transistors (IGBTs), trench structures of power metal-oxide semiconductor field-effect transistors (MOSFETs), etc.).

[0144] In a third aspect, embodiments of the present application further provide a plasma processing apparatus, which is used to perform the method for preparing the semiconductor structure corresponding to the above embodiment to form the deep trench 14 on the semiconductor structure corresponding to the above embodiment. The plasma processing apparatus includes an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus, etc.

[0145] In other aspects, embodiments of the present application further provide an electronic device comprising the semiconductor structure of the aforementioned embodiment or a semiconductor structure obtained using the method for preparing the semiconductor structure of the aforementioned embodiment. The electronic device may be a storage device, a mobile phone, a computer, a tablet computer, an electronic instrument, a television, an artificial intelligence device, or the like.

[0146] In summary, the embodiments of the present application organically combine the etching process with the sidewall treatment technology, and alternately cycle to balance the etching rate and sidewall quality, thereby achieving a high etching rate and high etching accuracy for high aspect ratio etching structures, increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residue and ion shadow effect, and effectively improving the uniformity and roughness of local CF polymers, thereby achieving deep silicon etching with a higher aspect ratio and smaller nanoscale size compared to the existing technology.

[0147] The above are only preferred embodiments of the present application, and the embodiments are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made using the description and drawings of the present application should also be included in the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of mask patterns on the surface of the substrate, and etching the substrate using the mask patterns as masks to form an etched structure with a high aspect ratio on the substrate; The etching process includes a plurality of periodic cycle steps formed in sequence by a deposition step and an etching step. During the process of etching the substrate using the etching process, after each predetermined number of periodic cycle steps are completed, a treatment process different from the etching process is used to perform the following treatment on the intermediate structure formed before the high aspect ratio etched structure is formed: Removing part of the thickness of the passivation layer deposited on the sidewall to adjust the thickness uniformity of the passivation layer on the sidewall, thereby preventing the formation of an excessively thick passivation layer on the sidewall after repeated deposition of the passivation layer, which would affect the uniformity of etching and the timely removal of by-products. At least part of the protrusions on the sidewall that are exposed from the remaining surface of the passivation layer are removed to smooth the sidewall, thereby reducing the accumulation of the passivation layer and providing a vertical guide during downward etching. The treatment process includes: Using plasma of a first gas to perform adsorption and reaction on the sidewalls to remove a portion of the passivation layer and react with the substrate material on the exposed surface of the protrusion to generate a volatile reaction product layer on the exposed surface of the protrusion; bombarding the reaction product layer with plasma of a second gas to remove the reaction product layer; After performing the last treatment on the last intermediate structure formed before forming the high aspect ratio etched structure, the high aspect ratio etched structure is obtained; Then removing the mask pattern; The deposition step is used to form the passivation layer on the sidewall to protect the sidewall during etching, the passivation layer is a polymer, the substrate material includes silicon, the first gas includes chlorine, the reaction product layer includes a tetrachlorosilane layer, and the second gas includes a rare gas.

2. The method for preparing a semiconductor structure according to claim 1, wherein: After the reaction product layer is generated, it is first purged using a third gas, and then the reaction product layer is removed.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The second gas includes a mixed gas of a rare gas and a fluorine-based gas; and / or the third gas includes a rare gas or nitrogen.

4. The method for preparing a semiconductor structure according to claim 2, wherein: When using the plasma of the first gas for adsorption and reaction, the temperature is 60°C to 100°C, the pressure is 30mTorr to 2Torr, the source power is 500W to 5000W, and the flow rate of the first gas is 20sccm to 500sccm; and / or, when using the plasma of the second gas to remove the reaction product layer, the temperature is 60°C to 100°C, the pressure is 5mTorr to 50mTorr, the source power is 300W to 2000W, the bias power is 50W to 300W, the pulse frequency includes 1KHz, and the duty cycle is 10% to 90%; and / or, when using the third gas for purging, the flow rate of the third gas is 1000sccm to 3000sccm.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The preset number of times is n, and the total number of the periodic cycle steps is m, where 1<n<m.

6. The method for preparing a semiconductor structure according to claim 5, wherein: m / n≧10; and / or, n is 2 to 5 times.

7. A semiconductor structure, characterized in that The method for preparing the semiconductor structure is used as claimed in any one of claims 1 to 6.

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