Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present application discloses a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: using an etching process to periodically etch a substrate a preset number of times to form a first intermediate structure on the substrate; and performing a first treatment on the first intermediate structure, including using a first gas and a second gas to remove a portion of the thickness of a passivation layer deposited on the sidewalls of the first intermediate structure, and reacting with the substrate material on the surface of the protrusions present and exposed on the sidewalls to generate a reaction product layer; and using a third gas and a fourth gas to remove the reaction product layer to remove at least a portion of the protrusions; and repeating the etching process and the first treatment process until a high aspect ratio etched structure is formed on the substrate. The present application organically combines the etching process with sidewall treatment technology, alternating cycles to balance the etching rate and sidewall quality, and can achieve deep silicon etching with higher aspect ratios and smaller nanoscale dimensions.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular to a semiconductor structure manufacturing method and a semiconductor structure. Background Art

[0002] The rapidly developing field of advanced packaging demands higher interconnect density, driving deep silicon etching (DSE) to achieve nanometer-scale linewidths (less than 50nm) and higher aspect ratios (greater than 100:1). Existing etching processes, which rely on a cyclical process of deposition and etching, struggle to meet these extreme aspect ratio requirements due to physical limitations such as ion shadowing and reactive gas transport efficiency. Furthermore, nanometer-scale linewidths are particularly sensitive to thickness fluctuations in sidewall passivation layers (such as CF polymers). Large variations in sidewall passivation thickness can easily lead to linewidth deviations and etch tilt (three-dimensional through-silicon vias and memory stacks require an etch verticality error of less than ±0.2°). Furthermore, existing etching processes face challenges such as plasma chemical residue and localized roughness peaks (Ra > 5nm) caused by random CF polymer deposition on the sidewalls. These factors significantly impact the achievement of higher aspect ratios and nanometer-scale deep silicon etching. Therefore, it is necessary to develop a process that can significantly improve these issues. Summary of the Invention

[0003] The purpose of this application is to overcome the above-mentioned problems existing in the prior art and to provide a semiconductor structure manufacturing method and a semiconductor structure to solve the shortcomings of the existing etching process in deep silicon etching, which is difficult to achieve deep silicon etching with higher aspect ratio and nanometer-scale size due to the corresponding physical limitations, large fluctuations in the thickness of the sidewall passivation layer, and rough sidewalls.

[0004] To achieve the above objectives, the technical solutions of this application are as follows:

[0005] According to a first aspect of the present application, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming a plurality of organic mask patterns on the surface of the substrate;

[0008] Using an etching process and using the organic mask pattern as a mask, the substrate is periodically etched for a preset number of times to form a first intermediate structure on the substrate;

[0009] Performing a first treatment on the first intermediate structure using a first treatment process different from the etching process includes:

[0010] using a first gas and a second gas to remove a portion of the thickness of the passivation layer deposited on the sidewalls of the first intermediate structure and reacting the passivation layer with the substrate material on the surface of the protrusions present and exposed on the sidewalls to generate a reaction product layer; and using a third gas and a fourth gas to remove the reaction product layer to remove at least a portion of the protrusions;

[0011] Repeating the etching process and the first treatment process to sequentially form one or more second intermediate structures below the first intermediate structure, and performing the first treatment on each new second intermediate structure after it is formed, until a high aspect ratio etching structure consisting of the intermediate structures is formed on the substrate.

[0012] In some embodiments, when performing the first treatment process, a portion of the thickness of the passivation layer deposited on the sidewall is removed by using a mixed plasma of a first gas and a second gas to react with the passivation layer to adjust the thickness uniformity of the passivation layer on the sidewall; a first reaction product layer is generated by in-situ oxidation by reacting the plasma of the first gas with the substrate material on the exposed surface of the protrusion, and a second reaction product layer with low volatility is generated by reacting the plasma of the second gas with the substrate material on the exposed surface of the protrusion, and the sidewall is bombarded with a mixed plasma of a third gas and a fourth gas to remove the first reaction product layer and the second reaction product layer, so as to remove at least a portion of the protrusion and smooth the sidewall.

[0013] In some embodiments, when performing the first treatment process, a second treatment process is further used to perform a second treatment on the organic mask pattern, including:

[0014] The plasma of the second gas is used to bombard the surface of the organic mask pattern to improve the etching resistance of the organic mask pattern through modification.

[0015] In some embodiments, the etching process includes a periodic cycle step formed by a deposition step, a first etching step, and a second etching step in sequence. After each preset number of the periodic cycle steps are completed, the first treatment and the second treatment are performed once.

[0016] In some embodiments, the substrate material includes silicon, the first gas includes oxygen, and the first reaction product layer includes a silicon oxide layer.

[0017] In some embodiments, the second gas comprises hydrogen bromide and the second reaction product layer comprises a silicon tetrabromide layer.

[0018] In some embodiments, the third gas includes a fluorine-based gas.

[0019] In some embodiments, the fourth gas includes a noble gas.

[0020] In some embodiments, before forming the first intermediate structure, the method further includes: bombarding the interface of the substrate with plasma of a fifth gas to form a carbon-based protective film.

[0021] In some embodiments, after forming the high aspect ratio etching structure, the method further includes: using plasma of a sixth gas to remove the organic mask pattern and the carbon-based protective film.

[0022] In some embodiments, the organic matter includes photoresist.

[0023] In some embodiments, the fifth gas includes a noble gas.

[0024] In some embodiments, the sixth gas comprises an oxidizing gas.

[0025] In some embodiments, the etching process and the first treatment process are performed at a temperature below 60° C.

[0026] In some embodiments, the time for performing the deposition step, the first etching step and / or the second etching step is 0.1s to 2s.

[0027] In some embodiments, the first gas and the second gas are used for a time period of 0.5 s to 2 s.

[0028] In some embodiments, the third gas and the fourth gas are used for a time period of 0.5 s to 2 s.

[0029] In some embodiments, the preset number of times is 1 to 2 times.

[0030] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure, which is obtained using the semiconductor structure manufacturing method provided in any one of the embodiments of the first aspect above.

[0031] The embodiments of the present application may or at least have the following advantages:

[0032] (1) By performing a treatment (first treatment) on the formed intermediate structure each time a preset number of periodic cycle steps are completed during the etching process of the substrate, a portion of the thickness of the passivation layer deposited on the sidewall is removed, and at least a portion of the protrusions existing and exposed on the sidewall is removed, the thickness uniformity of the passivation layer on the sidewall can be adjusted, and the surface of the sidewall can be smoothed. By performing a periodic cycle of the etching process and alternating cycles between the treatments, the etching rate and the sidewall quality can be balanced, thereby achieving a high etching rate and high aspect ratio etching structure. Etching accuracy (atomic level accuracy) can increase the diffusion coefficient, improve the reaction gas transmission efficiency, solve the problems of plasma chemical residue (polymer thickness fluctuation has a great influence on the control of nanoscale line width) and ion shadow effect (nanoscale involves atomic size level), thereby effectively improving the uniformity and roughness of local CF polymer, and solving the line width offset (titling) problem, achieving higher verticality (90°±0.2°), and achieving better uniformity (uniform size of the upper, middle and lower positions of the high aspect ratio etched structure), and better sidewall smoothness.

[0033] (2) By embedding the above-mentioned treatment process in the periodic cycle steps of the etching process, the by-products generated in the intermediate structure (deep hole or groove) during the etching process can be removed in time to prevent the polymer from being too thick and accumulating. At the same time, the side wall roughness is improved to avoid the etch stop phenomenon (etch stop) after etching to a certain depth, or the bottom angle tilting inward (high verticality is difficult to achieve), and the by-products generated are difficult to be removed from the deep hole or groove in time, resulting in limited process adjustment and difficulty in achieving more refined structures.

[0034] (3) By using oxygen to treat the sidewalls, the protrusions can be removed in a targeted manner by reacting with the silicon material of the protrusions exposed on the sidewalls; by using hydrogen bromide in combination with oxygen, it can react with the exposed silicon material to generate a low-volatile byproduct, silicon tetrabromide, which can be adsorbed in the recessed portion of the sidewall at low temperature, making the entire sidewall surface flat, which is beneficial for the subsequent smooth treatment and continuous cyclic treatment steps when removing the reaction product layer; and, through the modification effect of hydrogen bromide plasma on the organic mask pattern (photoresist), the C / H ratio of the photoresist material can also be changed, making the photoresist material more stable in structure and improving the etching resistance of the photoresist, thereby improving the etching blocking ability of the organic mask pattern in the deep silicon etching process, that is, improving the etching selectivity of the organic mask pattern.

[0035] (4) By adopting a cyclical method of embedded etching process and embedded treatment process, fine etching and surface treatment of internal structures can be carried out. In the same processing chamber, while gradually deepening the high aspect ratio etching structure to be completed, side wall treatment and by-product treatment can be carried out, thus laying a good foundation for achieving deep silicon etching with higher aspect ratio (for example, greater than 100:1) and nanometer size (for example, less than 50nm) (the current mainstream width size is more than 140nm, and the aspect ratio is about 50:1).

[0036] Other advantages of the present application will be described in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a flow chart of a semiconductor structure manufacturing method according to a preferred embodiment of the present application.

[0038] Figure 2 A schematic diagram of a structure after an organic mask pattern is formed on a substrate is provided in a preferred embodiment of the present application.

[0039] Figure 3 A schematic diagram of a structure after a first trench intermediate structure is formed on a substrate is provided in a preferred embodiment of the present application.

[0040] Figure 4 This is a schematic diagram of the principle of processing the sidewall provided in a preferred embodiment of the present application. Figure 4 (a) is adsorption and reaction, Figure 4 (b) Desorption.

[0041] Figure 5 A schematic diagram of the structure after processing the intermediate structure of the first groove is provided in a preferred embodiment of the present application.

[0042] Figure 6 A schematic diagram of a structure after forming a second trench intermediate structure is provided in a preferred embodiment of the present application.

[0043] Figure 7 A schematic diagram of the structure after processing the middle structure of the second groove is provided in a preferred embodiment of the present application.

[0044] Figure 8 A schematic diagram of a complete structure after deep trenches are formed on a substrate is provided in a preferred embodiment of the present application.

[0045] Figure 9 A schematic diagram of a structure after removing the organic mask pattern is provided in a preferred embodiment of the present application.

[0046] In the figure, 10. substrate; 11. opening; 12. organic mask pattern; 13. carbon-based protective film; 14. deep trench; 141. first trench intermediate structure; 142. second trench intermediate structure; 15. scalloped stripes; 16. raised portion; 17. recessed portion. DETAILED DESCRIPTION

[0047] The purpose of the embodiments of the present application is to solve the shortcomings of existing etching processes in deep silicon etching, such as the difficulty in achieving deep silicon etching structures with higher aspect ratios and nanometer-scale dimensions due to corresponding physical limitations, large fluctuations in the thickness of the sidewall passivation layer, and rough sidewalls.

[0048] In order to solve the above problems, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0049] providing a substrate;

[0050] forming a plurality of organic mask patterns on the surface of the substrate;

[0051] Using an etching process and using the organic mask pattern as a mask, the substrate is periodically etched for a preset number of times to form a first intermediate structure on the substrate;

[0052] Performing a first treatment on the first intermediate structure using a first treatment process different from the etching process includes:

[0053] using a first gas and a second gas to remove a portion of the thickness of the passivation layer deposited on the sidewalls of the first intermediate structure and reacting the passivation layer with the substrate material on the surface of the protrusions present and exposed on the sidewalls to generate a reaction product layer; and using a third gas and a fourth gas to remove the reaction product layer to remove at least a portion of the protrusions;

[0054] Repeating the etching process and the first treatment process to sequentially form one or more second intermediate structures below the first intermediate structure, and performing the first treatment on each new second intermediate structure after it is formed, until a high aspect ratio etching structure consisting of the intermediate structures is formed on the substrate.

[0055] The embodiment of the present application provides the above-mentioned novel high aspect ratio etching method for etching structures, organically combines the etching process with the sidewall processing technology, and alternately cycles to balance the etching rate and sidewall quality, thereby achieving a high etching rate and high etching accuracy for high aspect ratio etching structures, increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residue and ion shadow effect, and effectively improving the uniformity and roughness of local CF polymers, so as to ultimately achieve deep silicon etching of nanometer-scale dimensions with a higher aspect ratio.

[0056] An embodiment of the present application also provides a semiconductor structure obtained using the semiconductor structure manufacturing method as described above.

[0057] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0058] refer to Figure 1 The present invention provides a method for manufacturing a semiconductor structure, which includes the following steps:

[0059] Step S11: providing a substrate.

[0060] refer to Figure 2 In some embodiments, the material of the substrate 10 includes silicon (ie, a silicon substrate).

[0061] In some embodiments, a silicon wafer may be used as the substrate 10 to further form a desired high aspect ratio etched structure on the substrate 10 .

[0062] In some embodiments, the high aspect ratio etched structure includes a deep trench, a deep via, or a through via, etc. The following takes forming a deep trench as a high aspect ratio etched structure on the substrate 10 as an example to describe the embodiments of the present application in detail.

[0063] In some embodiments, the silicon wafer may be doped to provide the substrate 10 with desired electrical properties.

[0064] In some embodiments, integrated circuits, such as transistor structures, may be fabricated on the substrate 10 , so that after forming deep trenches (high aspect ratio etched structures), the required vertical interconnections are achieved by filling the deep trenches with conductive materials.

[0065] Step S12: forming a plurality of organic mask patterns on the surface of the substrate.

[0066] refer to Figure 2 In some embodiments, an organic mask layer is formed on the upper surface of the substrate 10 and patterned to form a plurality of organic mask patterns 12 on the upper surface of the substrate 10. An opening 11 serving as an etching window is provided between any two adjacent organic mask patterns 12, and the bottom of the opening 11 exposes the surface of the substrate 10 located between the two adjacent organic mask patterns 12.

[0067] It should be noted that Figure 2The figure schematically illustrates a case where two organic mask patterns 12 are formed on the upper surface of the substrate 10. However, it is understood that more organic mask patterns may be formed on the upper surface of the substrate 10, such as three organic mask patterns, four organic mask patterns, ten organic mask patterns, etc., and the present invention is not limited thereto.

[0068] In some embodiments, the organic material includes photoresist, that is, the organic material mask layer includes a photoresist layer.

[0069] In some embodiments, a spin coating process is used to form a photoresist layer on the upper surface of the substrate 10. Then, a photolithography process is used to photolithography the photoresist layer, thereby forming a plurality of photoresist patterns, namely, organic mask patterns 12, on the upper surface of the substrate 10.

[0070] In some embodiments, before etching substrate 10, a fifth gas plasma is first used to bombard the interface (upper surface) of substrate 10, forming a carbon-based protective film 13 at the junction between the bottom of organic mask pattern 12 and the upper surface of substrate 10 (i.e., at the inner bottom corner of opening 11). The fifth gas plasma is generated by ionizing the fifth gas introduced into the process chamber.

[0071] Due to the mask edge effect, the passivation layer will be insufficiently deposited in the edge area during the subsequent main etching process, thereby exacerbating the etching behavior at the top. Ion bombardment is more concentrated at the top, and lateral etching in this area is intensified during etching, resulting in deeper and rougher sidewall scallops at the top of the deep trench. Therefore, by pre-forming a carbon-based protective film 13 at the junction of the bottom of the organic mask pattern 12 and the upper surface of the substrate 10, the top morphology of the etched area can be effectively protected during the subsequent etching process of the substrate 10, preventing abnormal excessive lateral etching behavior at the top. This ensures dimensional uniformity at different depths at the top, middle, and bottom during subsequent high-aspect-ratio etching, that is, ensures the verticality of the sidewalls.

[0072] In some embodiments, the fifth gas includes a noble gas.

[0073] In this embodiment, argon is used as the fifth gas, and the formed argon plasma (plasma of the fifth gas) bombards the photoresist material of the organic mask pattern 12 and the upper surface of the substrate 10, forming a carbon-based protective film 13 (a protective film of a carbon-based material containing C, N, and O) at the junction of the bottom of the organic mask pattern 12 and the upper surface of the substrate 10.

[0074] In some embodiments, the temperature during the process of forming the carbon-based protective film 13 by bombardment with argon gas is -20° C. to 60° C. For example, the temperature can be -20° C., -10° C., 0° C., 10° C., 20° C., 30° C., 40° C., 50° C., or 60° C., or any value between any two of the aforementioned temperature values.

[0075] In some embodiments, during the process of bombarding the carbon-based protective film 13 with argon gas, the pressure is 50 mTorr to 800 mTorr. For example, the pressure can be 50 mTorr, 100 mTorr, 200 mTorr, 300 mTorr, 400 mTorr, 500 mTorr, 600 mTorr, 700 mTorr, or 800 mTorr, or any value between any two of the aforementioned pressure values.

[0076] In some embodiments, in the process of forming the carbon-based protective film 13 by bombardment with argon gas, the source power is 50 W to 100 W. For example, the source power can be 50 W, 55 W, 60 W, 65 W, 70 W, 75 W, 80 W, 85 W, 90 W, 95 W, or 100 W, or any value between any two of the foregoing source power values.

[0077] In some embodiments, during the process of forming the carbon-based protective film 13 by bombardment with argon gas, the bias power is 10 W to 50 W. For example, the bias power can be 10 W, 15 W, 20 W, 25 W, 30 W, 35 W, 40 W, 45 W, or 50 W, or any value between any two of the aforementioned bias power values.

[0078] In some embodiments, the process of bombarding the carbon-based protective film 13 with argon gas takes 5 to 20 seconds, for example, 5 seconds, 10 seconds, 15 seconds, or 20 seconds, or any value between any two of the aforementioned time values.

[0079] Step S13: using an etching process and using the organic mask pattern as a mask, performing a preset number of periodic cycle etchings on the substrate to form a first trench intermediate structure on the substrate, and using a first treatment process to perform a first treatment on the first trench intermediate structure.

[0080] refer to Figure 3 In some embodiments, an etching process is used, and the organic mask pattern 12 is used as a mask to perform a predetermined number of periodic cycles of etching on the upper surface of the substrate 10 exposed at the bottom of the opening 11, thereby first forming a first trench intermediate structure 141 (first intermediate structure) on the substrate 10, with the goal of ultimately forming a deep trench completed structure on the substrate 10 (refer to Figure 8 ).

[0081] In some embodiments, the etching process includes multiple (or more) periodic cycles of a passivation layer deposition step, a first etching step, and a second etching step. The passivation layer deposition step forms a passivation layer on the sidewalls to protect them during etching; the first etching step removes the passivation layer from the bottom to allow for further etching downwards in the second etching step. By performing multiple periodic cycles, deep trenches are formed in substrate 10.

[0082] However, existing etching processes have difficulty meeting the extreme aspect ratio requirements of nanometer-scale line widths (less than 50nm) and higher aspect ratios (greater than 100:1). This is because existing etching processes are subject to corresponding physical limitations (such as ion shadowing and reaction gas transmission efficiency). Nanometer-scale line widths are more sensitive to thickness fluctuations of sidewall passivation layers (such as CF polymer), which can easily lead to line width offset and increased verticality errors.

[0083] At the same time, due to the characteristics of the existing etching process, multiple regular scallop-shaped stripes 15 will be formed on the side wall during multiple periodic etching cycles. Among them, the bottom of each scallop-shaped stripe 15 has a recessed portion 17, and the junction of two scallop-shaped stripes 15 has a raised portion 16, which makes the side wall have a rough surface morphology. In addition, there are problems such as plasma chemical residues and local roughness differences (local roughness peaks) caused by random deposition of CF polymers on the side walls. The existence of the above factors will cause the etching to stop after a certain depth is etched, or the bottom angle will tilt inward (high verticality is difficult to achieve), and the by-products produced will be difficult to be removed from the deep hole or groove in time, resulting in limited process adjustment and difficulty in achieving more refined structures. Therefore, the embodiments of the present application promptly remove excess polymer on the sidewalls to prevent uneven etching caused by an excessively thick passivation layer, and reduce the roughness of the sidewalls through processing to improve the smoothness of the sidewalls, thereby increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residues and ion shadow effects, and effectively improving the uniformity and roughness of local CF polymers, thereby enabling deep silicon etching of nanoscale sizes with higher aspect ratios.

[0084] In some embodiments, when etching the substrate 10 using an etching process, after each predetermined number of periodic cycles (periodic cyclic etching) are completed and an intermediate structure before deep trenches (high aspect ratio etched structures) are formed on the substrate 10, a step of treating the intermediate structure is embedded. Specifically, after each predetermined number of periodic cycles are completed, a special treatment process (first treatment process) different from the etching process is used to perform the following treatment (first treatment) on the intermediate structure formed before the deep trenches are formed: a portion of the thickness of the passivation layer deposited on the sidewalls is removed, and at least a portion of the protrusion 16 existing on the sidewalls and exposed from the surface of the remaining passivation layer is removed.

[0085] In some embodiments, an etching process is used to etch the substrate 10 using the organic mask pattern 12 as a mask, and a predetermined number of periodic cycles are completed to form a first trench intermediate structure 141 on the substrate 10 as the first intermediate structure before the deep trench is formed. Figure 3 As shown in FIG. The first trench intermediate structure 141 is an intermediate structure before a deep trench of a desired depth is formed. That is, the depth of the first trench intermediate structure 141 is less than the total depth of the deep trench. A first treatment process different from the etching process is then used to perform a first treatment on the sidewalls of the first trench intermediate structure 141.

[0086] When etching the substrate 10, due to the presence of the carbon-based protective film 13, when etching to form the first trench intermediate structure 141, the top is prevented from being excessively laterally etched, so that the size of the first trench intermediate structure 141 is relatively uniform, thereby laying a good foundation for ensuring the uniform size of different positions at the top, middle and bottom of the entire deep trench.

[0087] In some embodiments, when etching the substrate 10 using an etching process (until the entire deep trench is etched, the same below), the time for performing the deposition step, the first etching step, and / or the second etching step is limited to a very short time and is limited to a range of 0.1s to 2s, and the three steps are switched quickly. For example, the time for performing the deposition step can be 0.1s, 0.2s, 0.3s, 0.4s, 0.5s, 0.7s, 0.9s, 1s, 1.2s, 1.5s, 1.8s, or 2s, or any value between any two of the foregoing time values. The time for performing the first etching step can be 0.1s, 0.2s, 0.3s, 0.4s, 0.5s, 0.7s, 0.9s, 1s, 1.2s, 1.5s, 1.8s, or 2s, or any value between any two of the foregoing time values. The time for performing the second etching step can be 0.1s, 0.2s, 0.3s, 0.4s, 0.5s, 0.7s, 0.9s, 1s, 1.2s, 1.5s, 1.8s or 2s, or any value between any two of the foregoing time values.

[0088] In some embodiments, when etching the substrate 10 using an etching process, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, or any value between any two of the aforementioned temperature values.

[0089] In some embodiments, when etching the substrate 10 using an etching process, the pressure is 10 mTorr to 200 mTorr. For example, the pressure can be 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 130 mTorr, 150 mTorr, 190 mTorr, or 200 mTorr, or any value between any two of the aforementioned pressure values.

[0090] In some embodiments, when etching the substrate 10 using an etching process, the source power is 1000 W to 4000 W. For example, the source power can be 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, or 4000 W, or any value between any two of the foregoing source power values.

[0091] In some embodiments, when etching the substrate 10 using an etching process, the bias power is 10W to 200W. For example, the bias power can be 10W, 20W, 50W, 70W, 100W, 130W, 160W, 180W, or 200W, or any value between any two of the aforementioned bias power values. By setting the bias power, pulsed etching can be achieved.

[0092] In some embodiments, when etching the substrate 10 using an etching process, the process gas used in the deposition step includes a mixture of C4F8 and Ar. The process gas used in the first etching step and the second etching step includes a mixture of SF6 and Ar. Vertical deep trenches are formed by alternating between depositing a passivation layer using C4F8 and etching using SF6.

[0093] In some embodiments, assuming that the preset number of times is n and the total number of periodic cycle steps is m, then: 1<n<m.

[0094] In some embodiments, m / n≧10, that is, m / n is the number of first treatments. In the process of etching to form deep trenches, at least 10 first treatments need to be performed on the sidewalls, and at least 1 treatment needs to be performed on the upper, middle, and lower positions of the deep trenches respectively.

[0095] In some embodiments, the total number of times (m / n) the first treatment is performed on the sidewall may be 3 or more, 5 or more, 10 or more, 20 or more, 50 or more, 100 or more, 200 or more, 500 or more, or 1000 or more, or any number between any two of the foregoing numbers, but is not limited thereto.

[0096] In some embodiments, the preset number n is 1 to 2. For example, the preset number n can be 1 or 2.

[0097] In some other embodiments, the preset number n may be 1 to 10. For example, the preset number n may be 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 times, or more than 10 times.

[0098] In this embodiment, the preset number n is set to 2 times. The first groove intermediate structure 141 formed is as follows Figure 3 As shown. After two periodic cycles, two scalloped stripes 15 are formed on the sidewalls of the first trench intermediate structure 141. Each scalloped stripe 15 has a concave portion 17 at its bottom, and a convex portion 16 at the junction of two adjacent scalloped stripes 15. This results in a rough surface topography on the sidewalls of the first trench intermediate structure 141. A first treatment process is required to improve the rough surface topography of the sidewalls, smoothing the sidewalls. This facilitates the timely removal of byproducts, prevents excessive polymer deposition on the sidewalls, and improves the verticality of the etching.

[0099] In some embodiments, during the first treatment of the sidewalls of the first trench intermediate structure 141, a reactive gas is used to react with the passivation layer (polymer) on the sidewalls, removing a portion of the passivation layer to adjust the thickness uniformity of the passivation layer along the sidewalls. As the thickness of the passivation layer decreases due to the removal, the protrusions 16 on the sidewalls gradually become exposed from the surface of the passivation layer. During this process, the reactive gas reacts with the substrate 10 material on the surface of the exposed protrusions 16 to form a reaction product layer. By removing the reaction product layer, at least a portion of the protrusions 16 can be removed, resulting in a smoother sidewall after the protrusions 16 are removed.

[0100] For deep silicon etching with nanometer-scale line widths and higher aspect ratios, due to the influence of the process characteristics of the etching process itself, the deposition rate will gradually exceed the etching rate. This will make the polymer (passivation layer) easily accumulate on the bottom and affect the timely removal of by-products, thus causing problems such as etching stopping after reaching a certain depth. The embodiment of the present application removes part of the thickness of the passivation layer deposited on the sidewall after each preset number of periodic cycle steps. This can avoid the formation of an excessively thick passivation layer on the sidewall after repeated deposition of the passivation layer, which affects the uniformity of etching and the timely removal of by-products. At the same time, by utilizing the fact that the thickness of the passivation layer on the protrusion 16 is thinner than that of the passivation layer on the recessed portion 17, when removing the excessively thick passivation layer on the sidewall, the top of the protrusion 16 can be exposed from the surface of the passivation layer remaining after removing part of the thickness. Therefore, by reacting and removing this part of the protrusion 16, the sidewall surface becomes smoother. It can also reduce the accumulation of the passivation layer and facilitate the timely removal of by-products. In addition, the smooth sidewalls are beneficial for providing vertical guidance during downward etching, thereby achieving higher verticality and improving the electrical performance after deep trench filling.

[0101] In some embodiments, a first treatment process different from an etching process is used to perform a first treatment on the first trench intermediate structure 141, and the method includes: using a first gas and a second gas to remove a portion of the thickness of the passivation layer deposited on the sidewall of the first trench intermediate structure 141, and reacting with the substrate 10 material on the surface of the protrusion 16 that is present and exposed on the sidewall to generate a reaction product layer; and using a third gas and a fourth gas to remove the reaction product layer to remove at least a portion of the protrusion 16.

[0102] In some embodiments, during the first treatment process, a mixed plasma of a first gas and a second gas is firstly adsorbed onto the sidewall surfaces of the first trench intermediate structure 141 and reacts with the passivation layer, removing a portion of the passivation layer deposited on the sidewalls to reduce the thickness of the passivation layer and adjust the thickness uniformity of the passivation layer along the sidewalls. Furthermore, the first gas plasma undergoes an oxidation reaction with the substrate 10 material on the surface of the protrusion 16 exposed from the remaining passivation layer surface, in-situ oxidizing the exposed protrusion 16 surface to form a first reaction product layer. Simultaneously, the second gas plasma undergoes a replacement reaction with the substrate 10 material on the exposed protrusion 16 surface, forming a low-volatility second reaction product layer on the sidewall surfaces of the first trench intermediate structure 141. The first gas plasma and the second gas plasma are generated by ionizing the first and second gases (reactant gases) introduced into the process chamber.

[0103] In some embodiments, the first gas includes oxygen and the second gas includes hydrogen bromide. Nitrogen may also be used as a diluent gas. The oxygen and hydrogen bromide gases introduced into the process chamber are ionized to form oxygen plasma (the plasma of the first gas) and hydrogen bromide plasma (the plasma of the second gas). Using the oxygen plasma and hydrogen bromide plasma as the reactant gases, the sidewalls of the first trench intermediate structure 141 are subjected to the aforementioned first treatment, thereby correspondingly forming a silicon oxide (SiO2) layer as a first reaction product layer and a silicon tetrabromide (SiBr4) layer as a second reaction product layer.

[0104] The passivation layer is deposited during the passivation layer deposition step to protect the sidewalls during the etching step. Due to the influence of the scalloped streaks 15 on the sidewalls, the thickness of the passivation layer deposited on the sidewalls is non-uniform. Furthermore, the random deposition of CF polymer on the sidewalls can cause localized roughness peaks, exacerbating the roughness of the sidewalls. As the dimensions of the deep trenches reach the nanometer scale, the already small channels within the trenches become even more difficult to remove byproducts due to the influence of the scalloped streaks 15, the random deposition of CF polymer, ion shadowing, reaction gas transport efficiency, and plasma chemical residues. This can easily lead to polymer accumulation in the trenches, resulting in line width deviation, poor verticality, and uneven etching depth. Therefore, before the deep trench etching is completed, the intermediate structures of the deep trenches being formed need to be gradually processed. This is because, after the deep trenches are etched to their final depth using the etching process, the effects of these factors have already been established (for example, the sidewall roughness and overall morphology have been determined), making them difficult to modify through post-processing. Moreover, the polymers produced on the sidewalls by the existing etching methods will increase with the increase of etching depth, and will eventually lead to the "etching stop" problem due to excessive accumulation of polymers, thereby hindering higher aspect ratio vertical etching in the nanometer lateral dimension, and the final etching depth at the nanometer scale is also limited.

[0105] In the embodiment of the present application, oxygen plasma and hydrogen bromide plasma are used to perform the first treatment on the sidewalls of the first trench intermediate structure 141. Byproducts and the like present in the first trench intermediate structure 141 are removed, and the plasma reacts with the polymer material of the passivation layer on the sidewalls to remove a portion of the passivation layer on the sidewalls, thereby avoiding accumulation caused by excessive thickness of the passivation layer. During the process of removing a portion of the passivation layer, the top of the protrusion 16 will gradually be exposed from the surface of the passivation layer remaining after the partial thickness is removed. At this time, the oxygen ions (O 2- ) and bromide ions (Br - ) will continue to be adsorbed on the surface of the exposed protrusion 16 and can penetrate into the exposed protrusion 16 from multiple directions and react with the silicon (Si) material of the substrate 10, such as Figure 4 (a). After the oxygen ions react with the silicon (Si) material of the substrate 10, a silicon oxide layer is in situ generated on the surface of the exposed protrusion 16, causing the silicon material interface to gradually retreat toward the outside of the sidewall, thereby making the new interface of the silicon material formed after the reaction (i.e., the new sidewall surface to be formed later, refer to Figure 4 The fluctuations in (b) become more gradual. The low-volatility tetrabromosilane (SiBr4) layer, formed by the reaction of bromide ions with the silicon (Si) material of substrate 10, can be adsorbed in the recessed areas of the sidewalls at low temperatures, flattening the entire sidewall surface. This facilitates smooth removal of the reaction product layer and the continuous cyclic processing steps.

[0106] It is worth noting that the adsorption and reaction of oxygen ions on the silicon material surface of the sidewall is a self-limiting reaction. Therefore, when the silicon material surface of the sidewall oxidizes to a certain degree, it will no longer react, thus preventing the silicon material on the sidewall surface at the protrusion 16 from being excessively etched away, effectively achieving longitudinal cyclic etching and lateral atomic-level precision surface treatment. When the protrusion 16 is fully removed, making the sidewall surface smoother after removal, the passivation layer deposited again in subsequent cycles can be used to protect the processed upper sidewall, thereby preventing loss of width dimension.

[0107] In some embodiments, when the adsorption and reaction are performed using the plasma of the first gas and the second gas, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, or any value between any two of the foregoing temperature values.

[0108] In some embodiments, when the plasma of the first gas and the second gas is used for adsorption and reaction, the time is 0.5s to 2s. For example, the time can be 0.5s, 0.6s, 0.7s, 0.8s, 0.9s, 1s, 1.1s, 1.3s, 1.5s, 1.7s, or 2s, or any value between any two of the foregoing time values.

[0109] In some embodiments, when the adsorption and reaction are performed using the plasma of the first gas and the second gas, the pressure is 10 mTorr to 50 mTorr. For example, the pressure can be 10 mTorr, 15 mTorr, 20 mTorr, 25 mTorr, 30 mTorr, 35 mTorr, 40 mTorr, 45 mTorr, or 50 mTorr, or any value between any two of the foregoing pressure values.

[0110] In some embodiments, when the plasma of the first gas and the second gas is used for adsorption and reaction, the source power is 200 W to 2000 W. For example, the source power can be 200 W, 500 W, 800 W, 1000 W, 1200 W, 1500 W, 1800 W, or 2000 W, or any value between any two of the foregoing source power values.

[0111] In some embodiments, when the adsorption and reaction are performed using the plasma of the first gas and the second gas, the bias power is 5 W to 30 W. For example, the bias power can be 5 W, 6 W, 8 W, 10 W, 15 W, 20 W, 25 W, or 30 W, or any value between any two of the foregoing bias power values.

[0112] In some embodiments, when executing the first treatment process, a second treatment process is also used simultaneously to perform a second treatment on the organic mask pattern 12. The method includes: using a plasma of a second gas to bombard the surface of the organic mask pattern 12 to improve the etching resistance of the organic mask pattern 12 through modification.

[0113] In some embodiments, the second gas used in the second treatment process is the same as the second gas used in performing the first treatment process, for example, the second gas is also hydrogen bromide gas.

[0114] When hydrogen bromide gas (the second gas) is used together with oxygen gas (the first gas) to perform the first treatment on the sidewalls of the already formed first trench intermediate structure 141, the hydrogen bromide plasma simultaneously modifies the photoresist material of the organic mask pattern 12 to improve the etch resistance of the organic mask pattern 12. The principle is that the hydrogen bromide plasma breaks and recombines the C=O, CO, and CH chemical bonds in the photoresist material of the organic mask pattern 12, converting a CH3 group into two CH2 groups. These two CH2 groups are more likely to recombine chemical bonds, forming high-molecular polymer chains. This alters the C / H ratio of the photoresist material, making it more structurally stable and thus improving the etch resistance of the photoresist. This, in turn, enhances the etch barrier capability of the organic mask pattern 12 during deep silicon etching, thereby increasing the etch selectivity of the organic mask pattern 12.

[0115] In some embodiments, the first treatment and the second treatment are performed after each predetermined number of periodic cycles of the etching process are completed. In other words, the second treatment is performed simultaneously during the adsorption and reaction process of the first treatment.

[0116] Then, a mixed plasma of the third gas and the fourth gas is used to bombard the sidewall surface of the first trench intermediate structure 141, removing the first reaction product layer and the second reaction product layer, thereby removing at least a portion of the protrusion 16 and smoothing the sidewall. The third gas plasma and the fourth gas plasma are generated by ionizing the third gas and the fourth gas introduced into the process chamber.

[0117] In some embodiments, the third gas includes a fluorine-based gas, such as CF4.

[0118] In some embodiments, the fourth gas includes a rare gas, such as argon.

[0119] In this embodiment, low-energy fluoride ions (F - ) and argon ions (Ar + ), bombarding the sidewall surfaces of the first trench intermediate structure 141 to etch away the silicon oxide on the protrusion 16 and desorb the tetrabromosilane, removing it from the sidewalls to form smoother new sidewalls. Fluorine ions react with the silicon oxide on the protrusion 16, decomposing it and generating gaseous silicon tetrafluoride (SiF4), which is then removed from the sidewalls.

[0120] In some embodiments, when the reaction product layer is removed using the plasma of the third gas and the fourth gas, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, or any value between any two of the foregoing temperature values.

[0121] In some embodiments, when the plasma of the third gas and the fourth gas is used to remove the reaction product layer, the time is 0.5s to 2s. For example, the time can be 0.5s, 0.6s, 0.7s, 0.8s, 0.9s, 1s, 1.1s, 1.3s, 1.5s, 1.7s, or 2s, or any value between any two of the foregoing time values.

[0122] In some embodiments, when removing the reaction product layer using the plasma of the third gas and the fourth gas, the pressure is 2 mTorr to 10 mTorr. For example, the pressure can be 2 mTorr, 3 mTorr, 4 mTorr, 5 mTorr, 6 mTorr, 7 mTorr, 8 mTorr, 9 mTorr, or 10 mTorr, or any value between any two of the foregoing pressure values.

[0123] In some embodiments, when the reaction product layer is removed using the plasma of the third gas and the fourth gas, the source power is 50 W to 500 W. For example, the source power can be 50 W, 80 W, 100 W, 200 W, 300 W, 400 W, or 500 W, or any value between any two of the foregoing source power values.

[0124] In some embodiments, when the reaction product layer is removed using the plasma of the third gas and the fourth gas, the bias power is 5 W to 30 W. For example, the bias power can be 5 W, 6 W, 8 W, 10 W, 15 W, 20 W, or 30 W, or any value between any two of the foregoing bias power values.

[0125] In some embodiments, when the reaction product layer is removed using a plasma of the third gas and the fourth gas, the total flow rate of the third gas and the fourth gas is 20 sccm to 200 sccm. For example, the flow rate can be 20 sccm, 50 sccm, 80 sccm, 100 sccm, 130 sccm, 160 sccm, or 200 sccm, or any value between any two of the foregoing flow rates.

[0126] In some embodiments, when the reaction product layer is removed using plasma of the third gas and the fourth gas, the flow ratio of the third gas to the fourth gas is 1:1 to 1:3. For example, the flow ratio may be 1:1, 1:2, or 1:3, but is not limited thereto.

[0127] After the reaction product layer is removed by the plasma of the third gas and the fourth gas, the newly formed sidewall surface becomes smooth, thereby reducing the roughness of the sidewall surface. Figure 4 (b) shows the sidewall morphology of the first trench intermediate structure 141 after processing. Figure 5 As shown. Figure 3 In comparison, it can be seen that the sidewalls are significantly smoothed, resulting in a significant reduction in sidewall roughness. This allows the passivation layer deposited in subsequent cycles to more evenly cover the smooth upper sidewall surface after treatment, eliminating the need for a very thick deposition thickness to provide good sidewall protection and effectively avoiding local roughness peaks (Ra > 5nm) caused by random deposition of CF polymer on the sidewalls.

[0128] Afterwards, the substrate 10 below the first trench intermediate structure 141 can be further etched using the aforementioned etching process based on the processed first trench intermediate structure 141 to form a deeper trench, and the sidewalls can be subjected to the first treatment process described above.

[0129] Step S14: using an etching process, continuing to perform a preset number of periodic cycle etching on the substrate below the first trench middle structure, forming a second trench middle structure below the first trench middle structure, and using a first processing process, performing a first processing on the second trench middle structure.

[0130] refer to Figure 6 In some embodiments, the same method as that used to form the first trench intermediate structure 141 is used, that is, an etching process is used, and the organic mask pattern 12 is used as a mask to perform a predetermined number of periodic cycle etchings on the substrate 10 below the bottom of the first trench intermediate structure 141, thereby forming a second trench intermediate structure 142 below the first trench intermediate structure 141 (for ease of understanding, Figure 6 The original bottom of the first trench intermediate structure 141 is indicated by an arc-shaped dashed line. The second trench intermediate structure 142 (second intermediate structure) and the first trench intermediate structure 141 together constitute an intermediate structure formed before the deep trench is formed.

[0131] In this embodiment, the preset number n can also be set to 2 times. The second groove intermediate structure 142 formed, such as Figure 6 After two more periodic cycle steps, two scallop-shaped stripes 15 will also be formed on the sidewalls of the newly formed second trench intermediate structure 142 etched below the first trench intermediate structure 141 whose sidewalls have been processed (refer to Figure 3 The bottom of each scallop-shaped stripe 15 also has a concave portion 17, and the junction of two adjacent scallop-shaped stripes 15 also has a convex portion 16, so that the sidewall of the second groove intermediate structure 142 has a rough surface morphology ( Figure 6 The vertical dotted line in the figure shows that the protrusion 16 on the sidewall of the second trench intermediate structure 142 is more protruding than the sidewall of the first trench intermediate structure 141 after treatment, for the sake of comparison. Therefore, it is also necessary to use the same first treatment method in the previous step to treat the sidewall of the second trench intermediate structure 142 to remove the excessively thick passivation layer on the sidewall and improve the rough morphology of the sidewall surface. The morphology of the sidewall of the second trench intermediate structure 142 after treatment is shown in FIG. Figure 7 As shown. You can see, Figure 6 The two scallop-shaped stripes 15 on the sidewall of the second groove intermediate structure 142 are shown. After processing, the protrusion has been significantly reduced, so that Figure 7 The overall sidewall morphology of the processed second trench intermediate structure 142 is smoother and is close to the smooth sidewall morphology of the processed first trench intermediate structure 141 ( Figure 7The vertical dotted line in the figure shows that the sidewalls of the second trench intermediate structure 142 after treatment have the same degree of undulation as the sidewalls of the first trench intermediate structure 141 for easy comparison), so that the overall roughness of the sidewalls is significantly reduced. For the specific treatment process of the sidewalls of the second trench intermediate structure 142, please refer to the corresponding description of step S13 and combine it with the following steps: Figure 4 Please understand it and I will not elaborate on it.

[0132] Step S15: Repeat step S14 until a deep trench with a target depth is formed on the substrate.

[0133] In some embodiments, the method of steps S13 and S14 can be used to further etch the substrate 10 in the depth direction. That is, using the method of forming the first trench intermediate structure 141 and the second trench intermediate structure 142, an etching process is used, using the organic mask pattern 12 as a mask, and the substrate 10 below the bottom of the second trench intermediate structure 142 is again periodically etched for a predetermined number of times, thereby continuing to form a new second trench intermediate structure (not shown) below the second trench intermediate structure 142, thereby obtaining a new deeper intermediate structure before the deep trench is formed. The sidewalls of the new second trench intermediate structure are then subjected to a first treatment using the same treatment method as described above to remove the excessively thick passivation layer on the sidewalls and improve the rough morphology of the sidewall surfaces.

[0134] The etching process and the first treatment process can be repeated in this manner to sequentially form one or more second trench intermediate structures below the first intermediate structure. After each new second trench intermediate structure is formed, the first treatment is performed on the new second trench intermediate structure until a deep trench 14 (high aspect ratio etched structure) having a target depth and processed sidewalls, which is composed of the intermediate structures, is formed on the substrate 10. Figure 8 shown.

[0135] Each adsorption, reaction, and removal of the reaction product layer in the first treatment process is considered a treatment cycle. At least one treatment cycle is inserted after each one or two periodic cycles of the etching process. After the final treatment of the last second trench intermediate structure formed before the formation of the deep trench 14, a deep trench 14 with smooth sidewalls and high verticality is obtained.

[0136] It should be noted that as the etch depth increases and the aspect ratio becomes larger, it becomes increasingly difficult for the etching reactants generated during the etching process to diffuse upward and evaporate from the bottom. This results in a phenomenon where the deeper the etch depth, the more polymer remains at the bottom. Therefore, as the etch depth increases, the deposition step in the etching process cycle can be shortened (compared to the etching step), resulting in a corresponding reduction in the amount of polymer produced during the deposition step. This can maintain a consistent level of polymer residue from the top to the bottom of the sidewalls, thereby facilitating the control and optimization of the time for the adsorption and reaction steps and the removal of the reaction product layer in the first treatment process, particularly the control and optimization of the reaction time for polymer removal in the first treatment process.

[0137] In some embodiments, as the etching depth increases, the reaction time for removing the polymer in the first treatment process may remain unchanged or be slightly lengthened to facilitate the full volatilization of volatiles generated by the reaction.

[0138] In some embodiments, as the etching depth continues to increase, the temperature during the etching process can be gradually increased to increase the etching effect on the bottom of the deep trench, which is beneficial to adjust the uniformity of the upper, middle and lower dimensions of the deep trench and improve the verticality of the deep trench sidewalls.

[0139] In some embodiments, the critical dimension of the deep trench 14 may be less than 50 nm, and the aspect ratio of the deep trench 14 may be greater than or equal to 100:1.

[0140] Afterwards, the following step S16 may be performed.

[0141] Step S16: removing the organic mask pattern.

[0142] In some embodiments, after forming the deep trench 14, the surface of the substrate 10 is bombarded with a plasma of a sixth gas to remove the organic mask pattern 12 and the carbon-based protective film 13 on the surface of the substrate 10. The plasma of the sixth gas is obtained by ionizing the sixth gas introduced into the process chamber. The semiconductor structure obtained after removing the organic mask pattern 12 and the carbon-based protective film 13 is as shown in FIG. Figure 9 shown.

[0143] In some embodiments, the sixth gas includes an oxidizing gas, wherein the oxidizing gas may be, for example, oxygen, and nitrogen may be introduced simultaneously as a diluent gas.

[0144] In a second aspect, an embodiment of the present application further provides a semiconductor structure, which is obtained using a semiconductor structure manufacturing method provided in any one of the embodiments of the first aspect above.

[0145] refer to Figure 9In some embodiments, the semiconductor structure includes a substrate 10 and a deep trench 14 formed on the substrate 10 using the semiconductor structure manufacturing method of the above embodiments.

[0146] In some embodiments, the semiconductor structure can be applied to MEMS devices (such as accelerometers, gyroscopes, pressure sensors, etc.), 3D integration and advanced packaging (such as through silicon via (TSV) preparation, chip stacking, etc.), optical devices (such as optical waveguides, diffraction gratings, etc.), power devices (such as insulated gate bipolar transistors (IGBTs), trench structures of power metal-oxide semiconductor field-effect transistors (MOSFETs), etc.).

[0147] In a third aspect, embodiments of the present application further provide a plasma processing apparatus, which is used to perform the semiconductor structure manufacturing method corresponding to the above embodiment to form the deep trench 14 on the semiconductor structure corresponding to the above embodiment. The plasma processing apparatus includes an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus, etc.

[0148] In other aspects, embodiments of the present application further provide an electronic device comprising the semiconductor structure of the aforementioned embodiment or a semiconductor structure obtained using the semiconductor structure manufacturing method of the aforementioned embodiment. The electronic device may be a storage device, a mobile phone, a computer, a tablet computer, an electronic instrument, a television, an artificial intelligence device, or the like.

[0149] In summary, the embodiments of the present application organically combine the etching process with the sidewall treatment technology, and alternately cycle to balance the etching rate and sidewall quality, thereby achieving a high etching rate and high etching accuracy for high aspect ratio etching structures, increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residue and ion shadow effect, and effectively improving the uniformity and roughness of local CF polymers. Therefore, it is possible to optimize the defects of the existing etching process and is suitable for the stringent requirements of deep silicon vertical morphology and high aspect ratio in advanced semiconductor manufacturing, thereby being able to achieve deep silicon etching with higher aspect ratio and smaller nanoscale size compared to the existing technology.

[0150] The above are only preferred embodiments of the present application, and the embodiments are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made using the description and drawings of the present application should also be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of organic mask patterns on the surface of the substrate; Using an etching process and using the organic mask pattern as a mask, the substrate is periodically etched for a preset number of times to form a first intermediate structure on the substrate; Performing a first treatment on the first intermediate structure using a first treatment process different from the etching process includes: using a first gas and a second gas to remove a portion of the thickness of the passivation layer deposited on the sidewalls of the first intermediate structure and react with the substrate material on the surface of the protrusions present and exposed on the sidewalls to generate a reaction product layer, wherein the first gas comprises oxygen and the second gas comprises hydrogen bromide; and removing the reaction product layer using a third gas and a fourth gas to remove at least a portion of the protrusion, wherein the third gas comprises a fluorine-based gas and the fourth gas comprises a rare gas; Repeating the etching process and the first treatment process to sequentially form one or more second intermediate structures below the first intermediate structure, and performing the first treatment on each new second intermediate structure after it is formed, until a high aspect ratio etching structure consisting of the intermediate structures is formed on the substrate.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: When performing the first treatment process, a portion of the thickness of the passivation layer deposited on the sidewall is removed by using a mixed plasma of a first gas and a second gas to react with the passivation layer, so as to adjust the thickness uniformity of the passivation layer on the sidewall; a first reaction product layer is generated by in-situ oxidation by allowing the plasma of the first gas to react with the substrate material on the exposed surface of the protrusion, and a second reaction product layer with low volatility is generated by allowing the plasma of the second gas to react with the substrate material on the exposed surface of the protrusion, and the sidewall is bombarded with a mixed plasma of a third gas and a fourth gas to remove the first reaction product layer and the second reaction product layer, so as to remove at least a portion of the protrusion and smooth the sidewall.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: When performing the first treatment process, a second treatment process is also used to perform a second treatment on the organic mask pattern, including: The plasma of the second gas is used to bombard the surface of the organic mask pattern to improve the etching resistance of the organic mask pattern through modification.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The etching process includes periodic cycle steps formed by a deposition step, a first etching step, and a second etching step in sequence. After each preset number of periodic cycle steps are completed, the first treatment and the second treatment are performed once.

5. The method for manufacturing a semiconductor structure according to claim 2, wherein: The substrate material includes silicon, the first reaction product layer includes a silicon oxide layer, and the second reaction product layer includes a silicon tetrabromide layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming the first intermediate structure, it also includes: using the plasma of the fifth gas to bombard the interface of the substrate to form a carbon-based protective film; after forming the high aspect ratio etching structure, it also includes: using the plasma of the sixth gas to remove the organic mask pattern and the carbon-based protective film.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The organic matter includes photoresist, the fifth gas includes a rare gas, and the sixth gas includes an oxidizing gas.

8. The method for manufacturing a semiconductor structure according to claim 4, wherein: The temperature for performing the etching process and the first treatment process is lower than 60°C, the time for performing the deposition step, the first etching step and / or the second etching step is 0.1s to 2s, the time for using the first gas and the second gas is 0.5s to 2s, and the time for using the third gas and the fourth gas is 0.5s to 2s.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The preset number of times is 1 to 2 times.

10. A semiconductor structure, characterized in that The method for manufacturing a semiconductor structure is used as claimed in any one of claims 1 to 9.

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