Wafer combination body capable of solving bubble problem of bonding interface, chip and preparation method

Abstract

The invention provides a wafer combination body capable of solving the bubble problem of a bonding interface, a chip and a preparation method. The preparation method comprises the following steps: providing a first wafer and a second wafer; forming a first dielectric layer on one surface of the first wafer; etching the first dielectric layer to form a groove; forming a second dielectric layer on the surface, opposite to the first dielectric layer, of the second wafer; and aligning and bonding the second dielectric layer and the first dielectric layer to form a wafer combination body. According to the method, the micro-texture structure of the groove is formed on the bonding surface of the wafer, a dissipation channel is provided for gas generated by chemical bonds formed on the bonding interface in the wafer bonding process, the generation rate of bubbles on the bonding interface is reduced, the quality and reliability of the bonding interface are effectively improved, and the yield of chip tape-out is improved. Especially, the quality of a direct bonding XOI film layer is improved, and the reliability of an XOI wafer material is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and particularly relates to a wafer combination, a chip and a preparation method capable of solving the problem of bubbles at a bonding interface. Background Art

[0002] Wafer bonding technology is a technology for tightly connecting two wafers or materials, and has a wide range of applications in the fields of chip packaging and MEMS, such as metal eutectic bonding, anodic bonding, polymer adhesive bonding, and direct bonding. Among them, wafer direct bonding can achieve low-temperature and high-efficiency bonding through the treatment of the bonding interface without the aid of other substances, effectively protecting the low-temperature process in the chip wafer process and reducing the thermal budget of the chip wafer process. However, due to the chemical reaction at the bonding interface during the wafer direct bonding process, hydrogen or water vapor is generated, resulting in the formation of bubbles or voids at the bonding interface, seriously affecting the quality reliability and property stability of the bonded wafers. Therefore, how to solve the problem of bubbles at the bonding interface is the key problem to promote the development of wafer bonding technology. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to some extent. For this reason, an embodiment of the present invention provides a wafer combination, a chip and a preparation method capable of solving the problem of bubbles at a bonding interface, which can effectively improve the bubble phenomenon in heterogeneous integration and enhance the bonding strength.

[0004] A first aspect embodiment of the present invention provides a preparation method of a wafer combination capable of solving the problem of bubbles at a bonding interface, including:

[0005] Providing a first wafer and a second wafer;

[0006] Forming a first dielectric layer on one surface of the first wafer;

[0007] Etching a groove in the first dielectric layer;

[0008] Forming a second dielectric layer on the surface of the second wafer opposite to the first dielectric layer;

[0009] Aligning and bonding the second dielectric layer with the first dielectric layer to form a wafer combination.

[0010] In some embodiments, the groove is a columnar groove, and the columnar groove is arranged along the thickness direction of the first dielectric layer.

[0011] In some embodiments, the groove is a strip-shaped groove, and the strip-shaped groove is arranged along the horizontal direction and penetrates both sides of the first dielectric layer.

[0012] In some embodiments, the depth of the groove is equal to the thickness of the first dielectric layer.

[0013] In some embodiments, a plurality of grooves are evenly distributed and parallel to each other.

[0014] In some embodiments, the materials of the first dielectric layer and the second dielectric layer are a stack of one or more of SiO2, Al2O3, Si3N4, and HfO2.

[0015] In some embodiments, before the first dielectric layer and the second dielectric layer are aligned and bonded, surface activation treatments are respectively performed on the first dielectric layer and the second dielectric layer, and the surface activation treatment methods include one or a combination of more of chemical wet activation, plasma activation, and ultraviolet ozone vacuum activation.

[0016] In some embodiments, the bonding temperature of the first dielectric layer and the second dielectric layer is 100 - 500 °C, and the bonding time is 10 - 600 min.

[0017] A second aspect embodiment of the present invention proposes a wafer bonding body prepared by the above preparation method.

[0018] A third aspect embodiment of the present invention proposes a chip including the above wafer bonding body. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings.

[0020] Among them:

[0021] Figure 1 is a flowchart of a method for preparing a wafer bonding body capable of solving the problem of air bubbles at the bonding interface in an embodiment of the present invention;

[0022] Figures 2 - 5 is a flowchart of a method for preparing a wafer bonding body in Embodiment 1 of the present invention;

[0023] Among them,

[0024] Figure 2 is a schematic diagram of steps S2 and S3 in Embodiment 1 of the present invention;

[0025] Figure 3 is Figure 2 a top view of;

[0026] Figure 4 is a schematic diagram of step S4 in Embodiment 1 of the present invention;

[0027] Figure 5 is a schematic diagram of step S5 in Embodiment 1 of the present invention;

[0028] Figures 6 - 9 is a flowchart of a method for preparing a wafer bonding body in Embodiment 2 of the present invention;

[0029] Among them,

[0030] Figure 6 is a schematic diagram of steps S2 and S3 in Embodiment 2 of the present invention;

[0031] Figure 7 is Figure 2 a top view of;

[0032] Figure 8 is a schematic diagram of step S4 in Embodiment 2 of the present invention;

[0033] Figure 9 is a schematic diagram of step S5 in Embodiment 2 of the present invention;

[0034] Reference signs:

[0035] 101, first wafer; 102, first dielectric layer; 103, columnar groove; 104, strip groove; 201, second wafer; 202, second dielectric layer; 301, wafer combination. Detailed implementation manners

[0036] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the accompanying drawings. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present invention and should not be construed as a limitation to the present invention.

[0037] The following refers to the accompanying drawings to describe a wafer combination, a chip and a preparation method capable of solving the problem of bubbles at the bonding interface in an embodiment of the present invention.

[0038] As Figures 1 - 9 shown, an embodiment of the first aspect of the present invention proposes a preparation method for a wafer combination capable of solving the problem of bubbles at the bonding interface, including:

[0039] S1. Provide a first wafer 101 and a second wafer 201;

[0040] S2. Form a first dielectric layer 102 on the upper surface of the first wafer 101;

[0041] S3. Etch to form a groove on the first dielectric layer 102;

[0042] S4. Form a second dielectric layer 202 on the lower surface of the second wafer 201;

[0043] S5. Align and bond the second dielectric layer 202 with the first dielectric layer 102 to form a wafer combination 301.

[0044] In the embodiments of the present invention, a micro-texture structure with grooves is formed on the wafer bonding surface, providing a dissipation channel for the gas generated by the formation of chemical bonds at the bonding interface during the wafer bonding process, reducing the generation rate of bubbles at the bonding interface, effectively improving the quality and reliability of the bonding interface, and increasing the yield of chip wafering. In particular, it improves the film quality of direct bonding XOI and enhances the reliability of XOI wafer materials.

[0045] Further, the first dielectric layer 102 and the second dielectric layer 202 are formed by any one of thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICPCVD), low temperature chemical vapor deposition (LPCVD), etc.

[0046] In some embodiments, as Figures 2 - 5 shown, the groove is a columnar groove 103, and the columnar groove 103 is arranged in the vertical direction. The dissipated bubbles will converge in the columnar groove 103.

[0047] In some embodiments, as Figures 6 - 9 shown, the groove is a strip groove 104, and the strip groove 104 is arranged in the horizontal direction and penetrates through the front and back sides of the first dielectric layer 102. The dissipated bubbles will converge in the strip groove 104 and be discharged outwards.

[0048] In some embodiments, the depth of the groove is equal to the thickness of the first dielectric layer 102.

[0049] Further, the thicknesses of the first dielectric layer 102 and the second dielectric layer 202 are respectively 10 nm to 2 μm, preferably 100 nm, 200 nm, 300 nm, 400 nm, 500 nm.

[0050] Further, when the groove is a columnar groove 103, the diameter of the columnar groove 103 is 5 μm to 500 μm, preferably 10 μm, 20 μm, 50 μm, 80 μm, 100 μm. When the groove is a strip groove 104, the length of the strip groove 104 is 500 μm to 150 mm, preferably 500 μm, 800 μm, 1000 μm, 5000 μm, and the width is 5 μm to 500 μm, preferably 5 μm, 20 μm, 30 μm, 50 μm, 100 μm.

[0051] In some embodiments, a number of grooves are evenly distributed and parallel to each other.

[0052] In some embodiments, the materials of the first dielectric layer 102 and the second dielectric layer 202 are one or more laminates of SiO2, Al2O3, Si3N4, HfO2.

[0053] In some embodiments, before the first dielectric layer 102 and the second dielectric layer 202 are aligned and bonded, the surfaces of the first dielectric layer 102 and the second dielectric layer 202 are respectively subjected to surface activation treatment, and the surface activation treatment methods include one or a combination of chemical wet activation, plasma activation, and ultraviolet ozone vacuum activation.

[0054] Furthermore, the surface roughness of the first dielectric layer 102 and the second dielectric layer 202 is less than or equal to 0.5 nm.

[0055] In some embodiments, the bonding temperature for bonding the first dielectric layer 102 and the second dielectric layer 202 is 100 - 500 °C, preferably 150 °C, 200 °C, 300 °C, 350 °C, 400 °C, and the bonding time is 10 - 600 min, preferably 60 min, 120 min, 180 min, 240 min, 300 min, 600 min.

[0056] In a second aspect embodiment of the present invention, a wafer bonding body 301 prepared by the above preparation method is proposed.

[0057] In a third aspect embodiment of the present invention, a chip is proposed, which includes the above wafer bonding body 301.

[0058] The present invention will be further described below through specific embodiments.

[0059] Embodiment 1

[0060] As Figures 2 - 5 shown, a preparation method of a wafer bonding body that can solve the problem of air bubbles at the bonding interface includes:

[0061] S1. Provide a first wafer 101 and a second wafer 201 that have been subjected to single-sided polishing or double-sided polishing.

[0062] S2. Grow SiO2 as the first dielectric layer 102 on the polished surface of the first wafer 101 by thermal oxidation, with a thickness of 500 nm.

[0063] S3. Etch columnar grooves 103 on the surface of the first dielectric layer 102 of the first wafer 101 by lithography, with the depth of the columnar grooves 103 being 500 nm and the diameter being 100 um.

[0064] S4. Deposit SiO2 as the second dielectric layer 202 on the polished surface of the second wafer 201 by chemical vapor deposition, with a thickness of 300 nm.

[0065] S5. Chemically mechanically polish the surfaces of the first dielectric layer 102 and the second dielectric layer 202 to obtain a flat surface with a roughness less than 0.5 nm. Place the polished wafers in a surface activation bonder, and perform surface activation treatment on the first dielectric layer 102 of the first wafer 101 and the second dielectric layer 202 of the second wafer 201 in an argon atmosphere. The plasma power is 300 W, the flow rate is 300 ml / min, and the treatment time is 2 min. Then align and bond the first dielectric layer 102 and the second dielectric layer 202 on the surfaces of the two wafers. The bonding pressure is 4000 mbar, the bonding temperature is 300 °C, and the bonding time is 120 min to form a wafer assembly 301.

[0066] Example 2

[0067] As Figures 6 - 9 shown, a method for preparing a wafer assembly that can solve the problem of bubbles at the bonding interface includes:

[0068] S1. Provide a first wafer 101 and a second wafer 201 that have been single-polished or double-polished.

[0069] S2. Grow SiO2 as the first dielectric layer 102 with a thickness of 300 nm on the polished surface of the first wafer 101 by thermal oxidation.

[0070] S3. Etch a strip groove 104 with a depth of 300 nm, a width of 100 μm, and a length of 1000 μm on the surface of the first dielectric layer 102 of the first wafer 101 by lithography.

[0071] S4. Deposit SiO2 as the second dielectric layer 202 with a thickness of 300 nm on the polished surface of the second wafer 201 by chemical vapor deposition.

[0072] S5. Chemically mechanically polish the surfaces of the first dielectric layer 102 and the second dielectric layer 202 to obtain a flat surface with a roughness less than 0.5 nm. Place the polished wafers in an oxygen plasma atmosphere. The oxygen plasma power is 300 W, the flow rate is 300 ml / min, and the treatment time is 2 min. Then immerse them in deionized water for 2 min, and finally dry them. Align and bond the first dielectric layer 102 and the second dielectric layer 202 on the surfaces of the two wafers. The bonding temperature is 300 °C, and the bonding time is 120 min to form a wafer assembly 301.

[0073] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention.

[0074] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0075] In the present invention, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or communicable with each other; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0076] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0077] In the present invention, terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0078] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A preparation method of a wafer bonding body capable of solving the problem of bubbles at the bonding interface, characterized in that Comprising: Providing a first wafer and a second wafer; Forming a first dielectric layer on one surface of the first wafer; Etching a groove in the first dielectric layer; Forming a second dielectric layer on the surface of the second wafer opposite to the first dielectric layer; Aligning and bonding the second dielectric layer with the first dielectric layer to form a wafer bonded body.

2. The preparation method according to claim 1, wherein, The groove is a columnar groove, and the columnar groove is arranged along the thickness direction of the first dielectric layer.

3. The preparation method according to claim 1, characterized in that, The groove is a strip-shaped groove, and the strip-shaped groove is arranged in the horizontal direction and penetrates both sides of the first dielectric layer.

4. The preparation method according to claim 1, characterized in that, The depth of the groove is equal to the thickness of the first dielectric layer.

5. The preparation method according to claim 1, characterized in that, A plurality of the grooves are evenly distributed and parallel to each other.

6. The preparation method according to claim 1, wherein The materials of the first dielectric layer and the second dielectric layer are a laminate of one or more of SiO2, Al2O3, Si3N4, and HfO2.

7. The preparation method according to claim 1, wherein Before the first dielectric layer and the second dielectric layer are aligned and bonded, surface activation treatment is respectively performed on the first dielectric layer and the second dielectric layer, and the surface activation treatment methods include one or more combinations of chemical wet activation, plasma activation, and ultraviolet ozone vacuum activation.

8. The preparation method according to claim 1, wherein, The bonding temperature for bonding the first dielectric layer and the second dielectric layer is 100 - 500 °C, and the bonding time is 10 - 600 min.

9. A wafer bonded body prepared by the preparation method according to any one of claims 1 - 8.

10. A chip, characterized in that, Comprising the wafer bonded body according to claim 9.

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