Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate, a through hole, a buffer layer, a first circuit structure and an electronic element. The substrate includes a first side and a second side opposite to the first side. The through hole penetrates through the substrate. The buffer layer is arranged on the first side of the substrate, the second side of the substrate and the inner wall of the through hole. The first circuit structure is arranged on the first side. The electronic component is disposed on the first circuit structure. The buffer layer includes a plurality of layers. According to the electronic device disclosed by the invention, the structural strength of the substrate can be improved or the adhesion between the substrate and other film layers can be improved.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device that can improve the structural strength of a substrate or the adhesion ability between the substrate and other film layers. Background Art

[0002] Electronic devices or spliced electronic devices including semiconductor elements have been widely used in different fields such as communication, display, automotive, or aviation. With the booming development of electronic devices, electronic devices are being developed towards being thinner and lighter, so the requirements for the reliability or quality of electronic devices are getting higher. Summary of the Invention

[0003] The present disclosure provides an electronic device that can improve the structural strength of a substrate or the adhesion ability between the substrate and other film layers.

[0004] According to an embodiment of the present disclosure, the electronic device includes a substrate, a through hole, a buffer layer, a first circuit structure, and an electronic component. The substrate includes a first side and a second side opposite to the first side. The through hole penetrates the substrate. The buffer layer is disposed on the first side of the substrate, the second side of the substrate, and the inner wall of the through hole. The first circuit structure is disposed on the first side. The electronic component is disposed on the first circuit structure. The buffer layer includes multiple layers. Brief Description of the Drawings

[0005] The drawings are included to provide a further understanding of the present disclosure, and the drawings are incorporated into the specification and form a part of the specification. The drawings illustrate embodiments of the present disclosure and are used in conjunction with the description to explain the principles of the present disclosure.

[0006] Figure 1A A cross-sectional schematic view of the electronic device according to the first embodiment of the present disclosure;

[0007] Figure 1B is Figure 1A a top view schematic view of the through hole in the electronic device of;

[0008] Figure 2 is Figure 1A an enlarged schematic view of the region R1 of;

[0009] Figure 3 A cross-sectional schematic view of the electronic device according to the second embodiment of the present disclosure;

[0010] Figure 4 is Figure 3 an enlarged schematic view of the region R2 of;

[0011] Figure 5 A cross-sectional schematic view of the electronic device according to the third embodiment of the present disclosure;

[0012] Figure 6 A cross-sectional schematic view of the electronic device according to the fourth embodiment of the present disclosure;

[0013] Figure 7 A cross-sectional schematic diagram of the electronic device according to the fifth embodiment of the present disclosure;

[0014] Figure 8A A cross-sectional schematic diagram of the electronic device according to the sixth embodiment of the present disclosure;

[0015] Figure 8B is Figure 8A An enlarged schematic diagram of the region R3 of.

[0016] Explanation of reference numerals in the drawings

[0017] 100, 100a, 100b, 100c, 100d, 100e: Electronic devices;

[0018] 110, 210: Substrates;

[0019] 111: Groove;

[0020] 111a: Bottom surface;

[0021] 111b, 121, 221: Inner walls;

[0022] 110a, 210a, HS1: First side;

[0023] 110b, 210b, HS2: Second side;

[0024] 120, 120b, 120e, 220: Through holes;

[0025] 130, 130a, 230: Buffer layers;

[0026] 131: First sub-layer;

[0027] 132: Second sub-layer;

[0028] 133: Third sub-layer;

[0029] 135: Adjustment layer;

[0030] 1351: Surface;

[0031] 1352, 140a, 160c, 170a, IL2a: Side surfaces;

[0032] 140, 140d: First circuit structures;

[0033] 141, 144, 147, 171, 174, 177, 191, 241, 271: Conductive layers; 142, 145, 148, 172, 175, 178, 192, 242, DL: Dielectric layers; 143, 146, 149, 173, 176, 179: Through holes;

[0034] 150, 180, 181, 182, 183, 280: Conductive members;

[0035] 160, 200, 300: Electronic components;

[0036] 160a: Active surface;

[0037] 160b: Back surface;

[0038] 161, 210, 310: Pads;

[0039] 170, 170d: Second circuit structure;

[0040] 190: Component integration layer;

[0041] 194: Component;

[0042] 200: Carrier board;

[0043] 250: Optical fiber;

[0044] 300a: Side surface;

[0045] 350: Adhesive layer;

[0046] 360: Underfill;

[0047] CM1, CM2, CM3: Conductive materials;

[0048] IL1: First insulating layer;

[0049] IL2: Second insulating layer;

[0050] IL3: Third insulating layer;

[0051] HS: Heat sink;

[0052] O1: Center of the circle;

[0053] P1, P2: Pitch;

[0054] PL: Passivation layer;

[0055] R1, R2, R3: Regions;

[0056] SR1, SR2: Solder mask layers;

[0057] T1, T2, T21, T22, T23, T3, T4, T5, T6, T7, T8: Thicknesses;

[0058] W1: First width;

[0059] W2: Second width;

[0060] X, Z: directions

[0061] θ1, θ2, θ3: included angles Detailed implementation manners

[0062] This disclosure can be understood by referring to the following detailed description and simultaneously combining the accompanying drawings. It should be noted that, for the convenience of the reader's understanding and for the simplicity of the drawings, only a part of the electronic device is shown in the multiple accompanying drawings of this disclosure, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of this disclosure.

[0063] In the following specification and claims, words such as "comprising" and "including" are open-ended terms and should therefore be interpreted as meaning "including but not limited to...".

[0064] It should be understood that when an element or film layer is said to be "on" or "connected to" another element or film layer, it can be directly on this other element or film layer or directly connected to this other element or layer, or there are intervening elements or film layers between the two (non-direct case). Conversely, when an element is said to be "directly" "on" or "directly connected to" another element or film layer, there are no intervening elements or film layers between the two.

[0065] Although terms such as "first", "second", "third",... can be used to describe various constituent elements, the constituent elements are not limited to these terms. This term is only used to distinguish a single constituent element in the specification from other constituent elements. The same term may not be used in the claims, and the first, second, third,... may be substituted according to the order of the element declarations in the claims. Therefore, in the following specification, the first constituent element may be the second constituent element in the claims.

[0066] In the text, terms such as "about", "approximately", "substantially", "essentially" generally mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meaning of "about", "approximately", "substantially", "essentially" can still be implied even without specifically stating "about", "approximately", "substantially", "essentially".

[0067] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect" and "interconnect", unless otherwise specifically defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures disposed between these two structures. And these terms related to joining and connection may also include cases where both structures are movable, or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means.

[0068] In some embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable means may be used to measure the area, width, thickness, or height of each component, or the distance or spacing between components. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structure image of the component to be measured, and measure the area, width, thickness, or height of each component, or the distance or spacing between components.

[0069] In the present disclosure, the definition of roughness judgment can be observed by SEM. On an uneven surface, the distance difference between the peaks and valleys of the surface undulation can be seen to be from 0.15 micrometers (μm) to 1 μm. The measurement of roughness judgment may include using SEM, a transmission electron microscope (TEM), etc., observing the surface undulation condition at an appropriate same magnification, and comparing the undulation condition by taking a sample of a unit length (such as 10 μm), which is the roughness range. Herein, "appropriate magnification" means that at least one surface can see at least 10 undulating peaks of roughness (Rz) or average roughness (Ra) in the field of view at this magnification.

[0070] The electronic device disclosed herein may include, but is not limited to, a display device, an antenna device, a sensing device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The electronic device may include, for example, a liquid crystal light emitting diode; the light emitting diode may include, for example, an organic light emitting diode (OLED), a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot, QD, which may be, for example, QLED, QDLED), fluorescence, phosphor, or other suitable materials, and the materials may be arranged and combined arbitrarily, but are not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, a shelf system, etc. The electronic device may include an electronic unit, where the electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. It should be noted that the electronic device disclosed herein may be various combinations of the above devices, but is not limited thereto. The electronic device disclosed herein may be applied to, for example, a power module, a semiconductor packaging device, a display device, a light emitting device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto. The electronic device may include a system on a chip (SoC), a system in a package (SiP), an antenna in package (AiP), or various combinations of the above devices, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. The following will illustrate the content of the present disclosure with an electronic device as an example, but the present disclosure is not limited thereto.

[0071] It should be noted that, without departing from the spirit of the present disclosure, the features in several different embodiments may be replaced, reorganized, and mixed to complete other embodiments in the following examples. As long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily mixed and used.

[0072] Now, reference will be made in detail to the exemplary embodiments of the present disclosure, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and the description to represent the same or similar parts.

[0073] Figure 1A It is a cross-sectional schematic diagram of the electronic device according to the first embodiment of the present disclosure. Figure 1B is Figure 1A a top view schematic diagram of a via hole in the electronic device of Figure 2 isFigure 1A An enlarged schematic view of the region R1.

[0074] Please refer to Figure 1A and Figure 2 For example, the electronic device 100 of the present embodiment may include a substrate 110, a via hole 120, a buffer layer 130, a first circuit structure 140, a conductive member 150, an electronic component 160, a second circuit structure 170, a conductive member 180, a first insulating layer IL1, and a second insulating layer IL2. In the present embodiment, the electronic device 100 can be applied to a power module, a semiconductor packaging device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto.

[0075] Specifically, the substrate 110 has a first side 110a and a second side 110b opposite to the first side 110a. In the present embodiment, the substrate 110 may include borosilicate glass, phosphate glass, but is not limited thereto. According to some embodiments, the coefficient of thermal expansion (CTE) of the substrate 110 may be greater than or equal to 1 ppm / °C and less than or equal to 10 ppm / °C. In some embodiments, the substrate 110 may also include a rigid substrate, a flexible substrate, or a combination of the foregoing. For example, the material of the substrate 110 may include quartz, sapphire, ceramic, wafer, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), silicon carbide (SiC), gallium nitride (GaN), other suitable substrate materials, or a combination of the foregoing, but is not limited thereto. In the present embodiment, the substrate 110 has a thickness T1, and the thickness T1 may be 0.03 millimeters (mm) to 10 millimeters, but is not limited thereto. Wherein, the thickness T1 may be the maximum thickness measured along the direction Z of the substrate 110.

[0076] In the present embodiment, the direction X and the direction Z are different directions. Wherein, the direction Z may be the normal direction of the substrate 110 or the normal direction of the electronic device 100, and the direction X is substantially perpendicular to the direction Z, but is not limited thereto.

[0077] The via hole 120 penetrates through the substrate 110. The via hole 120 is filled with a conductive material CM1 so that the via hole 120 can be electrically connected to the first circuit structure 140 and the second circuit structure 170. In the present embodiment, the conductive material CM1 may fill the via hole 120, but is not limited thereto. In some embodiments, the conductive material may not fill the via hole, as Figure 3 shown.

[0078] The through hole 120 has a first width W1 and a second width W2. Wherein, the first width W1 can be the maximum width measured along the direction X on one side of the through hole 120 adjacent to the first circuit structure 140 (or on the other side of the through hole 120 adjacent to the second circuit structure 170), and the second width W2 can be the minimum width measured along the direction X at the center of the through hole 120. In this embodiment, the first width W1 can be greater than the second width W2, such that the shape of the through hole 120 can be similar to an hourglass shape, but is not limited thereto. In some embodiments, the first width can also be substantially equal to the second width, as Figure 5 or Figure 6 shown. In this embodiment, the included angle θ1 between the inner wall 121 of the through hole 120 and the direction Z can be between 0 degrees and 20 degrees (i.e., 0 < θ1 ≤ 20), but is not limited thereto. According to some embodiments, the roughness of the inner wall 121 can be less than the roughness of the first side 110a of the substrate 110, and the roughness of the inner wall 121 can be less than the roughness of the second side 110b of the substrate 110, so as to avoid discontinuity or non-uniformity of the conductive material CM1 by controlling the roughness of the inner wall 121, but is not limited thereto.

[0079] According to some embodiments, in Figure 1B the top view of the through hole shown, the contour of the through hole 120 can be approximately circular, but is not limited thereto. Specifically, the roundness (%) of the through hole 120 can be greater than or equal to 85%, or greater than or equal to 90%, or greater than or equal to 95%, but is not limited thereto. Among them, the measurement method of the roundness of the through hole 120 can be, for example: first, at least ten diameters passing through the same center O1 of the through hole 120 are taken; then, a minimum diameter and a maximum diameter are found; then, the ratio of the minimum diameter to the maximum diameter is calculated to obtain the roundness (%) of the through hole 120, but the present disclosure does not limit the measurement method of the roundness.

[0080] The buffer layer 130 is disposed on at least a portion of the first side 110a of the substrate 110, the second side 110b of the substrate 110, and the inner wall 121 of the through hole 120. The buffer layer 130 is disposed between the first side 110a of the substrate 110 and the first circuit structure 140, between the second side 110b of the substrate 110 and the second circuit structure 170, and between the inner wall 121 of the through hole 120 and the conductive material CM1. The buffer layer 130 can contact at least a portion of the first side 110a of the substrate 110, at least a portion of the second side 110b of the substrate 110, and at least a portion of the inner wall 121 of the through hole 120. In this embodiment, the buffer layer 130 can improve the structural strength of the substrate 110 or can improve the adhesion ability between the substrate 110 and other film layers, thereby improving the reliability of the electronic device 100. For example, although the coefficient of thermal expansion (CTE) of the material of the substrate 110 (such as glass) is different from that of the material of the metal layer (such as the conductive material CM1, the conductive layer of the first circuit structure 140, or the conductive layer of the second circuit structure 170), by disposing the buffer layer 130 between the substrate 110 and the metal layer, the stress generated by the process of the electronic device 100 (such as: forming the conductive material CM1 in the through hole 120, forming the first circuit structure 140, or forming the second circuit structure 170, etc.) can be reduced, thereby avoiding the problems of substrate cracking or peeling at the interface between the substrate 110 and the metal layer.

[0081] In this embodiment, the buffer layer 130 has a thickness T2, and the thickness T2 can be from 0.01 micrometers (μm) to 10 micrometers, but is not limited thereto. Wherein, the thickness T2 can be the maximum thickness measured along the direction Z of the buffer layer 130 covering the first side 110a and the second side 110b of the substrate 110, or the thickness T2 can be the maximum thickness measured along the direction X of the buffer layer 130 covering the inner wall 121 of the through hole 120. In this embodiment, the ratio of the thickness T2 of the buffer layer 130 to the width W1 (or width W2) of the through hole 120 can be from 0.02 to 0.2 (i.e., 0.02 ≤ T2 / W1 ≤ 0.2, or 0.02 ≤ T2 / W2 ≤ 0.2), so that the design of the buffer layer 130 is sufficient to provide a certain protective force for the substrate 110 to reduce the problem of the substrate 110 breaking, but is not limited thereto.

[0082] The buffer layer 130 includes multiple layers. The buffer layer 130 may include a first sub-layer 131, a second sub-layer 132, and a third sub-layer 133. The first sub-layer 131 is disposed between the substrate 110 (or the inner wall 121 of the through hole 120) and the second sub-layer 132. The second sub-layer 132 is disposed between the first sub-layer 131 and the third sub-layer 133. The third sub-layer 133 is disposed between the second sub-layer 132 and a metal material (such as a conductive material CM1, the conductive layer 141 of the first circuit structure 140, or the conductive layer 171 of the second circuit structure 170). Although the buffer layer 130 of this embodiment may be a multi-layer stack of 3 sub-layers, the present disclosure does not limit the number of sub-layers of the multi-layer stack of the buffer layer 130, as long as the buffer layer 130 can include at least one organic material layer for contacting the substrate 110 to absorb stress and another inorganic material layer for increasing the overall Young's modulus of the buffer layer 130.

[0083] In this embodiment, the first sub-layer 131 and the third sub-layer 133 may include organic materials so that the buffer layer 130 can be used to absorb stress; for example, the materials of the first sub-layer 131 and the third sub-layer 133 may include polyimide, parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate, polyethylene terephthalate, polyethylene naphthalate (PEN), other ductile polymer materials for absorbing stress, or a combination of the foregoing, but not limited thereto. Among them, the organic material of the first sub-layer 131 may be the same as or different from the organic material of the third sub-layer 133. The second sub-layer 132 may include an inorganic material so that the strength of the buffer layer 130 can be increased and the probability of cracking can be reduced; for example, the material of the second sub-layer 132 may include silicon nitride (SiNx), silicon oxide (SiOx), other inorganic materials helpful for increasing the overall Young's modulus, or a combination of the foregoing, but not limited thereto.

[0084] In this embodiment, the toughness of the first sub-layer 131 and the third sub-layer 133 of the buffer layer 130 may be 0.1 kJ / m 2 to 100 kJ / m 2, so that the buffer layer 130 has buffer characteristics, but not limited thereto. Toughness is measured, for example, by the standard test method (ASTM D3039 / D3039M) of polymer matrix composites. Specifically, first, the component to be subjected to the tensile test is separated from the electronic device 100; then, two punctuation marks pre-marked on the component, and the distance between the two punctuation marks is called the gage length; then, the component is stretched by a tensile machine (such as a universal testing machine) so that the gage length gradually elongates during the tensile test. Among them, toughness can be obtained by calculating the area under the stress-strain curve (by integration).

[0085] In this embodiment, the dissipation factor (Df) of the first sub-layer 131 and the third sub-layer 133 of the buffer layer 130 at a frequency of 5 gigahertz (GHz) or a frequency greater than or equal to 5 GHz can be less than 0.005 to reduce the loss of electrical signals, but not limited thereto. For example, at a frequency of 5 GHz, the dissipation factor of the third sub-layer 133 in contact with the metal material can be less than the dissipation factor of the first sub-layer 131 to further reduce the loss of electrical signals, but not limited thereto. According to some embodiments, the difference between the dissipation factor of the first sub-layer 131 and the dissipation factor of the second sub-layer 132 can be between 0% and 70% of the dissipation factor of the second sub-layer 132. For example, the ratio of the absolute difference between the dissipation factor of the first sub-layer 131 and the dissipation factor of the second sub-layer 132 to the dissipation factor of the second sub-layer 132. Or, through the above design, the insertion loss of the electronic device 100 or the electronic component 160 can be improved, but not limited thereto.

[0086] In this embodiment, the Young's modulus of the first sub-layer 131 and the third sub-layer 133 of the buffer layer 130 can be greater than or equal to 20 GPa and less than or equal to 200 GPa, so that the buffer layer 130 has buffer characteristics, but not limited thereto.

[0087] In this embodiment, the first sub-layer 131 has a thickness T21, the second sub-layer 132 has a thickness T22, and the third sub-layer 133 has a thickness T23, but is not limited thereto. Among them, the thickness T21 of the first sub-layer 131 may be the same as or different from the thickness T23 of the third sub-layer 133. In this embodiment, the ratio of the thickness T21 of the first sub-layer 131 to the thickness T2 of the buffer layer 130 may be from 0.01 to 0.9 (i.e., 0.01 ≤ T21 / T2 ≤ 0.9), and the ratio of the thickness T23 of the third sub-layer 133 to the thickness T2 of the buffer layer 130 may be from 0.01 to 0.9 (i.e., 0.01 ≤ T23 / T2 ≤ 0.9), but is not limited thereto. In this embodiment, the ratio of the thickness T22 of the second sub-layer 132 to the thickness T2 of the buffer layer 130 may be from 0.01 to 0.1 (i.e., 0.01 ≤ T22 / T2 ≤ 0.1), but is not limited thereto. By designing the buffer layer 130 to have multiple layers, the buffering ability of the substrate when impacted by an external force can be improved, or the substrate strength can be further improved, but is not limited thereto.

[0088] The first circuit structure 140 is disposed on the first side 110a of the substrate 110, and the first circuit structure 140 may expose a part of the buffer layer 130 disposed on the first side 110a. The first circuit structure 140 may be electrically connected to the via 120, and the first circuit structure 140 may be electrically connected to the second circuit structure 170 through the via 120. The first circuit structure 140 includes a conductive layer 141, a dielectric layer 142, a via 143, a conductive layer 144, a dielectric layer 145, a via 146, and a conductive layer 147. The conductive layer 141 is disposed on the first side 110a of the substrate 110 and the buffer layer 130. The conductive layer 141 may contact and be electrically connected to the via 120. The dielectric layer 142, the conductive layer 144, the dielectric layer 145, and the conductive layer 147 are sequentially stacked on the conductive layer 141 in an alternating manner along the direction Z. The vias 143 and 146 are filled with a conductive material. The via 143 may penetrate through the dielectric layer 142 to electrically connect the conductive layer 144 and the conductive layer 141, and the via 146 may penetrate through the dielectric layer 145 to electrically connect the conductive layer 147 and the conductive layer 144. In this embodiment, the conductive layers and dielectric layers of the first circuit structure 140 may be single-layer or multi-layer stacked, wherein the material of the conductive layer may include copper, titanium, molybdenum, aluminum, nickel, tantalum, gallium, or other suitable conductive materials, and the material of the dielectric layer may include polyimide, photosensitive polyimide (PSPI), polybenzoxazole (PBO), epoxy resin, polymer, benzocyclobutene (BCB), ajinomoto build-up layer (ABF), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiNxOy), or other suitable dielectric materials, but is not limited thereto.

[0089] The conductive layer 141, the conductive layer 144, and the conductive layer 147 have a thickness T3, and the thickness T3 may be 0.5 mm to 12 mm, but is not limited thereto. Wherein, the thickness T3 may be the maximum thickness measured along the direction Z of the conductive layer 141, the conductive layer 144, or the conductive layer 147. According to some embodiments, the thicknesses of the conductive layer 141, the conductive layer 144, and the conductive layer 147 may be the same or different. For example, the thickness of the conductive layer 147 may be greater than the thickness of the conductive layer 141.

[0090] The dielectric layers 142 and 145 have a thickness T4, and the thickness T4 can be 5 mm to 15 mm, but is not limited thereto. Among them, the thickness T4 can be the maximum thickness measured along the direction Z of the dielectric layer 142 or the dielectric layer 145. In this embodiment, the thickness T4 of the dielectric layers 142 and 145 can be greater than the thickness T2 of the buffer layer 130 (i.e., T4>T2), but is not limited thereto. According to some embodiments, the thicknesses of the dielectric layers 142 and 145 can be the same or different. For example, the thickness of the dielectric layer 145 can be greater than the thickness of the dielectric layer 142.

[0091] In this embodiment, the first circuit structure 140 and the second circuit structure 170 can be redistribution layers (RDLs) and include at least one conductive layer and at least one dielectric layer ( Figure 1A Three conductive layers and two dielectric layers are schematically shown, but are not limited thereto). The redistribution layer can re-route the circuit and / or further increase the circuit fan-out area. The redistribution layer can be used to electrically connect different electronic components. The redistribution layer can expand the connection to a wider pitch or re-distribute the connection to another connection with a different pitch, and / or the redistribution layer can be used as a substrate for electrical interface wiring between one connection and another connection. For example, the pitch between two adjacent contact pads at one end of the redistribution structure in contact with the electronic component can be less than or equal to the pitch between two adjacent contact pads at the end of the redistribution structure away from the electronic component. Therefore, the redistribution structure can adjust the circuit fan-out condition or electrically connect a circuit structure / electronic component with a first pitch to a circuit structure / electronic component with a second pitch, but is not limited thereto. Among them, the steps of forming the redistribution layer can include providing a stack of at least one conductive layer and at least one dielectric layer, and the method of forming the redistribution layer can include processes such as photolithography, etching, surface treatment, laser, electroplating, chemical plating, deposition, atomic layer deposition, etc. Among them, the surface treatment can include roughening or activating the surface of the dielectric layer or the conductive layer to improve the adhesion ability of the dielectric layer or the conductive layer. For example, the adhesion force with the subsequent film layer can be improved by increasing the surface roughness.

[0092] The conductive member 150 is disposed on the conductive layer 147 of the first circuit structure 140. The conductive member 150 can contact and electrically connect the conductive layer 147 of the first circuit structure 140. The material of the conductive member 150 can include tin, copper, nickel, gold, silver, gallium, the above combinations, the above alloys, or other suitable materials, but is not limited thereto. For example, the conductive member 150 can be, for example, a solder ball, a tin ball, or a copper pillar (Cu pillar), but is not limited thereto. By designing that the thickness of the conductive layer 147 can be greater than the thickness of the conductive layer 141, it helps to improve the bonding strength after the bonding of the conductive layer 147 and the conductive member 150, but is not limited thereto.

[0093] The electronic component 160 is disposed on the first circuit structure 140 and on the conductive member 150. The electronic component 160 has an active surface 160a, a back surface 160b, and a side surface 160c. The active surface 160a faces the first circuit structure 140, the active surface 160a and the back surface 160b are opposite to each other, and the side surface 160c connects the active surface 160a and the back surface 160b. The electronic component 160 includes pads 161 disposed on the active surface 160a. The pads 161 of the electronic component 160 can be electrically connected to the conductive layer 147 of the first circuit structure 140 through the conductive member 150. The electronic component 160 can include passive components or active components, such as chips, known good die (KGD), semiconductor structures, silicon photonics chips, diodes, transistors, capacitors, resistors, inductors, etc., but is not limited thereto.

[0094] The second circuit structure 170 is disposed on the second side 110b of the substrate 110, and the second circuit structure 170 is disposed between the substrate 110 and the conductive member 180. The second circuit structure 170 can be electrically connected to the via 120. The second circuit structure 170 includes a conductive layer 171, a dielectric layer 172, a via 173, a conductive layer 174, a dielectric layer 175, a via 176, and a conductive layer 177. The conductive layer 171 is disposed under the second side 110b of the substrate 110. The conductive layer 171 can contact and be electrically connected to the via 120. The dielectric layer 172, the conductive layer 174, the dielectric layer 175, and the conductive layer 177 are stacked in an alternating manner along the direction Z under the conductive layer 171 in sequence. The vias 173 and 176 are filled with conductive materials. The via 173 can penetrate the dielectric layer 172 to electrically connect the conductive layer 174 and the conductive layer 171, and the via 176 can penetrate the dielectric layer 175 to electrically connect the conductive layer 177 and the conductive layer 174. In this embodiment, the conductive layers and dielectric layers of the second circuit structure 170 can be single-layer or multi-layer stacks, and the materials of the conductive layers and dielectric layers can be the same as or similar to the conductive layers and dielectric layers in the first circuit structure 140, so details are not described again.

[0095] The conductive layer 171, the conductive layer 174, and the conductive layer 177 have a thickness T5, and the thickness T5 can be 0.5 mm to 12 mm, but is not limited thereto. Wherein, the thickness T5 can be the maximum thickness measured along the direction Z of the conductive layer 171, the conductive layer 174, or the conductive layer 177. According to some embodiments, the thicknesses of the conductive layer 171, the conductive layer 174, and the conductive layer 177 can be the same as or different from the thicknesses of the conductive layer 141, the conductive layer 144, and the conductive layer 147.

[0096] The dielectric layers 172 and 175 have a thickness T6, and the thickness T6 can be 5 millimeters to 15 millimeters, but is not limited thereto. Among them, the thickness T6 can be the maximum thickness measured along the direction Z of the dielectric layer 172 or the dielectric layer 175. In this embodiment, the thickness T6 of the dielectric layer 172 or the dielectric layer 175 can be greater than the thickness T2 of the buffer layer 130 (i.e., T6>T2), but is not limited thereto. According to some embodiments, the thicknesses of the dielectric layers 172 and 175 can be the same as or different from the thicknesses of the dielectric layers 142 and 145. For example, the thickness of the dielectric layer 175 can be greater than the thickness of the dielectric layer 145.

[0097] The conductive member 180 is disposed on the second side 110b of the substrate 110. The conductive member 180 can be electrically connected to the electronic component 160 through the via hole 120 and the first circuit structure 140. The conductive member 180 can be a solder ball or a tin ball, but is not limited thereto. In addition, in this embodiment, the conductive member 180 can be disposed under the conductive layer 177 of the second circuit structure 170, and the conductive member 180 can be electrically connected to the via hole 120 through the second circuit structure 170, but is not limited thereto. In some embodiments, the second circuit structure can be not provided according to requirements or design needs, so that the conductive member can contact or be electrically connected to the via hole through other components.

[0098] In some embodiments, the spacing between two adjacent conductive members 180 can be the same or different. For example, the conductive member 180 can include a conductive member 181, a conductive member 182, and a conductive member 183. There is a spacing P1 between the conductive member 181 and the conductive member 182, and there is a spacing P2 between the conductive member 182 and the conductive member 183. Among them, the spacing P1 can be the minimum distance measured along the direction X between the midpoints of the conductive member 181 and the conductive member 182, and the spacing P2 can be the minimum distance measured along the direction X between the midpoints of the conductive member 182 and the conductive member 183. In some embodiments, the spacing P1 can be less than the spacing P2 (i.e., P1<P2), but is not limited thereto.

[0099] The first insulating layer IL1 is disposed between the electronic component 160 and the first circuit structure 140 for fixing the electronic component 160. The first insulating layer IL1 can surround the conductive member 150 and the conductive layer 147. In the cross-sectional view of the electronic device 100, the first insulating layer IL1 can at least contact the side surfaces of the conductive member 150 and the conductive layer 147. In this embodiment, the first insulating layer IL1 can include an organic material or an inorganic material. For example, the organic material can be an underfill or other suitable polymer material, and the inorganic material can include silicon oxide, silicon nitride, or other suitable inorganic materials, but is not limited thereto.

[0100] The second insulating layer IL2 is disposed on the first side 110a of the substrate 110, and the second insulating layer IL2 can surround the electronic component 160 and the first circuit structure 140 to protect the electronic component 160 or isolate moisture. In the cross-sectional view of the electronic device 100, the second insulating layer IL2 can at least contact the side surface 160c of the electronic component 160 and the side surface 140a of the first circuit structure 140. The second insulating layer IL2 can contact the buffer layer 130. In this embodiment, the second insulating layer IL2 can include an organic material or an inorganic material. For example, the organic material can be a molding layer, and the inorganic material can include silicon oxide, silicon nitride, or other suitable materials, but is not limited thereto.

[0101] In this embodiment, the manufacturing method of the electronic device 100 can include, but is not limited to, the following steps and step sequences: First, provide a substrate 110, where the substrate 110 has a first side 110a and a second side 110b opposite to the first side 110a; then, drill the substrate 110 by means of, for example, laser modification or etching to form a through hole 120 that can penetrate the substrate 110; then, form a buffer layer 130 so that the buffer layer 130 can cover and contact the first side 110a, the second side 110b, and the inner wall 121 of the through hole 120; then, form a conductive material CM1 in the through hole 120 by means of, for example, electroplating or chemical plating, so that the buffer layer 130 disposed in the through hole 120 is located between the conductive material CM1 and the substrate 110; then, use processes such as, for example, yellow light, etching, surface treatment, laser, and electroplating to form the first circuit structure 140 and the second circuit structure 170 on the first side 110a and the second side 110b respectively, so that the buffer layer 130 disposed on the first side 110a is located between the first circuit structure 140 and the substrate 110, and the buffer layer 130 disposed on the second side 110b is located between the second circuit structure 170 and the substrate 110; then, bond the electronic component 160 to the first circuit structure 140 through the conductive member 150; then, form a conductive member 180 under the second circuit structure 170 so that the conductive member 180 can be used to bond to a carrier board or a circuit board in subsequent processes, as Figure 6 shown; then, form a first insulating layer IL1 between the electronic component 160 and the first circuit structure 140; then, form a second insulating layer IL2 so that the second insulating layer IL2 can surround the electronic component 160 and the first circuit structure 140.

[0102] In this embodiment, the manufacturing method of the electronic device 100 can be applied, for example, in a wafer-level package (WLP) process or a panel-level package (PLP) process, and can be a redistribution layer first (RDL first) manufacturing method of chip first or chip last.

[0103] Other embodiments will be listed below for illustration. It must be noted here that the following embodiments follow the component numbers and some content of the previous embodiments, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the previous embodiments, and the following embodiments will not be repeated.

[0104] Figure 3 It is a cross-sectional schematic diagram of the electronic device according to the second embodiment of the present disclosure. Figure 4 is Figure 3 an enlarged schematic diagram of the region R2. Please refer to Figures 3 to 4 and Figures 1A to 2 simultaneously. The electronic device 100a of this embodiment is similar to Figures 1A to 2 the electronic device 100, but the difference between the two is that in the electronic device 100a of this embodiment, the thickness T2 of the buffer layer 130 outside the through hole 120 is different from the thickness T7 of the buffer layer 130a inside the through hole 120, and the conductive material CM1 does not fill the through hole 120.

[0105] Specifically, please refer to Figure 3 and Figure 4 simultaneously. The thickness T2 of the buffer layer 130 can be the maximum thickness measured along the direction Z of the buffer layer 130 covering the first side 110a and the second side 110b of the substrate 110. The thickness T7 of the buffer layer 130a can be the thickness measured along the direction X of the buffer layer 130a covering the inner wall 121 of the through hole 120. In this embodiment, the thickness T2 of the buffer layer 130 can be greater than the thickness T7 of the buffer layer 130a, but it is not limited thereto. In addition, in this embodiment, the thickness T7 of the buffer layer 130a can gradually decrease from the side of the through hole 120 adjacent to the first circuit structure 140 (or the other side of the through hole 120 adjacent to the second circuit structure 170) to the center of the through hole 120, so that the thickness T7 of the buffer layer 130a presents a gradient state, but it is not limited thereto.

[0106] The conductive material CM1 is disposed on the inner wall 121 of the through hole 120, such that the buffer layer 130a is located between the inner wall 121 of the through hole 120 and the conductive material CM1. The conductive material CM1 has a thickness T8, and the thickness T8 can be the thickness of the conductive material CM1 measured along the direction X. In this embodiment, the thickness T3 of the conductive layer 141 (or the thickness T5 of the conductive layer 171) can be greater than the thickness T8 of the conductive material CM1, but is not limited thereto. In addition, in this embodiment, the thickness T8 of the conductive material CM1 can gradually decrease from the side of the through hole 120 adjacent to the first circuit structure 140 (or the other side of the through hole 120 adjacent to the second circuit structure 170) towards the center of the through hole 120, such that the thickness T8 of the conductive material CM1 presents a gradient state, but is not limited thereto.

[0107] In addition, a part of the conductive layer 177 can have a groove design. For example, the outer conductive layer 177 can have a groove design. Such that a part of the conductive member 180 can be filled into the groove of the conductive layer 177, improving the bonding ability between the conductive member 180 and the conductive layer 177. Since the electronic device may be further bonded to other external devices through the conductive member 180, the bonding force between the electronic device and the external components can be enhanced by the groove design of the conductive layer 177, but is not limited thereto.

[0108] In this embodiment, the electronic device 100a further includes a passivation layer PL. The passivation layer PL is disposed on the side edges of the dielectric layer 172, the side edges of the dielectric layer 175, and the surface of the dielectric layer 175 facing the conductive member 180. The passivation layer PL may or may not contact the conductive layer 177. The passivation layer PL may include an organic material or an inorganic material. The passivation layer PL may include a single-layer structure or a multi-layer structure, wherein the passivation layer PL may have the same structure as the buffer layer 130. The passivation layer PL can be used to block moisture, reducing the influence of moisture on the second circuit structure 170, but is not limited thereto.

[0109] In this embodiment, the electronic device 100a further includes a dielectric layer DL. The dielectric layer DL is disposed in the through hole 120 to fill the through hole 120, and the conductive material CM1 can be located between the buffer layer 130a and the dielectric layer DL.

[0110] Figure 5 A cross-sectional schematic diagram of the electronic device according to the third embodiment of the present disclosure. Please refer to Figure 5 and Figures 1A to 2 , the electronic device 100b of this embodiment is similar to Figures 1A to 2 the electronic device 100, except that the electronic device 100b of this embodiment further includes an element integration layer 190, and the shape of the through hole 120b can be columnar.

[0111] Specifically, please refer to Figure 5, the component integration layer 190 is disposed on the first side 110a of the substrate 110, and the component integration layer 190 is disposed between the first circuit structure 140 and the substrate 110. The component integration layer 190 includes a conductive layer 191, a dielectric layer 192, and components 194. Among them, the conductive layer 191 is disposed on the buffer layer 130, the dielectric layer 192 is disposed on the conductive layer 191, and the components 194 are disposed within the dielectric layer 192. In this embodiment, the components 194 can overlap the electronic components 160 in the Z direction, thereby shortening the signal transmission path between the components 194 and the electronic components 160, and thus reducing signal loss or achieving an energy-saving effect.

[0112] In this embodiment, the conductive layer 191 and the dielectric layer 192 of the component integration layer 190 can be single-layer or multi-layer stacks. The material of the conductive layer can include copper, titanium, molybdenum, aluminum, or other suitable conductive materials, and the material of the dielectric layer can include polyimide, photosensitive polyimide, polybenzoxazole, epoxy resin, polymer, Ajinomoto build-up film, silicon oxide, silicon nitride, or other suitable dielectric materials, but not limited thereto. Among them, the material of the dielectric layer 192 of the component integration layer 190 can be the same as or different from the material of the dielectric layer of the first circuit structure 140.

[0113] In this embodiment, the component integration layer 190 includes at least one component 194, for example, it can include active components, passive components, or other suitable components. In some embodiments, the components 194 can at least partially overlap the electronic components 160, thereby shortening the signal transmission path, but not limited thereto. In some embodiments, the active component can be a transistor or a thin film transistor. In some embodiments, the passive component can be a capacitor, a resistor, or an inductor.

[0114] In this embodiment, the first width W1 of the through hole 120b can be substantially equal to the second width W2, and the shape of the through hole 120b can be columnar, but not limited thereto.

[0115] Figure 6 is a cross-sectional schematic diagram of the electronic device according to the fourth embodiment of the present disclosure. Please refer to Figure 6 and Figure 5 , the electronic device 100c of this embodiment is similar to Figure 5 the electronic device 100b, but the difference between the two is that: the electronic device 100c of this embodiment further includes a heat sink HS, a carrier plate 200, a conductive member 280, and a third insulating layer IL3.

[0116] Specifically, please refer to Figure 6, the second insulating layer IL2 exposes the back surface 160b of the electronic component 160. A heat sink HS is disposed on the electronic component 160 and the second insulating layer IL2. The heat sink HS has a first side HS1 and a second side HS2 opposite to each other. The first side HS1 of the heat sink HS can contact the back surface 160b of the electronic component 160 for conducting the heat generated by the electronic component 160 to the outside. The second side HS2 of the heat sink HS may have fins and grooves to enhance the heat dissipation effect.

[0117] The carrier plate 200 is disposed on the second side 110b of the substrate 110. The carrier plate 200 can be bonded to the substrate 110 through the conductive member 180 so that the conductive member 180 is disposed between the second side 110b of the substrate 110 and the carrier plate 200. The carrier plate 200 may include a substrate 210, vias 220, a buffer layer 230, a conductive material CM2, a conductive layer 241, a dielectric layer 242, and a conductive layer 271.

[0118] Specifically, the substrate 210 has a first side 210a and a second side 210b opposite to each other. The first side 210a faces the substrate 110, and the second side 210b faces away from the substrate 110. The vias 220 penetrate through the substrate 210. The buffer layer 230 is disposed on the first side 210a of the substrate 210, the second side 210b of the substrate 210, and the inner wall 221 of the vias 220. The conductive material CM2 is filled in the vias 220. The conductive layer 241 is disposed on the first side 210a of the substrate 210. The conductive layer 241 is located between the conductive member 180 and the vias 220, and the conductive layer 241 can be electrically connected to the conductive member 180 and the vias 220. The dielectric layer 242 is disposed on the conductive layer 241, and the dielectric layer 242 can surround the conductive layer 241 and the conductive member 180. The conductive layer 271 and the conductive member 280 are disposed on the second side 210b of the substrate 210. The conductive layer 271 is located between the vias 220 and the conductive member 280, and the conductive layer 271 can be electrically connected to the vias 220 and the conductive member 280.

[0119] In this embodiment, the conductive member 180 can be electrically connected to the conductive member 280 through the conductive layer 241, the vias 220, and the conductive layer 271. The electronic component 160 can be electrically connected to the carrier plate 200 through the conductive member 150, the first circuit structure 140, the vias 120, the second circuit structure 170, and the conductive member 180.

[0120] The third insulating layer IL3 is disposed on the first side 210a of the substrate 210, and the third insulating layer IL3 can surround the second insulating layer IL2, the second circuit structure 170, and the dielectric layer 242 for protecting the electronic component 160 or isolating moisture. In the cross-sectional view of the electronic device 100c, the third insulating layer IL3 can at least contact the side surface IL2a of the second insulating layer IL2, the side surface 170a of the second circuit structure 170, and the side surface of the dielectric layer 242. The third insulating layer IL3 can also contact a part of the buffer layer 230 of the carrier 200. In this embodiment, the third insulating layer IL3 can include an organic material or an inorganic material. For example, the organic material can be a molding compound layer, and the inorganic material can include silicon oxide, silicon nitride, or other suitable materials, but is not limited thereto.

[0121] Figure 7 FIG. is a schematic cross-sectional view of an electronic device according to the fifth embodiment of the present disclosure. Please refer to Figure 7 and Figures 1A to 2 , the electronic device 100d of this embodiment is similar to Figures 1A to 2 the electronic device 100, except that the electronic device 100d of this embodiment further includes an electronic component 200, an optical fiber 250, an electronic component 300, a solder resist SR1, and a solder resist SR2, and the substrate 110 includes a groove 111 recessed in the first side 110a.

[0122] Specifically, please refer to Figure 7 , the first circuit structure 140d further includes a dielectric layer 148 and a via 149. The dielectric layer 148 is disposed between the dielectric layer 142 and the first side 110a of the substrate 110. The via 149 is filled with a conductive material, and the via 149 can penetrate through the dielectric layer 148 to electrically connect the conductive layer 141 and the via 120.

[0123] The second circuit structure 170d further includes a dielectric layer 178 and a via 179. The dielectric layer 178 is disposed between the second side 110b of the substrate 110 and the dielectric layer 172. The via 179 is filled with a conductive material, and the via 179 can penetrate through the dielectric layer 178 to electrically connect the via 120 and the conductive layer 171.

[0124] The solder resist SR1 can cover and surround the first circuit structure 140d to protect the first circuit structure 140d by blocking external water and oxygen or preventing the influence on the first circuit structure 140d when manufacturing the conductive member 150. The solder resist SR2 can cover and surround the second circuit structure 170d to protect the second circuit structure 170d by blocking external water and oxygen or preventing the influence on the second circuit structure 170d when manufacturing the conductive member 180.

[0125] The electronic component 200 is disposed on the first circuit structure 140d and on the conductive member 150, and the electronic component 200 is disposed adjacent to the electronic component 160. The pad 210 of the electronic component 200 can be electrically connected to the conductive layer 147 of the first circuit structure 140d through the conductive member 150. In this embodiment, the electronic component 200 can be a silicon photonics chip (photonic IC, PIC), and the electronic component 200 can be electrically connected to the optical fiber 250, but is not limited thereto.

[0126] The groove 111 can be correspondingly overlapped with the electronic component 200 and the electronic component 160 in the Z direction. The groove 111 has a bottom surface 111a and an inner wall 111b. The buffer layer 130 can cover a part of the inner wall 111b of the groove 111. The adhesive layer 350 is disposed on the bottom surface 111a of the groove 111. The underfill 360 is filled into the groove 111. According to some embodiments, the included angle θ2 between the inner wall 111b of the groove 111 and the Z direction can be between 20 degrees and 60 degrees (i.e., 20 ≤ θ2 ≤ 60), so that the electronic component 300 can be placed more easily, but is not limited thereto.

[0127] The electronic component 300 is embedded and fixed in the groove 111 through the adhesive layer 350. The electronic component 300 can be correspondingly overlapped with the electronic component 200 and the electronic component 160 in the Z direction. The pad 310 of the electronic component 300 can be electrically connected to the through hole 149 of the first circuit structure 140d. In this embodiment, the electronic component 300 can be a connector for processing signals between the electronic component 160 and the electronic component 200, but is not limited thereto. According to some embodiments, the adhesive layer 350 can also contact the side surface 300a of the electronic component 300 to more firmly fix the electronic component 300, but is not limited thereto.

[0128] Figure 8A It is a cross-sectional schematic diagram of the electronic device according to the sixth embodiment of the present disclosure. Figure 8B is Figure 8A an enlarged schematic diagram of the region R3 of. Please refer to Figures 8A to 8B and Figures 1A to 2 simultaneously. The electronic device 100e of this embodiment is similar to Figures 1A to 2 the electronic device 100 of, except that the electronic device 100e of this embodiment further includes an adjustment layer 135 and a through hole 120e.

[0129] Specifically, please refer to Figure 8A and Figure 8B . The adjustment layer 135 is disposed on the buffer layer 130 in the through hole 120, so that the buffer layer 130 in the through hole 120 is located between the substrate 110 and the adjustment layer 135. The adjustment layer 135 can cover and contact the buffer layer 130.

[0130] The through hole 120e penetrates through the substrate 110 and the adjustment layer 135. The through hole 120e is filled with a conductive material CM3, such that the adjustment layer 135 is located between the buffer layer 130 and the conductive material CM3 within the through hole 120, and the through hole 120e can electrically connect the first circuit structure 140 and the second circuit structure 170.

[0131] In this embodiment, the adjustment layer 135 can be used to adjust the shape of the conductive material CM3 and the through hole 120e, such that the through hole 120e filled with the conductive material CM3 can be columnar or elongated columnar, and the shape of the through hole 120e can approximate a rectangle, thereby reducing the impact on signal transmission.

[0132] In this embodiment, the included angle θ1 between the inner wall 121 of the through hole 120 and the direction Z can be greater than or equal to 3 degrees and less than or equal to 20 degrees (i.e., 3 ≤ θ1 ≤ 20), but is not limited thereto.

[0133] The adjustment layer 135 has an adjacent surface 1351 and a side surface 1352. The surface 1351 faces the conductive layer 141 of the first circuit structure 140, and the side surface 1352 faces the conductive material CM3. In this embodiment, the included angle between the surface 1351 and the side surface 1352 can be approximately a right angle, and the included angle θ3 between the side surface 1352 and the direction Z can be greater than or equal to 0 degrees and less than or equal to 3 degrees (i.e., 0 ≤ θ3 ≤ 3), but is not limited thereto.

[0134] In this embodiment, the manufacturing method of the adjustment layer 135 can include but is not limited to the following steps and step sequence: First, after forming the through hole 120 and the buffer layer 130, an adjustment material is filled into the through hole 120; then, part of the adjustment material is removed by a method such as a laser to form the adjustment layer 135 and the through hole 120e.

[0135] In summary, in the electronic device of the disclosed embodiment, by disposing the buffer layer on the first side of the substrate, the second side of the substrate, and the inner wall of the through hole, the structural strength of the substrate can be improved or the adhesion ability between the substrate and other film layers can be improved, thereby improving the reliability of the electronic device. For example, the setting of the buffer layer can reduce the problem of substrate cracking or peeling at the interface between the substrate and the metal layer caused by the stress generated by the processes of the electronic device (such as: forming a conductive material in the through hole, forming the first circuit structure, or forming the second circuit structure, etc.).

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that, Comprising: A substrate, including a first side and a second side opposite to the first side; A through-hole, penetrating through the substrate; A buffer layer, disposed on the first side of the substrate, the second side of the substrate, and the inner wall of the through-hole; A first circuit structure, disposed on the first side; And An electronic component, disposed on the first circuit structure, Wherein, the buffer layer includes multiple layers.

2. The electronic device according to claim 1, characterized in that, The buffer layer includes: A first sub-layer, including an organic material; and A second sub-layer, including an inorganic material, Wherein the first sub-layer is disposed between the substrate and the second sub-layer.

3. The electronic device according to claim 2, wherein The buffer layer further includes: A third sub-layer, including an organic material, Wherein the second sub-layer is disposed between the first sub-layer and the third sub-layer.

4. The electronic device according to claim 3, wherein The toughness of the first sub-layer and the third sub-layer is from 0.1 kJ / m2 to 100 kJ / m2.

5. The electronic device according to claim 3, wherein The loss factor of the first sub-layer and the third sub-layer is less than 0.

005.

6. The electronic device according to claim 3, wherein, The Young's modulus of the first sub-layer and the third sub-layer is greater than or equal to 20 GPa and less than or equal to 200 GPa.

7. The electronic device according to claim 1, wherein The substrate includes glass.

8. The electronic device according to claim 1, wherein Further comprising: A first insulating layer, disposed between the electronic component and the first circuit structure.

9. The electronic device according to claim 1, wherein Further comprising: A second insulating layer, surrounding the electronic component and the first circuit structure.

10. The electronic device according to claim 1, characterized in that, Further comprising: An element integration layer, disposed between the first circuit structure and the substrate, Wherein the element integration layer includes elements, and the elements overlap with the electronic component.

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