A substrate chip packaging structure and preparation method thereof

Abstract

To overcome the problems of poor heat dissipation and functional impairments caused by inter-chip heat conduction in existing chip packaging structures, the present invention provides a substrate-chip packaging structure comprising a substrate, a control chip, a memory chip, a thermally conductive layer, an aerogel layer, an interposer, and an encapsulation layer. A groove is defined on one surface of the substrate, into which the control chip is embedded. The thermally conductive layer covers the surfaces of the control chip and the substrate. The aerogel layer is located on a side of the thermally conductive layer facing away from the control chip. The interposer is located on a side of the aerogel layer facing away from the thermally conductive layer. The memory chip is located on a side of the interposer facing away from the aerogel layer. The encapsulation layer is disposed on the substrate, with the thermally conductive layer partially located within the encapsulation layer and partially extending and exposed from the encapsulation layer. The present invention also discloses a method for preparing the aforementioned substrate-chip packaging structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a substrate chip packaging structure and a preparation method thereof. Background Art

[0002] In modern electronic devices, as functional integration continues to increase, chip performance requirements are becoming increasingly stringent, and the space occupied by chips on circuit boards is becoming increasingly prominent. Traditional chips are typically mounted on circuit boards using a planar layout. Due to the limited functionality of a single chip, a large number of chips must be arranged in parallel to achieve complex functions, resulting in a significant increase in circuit board area. This makes it difficult to meet the design requirements for miniaturization and lightweighting in applications such as portable electronic devices and high-density servers.

[0003] To address the chip space issue, two main technical solutions have been developed: substrate-embedded chips and three-dimensional stacked chip packaging. While substrate-embedded chips embed the chip within the substrate, which reduces the board's footprint to a certain extent, the chip's encapsulation within the substrate makes it difficult to effectively dissipate heat, which can easily cause localized overheating of the chip, leading to performance degradation or even damage.

[0004] The three-dimensional stacking architecture of chip packaging significantly increases integration within the same projected area by vertically stacking multiple chips. However, this architecture also faces severe heat dissipation challenges. In a three-dimensional stacking architecture, the control chip, as the core unit of system operation, must process large amounts of data and instructions, generating much more heat than other chips. Furthermore, due to design considerations such as wiring and signal transmission, the control chip is typically placed at the bottom of the stack. During the heat dissipation process, the heat dissipated by the control chip must pass through multiple layers of stacked chips and packaging materials before being transferred to an external heat sink, resulting in extremely high thermal resistance. This high heat not only limits the performance of the control chip itself but also seriously affects the normal operation of adjacent chips. This is especially true for temperature-sensitive memory chips. The heat dissipated by the control chip can significantly increase the operating temperature of the memory chip, resulting in reduced stability of stored data, decreased read and write speeds, and even the risk of data loss. This significantly restricts the performance and application expansion of chips in a three-dimensional stacking architecture. Summary of the Invention

[0005] In order to solve the problems of poor heat dissipation in existing chip packaging structures and functional impact caused by heat conduction between chips, the present invention provides a substrate chip packaging structure and a preparation method thereof.

[0006] The technical solutions adopted by the present invention to solve the above technical problems are as follows:

[0007] On the one hand, the present invention provides a substrate-chip packaging structure, comprising a substrate, a control chip, a memory chip, a thermally conductive layer, an aerogel layer, an interposer and an encapsulation adhesive layer, wherein a groove is provided on one surface of the substrate, the control chip is embedded in the groove, the thermally conductive layer covers the surface of the control chip and the substrate, a cavity is formed inside the thermally conductive layer, a capillary structure is formed on the inner wall of the cavity, a phase change medium is filled in the cavity, the aerogel layer is located on a side of the thermally conductive layer away from the control chip, the interposer is located on a side of the aerogel layer away from the thermally conductive layer, the memory chip is located on a side of the interposer away from the aerogel layer, the encapsulation adhesive layer is arranged on the substrate, the control chip, the memory chip, the aerogel layer and the interposer are all located inside the encapsulation adhesive layer, the thermally conductive layer is partially located inside the encapsulation adhesive layer, and the thermally conductive layer partially extends and is exposed from the encapsulation adhesive layer.

[0008] Optionally, there are multiple memory chips, and the multiple memory chips are stacked in a stepped manner to form a stepped surface on one side of the multiple memory chips. The memory chip is provided with at least one first solder pad at the position of the stepped surface, and the first solder pads of two adjacent memory chips are connected to each other by providing a first lead. At least one second solder pad is provided on the surface of the intermediary piece facing away from the aerogel layer, and at least one second solder pad is connected to at least one first solder pad by providing a second lead. A third solder pad is provided on the other side surface of the intermediary piece corresponding to the second solder pad, and the second solder pad is electrically connected to the third solder pad. A connecting solder ball is provided between the third solder pad and the substrate to electrically connect them to each other.

[0009] Optionally, the substrate includes a hollow substrate and a multi-layer bottom substrate, the multi-layer bottom substrates are stacked, the hollow substrate is stacked on the bottom substrate located at the top, and the hollow substrate is hollowed out corresponding to the position of the control chip to form the groove, the surface of the bottom substrate is provided with a first circuit pattern, the bottom surface of the hollow substrate is provided with a second circuit pattern, the top surface of the hollow substrate is provided with a fourth solder pad at a position not covering the thermal conductive layer, the connecting solder balls are respectively connected to the third solder pad and the fourth solder pad, the bottom surface of the control chip is provided with a welding terminal, a plurality of first metallized through-holes are provided in the bottom substrate, the first circuit pattern, the second circuit pattern and the welding terminal are electrically connected by the first metallized through-holes, a plurality of second metallized through-holes are provided inside the hollow substrate, and the second metallized through-holes are used to electrically connect the second circuit pattern and the fourth solder pad.

[0010] Optionally, the aerogel layer includes silica aerogel and inorganic particles and a glass fiber layer located in the silica aerogel.

[0011] Optionally, the heat conductive layer is a copper layer, the inner wall of the cavity is formed with a grid-like groove, the capillary structure is located on the inner wall of the cavity and inside the grid-like groove, the capillary structure is a clustered nickel layer, and the boiling point of the phase change working fluid is 40~90°C.

[0012] Optionally, the heat conductive layer is exposed on the surface of the encapsulation adhesive layer, and the surface of the encapsulation adhesive layer is covered with a graphene coating.

[0013] In another aspect, the present invention provides a method for preparing the substrate chip packaging structure as described above, comprising the following operations:

[0014] Embed the control chip in the groove on one side of the substrate;

[0015] Covering the surfaces of the control chip and the substrate with a heat-conducting layer;

[0016] placing an aerogel layer on a side of the heat-conducting layer facing away from the control chip;

[0017] Welding the interposer to the surface of the substrate and clamping and fixing the thermal conductive layer and the aerogel layer;

[0018] placing a memory chip on the top surface of the interposer;

[0019] The control chip, the memory chip, the aerogel layer, the heat-conducting layer and the interposer are encapsulated with encapsulating glue to form an encapsulating glue layer, and the heat-conducting layer is partially exposed from the encapsulating glue layer.

[0020] Optionally, the method for preparing the thermal conductive layer includes the following operations:

[0021] A copper layer is used as a substrate, and grid-shaped grooves are etched on one surface of the copper layer by laser etching;

[0022] The other side of the copper layer is protected by a mask, and the copper layer is placed in a nitric acid solution for activation treatment, and then washed with water;

[0023] The activated copper layer is placed as a cathode in an electroplating solution for electroplating, forming a clustered nickel layer on one surface of the copper layer and in the grid-like grooves. The electroplating solution includes the following components:

[0024] Nickel salt 2-5g / L, ammonium salt 40-80g / L;

[0025] The current density of the electroplating process is 12 to 20 A / dm 2 ;

[0026] After the electroplating treatment, the clustered nickel layer is subjected to plasma hydroxylation treatment;

[0027] The mask of the copper layer is removed, and the copper layer is folded with the clustered nickel layer as the inner side. The edge of the copper layer is initially welded by laser welding and the injection port is retained. The injection port is vacuumed and the phase change working fluid is injected. The injection port is welded for the second time to form a closed cavity filled with the phase change working fluid inside the copper layer.

[0028] Optionally, the method for preparing the aerogel layer includes the following operations:

[0029] Mix ethyl orthosilicate, ethanol, and water in a molar ratio of 1:(7-20):(3-8), add acid to adjust the pH to 2-6, and stir at 40-80°C for 200-500 minutes to obtain silica sol;

[0030] Ammonia water and inorganic particles are added to adjust the pH value of the silica sol to 6.5-8, and the silica sol is mixed with the glass fiber layer to obtain a gel layer;

[0031] The gel layer is placed in a hydrophobic modification liquid for hydrophobic modification, wherein the hydrophobic modification liquid comprises ethanol and hexamethyldisilazane, wherein the mass percentage of hexamethyldisilazane is 1% to 10%;

[0032] The hydrophobically modified gel layer is dried to obtain an aerogel layer.

[0033] Optionally, after forming the encapsulation adhesive layer, the following operations are further included:

[0034] Graphene coating is coated on the surface of the heat-conducting layer exposed from the packaging adhesive layer and the surface of the packaging adhesive layer, and is cured to obtain a graphene coating.

[0035] According to the substrate-chip packaging structure provided by the present invention, on the one hand, the control chip and the memory chip are integrated and packaged on the same substrate; on the other hand, the control chip is embedded in the substrate. This structure fully utilizes the vertical space of the substrate, breaking through the physical limits of traditional planar packaging. The signal transmission distance is shortened by more than 90% compared with PCB wiring, greatly reducing latency and signal loss, and achieving multi-dimensional optimization in dimensions such as integration, performance, power consumption, and cost. In order to solve the problem of poor heat dissipation caused by high integration, a heat-conducting layer with a cavity is provided on the top of the control chip with a larger heat generation. When the control chip generates heat during operation, the phase-change working fluid in the heat-conducting layer absorbs heat, vaporizes and diffuses. At the position exposed to the packaging glue layer, the phase-change working fluid in the heat-conducting layer condenses, liquefies and releases heat. At the same time, it is absorbed and conducted to the position of the control chip through the capillary action of the capillary structure in the cavity, forming an efficient heat dissipation cycle and effectively reducing the temperature of the control chip. At the same time, in order to avoid the problem that the heat conduction of the control chip affects the function of the memory chip, an aerogel layer is provided between the heat-conducting layer and the intermediate sheet. The aerogel layer has a low thermal conductivity and can effectively block the upward conduction of heat from affecting the function of the memory chip. Furthermore, through the cooperation of the heat-conducting layer and the aerogel layer, the directional heat dissipation efficiency of the substrate chip packaging structure can be improved under the premise of reducing the influence between chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a structural schematic diagram of the substrate chip packaging structure provided by the present invention;

[0037] Figure 2 is a top view of multiple memory chips provided by the present invention;

[0038] Figure 3 It is a schematic diagram of the inner wall structure of the copper layer provided by the present invention.

[0039] The reference numerals in the drawings of the specification are as follows:

[0040] 1. Substrate; 11. Hollow substrate; 111. Second circuit pattern; 112. Second metallized through hole; 113. Fourth solder pad; 12. Bottom substrate; 13. Groove; 14. Insulation layer; 121. First circuit pattern; 122. First metallized through hole; 123. Solder ball; 2. Thermal conductive layer; 21. Cavity; 22. Grid-like groove; 3. Aerogel layer; 4. Interposer; 5. Memory chip; 51. First solder pad; 52. First lead; 53. Second lead; 6. Encapsulation adhesive layer; 7. Graphene coating; 8. Connecting solder ball; 9. Control chip; 91. Welding terminal. DETAILED DESCRIPTION

[0041] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] See also Figure 1 As shown, an embodiment of the present invention provides a substrate chip packaging structure, including a substrate 1, a control chip 9, a memory chip 5, a heat-conducting layer 2, an aerogel layer 3, an interposer 4 and an encapsulation adhesive layer 6. A groove 13 is provided on one side surface of the substrate 1, and the control chip 9 is embedded in the groove 13. The heat-conducting layer 2 covers the surface of the control chip 9 and the substrate 1. A cavity 21 is formed inside the heat-conducting layer 2, and the inner wall of the cavity 21 is formed with a capillary structure. The cavity 21 is filled with a phase change medium. The aerogel layer 3 The intermediate sheet 4 is located on the side of the thermal conductive layer 2 facing away from the control chip 9, the intermediate sheet 4 is located on the side of the aerogel layer 3 facing away from the thermal conductive layer 2, the memory chip 5 is located on the side of the intermediate sheet 4 facing away from the aerogel layer 3, the encapsulation layer 6 is arranged on the substrate 1, the control chip 9, the memory chip 5, the aerogel layer 3 and the intermediate sheet 4 are all located inside the encapsulation layer 6, the thermal conductive layer 2 is partially located inside the encapsulation layer 6, and the thermal conductive layer 2 partially extends and is exposed from the encapsulation layer 6.

[0043] In the substrate-chip packaging structure, on the one hand, the control chip 9 and the memory chip 5 are integrated and packaged on the same substrate 1; on the other hand, the control chip 9 is embedded in the substrate 1. This structure fully utilizes the vertical space of the substrate 1, breaking through the physical limits of traditional planar packaging. The signal transmission distance is shortened by more than 90% compared with PCB wiring, greatly reducing latency and signal loss, and achieving multi-dimensional optimization in terms of integration, performance, power consumption, cost, and other dimensions. In order to solve the problem of poor heat dissipation caused by high integration, a heat-conducting layer 2 with a cavity 21 is provided on the top of the control chip 9 with a large heat generation. When the control chip 9 is working and generating heat, the phase-change working medium in the heat-conducting layer 2 absorbs heat, vaporizes and diffuses. At the position exposed to the packaging glue layer 6, the phase-change working medium in the heat-conducting layer 2 condenses, liquefies and releases heat. At the same time, it is absorbed and conducted to the position of the control chip 9 through the capillary action of the capillary structure in the cavity 21, forming an efficient heat dissipation cycle, effectively reducing the temperature of the control chip 9. At the same time, in order to avoid the problem that the heat conduction of the control chip 9 affects the function of the memory chip 5, an aerogel layer 3 is provided between the heat-conducting layer 2 and the intermediate sheet 4. The aerogel layer 3 has a low thermal conductivity and can effectively block the upward conduction of heat from affecting the function of the memory chip 5. Furthermore, through the cooperation of the heat-conducting layer 2 and the aerogel layer 3, the directional heat dissipation efficiency of the substrate chip packaging structure can be improved while reducing the impact between chips.

[0044] In some embodiments, the portion of the heat-conducting layer 2 exposed from the packaging adhesive layer 6 can be connected to other external heat dissipation devices to improve heat dissipation efficiency.

[0045] In some embodiments, there are multiple memory chips 5, and the multiple memory chips 5 are stacked in a stepped manner to form a stepped surface on one side of the multiple memory chips 5. The memory chip 5 is provided with at least one first solder pad 51 at the position of the stepped surface, and the first solder pads 51 of two adjacent memory chips 5 are connected to each other by a first lead 52. The surface of the interposer 4 facing away from the aerogel layer 3 is provided with at least one second solder pad, and at least one second solder pad and at least one first solder pad 51 are connected to each other by a second lead 53. The other side surface of the interposer 4 is provided with a third solder pad corresponding to the second solder pad, and the second solder pad is electrically connected to the third solder pad. A connecting solder ball 8 is provided between the third solder pad and the substrate 1 to electrically connect them to each other.

[0046] Multiple memory chips 5 are stacked in a stepped manner, which increases the integration of the memory chip 5 and reduces signal interference; through the electrical connection structure of the first solder pad 51, the second solder pad, the third solder pad, the lead and the connecting solder ball 8, stable signal transmission between the memory chip 5 and the substrate 1 and the control chip 9 is ensured, thereby improving the reliability of data transmission.

[0047] like Figure 2 As shown, the memory chip 5 is provided with a plurality of first solder pads 51 at the position of the stepped surface. Specifically, the first solder pads 51 are located on the surface of the first stepped surface away from the interposer 4, and the first solder pads 51 of the plurality of memory chips 5 are provided one by one to form a matrix arrangement structure with multiple rows and columns. The first solder pads 51 in the same column are soldered and connected in sequence through the first lead 52. Correspondingly, the interposer 4 is provided with a plurality of second solder pads at the arrangement extension positions corresponding to the plurality of first solder pads 51. The second solder pads on the interposer 4 are soldered and connected to the first solder pads 51 closest to the second solder pads through the second lead 53. The interposer 4 is electrically connected to the substrate 1 through the connecting solder ball 8, and the substrate 1 is electrically connected to the control chip 9, so as to realize the control chip 9's control of the read and write operations of the memory chip 5.

[0048] In some embodiments, the substrate 1 includes a hollow substrate 11 and a multi-layer bottom substrate 12, the multi-layer bottom substrate 12 is stacked, the hollow substrate 11 is stacked on the bottom substrate 12 at the top, and the hollow substrate 11 is hollowed out corresponding to the position of the control chip 9 to form the groove 13, the surface of the bottom substrate 12 is provided with a first circuit pattern 121, the bottom surface of the hollow substrate 11 is provided with a second circuit pattern 111, and the top surface of the hollow substrate 11 is not covered with the position of the heat conducting layer 2 and is provided with a fourth pad 113 The connecting solder balls 8 are respectively connected to the third pad and the fourth pad 113. The bottom surface of the control chip 9 is provided with a welding terminal 91. The bottom substrate 12 is provided with a plurality of first metallized through-holes 122, and the first circuit pattern 121, the second circuit pattern 111 and the welding terminal 91 are electrically connected by the first metallized through-holes 122. The hollow substrate 11 is provided with a plurality of second metallized through-holes 112, and the second metallized through-holes 112 are used to electrically connect the second circuit pattern 111 and the fourth pad 113.

[0049] The substrate adopts a structural design of a hollow substrate 11 and a multi-layer bottom substrate 12, which ensures strength and stability while providing space for the embedding of the control chip 9 and reducing costs; the circuit connection achieved through the first metallized through-hole 122 and the second metallized through-hole 112 ensures efficient signal transmission between the control chip 9, the storage chip 5 and the substrate 1, thereby improving the electrical performance of the packaging structure.

[0050] In some embodiments, the hollow substrate 11 and the bottom substrate 12 are both polyimide plates.

[0051] In some embodiments, an insulating layer 14 is further disposed between the interposer 4 and the substrate 1 , and the insulating layer 14 surrounds the outer periphery of the connecting solder balls 8 .

[0052] The insulating layer 14 is used to prevent electrical interference between the connecting solder balls 8 and other structures.

[0053] In some embodiments, a plurality of solder balls 123 are disposed on the bottom of the substrate 1 .

[0054] In some embodiments, the insulating layer 14 is selected from silicone resin.

[0055] In some embodiments, the aerogel layer 3 includes silica aerogel and inorganic particles and glass fiber layers located in the silica aerogel.

[0056] The silica aerogel contains a large number of nanopores, which bind the gas therein, thereby achieving a better heat conduction and isolation effect. The inorganic particles and the glass fiber layer are used to support the silica aerogel, reducing its deformation and gas loss after being compressed. The combination of silica aerogel, inorganic particles and glass fiber layer not only ensures excellent thermal insulation performance, but also enhances mechanical strength and structural stability.

[0057] In some embodiments, the thermal conductive layer 2 is a copper layer, the inner wall of the cavity 21 is formed with a grid-like groove 22, the capillary structure is located on the inner wall of the cavity 21 and inside the grid-like groove 22, the capillary structure is a clustered nickel layer, and the boiling point of the phase change working fluid is 40~90°C.

[0058] like Figure 3 The figure shows a schematic diagram of the expanded inner wall of the copper layer.

[0059] In this embodiment, the heat-conducting layer 2 is formed by folding and sealing the copper layer to obtain its cavity 21. The heat-conducting layer 2 is a flat sheet structure. Therefore, the cavity 21 is also a flat cavity. The two opposing inner walls of the cavity 21 are easily abutted against each other, which affects the flow of the phase-change medium and thus affects the heat dissipation. To avoid this problem, the present invention further improves the structure of the heat-conducting layer 2. A grid-like groove 22 is provided on the inner wall of the cavity 21. Even when the two opposing inner walls of the cavity 21 are in contact with each other, the phase-change medium can flow through the grid-like groove 22. Ensure the flow of phase change medium; more importantly, a clustered nickel layer is arranged on the inner wall of the cavity 21 and inside the grid-like groove 22. Compared with other existing capillary structures, the clustered nickel layer has a large number of clustered nickel structures, and a large number of micron-level mesh grooves are formed between the clustered nickel structures, which can play a better capillary absorption role for liquid phase change medium, and can quickly absorb the liquid phase change medium from the high concentration area (the part of the thermal conductive layer 2 exposed to the packaging glue layer 6) to the low concentration area (the part of the thermal conductive layer 2 in contact with the control chip 9), thereby improving the heat dissipation cycle efficiency.

[0060] In this embodiment, the phase change working fluid is ethanol.

[0061] In some embodiments, the heat-conducting layer 2 is exposed on the surface of the packaging adhesive layer 6 , and the surface of the packaging adhesive layer 6 is covered with a graphene coating 7 .

[0062] The graphene coating 7 effectively increases the heat dissipation area of ​​the portion of the thermally conductive layer 2 exposed by the encapsulating adhesive layer 6, thereby improving heat dissipation efficiency without increasing the overall package structure volume. Furthermore, the graphene coating 7 provides effective electromagnetic shielding. According to electromagnetic principles, due to the high conductivity of the graphene coating 7, under the influence of an external electromagnetic signal, free electrons in the conductor will undergo directed migration under the influence of the electric field force. On the outer surface of the graphene coating 7, a charge distribution opposite to the external electric field is induced, thereby generating an electromagnetic field opposite to the incident electromagnetic wave. This reduces the intensity of the electromagnetic wave that passes through the graphene coating 7, achieving a signal shielding effect, reducing external electromagnetic interference, and improving the operational stability of the memory chip 5 and the control chip 9.

[0063] Another embodiment of the present invention provides a method for preparing the substrate chip packaging structure as described above, comprising the following operations:

[0064] Embed the control chip 9 in the groove 13 on one side surface of the substrate 1;

[0065] Covering the heat-conducting layer 2 on the surface of the control chip 9 and the substrate 1;

[0066] An aerogel layer 3 is placed on the side of the heat conducting layer 2 facing away from the control chip 9;

[0067] Welding the interposer 4 to the surface of the substrate 1, and clamping and fixing the thermal conductive layer 2 and the aerogel layer 3;

[0068] Placing the memory chip 5 on the top surface of the interposer 4;

[0069] The control chip 9 , the memory chip 5 , the aerogel layer 3 , the heat-conducting layer 2 and the interposer 4 are encapsulated with encapsulating glue to form an encapsulating glue layer 6 . Meanwhile, a portion of the heat-conducting layer 2 is exposed from the encapsulating glue layer 6 .

[0070] The method for preparing the substrate chip packaging structure of the present invention has simple steps and is easy to operate, can ensure accurate installation and connection between the components of the packaging structure, ensure the stability and reliability of the packaging structure, and is conducive to large-scale production.

[0071] In some embodiments, the method for preparing the thermal conductive layer 2 includes the following operations:

[0072] A copper layer is used as a substrate, and grid-shaped grooves 22 are etched on one surface of the copper layer by laser etching;

[0073] The other side of the copper layer is protected by a mask, and the copper layer is placed in a nitric acid solution for activation treatment, and then washed with water;

[0074] The activated copper layer is placed in an electroplating solution as a cathode for electroplating, forming a clustered nickel layer on one side surface of the copper layer and in the grid-like grooves 22. The electroplating solution includes the following components:

[0075] Nickel salt 2-5g / L, ammonium salt 40-80g / L;

[0076] The current density of the electroplating process is 12 to 20 A / dm 2 ;

[0077] After the electroplating treatment, the clustered nickel layer is subjected to plasma hydroxylation treatment;

[0078] The mask of the copper layer is removed, and the copper layer is folded with the clustered nickel layer as the inner side. The edge of the copper layer is initially welded by laser welding and the injection port is retained. The injection port is vacuumed and the phase change working fluid is injected. The injection port is welded for the second time to form a closed cavity 21 filled with the phase change working fluid inside the copper layer.

[0079] In the present invention, when performing electroplating treatment, a relatively low concentration of nickel salt is required in the electroplating solution, because when the nickel salt concentration is low, nickel ions and hydrogen ions compete and precipitate simultaneously on the surface of the copper layer during the electroplating process, and the precipitated hydrogen bubbles affect the precipitation position of the nickel element, thereby forming a clustered nickel structure.

[0080] When the phase change fluid is an alcohol (such as ethanol), due to the presence of a certain contact angle between nickel and the alcohol, the diffusion of the phase change fluid on the clustered nickel layer is not conducive. In order to improve the affinity between the clustered nickel layer and the phase change fluid, a plasma hydroxylation treatment is performed after the clustered nickel layer is prepared, so that the surface of the clustered nickel layer has hydroxyl groups, which are hydrogen-bonded with the hydroxyl groups of the alcohol. This can effectively improve the affinity between the clustered nickel layer and the alcohol phase change fluid, thereby improving the diffusion efficiency of the phase change fluid on the surface of the clustered nickel layer and improving the heat dissipation effect.

[0081] In some embodiments, the concentration of the nitric acid solution is 50-300 g / L, and the soaking time is 2-5 min.

[0082] In some embodiments, the nickel salt is selected from nickel chloride, and the ammonium salt is selected from ammonium chloride.

[0083] In some embodiments, the method for preparing the aerogel layer 3 includes the following operations:

[0084] Mix ethyl orthosilicate, ethanol, and water in a molar ratio of 1:(7-20):(3-8), add acid to adjust the pH to 2-6, and stir at 40-80°C for 200-500 minutes to obtain silica sol;

[0085] Ammonia water and inorganic particles are added to adjust the pH value of the silica sol to 6.5-8, and the silica sol is mixed with the glass fiber layer to obtain a gel layer;

[0086] The gel layer is placed in a hydrophobic modification liquid for hydrophobic modification, wherein the hydrophobic modification liquid comprises ethanol and hexamethyldisilazane, wherein the mass percentage of hexamethyldisilazane is 1% to 10% and the remainder is ethanol;

[0087] The hydrophobically modified gel layer is dried to obtain an aerogel layer 3 .

[0088] In some embodiments, the inorganic particles are titanium dioxide.

[0089] In some embodiments, the drying is carried out using supercritical carbon dioxide drying.

[0090] In some embodiments, after forming the encapsulation adhesive layer 6, the following operations are further included:

[0091] Graphene coating is coated on the surface of the heat-conducting layer 2 exposed from the packaging adhesive layer 6 and the surface of the packaging adhesive layer 6 , and is cured to obtain a graphene coating 7 .

[0092] The present invention is further described below with reference to the following examples.

[0093] Example 1

[0094] This embodiment is used to illustrate the method for preparing the substrate chip packaging structure disclosed in the present invention, which includes the following steps:

[0095] 1) Preparation of thermal conductive layer:

[0096] A copper layer is used as a substrate, and grid-shaped grooves are etched on one surface of the copper layer by laser etching;

[0097] The other side of the copper layer is protected by a mask, and the copper layer is placed in a nitric acid solution for activation treatment, and then washed with water;

[0098] The activated copper layer is placed as a cathode in an electroplating solution for electroplating, forming a clustered nickel layer on one surface of the copper layer and in the grid-like grooves. The electroplating solution includes the following components:

[0099] Nickel chloride 3g / L, ammonium chloride 50g / L;

[0100] The current density of the electroplating process is 15A / dm 2 ;

[0101] After the electroplating treatment, the clustered nickel layer is subjected to plasma hydroxylation treatment;

[0102] The mask of the copper layer is removed, and the copper layer is folded with the clustered nickel layer as the inner side. The edge of the copper layer is initially welded by laser welding and the injection port is retained. The injection port is vacuumed and ethanol is injected. The injection port is welded for the second time to form a closed cavity filled with ethanol inside the copper layer.

[0103] 2) Preparation of aerogel layer:

[0104] TEOS, ethanol, and water were mixed in a molar ratio of 1:10:5, and hydrochloric acid was added to adjust the pH value to 4. The mixture was stirred at 50°C for 400 minutes to obtain silica sol.

[0105] adding ammonia and titanium dioxide, adjusting the pH value of the silica sol to 7, and mixing the silica sol with the glass fiber layer to obtain a gel layer;

[0106] The gel layer is placed in a hydrophobic modification solution for hydrophobic modification, wherein the hydrophobic modification solution comprises ethanol and hexamethyldisilazane, wherein the mass percentage of hexamethyldisilazane is 5% and the rest is ethanol;

[0107] The hydrophobically modified gel layer is dried to obtain an aerogel layer.

[0108] 3) Preparation of substrate chip packaging structure

[0109] Embed the control chip in a groove on one side of the substrate, and attach a first temperature sensor to the side wall of the control chip;

[0110] Covering the surfaces of the control chip and the substrate with a heat-conducting layer;

[0111] placing an aerogel layer on a side of the heat-conducting layer facing away from the control chip;

[0112] The interposer is welded to the surface of the substrate through the connecting solder balls, and the thermal conductive layer and the aerogel layer are clamped and fixed;

[0113] A plurality of memory chips are stacked in a staggered manner and then placed on the top surface of the interposer, and a second temperature sensor is attached to the side wall of the memory chip;

[0114] The control chip, the memory chip, the aerogel layer, the heat-conducting layer and the interposer are encapsulated with an encapsulating adhesive to form an encapsulating adhesive layer, with the heat-conducting layer partially exposed from the encapsulating adhesive layer;

[0115] Graphene coating is coated on the surface of the heat-conducting layer exposed from the packaging adhesive layer and the surface of the packaging adhesive layer, and is cured to obtain a graphene coating.

[0116] Example 2

[0117] This embodiment is used to illustrate the method for preparing the substrate chip packaging structure disclosed in the present invention, and includes most of the operating steps in Example 1, except that:

[0118] In step 1), the electroplating operation and plasma hydroxylation treatment of the clustered nickel layer are not performed.

[0119] Example 3

[0120] This embodiment is used to illustrate the method for preparing the substrate chip packaging structure disclosed in the present invention, and includes most of the operating steps in Example 1, except that:

[0121] In step 1), no plasma hydroxylation treatment is performed.

[0122] Example 4

[0123] This embodiment is used to illustrate the method for preparing the substrate chip packaging structure disclosed in the present invention, and includes most of the operating steps in Example 1, except that:

[0124] In step 3), no graphene coating operation is performed.

[0125] Comparative Example 1

[0126] This comparative example is used to illustrate the method for preparing the substrate chip packaging structure disclosed in the present invention, and includes most of the operating steps in Example 1, except that:

[0127] Do not proceed to step 1);

[0128] In step 3), no heat-conducting layer is added, and the aerogel layer is directly placed on the top surface of the control chip.

[0129] Comparative Example 2

[0130] This comparative example is used to illustrate the method for preparing the substrate chip packaging structure disclosed in the present invention, and includes most of the operating steps in Example 1, except that:

[0131] Do not proceed to step 2);

[0132] In step 3), no aerogel layer is added, and the intermediate sheet is directly placed on the top surface of the thermal conductive layer.

[0133] Performance Testing

[0134] The following performance tests were performed on the substrate chip packaging structure prepared above:

[0135] Connect the substrate chip package structure to the power supply and external control device, perform the same read and write operations on the substrate chip package structure for 1 hour, and then use the first temperature sensor and the second temperature sensor to detect the surface temperature of the control chip and the memory chip respectively, and fill in the obtained test results in Table 1.

[0136] Table 1

[0137]

[0138] The test results in Table 1 demonstrate that the packaging structure provided by the present invention significantly improves the efficiency of heat conduction between the internal chips and the external environment, thereby enhancing the cooling effect on the memory and control chips. This design effectively prevents the performance of the chips from being affected by excessive internal temperatures during operation, which has a positive impact on chip lifespan. Furthermore, the packaging structure provided by the present invention effectively reduces the conduction of heat generated by the control chip to the memory chips.

[0139] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A substrate chip packaging structure, characterized in that: The invention comprises a substrate, a control chip, a memory chip, a heat-conducting layer, an aerogel layer, an interposer and an encapsulating adhesive layer. A groove is provided on one surface of the substrate, the control chip is embedded in the groove, the heat-conducting layer covers the surfaces of the control chip and the substrate, a cavity is formed inside the heat-conducting layer, the inner wall of the cavity is formed with a capillary structure, the cavity is filled with a phase-change medium, the aerogel layer is located on the side of the heat-conducting layer away from the control chip, the interposer is located on the side of the aerogel layer away from the heat-conducting layer, the memory chip is located on the side of the interposer away from the aerogel layer, the encapsulating adhesive layer is arranged on the substrate, the control chip, the memory chip, the aerogel layer and the interposer are all located inside the encapsulating adhesive layer, the heat-conducting layer is partially located inside the encapsulating adhesive layer, and the heat-conducting layer partially extends and is exposed from the encapsulating adhesive layer.

2. The substrate chip packaging structure according to claim 1, wherein: There are multiple memory chips, and the multiple memory chips are stacked in a stepped manner to form a stepped surface on one side of the multiple memory chips. The memory chip is provided with at least one first pad at the position of the stepped surface, and the first pads of two adjacent memory chips are connected to each other by a first lead. The interposer is provided with at least one second pad on a surface facing away from the aerogel layer, and at least one second pad is connected to at least one first pad by a second lead. The other side of the interposer is provided with a third pad corresponding to the second pad, and the second pad is electrically connected to the third pad. A connecting solder ball is provided between the third pad and the substrate to electrically connect them to each other.

3. The substrate chip packaging structure according to claim 2, wherein: The substrate includes a hollow substrate and a multi-layer bottom substrate, the multi-layer bottom substrates are stacked, the hollow substrate is stacked on the bottom substrate located at the top, and the hollow substrate is hollowed out corresponding to the position of the control chip to form the groove, the surface of the bottom substrate is provided with a first circuit pattern, the bottom surface of the hollow substrate is provided with a second circuit pattern, the top surface of the hollow substrate is provided with a fourth solder pad at a position not covering the heat conductive layer, the connecting solder balls are respectively connected to the third solder pad and the fourth solder pad, the bottom surface of the control chip is provided with a soldering terminal, a plurality of first metallized through-holes are provided in the bottom substrate, the first circuit pattern, the second circuit pattern and the soldering terminal are electrically connected by the first metallized through-holes, a plurality of second metallized through-holes are provided inside the hollow substrate, and the second metallized through-holes are used to electrically connect the second circuit pattern and the fourth solder pad.

4. The substrate chip packaging structure according to claim 1, wherein: The aerogel layer includes silica aerogel and inorganic particles and a glass fiber layer located in the silica aerogel.

5. The substrate chip packaging structure according to claim 1, wherein: The heat conducting layer is a copper layer, the inner wall of the cavity is formed with a grid-like groove, the capillary structure is located on the inner wall of the cavity and inside the grid-like groove, the capillary structure is a clustered nickel layer, and the boiling point of the phase change working medium is 40-90°C.

6. The substrate chip packaging structure according to claim 1, wherein: The heat-conducting layer is exposed on the surface of the packaging adhesive layer, and the surface of the packaging adhesive layer is covered with a graphene coating.

7. The method for preparing a substrate chip packaging structure according to any one of claims 1 to 6, wherein: The following operations are included: Embed the control chip in the groove on one side of the substrate; Covering the surfaces of the control chip and the substrate with a heat-conducting layer; placing an aerogel layer on a side of the heat-conducting layer facing away from the control chip; Welding the interposer to the surface of the substrate and clamping and fixing the thermal conductive layer and the aerogel layer; placing a memory chip on the top surface of the interposer; The control chip, the memory chip, the aerogel layer, the heat-conducting layer and the interposer are encapsulated with encapsulating glue to form an encapsulating glue layer, and the heat-conducting layer is partially exposed from the encapsulating glue layer.

8. The method for preparing a substrate chip packaging structure according to claim 7, wherein: The preparation method of the thermal conductive layer comprises the following operations: A copper layer is used as a substrate, and grid-shaped grooves are etched on one surface of the copper layer by laser etching; The other side of the copper layer is protected by a mask, and the copper layer is placed in a nitric acid solution for activation treatment, and then washed with water; The activated copper layer is placed as a cathode in an electroplating solution for electroplating, forming a clustered nickel layer on one surface of the copper layer and in the grid-like grooves. The electroplating solution includes the following components: Nickel salt 2-5g / L, ammonium salt 40-80g / L; The current density of the electroplating process is 12 to 20 A / dm 2 ; After the electroplating treatment, the clustered nickel layer is subjected to plasma hydroxylation treatment; The mask of the copper layer is removed, and the copper layer is folded with the clustered nickel layer as the inner side. The edge of the copper layer is initially welded by laser welding and the injection port is retained. The injection port is vacuumed and the phase change working fluid is injected. The injection port is welded for the second time to form a closed cavity filled with the phase change working fluid inside the copper layer.

9. The method for preparing a substrate chip packaging structure according to claim 7, wherein: The preparation method of the aerogel layer comprises the following operations: Tetraethyl orthosilicate, ethanol, and water are mixed in a molar ratio of 1:(7-20):(3-8), acid is added to adjust the pH to 2-6, and the mixture is stirred at 40-80°C for 200-500 minutes to obtain a silica sol; Ammonia water and inorganic particles are added to adjust the pH value of the silica sol to 6.5-8, and the silica sol is mixed with the glass fiber layer to obtain a gel layer; The gel layer is placed in a hydrophobic modification liquid for hydrophobic modification, wherein the hydrophobic modification liquid comprises ethanol and hexamethyldisilazane, wherein the mass percentage of hexamethyldisilazane is 1% to 10%; The hydrophobically modified gel layer is dried to obtain an aerogel layer.

10. The method for preparing a substrate chip packaging structure according to claim 7, wherein: After the encapsulation glue layer is formed, the following operations are also included: Graphene coating is coated on the surface of the heat-conducting layer exposed from the packaging adhesive layer and the surface of the packaging adhesive layer, and is cured to obtain a graphene coating.

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