Semiconductor device and manufacturing method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor structure; wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body; the first dielectric layer comprises a first conductive hole and a second conductive hole; the first conductive layer is located in the first conductive hole, and the first conductive layer is electrically connected with the semiconductor body; the second conductive layer is located in the second conductive hole, and the second conductive layer is electrically connected with the semiconductor structure; the material of the first conductive layer is different from the material of the second conductive layer. The invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, which can improve the reliability of the semiconductor device and reduce the manufacturing cost of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technologies, and particularly to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] In semiconductor devices of integrated circuits, during the process of filling conductive vias in the conductive layer of the semiconductor device, problems such as voids are likely to occur, resulting in low filling quality of the conductive layer in the conductive vias, and further leading to low reliability of the semiconductor device. Summary of the Invention

[0003] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle, which can improve the reliability of the semiconductor device and also reduce the manufacturing cost of the semiconductor device.

[0004] According to one aspect of the present invention, a semiconductor device is provided, which includes:

[0005] A semiconductor structure; wherein, the semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body; the first dielectric layer includes a first conductive hole and a second conductive hole;

[0006] A first conductive layer, located in the first conductive hole, wherein the first conductive layer is electrically connected to the semiconductor body;

[0007] A second conductive layer, located in the second conductive hole, wherein the second conductive layer is electrically connected to the semiconductor structure; the material of the first conductive layer is different from the material of the second conductive layer.

[0008] Optionally, the semiconductor device provided in this embodiment further includes a third conductive layer and a fourth conductive layer;

[0009] The third conductive layer is located on the side of the first conductive layer away from the semiconductor body and is electrically connected to the first conductive layer;

[0010] The fourth conductive layer is located on the side of the second conductive layer away from the semiconductor body and is electrically connected to the second conductive layer.

[0011] Optionally, the semiconductor body includes a first surface and a second surface which are oppositely arranged;

[0012] The semiconductor body further includes a well region, a first region, and a second region. The first region is of a first conductivity type and is disposed on the first surface. The well region is of the first conductivity type and is disposed on a side of the first region away from the first surface. The second region is of a second conductivity type and is disposed on the first surface, and the second region is in contact with the first region. The first conductive layer is in contact with the first region and the second region, and the second conductive layer is in contact with the gate.

[0013] The semiconductor body further includes a gate structure. Wherein, the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body. The gate structure includes a second dielectric layer and a gate, and the second dielectric layer is used for insulating and spacing the gate and the semiconductor body.

[0014] The semiconductor device further includes a drain, and the drain is located on the second surface.

[0015] Optionally, the material of the gate includes polysilicon.

[0016] The material of the first conductive layer includes a compound generated by the reaction of nickel with the material of the second region or a compound generated by the reaction of aluminum with the material of the second region.

[0017] The material of the second conductive layer includes titanium and titanium nitride.

[0018] Optionally, the semiconductor structure includes an edge region and a central region, and the edge region surrounds the central region.

[0019] The thickness of the second dielectric layer located in the edge region is greater than the thickness of the second dielectric layer located in the central region.

[0020] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body. According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, and the manufacturing method includes:

[0021] Forming a semiconductor structure. Wherein, the semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body. The first dielectric layer includes a first conductive hole and a second conductive hole.

[0022] Forming a first conductive layer in the first conductive hole and forming a second conductive layer in the second conductive hole. Wherein, the first conductive layer is electrically connected to the semiconductor body. The second conductive layer is electrically connected to the semiconductor structure. The materials of the first conductive layer and the second conductive layer are different.

[0023] Optionally, the forming of the semiconductor structure includes:

[0024] Form a semiconductor body;

[0025] Form a first dielectric layer on one side of the semiconductor body;

[0026] Simultaneously form a first conductive hole and a second conductive hole in the first dielectric layer;

[0027] Forming a first conductive layer in the first conductive hole and a second conductive layer in the second conductive hole includes:

[0028] Form an isolation layer in the second conductive hole;

[0029] Deposit a first conductive material on the side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive hole;

[0030] Remove the isolation layer and the first conductive material outside the first conductive hole;

[0031] Form a second conductive layer in the second conductive hole.

[0032] Optionally, simultaneously forming a first conductive hole and a second conductive hole in the first dielectric layer includes:

[0033] Form a mask layer on the side of the first dielectric layer away from the semiconductor body; wherein, the mask layer includes through holes that expose the first dielectric layer;

[0034] Etch the first dielectric layer using the mask layer as a mask to simultaneously form the first conductive hole and the second conductive hole.

[0035] Optionally, forming an isolation layer in the second conductive hole includes:

[0036] Form a sacrificial layer on the side of the first dielectric layer away from the semiconductor body, wherein the sacrificial layer covers the surface of the first dielectric layer and fills the first conductive hole and the second conductive hole; a first thickness is greater than a second thickness, the first thickness is the vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the first conductive hole, and the second thickness is the vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the second conductive hole;

[0037] Remove the sacrificial layer located in the second conductive hole, and a part of the sacrificial layer located in the first conductive hole is retained;

[0038] An isolation transition layer is formed on a side of the first dielectric layer away from the semiconductor structure, where the isolation transition layer is located in the second conductive hole and the first conductive hole and covers a sacrificial layer in the first conductive hole;

[0039] The sacrificial layer and the isolation transition layer in the first conductive hole are removed, and the isolation transition layer retained in the second conductive hole serves as the isolation layer.

[0040] Optionally, forming the semiconductor structure includes:

[0041] Providing a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, and a second region, the first region is set to a first conduction type and is disposed on the first surface; the well region is set to the first conduction type and is disposed on a side of the first region away from the first surface; the second region is set to a second conduction type and is disposed on the first surface, and the second region is in contact with the first region;

[0042] Forming a gate structure on the first surface; wherein, the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure includes a second dielectric layer and a gate, and the second dielectric layer is used for insulating and spacing the gate and the semiconductor body;

[0043] Forming the first dielectric layer on a side of the gate structure away from the second dielectric layer;

[0044] After forming the second conductive layer in the second conductive hole, further including:

[0045] Forming a third conductive layer located on a side of the first conductive layer away from the semiconductor body and electrically connected to the first conductive layer, and a fourth conductive layer located on a side of the second conductive layer away from the semiconductor body and electrically connected to the second conductive layer;

[0046] Forming a drain on the second surface.

[0047] According to another aspect of the present invention, a power module is provided, the power module includes a substrate and at least one semiconductor device provided by an embodiment of the present invention, and the substrate is used for carrying the semiconductor device.

[0048] According to another aspect of the present invention, a power conversion circuit is provided, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0049] The power conversion circuit includes a circuit board and at least one semiconductor device provided by an embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0050] According to another aspect of the present invention, a vehicle is provided, which includes a load and a power conversion circuit provided by any embodiment of the present invention. The power conversion circuit is configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current, and then input the converted current to the load.

[0051] An embodiment of the present invention provides a semiconductor device, which includes: a semiconductor structure, a first conductive layer, and a second conductive layer. The semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer includes a first conductive hole and a second conductive hole. The first conductive layer is located in the first conductive hole, and the second conductive layer is located in the second conductive hole. The first conductive layer is electrically connected to the semiconductor body, and the second conductive layer is electrically connected to the semiconductor structure. In the embodiment of the present invention, the material of the first conductive layer is different from the material of the second conductive layer. Even when depositing metals such as nickel and aluminum during the formation of the first conductive layer, since the material of the second conductive layer is different from the material of the first conductive layer, the second conductive layer will not be nickel and aluminum, thus avoiding problems such as severe reaction between the second conductive layer and the semiconductor structure to generate voids. In summary, the semiconductor device provided by the embodiment of the present invention can improve the reliability of the semiconductor device.

[0052] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0054] Figure 1 and Figure 2 is a schematic structural diagram of the manufacturing process of a semiconductor device provided in the related art of the present invention.

[0055] Figure 3 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention.

[0056] Figure 4 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present invention.

[0057] Figure 5 It is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention.

[0058] Figure 6 It is a schematic flowchart of a manufacturing method of a semiconductor device provided according to an embodiment of the present invention.

[0059] Figure 7 It is a schematic structural diagram of a semiconductor structure before forming the first dielectric layer.

[0060] Figure 8 It is a schematic flowchart of another manufacturing method of a semiconductor device provided according to an embodiment of the present invention.

[0061] Figure 9 It is a schematic structural diagram after forming the first dielectric layer on one side of the semiconductor body.

[0062] Figure 10 It is a schematic structural diagram of forming an isolation layer in the second conductive hole.

[0063] Figure 11 It is a schematic structural diagram after forming the first conductive layer.

[0064] Figure 12 It is a schematic structural diagram after removing the isolation layer and the material of the first conductive layer outside the first conductive hole.

[0065] Figure 13 It is a schematic flowchart of another manufacturing method of a semiconductor device provided according to an embodiment of the present invention.

[0066] Figure 14 It is a schematic structural diagram after forming the sacrificial layer.

[0067] Figure 15 It is a schematic structural diagram after removing the sacrificial layer located in the second conductive hole.

[0068] Figure 16 It is a schematic structural diagram after forming the isolation transition layer.

[0069] Figure 17 It is a schematic structural diagram of a semiconductor body provided according to an embodiment of the present invention. Detailed implementation manners

[0070] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0071] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0072] Through research and analysis by the inventor, it is found that the reasons for problems such as voids generated during the process of filling the conductive vias in the conductive layer are: Figure 1 and Figure 2 is a schematic structural diagram of the manufacturing process of a semiconductor device provided in the related art of the present invention. Referring to Figure 1 and Figure 2 , before forming the conductive layer, first form a first conductive hole 101 and a second conductive hole 102 in the first dielectric layer 110 (reference can be made to Figure 1 ), and then deposit metals such as nickel or aluminum with relatively low contact resistance into the first conductive hole 101 and the second conductive hole 102 simultaneously to form the conductive layer 130. Since the second conductive hole 102 exposes the gate 120, during the process of forming the conductive layer 130, metals such as nickel and aluminum will react violently with the gate 120 to generate an alloy, resulting in problems such as voids.

[0073] In order to improve the reliability of the semiconductor device, an embodiment of the present invention provides a semiconductor device.

[0074] Figure 3 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention. Figure 4 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present invention. Referring to Figure 3 and Figure 4 , the semiconductor device provided in this embodiment includes: a semiconductor structure 100, a first conductive layer 150, and a second conductive layer 160; the semiconductor structure 100 includes a semiconductor body 210 and a first dielectric layer 110, and the first dielectric layer 110 is located on one side of the semiconductor body 210; the first dielectric layer 110 includes a first conductive hole 101 and a second conductive hole 102 (reference can be made to Figure 4); The first conductive layer 150 is located in the first conductive via 101, and the first conductive layer 150 is electrically connected to the semiconductor body 210; the second conductive layer 160 is located in the second conductive via 102, wherein the second conductive layer 160 is electrically connected to the semiconductor structure 100; the material of the first conductive layer 150 is different from the material of the second conductive layer 160.

[0075] Specifically, when manufacturing a semiconductor device, the first conductive via 101 and the second conductive via 102 in the first dielectric layer 110 can be formed simultaneously, thereby reducing the manufacturing steps of the semiconductor device and lowering the manufacturing cost of the semiconductor device.

[0076] In this embodiment, the material of the first conductive layer 150 is different from the material of the second conductive layer 160, which can avoid problems such as voids caused by the reaction between the material of the second conductive layer 160 and the gate in the semiconductor structure 100 exposed by the second conductive via 102 when the material of the second conductive layer 160 is the same as that of the first conductive layer 150, thus improving the reliability of the semiconductor device.

[0077] This embodiment provides a semiconductor device, which includes: a semiconductor structure, a first conductive layer, and a second conductive layer. The semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer includes a first conductive via and a second conductive via. The first conductive layer is located in the first conductive via, and the second conductive layer is located in the second conductive via. The first conductive layer is electrically connected to the semiconductor body, and the second conductive layer is electrically connected to the semiconductor structure. In this embodiment, the material of the first conductive layer is different from the material of the second conductive layer. When depositing metals such as nickel and aluminum during the formation of the first conductive layer, since the material of the second conductive layer is different from that of the first conductive layer, the second conductive layer will not be nickel and aluminum, thus avoiding problems such as violent reaction between the second conductive layer and the semiconductor structure to generate voids. In summary, the semiconductor device provided in this embodiment can improve the reliability of the semiconductor device.

[0078] Optionally, Figure 5 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention. Refer to Figure 5 , the semiconductor device provided in this embodiment further includes a third conductive layer 170 and a fourth conductive layer 180; the third conductive layer 170 is located on the side of the first conductive layer 150 away from the semiconductor body 210 and is electrically connected to the first conductive layer 150; the fourth conductive layer 180 is located on the side of the second conductive layer 160 away from the semiconductor body 210 and is electrically connected to the second conductive layer 160.

[0079] Specifically, the third conductive layer 170 is the source conductive layer of the semiconductor device, and the fourth conductive layer 180 can be the gate conductive layer of the semiconductor device. The third conductive layer 170 and the fourth conductive layer 180 can be electrically connected to external devices, thereby realizing the electrical connection between the semiconductor device provided in this embodiment and the external devices.

[0080] The material of the third conductive layer 170 may include aluminum, copper, tungsten, or Ti / Al / Ti, etc. The material of the fourth conductive layer 180 may include titanium nitride, molybdenum, or TiN / Al / TiN, etc.

[0081] Optionally, continuing to refer to Figure 5 , the semiconductor body 210 includes a first surface S1 and a second surface S2 which are oppositely arranged; the semiconductor body 210 further includes a well region 211, a first region 212, and a second region 213. The first region 212 is set to a first conduction type and is disposed on the first surface S1. The well region 211 is set to the first conduction type and is disposed on a side of the first region 212 away from the first surface S1. The second region 213 is set to a second conduction type and is disposed on the first surface S1. The second region 213 is in contact with the first region 212; the first conductive layer 150 is in contact with the first region 212 and the second region 213, and the second conductive layer 160 is in contact with the gate 120; the semiconductor body 210 further includes a gate structure 220; wherein, the gate structure 220 is disposed on the first surface S1 or the gate structure 220 extends from the first surface S1 into the semiconductor body 210; the gate structure 220 includes a second dielectric layer 221 and a gate 120, and the second dielectric layer 221 is used for insulating and spacing the gate 120 and the semiconductor body 210; the semiconductor device further includes a drain 190; the drain 190 is located on the second surface S2.

[0082] Specifically, the first conductive layer 150 may be an ohmic contact layer, and the second conductive layer 160 may be another ohmic contact layer. The semiconductor body 210 may further include a substrate 215 and an epitaxial layer 216. The epitaxial layer 216 is located on one side of the substrate 215, and the active region 214 and the well region 211 are both located on a side of the epitaxial layer 216 away from the substrate 215. The active region 214 may include the first region 212 and the second region 213, or may only include the second region 213.

[0083] In some embodiments of the present invention, the semiconductor body 210 may further only include the epitaxial layer 216. The epitaxial layer 216 is a semiconductor layer formed on the basis of the substrate 215 through a single epitaxial process. The epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0084] The second dielectric layer 221 may be formed on the epitaxial layer 216 away from the substrate 215 at one time through a film forming process. The second dielectric layer 221 may be selected from silicon oxide or a dielectric layer with a higher dielectric constant. The gate 120 is formed on a side of the second dielectric layer 221 away from the epitaxial layer 216.

[0085] Optionally, the material of the gate includes polysilicon; the material of the first conductive layer includes a compound formed by the reaction of nickel with the material of the second region or a compound formed by the reaction of aluminum with the material of the second region; the material of the second conductive layer includes titanium and titanium nitride.

[0086] Specifically, setting the material of the first conductive layer to include a compound formed by the reaction of nickel with the material of the second region or a compound formed by the reaction of aluminum with the material of the second region, the first conductive material deposited during the formation of the first conductive layer can be nickel or aluminum, which reduces the cost of manufacturing the first conductive layer and can also make the resistivity of the formed first conductive layer relatively low, improving the reliability of the semiconductor device. In addition, when depositing metallic nickel or aluminum in the first conductive hole, during the annealing process, the deposited metal will react with the material of the second region to form a compound. Setting the material of the first conductive layer to include a compound formed by the reaction of nickel with the material of the second region or a compound formed by the reaction of aluminum with the material of the second region can prevent the first conductive layer in the first conductive hole from being easily removed when removing the first conductive material outside the first conductive hole during the manufacturing process of the semiconductor structure.

[0087] Setting the material of the second conductive layer to include titanium and titanium nitride can avoid problems such as voids generated when the material of the second conductive layer reacts with the polysilicon material of the gate, and can also reduce the ohmic resistance and manufacturing cost of the second conductive layer. The material of the second conductive layer can also be relatively stable metals such as silver and gold.

[0088] Optionally, continue to refer to Figure 5 , the semiconductor structure includes an edge region 100b and a central region 100a, and the edge region 100b surrounds the central region 100a; the thickness of the second dielectric layer 221 located in the edge region 100b is greater than the thickness of the second dielectric layer 221 located in the central region 100a.

[0089] Specifically, the thick thickness of the second dielectric layer 221 located in the edge region 100b can make the second dielectric layer 221 in the edge region 100b have better stress, so that when packaging the semiconductor device, the second dielectric layer 221 in the edge region 100b can play a protective role. In addition, setting the thickness of the second dielectric layer 221 in the edge region 100b to be thick can make the position of the second conductive hole higher than the position of the first conductive hole in the thickness direction of the semiconductor body 210, that is, the second conductive hole can be located on the side of the first conductive hole away from the semiconductor body 210, which is convenient for manufacturing the semiconductor device and will be introduced in detail in the subsequent manufacturing method.

[0090] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0091] Specifically, the MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device. The silicon carbide MOSFET power device or the gallium nitride MOSFET power device has the advantages of high breakdown voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices. Among them, when silicon carbide or gallium nitride is used as the semiconductor body 210, due to the high-temperature resistance of silicon carbide or gallium nitride, it can also prevent particles in the semiconductor body 210 from dissolving in the conductive materials of the first conductive layer 150 and the second conductive layer 160 to generate cracks when the conductive materials of the first conductive layer 150 and the second conductive layer 160 come into contact with the semiconductor body 210, thereby further improving the filling quality of the first conductive layer 150 and the second conductive layer 160.

[0092] Figure 6 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Refer to Figure 6 The method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0093] S110. Form a semiconductor structure.

[0094] Among them, Figure 4 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention. Refer to Figure 4 The semiconductor structure 100 provided in this embodiment includes a semiconductor body 210 and a first dielectric layer 110. The first dielectric layer 110 is located on one side of the semiconductor body 210. The first dielectric layer 110 includes a first conductive hole 101 and a second conductive hole 102.

[0095] Specifically, the semiconductor device provided in this embodiment can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The semiconductor structure provided in this embodiment can be a structure that realizes the semiconductor function of a MOSFET power device. Refer to Figure 7 Figure 7 is a schematic diagram of the semiconductor structure before the first dielectric layer is fabricated. The semiconductor structure 100 further includes a gate structure 220. The gate structure 220 includes a second dielectric layer 221 and a gate 120. The gate structure 220 can be located on one side of the semiconductor body 210. The first dielectric layer can be formed on the side of the gate structure 220 away from the semiconductor body 210 to form the semiconductor structure 100.

[0096] S120. Form a first conductive layer in the first conductive hole and a second conductive layer in the second conductive hole. ​

[0097] Among them, continue to refer to Figure 3 , the first conductive layer 150 is electrically connected to the semiconductor body 210; the second conductive layer 160 is electrically connected to the semiconductor structure 100; the material of the first conductive layer 150 is different from the material of the second conductive layer 160.

[0098] This embodiment provides a manufacturing method of a semiconductor device. The manufacturing method includes: first forming a semiconductor structure. The semiconductor structure includes a semiconductor body and a first dielectric layer. The first dielectric layer includes a first conductive hole and a second conductive hole. Then, a first conductive layer is formed in the first conductive hole and a second conductive layer is formed in the second conductive hole. The formed first conductive layer is electrically connected to the semiconductor body, and the second conductive layer is electrically connected to the semiconductor structure. In this embodiment, the material of the first conductive layer is different from the material of the second conductive layer. When the conductive material deposited during the formation of the first conductive layer is a metal such as nickel and aluminum, since the material of the second conductive layer is different from the material of the first conductive layer, therefore, the second conductive layer will not be nickel and aluminum, thus avoiding problems such as severe reaction between the second conductive layer and the semiconductor structure to generate voids. In summary, the manufacturing method of the semiconductor device provided in this embodiment can improve the reliability of the semiconductor device.

[0099] Figure 8 is a schematic flowchart of another manufacturing method of a semiconductor device according to an embodiment of the present invention. Refer to Figure 8 , the manufacturing method of the semiconductor device provided in this embodiment includes the following steps:

[0100] S210. Form a semiconductor body.

[0101] S220. Form a first dielectric layer on one side of the semiconductor body.

[0102] Specifically, Figure 9 is a schematic diagram of the structure after forming the first dielectric layer on one side of the semiconductor body. Refer to Figure 9 , the first dielectric layer can be formed on one side of the semiconductor body through a deposition process, and the first dielectric layer can cover the gate.

[0103] S230. Simultaneously form a first conductive hole and a second conductive hole in the first dielectric layer.

[0104] Specifically, continue to refer to Figure 4 , Figure 4 is the structure formed in step S230. The first conductive hole 101 exposes a part of the semiconductor body 210, and the second conductive hole 102 exposes a part of the gate 120. The number of the first conductive holes 101 can be multiple.

[0105] The first dielectric layer 110 can be lithographed to simultaneously form the first conductive via 101 and the second conductive via 102. The simultaneous formation of the first conductive via 101 and the second conductive via 102 can reduce the manufacturing process of semiconductor devices. Moreover, the simultaneous formation of the first conductive via 101 and the second conductive via 102 can avoid the use of two lithography processes, reducing the lithography process and also preventing the increase in the manufacturing cost of semiconductor devices and the decrease in the manufacturing yield of semiconductor devices due to the increase in the lithography process.

[0106] S240. Form an isolation layer in the second conductive via.

[0107] Specifically, Figure 10 is a schematic structural diagram of forming an isolation layer in the second conductive via. Refer to Figure 10 , after step S240, there is no isolation layer 140 in the first conductive via 101, and the first conductive via 101 still exposes the semiconductor body 210. The isolation layer 140 in the second conductive via covers the gate 120 that can be exposed by the second conductive via. The material of the isolation layer 140 can be titanium or silicon nitride.

[0108] S250. Deposit a first conductive material on the side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive via.

[0109] Specifically, Figure 11 is a schematic structural diagram after forming the first conductive layer. Refer to Figure 11 , during the process of forming the first conductive layer 150, since the isolation layer 140 is provided in the second conductive via, therefore, the first conductive material will only cover the isolation layer 140 and will not directly contact and react with the gate 120 that can be exposed by the second conductive via to cause problems such as voids. Forming the first conductive layer by a deposition process can reduce the manufacturing cost of semiconductor devices. The first conductive material can be nickel or aluminum.

[0110] S260. Remove the isolation layer and the first conductive material outside the first conductive via.

[0111] Specifically, Figure 12 is a schematic structural diagram after removing the isolation layer and the first conductive material outside the first conductive via. Refer to Figure 12 , the isolation layer and the first conductive material outside the first conductive via can be removed by a wet etching method. After removing the isolation layer, the first conductive material covering the surface of the isolation layer will also be removed. At this time, there is no isolation layer and first conductive material in the second conductive via 102, and the second conductive via 102 exposes the gate 120.

[0112] S270. Form a second conductive layer in the second conductive via.

[0113] Specifically, continue to refer to Figure 3 , Figure 3Schematic diagram of the structure after forming the second conductive layer 160.

[0114] This embodiment provides a method for manufacturing a semiconductor device. The manufacturing method includes: first, simultaneously forming a first conductive hole and a second conductive hole in a first dielectric layer in a semiconductor structure. Forming the first conductive hole and the second conductive hole simultaneously can reduce the photolithography process, thereby reducing the manufacturing cost, and can also avoid problems such as alignment deviation generated during the two photolithography processes. Then, form an isolation layer in the second conductive hole, so that the isolation layer covers the second conductive hole while the first conductive hole still exposes the semiconductor body. Next, form a first conductive layer in the first conductive hole. Since the second conductive hole is covered with an isolation layer, during the process of forming the first conductive layer, the first conductive material cannot fall into the second conductive hole. Even if the contact metal in the first conductive hole is nickel, aluminum, etc., it can avoid problems such as voids caused by the reaction between the first conductive material and the semiconductor structure that the second conductive hole can expose. Then, remove the isolation layer and the first conductive material outside the first conductive hole and form a second conductive layer electrically connected to the semiconductor structure in the second conductive hole, thereby forming a semiconductor device. In summary, the method for manufacturing a semiconductor device provided in this embodiment can improve the reliability of the semiconductor device and also reduce the manufacturing cost of the semiconductor device.

[0115] Optionally, simultaneously forming the first conductive hole and the second conductive hole in the first dielectric layer includes the following steps:

[0116] S231. Form a mask layer on the side of the first dielectric layer away from the semiconductor body; wherein, the mask layer includes a through hole, and the through hole exposes the first dielectric layer.

[0117] S232. Etch the first dielectric layer using the mask layer as a mask to simultaneously form the first conductive hole and the second conductive hole.

[0118] Specifically, continue to refer to Figure 9 , and a mask layer can be formed on the side of the first dielectric layer 110 away from the semiconductor body 210 as shown in Figure 9 . The mask layer can be a photoresist layer.

[0119] Optionally, Figure 13 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to Figure 13 , the method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0120] S310. Form a semiconductor body.

[0121] Among them, the content of step S310 is the same as the content of step S210. For the description of step S310, please refer to the description of step S210 for details, and it will not be repeated here.

[0122] S320. Form a first dielectric layer on one side of the semiconductor body.

[0123] Wherein, the content of step S320 is the same as that of step S220. For the description of step S320, please refer to the description of step S220, which will not be repeated here.

[0124] S330. Simultaneously form a first conductive hole and a second conductive hole in the first dielectric layer.

[0125] Wherein, the content of step S330 is the same as that of step S230. For the description of step S330, please refer to the description of step S230, which will not be repeated here.

[0126] S340. Form a sacrificial layer on the side of the first dielectric layer away from the semiconductor body.

[0127] Wherein, referring to Figure 14 , Figure 14 , Fig. [ID] is a schematic structural diagram after forming the sacrificial layer. The sacrificial layer 310 covers the surface of the first dielectric layer 110 and fills the first conductive hole 101 and the second conductive hole 102; the first thickness h1 is greater than the second thickness h2. The first thickness h1 is the vertical distance from the surface of the sacrificial layer 310 away from the semiconductor structure 100 to the surface of the semiconductor structure 100 exposed by the first conductive hole 101, and the second thickness h2 is the vertical distance from the surface of the sacrificial layer 310 away from the semiconductor structure 100 to the surface of the semiconductor structure 100 exposed by the second conductive hole 102. The material of the sacrificial layer 310 can be photoresist. A photoresist is coated on the side of the first dielectric layer 110 away from the semiconductor body and cured to form the sacrificial layer 310. The photoresist can be a positive photoresist or a negative photoresist.

[0128] Specifically, the surface of the sacrificial layer 310 away from the semiconductor structure 100 can be flat. The first thickness h1 is greater than the second thickness h2, indicating that the thickness of the sacrificial layer 310 on the side of the first conductive hole 101 away from the semiconductor body 210 is greater than the thickness of the sacrificial layer 310 on the side of the second conductive hole 102 away from the semiconductor body 210. With this setting, when etching the sacrificial layer 310, after the sacrificial layer 310 in the second conductive hole 102 is etched completely, there is still a part of the sacrificial layer 310 remaining in the first conductive hole 101.

[0129] S350. Remove the sacrificial layer located in the second conductive hole, and part of the sacrificial layer located in the first conductive hole is retained.

[0130] Specifically, referring to Figure 15 , Figure 15Schematic diagram of the structure after removing the sacrificial layer in the second conductive hole. The sacrificial layer 310 on the side of the second conductive hole 102 away from the semiconductor body 210 and the sacrificial layer 310 on the side of the first conductive hole 101 away from the semiconductor body 210 can be etched synchronously. Since the first thickness is greater than the second thickness, after all the sacrificial layer in the second conductive hole is removed, there will still be some sacrificial layer 310 left in the first conductive hole covering the first conductive hole.

[0131] S360. Form an isolation transition layer on the side of the first dielectric layer away from the semiconductor structure.

[0132] Among them, referring to Figure 16 , Figure 16 Schematic diagram of the structure after forming the isolation transition layer. The isolation transition layer 320 is located in the second conductive hole and the first conductive hole and covers the sacrificial layer 310 in the first conductive hole.

[0133] Specifically, since the first conductive hole is filled with the sacrificial layer 310, the isolation transition layer 320 does not directly contact the semiconductor body 210 that can be exposed by the first conductive hole. Since there is no filler in the second conductive hole, the isolation transition layer 320 fills the second conductive hole. The isolation transition layer 320 can be formed by a deposition process. The isolation transition layer 320 not only covers the surface of the sacrificial layer 310 in the second conductive hole, but also covers the surface of the first dielectric layer 110 away from the semiconductor body 210.

[0134] S370. Remove the sacrificial layer and the isolation transition layer in the first conductive hole. The isolation transition layer retained in the second conductive hole serves as an isolation layer.

[0135] Specifically, since the isolation transition layer in the first conductive hole adheres to one side of the sacrificial layer, when removing the isolation transition layer on the side of the sacrificial layer, only the sacrificial layer needs to be removed. After the sacrificial layer is removed, the isolation transition layer adhering to one side of the sacrificial layer will be removed. The sacrificial layer in the first conductive hole can be removed by a wet etching process to remove the isolation transition layer on the side of the sacrificial layer at the same time. The isolation transition layer in the second conductive hole is in direct contact with the semiconductor structure. During the process of removing the sacrificial layer, the isolation transition layer in the second conductive hole does not react with the solution for removing the sacrificial layer. Continuing to refer to Figure 10 , the isolation transition layer retained in the second conductive hole is the isolation layer 140. If the isolation transition layer 320 covers the surface of the first dielectric layer 110 away from the semiconductor body 210, after step S360, the isolation transition layer 320 on the surface of the first dielectric layer 110 away from the semiconductor body 210 may still exist, but at step S390, the isolation transition layer 320 on the surface of the first dielectric layer 110 will be removed.

[0136] S380. Deposit a first conductive material on a side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive via.

[0137] Among them, the content of step S380 is the same as that of step S250. For the description of step S380, please refer to the description of step S250 for details and will not be elaborated here.

[0138] S390. Remove the isolation layer and the first conductive material outside the first conductive via.

[0139] Among them, the content of step S390 is the same as that of step S260. For the description of step S390, please refer to the description of step S260 for details and will not be elaborated here.

[0140] S391. Form a second conductive layer in the second conductive via.

[0141] Among them, the content of step S391 is the same as that of step S270. For the description of step S391, please refer to the description of step S270 for details and will not be elaborated here.

[0142] Optionally, continue to refer to Figure 10 , the thickness of the isolation layer 140 is greater than or equal to the depth of the second conductive via.

[0143] Specifically, setting the thickness of the isolation layer 140 to be greater than the depth of the second conductive via can avoid problems such as voids caused by the deposition of the first conductive material into the second conductive via and reaction with the gate in the second conductive via during the formation of the first conductive layer.

[0144] Optionally, the semiconductor structure further includes a gate structure. Forming the semiconductor structure includes the following steps:

[0145] S111. Provide a semiconductor body.

[0146] Among them, referring to Figure 17 , Figure 17 is a schematic structural diagram of a semiconductor body provided according to an embodiment of the present invention. The semiconductor body 210 includes a first surface S1 and a second surface S2 arranged oppositely; the semiconductor body 210 further includes a well region 211 and a first region 212. The first region 212 is disposed on the first surface S1, and the well region 211 is disposed on a side of the first region 212 away from the first surface S1.

[0147] Specifically, the semiconductor body 210 may further include a second region 213, a substrate 215, and an epitaxial layer 216. The epitaxial layer 216 is located on one side of the substrate 215, and the active region 214 and the well region 211 are both located on a side of the epitaxial layer 216 away from the substrate 215. The active region 214 may include the first region 212 and the second region 213, or may only include the second region 213.

[0148] In some embodiments of the present invention, the semiconductor body 210 may also include only the epitaxial layer 216. The epitaxial layer 216 is a semiconductor layer formed on the basis of the substrate 215 through a single epitaxial process. The epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0149] S112. Form a gate structure on the first surface.

[0150] Among them, continuing to refer to Figure 7 , the gate structure 220 is disposed on the first surface S1 or the gate structure 220 extends from the first surface S1 into the semiconductor body 210; the gate structure 220 includes a second dielectric layer 221 and a gate 120, and the second dielectric layer 221 is used to insulate and separate the gate 120 and the semiconductor body 210;

[0151] Specifically, the second dielectric layer 221 can be formed on the side of the epitaxial layer 216 away from the substrate 215 through a film-forming process. The second dielectric layer 221 can be selected as silicon oxide or a dielectric layer with a higher dielectric constant. The gate 120 is formed on the side of the second dielectric layer 221 away from the epitaxial layer 216.

[0152] S113. Form a first dielectric layer on the side of the gate structure away from the second dielectric layer.

[0153] Specifically, continuing to refer to Figure 9 , the first dielectric layer 110 is formed on the side of the gate 120 away from the second dielectric layer 221 through a film-forming process. The first dielectric layer 110 is used to insulate the gate 120 and the first conductive layer and the second conductive layer formed subsequently. In the embodiments of the present invention, there is no special limitation on the material of the first dielectric layer 110, and a dielectric layer with insulating properties can be selected.

[0154] Optionally, the material of the gate includes polysilicon; the first conductive material includes nickel or aluminum; the material of the second conductive layer includes titanium and titanium nitride.

[0155] Optionally, providing the semiconductor body includes: providing a silicon carbide semiconductor body or providing a gallium nitride semiconductor body.

[0156] Specifically, the MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device. The silicon carbide MOSFET power device or the gallium nitride MOSFET power device has the advantages of high breakdown voltage, low on-resistance, and high frequency, which can further improve the performance of the semiconductor device. Among them, when silicon carbide or gallium nitride is used as the semiconductor body 210, due to the high temperature resistance of silicon carbide or gallium nitride, it can also prevent particles in the semiconductor body 210 from dissolving in the conductive materials of the first conductive layer 150 and the second conductive layer 160 to generate cracks when the conductive materials of the first conductive layer 150 and the second conductive layer 160 are in contact with the semiconductor body 210, thereby further improving the filling quality of the first conductive layer 150 and the second conductive layer 160.

[0157] It should be noted that the semiconductor device provided by the embodiment of the present invention can be manufactured by the manufacturing method of the semiconductor device provided by the embodiment of the present invention.

[0158] The manufacturing method of a semiconductor device provided in this embodiment has corresponding beneficial effects to the semiconductor device provided in any embodiment of the present invention. For the technical details not elaborated in this embodiment, please refer to the semiconductor device provided in any embodiment of the present invention.

[0159] The embodiment of the present invention provides a power module, which includes a substrate and at least one semiconductor device described in any embodiment of the present invention. The substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the semiconductor device described in any embodiment of the present invention are included in this power module, and will not be elaborated here.

[0160] The embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. Therefore, the beneficial effects of the semiconductor device described in any embodiment of the present invention are included in this power conversion circuit, and will not be elaborated here.

[0161] The embodiment of the present invention further provides a vehicle, which includes a load and a power conversion circuit as described in any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are included in this vehicle, and will not be elaborated here.

[0162] It should be understood that the various forms of processes shown above can be used, with steps reordered, added or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0163] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor structure, the semiconductor structure comprising a semiconductor body and a first dielectric layer, the first dielectric layer being located on one side of the semiconductor body; The first dielectric layer comprises a first conductive via and a second conductive via; A first conductive layer, located in the first conductive via, wherein the first conductive layer is electrically connected to the semiconductor body; A second conductive layer, located in the second conductive via, wherein the second conductive layer is electrically connected to the semiconductor structure; the material of the first conductive layer is different from the material of the second conductive layer.

2. The semiconductor device according to claim 1, characterized in that, It further comprises a third conductive layer and a fourth conductive layer; The third conductive layer is located on the side of the first conductive layer away from the semiconductor body and is electrically connected to the first conductive layer; The fourth conductive layer is located on the side of the second conductive layer away from the semiconductor body and is electrically connected to the second conductive layer.

3. The semiconductor device according to claim 1, wherein, The semiconductor body comprises a first surface and a second surface which are oppositely arranged; The semiconductor body further comprises a well region, a first region and a second region, the first region is set to a first conduction type and is arranged on the first surface; the well region is set to the first conduction type and is arranged on the side of the first region away from the first surface; the second region is set to a second conduction type and is arranged on the first surface, the second region is in contact with the first region; the first conductive layer is in contact with the first region and the second region, and the second conductive layer is in contact with the gate; The semiconductor body further comprises a gate structure; wherein, the gate structure is arranged on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a second dielectric layer and a gate, and the second dielectric layer is used for insulating and spacing the gate and the semiconductor body; The semiconductor device further comprises a drain, and the drain is located on the second surface.

4. The semiconductor device according to claim 3, wherein: The material of the gate comprises polysilicon; The material of the first conductive layer comprises a compound generated by the reaction of nickel with the material of the second region or a compound generated by the reaction of aluminum with the material of the second region; The material of the second conductive layer comprises titanium and titanium nitride.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor structure comprises an edge region and a central region, and the edge region surrounds the central region; The thickness of the second dielectric layer located in the edge region is greater than the thickness of the second dielectric layer located in the central region.

6. The semiconductor device according to claim 1, wherein The semiconductor body comprises a silicon carbide semiconductor body or a gallium nitride semiconductor body.

7. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a semiconductor structure; wherein, the semiconductor structure comprises a semiconductor body and a first dielectric layer, the first dielectric layer being located on one side of the semiconductor body; the first dielectric layer comprises a first conductive via and a second conductive via; Forming a first conductive layer in the first conductive via and forming a second conductive layer in the second conductive via, wherein the first conductive layer is electrically connected to the semiconductor body; the second conductive layer is electrically connected to the semiconductor structure; the material of the first conductive layer is different from the material of the second conductive layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein The forming of the semiconductor structure comprises: Forming a semiconductor body; Form a first dielectric layer on one side of the semiconductor body; Simultaneously form a first conductive hole and a second conductive hole in the first dielectric layer; Forming a first conductive layer in the first conductive hole and a second conductive layer in the second conductive hole includes: Form an isolation layer in the second conductive hole; Deposit a first conductive material on the side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive hole; Remove the isolation layer and the first conductive material outside the first conductive hole; Form a second conductive layer in the second conductive hole.

9. The manufacturing method according to claim 8, characterized in that Simultaneously forming a first conductive hole and a second conductive hole in the first dielectric layer includes: Form a mask layer on the side of the first dielectric layer away from the semiconductor body; wherein, the mask layer includes through holes that expose the first dielectric layer; Etch the first dielectric layer using the mask layer as a mask to simultaneously form the first conductive hole and the second conductive hole.

10. The manufacturing method according to claim 8, wherein Forming an isolation layer in the second conductive hole includes: Form a sacrificial layer on the side of the first dielectric layer away from the semiconductor body, wherein the sacrificial layer covers the surface of the first dielectric layer and fills the first conductive hole and the second conductive hole; a first thickness is greater than a second thickness, the first thickness is the vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the first conductive hole, and the second thickness is the vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the second conductive hole; Remove the sacrificial layer located in the second conductive hole, and a part of the sacrificial layer in the first conductive hole is retained; Form an isolation transition layer on the side of the first dielectric layer away from the semiconductor structure, wherein the isolation transition layer is located in the second conductive hole and the first conductive hole and covers the sacrificial layer in the first conductive hole; Remove the sacrificial layer and the isolation transition layer in the first conductive hole, and the isolation transition layer retained in the second conductive hole serves as the isolation layer.

11. The manufacturing method according to claim 8, characterized in that, Forming the semiconductor structure includes: Provide a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other; the semiconductor body further includes a well region, a first region, and a second region, the first region is set to a first conduction type and is arranged on the first surface; the well region is set to a first conduction type and is arranged on the side of the first region away from the first surface; the second region is set to a second conduction type and is arranged on the first surface, and the second region is in contact with the first region; Form a gate structure on the first surface; wherein, the gate structure is arranged on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure includes a second dielectric layer and a gate, and the second dielectric layer is used to insulate and separate the gate and the semiconductor body; Form the first dielectric layer on the side of the gate structure away from the second dielectric layer; After forming the second conductive layer in the second conductive hole, further includes: Form a third conductive layer formed on a side of the first conductive layer away from the semiconductor body and electrically connected to the first conductive layer, and a fourth conductive layer formed on a side of the second conductive layer away from the semiconductor body and electrically connected to the second conductive layer; Form a drain on the second surface.

12. A power module, characterized in that, Comprising a substrate and at least one semiconductor device as described in any one of claims 1-6, the substrate being used to carry the semiconductor device.

13. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-6, the semiconductor device being electrically connected to the circuit board.

14. A vehicle, characterized in that, Comprising a load and the power conversion circuit as described in claim 13, the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

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