Cascade sensing circuitry for detecting and monitoring cracks in integrated circuits

Abstract

The invention relates to a cascade sensing circuit for detecting and monitoring cracks in an integrated circuit. Embodiments of the present disclosure provide a crack detection and monitoring system comprising: a plurality of conductive structures extending around a protective barrier formed in a non-active area of an integrated circuit (IC), where an active area of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and receiving an enable signal, where each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic being indicative of a damage to the respective structure, wherein each sensing circuit includes circuitry for selectively generating an enable signal for a next sensing circuit in the multi-stage sensing circuits.

Description

[0001] This application is a divisional application of the application with the filing date of April 12, 2021, application number 202110390089.7, and invention name "Cascaded Sensing Circuit for Detecting and Monitoring Cracks in Integrated Circuits". Technical Field

[0002] The present disclosure relates to integrated circuits, and more particularly to a cascaded sensing circuit for detecting and monitoring cracks in an integrated circuit (IC). Background Art

[0003] Processes such as wafer dicing may cause the formation and propagation of cracks in an IC. Such cracks typically form at the interface between the dielectric material and the metal wires / contacts in the IC.

[0004] ICs are often exposed to harsh, hostile, and stressful environments (e.g., automotive, aerospace, military, etc.). Fluctuations in environmental conditions (e.g., temperature, humidity, and air pressure changes) may exacerbate and activate the slow crack growth mechanism on incipient and stationary cracks (e.g., cracks formed during wafer dicing) in the IC. The continuous fluctuations in environmental conditions will enhance the growth of incipient and stationary cracks over time, potentially leading to IC failure.

[0005] Crackstop structures (e.g., an interconnected structure of metal wires and vias) have been fabricated and used to prevent crack propagation into the active region of the IC. Such crackstop structures are typically formed around the periphery of the IC and enclose the inner core (active region) of the IC.

[0006] Although effective, the crackstop structure may not always be able to prevent crack propagation into the active region of the IC. To this end, crack detection structures have been developed and placed in the active region of the IC inside the crackstop structure to detect the presence of cracks that have propagated past the crackstop structure into the active region of the IC chip. However, such crack detection structures inherently have defects because they are designed to detect cracks at too late a time and after the cracks have reached the active region of the IC chip. Summary of the Invention

[0007] One aspect of the present disclosure relates to a system for detecting and monitoring cracks in an integrated circuit (IC), comprising: a plurality of conductive structures extending around a protective barrier formed in an inactive region of the integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a multi-stage sensing circuit connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and receiving an enable signal, wherein each sensing circuit is coupled to a corresponding one of the plurality of structures, the change in the electrical characteristic indicating damage to the corresponding structure, and wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the multi-stage sensing circuit.

[0008] Another aspect relates to a method for detecting and monitoring cracks in an integrated circuit (IC), comprising: disposing a plurality of conductive structures in an inactive region of the IC, the plurality of conductive structures extending around a protective barrier formed in the inactive region of the IC, wherein an active region of the IC is enclosed within the protective barrier; coupling a multi-stage sensing circuit connected in series to the plurality of conductive structures, wherein each sensing circuit is coupled to a corresponding one of the plurality of structures; enabling a sensing circuit in an Nth stage of the multi-stage sensing circuit; monitoring, by the enabled sensing circuit, an electrical characteristic of the corresponding structure coupled to the enabled sensing circuit; and in response to detecting a change in the electrical characteristic of the corresponding structure coupled to the enabled sensing circuit, outputting, by the enabled sensing circuit, an enable signal for enabling a sensing circuit in a downstream (N + 1)th stage of the multi-stage sensing circuit.

[0009] Another aspect relates to a method, comprising: coupling a multi-stage sensing circuit connected in series to a plurality of conductive structures on an integrated circuit (IC), wherein each sensing circuit is coupled to a corresponding one of the plurality of structures; enabling a sensing circuit in an Nth stage of the multi-stage sensing circuit; monitoring, by the enabled sensing circuit, an electrical characteristic of the corresponding structure coupled to the enabled sensing circuit; and in response to detecting a change in the electrical characteristic of the corresponding structure coupled to the enabled sensing circuit, outputting, by the enabled sensing circuit, an enable signal for enabling a sensing circuit in a downstream (N + 1)th stage of the multi-stage sensing circuit.

[0010] The above and other features of the present disclosure will become apparent from the following more specific description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present disclosure will be described in detail with reference to the following drawings, where like reference numerals represent like elements, and where:

[0012] Figure 1 A plan view of an integrated circuit (IC) including a system for detecting and monitoring crack growth according to an embodiment is shown.

[0013] Figure 2 A cross-sectional view of the IC taken along line A-A according to an embodiment is shown. Figure 1 of the IC.

[0014] Figure 3 A plan view of an IC including a system for detecting and monitoring crack growth according to an embodiment is shown, where the crack detection and monitoring system includes a peripheral line (PLINE) and a jumper connection.

[0015] Figure 4 A partially enlarged plan view of the IC according to an embodiment is shown. Figure 3 of the IC.

[0016] Figure 5 A partially enlarged plan view of the IC according to an embodiment is shown. Figure 3 of the PLINE in the IC.

[0017] Figure 6 A plan view of an IC including a system for detecting and monitoring crack growth according to an embodiment is shown, where the crack detection and monitoring system includes a PLINE and a tunneling connection.

[0018] Figure 7 A partially enlarged plan view of the IC according to an embodiment is shown. Figure 6 of the IC.

[0019] Figure 8 A partially enlarged plan view of the IC according to an embodiment is shown. Figure 6 of the PLINE in the IC.

[0020] Figure 9 A partial cross-sectional view of the IC taken along line B-B according to an embodiment is shown. Figure 6 of the IC.

[0021] Figure 10 A cross-sectional view of a PLINE for guiding and capturing a propagating crack according to an embodiment is shown.

[0022] Figure 11A , 11B and 11C show examples of the crack guiding and capturing function of the PLINE according to an embodiment. Figure 10 of the PLINE.

[0023] Figure 12A flowchart showing a process for detecting and monitoring cracks in an IC according to an embodiment is shown.

[0024] Figure 13 A plan view of an IC including a crack detection and monitoring system according to other embodiments is shown.

[0025] Figure 14 A plan view of an IC including a system for detecting and monitoring the growth of cracks according to an embodiment is shown.

[0026] Figure 15 A circuit diagram of a detection and monitoring circuit including a cascaded arrangement of sensing circuits according to an embodiment is shown.

[0027] Figure 16 A circuit diagram of a detection and monitoring circuit including a cascaded arrangement of sensing circuits according to an embodiment is shown.

[0028] Note that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are only intended to depict typical aspects of the present disclosure and should not be considered as limiting the scope of the present disclosure. In the drawings, like reference numerals denote like elements between the drawings. Detailed Description

[0029] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Accordingly, the following description is merely illustrative.

[0030] Figure 1A plan view of an integrated circuit (IC) 102 including a crack detection and monitoring system 100 for detecting and monitoring the growth of cracks is shown. The IC 102 is formed on a semiconductor substrate 104 (e.g., a silicon wafer) and includes a core (hereinafter referred to as the working area 106), which is surrounded by a guard ring 110 and at least one crack stop structure 112, 114 and isolated from the non-working area 108 by the guard ring 110 and at least one crack stop structure 112, 114. The working area 106 generally includes a plurality of active and passive components (e.g., transistors, resistors, etc.). The guard ring 110 and the crack stop structures 112, 114 provide environmental protection, electrical protection (e.g., the guard ring provides electrical grounding), and / or mechanical protection for the working area 106 of the IC 102. For example, the crack stop structures 112, 114 can be employed to prevent cracks from propagating from the non-working area 108 of the IC 102 to the working area 106 of the IC 102. The guard ring 110 and the crack stop structures 112, 114 can be conventional in nature and can be provided using any currently known or later developed processes / technologies.

[0031] According to an embodiment, the crack detection and monitoring system 100 is configured to detect and monitor the growth of one or more cracks in the non-working area 108 of the IC 102 before any cracks propagate into the working area 106 of the IC 102. Generally, as Figure 1 shown, the crack detection and monitoring system 100 can include at least one conductive perimeter line (PLINE) formed in the non-working area 108 of the IC 102. For example, a first PLINE 120, a second PLINE 122, and a third PLINE 124 can be formed in the non-working area 108 of the IC 102. In this example, as Figure 1 shown, the first PLINE 120 can be formed around the outer perimeter of the guard ring 110, located between the guard ring 110 and the crack stop structure 112. The second PLINE 122 can be formed around the outer perimeter of the crack stop structure 112, located between the crack stop structure 112 and the crack stop structure 114. The third PLINE 124 can be formed around the outer perimeter of the crack stop structure 114. Although three PLINEs 120, 122, 124 are used in this embodiment, it is apparent that the crack detection and monitoring system 100 can include a greater or lesser number of PLINEs (e.g., one or more). Additionally, the PLINEs can be formed at other locations in the non-working area 108 of the IC 102, and / or multiple PLINEs can be formed adjacent to each other in the non-working area 108 of the IC 102. Various other embodiments showing such an arrangement of the PLINEs are described herein.

[0032] Each of the PLINEs 120, 122, 124 is independently coupled to the detection and monitoring circuit 126. In this and other embodiments, the functionality of the detection and monitoring circuit 126 may be provided by the illustrated IC 102 or via an external circuit (not shown). According to an embodiment, connections may be provided above and / or below one or more of the guard ring 110, crack stop structures 112, and crack stop structures 114 to couple the PLINEs 120, 122, 124 to the detection and monitoring circuit 126. To the extent that, depending on the embodiment, the integrity of the guard ring 110, crack stop structures 112, and crack stop structures 114 is not impaired or is minimally impaired by the connections (e.g., no holes are formed in or through the guard ring 110, crack stop structures 112, or crack stop structures 114).

[0033] The detection and monitoring circuit 126 is configured to sense changes in the electrical characteristics (e.g., resistance) of each individual PLINE 120, 122, 124, where a change in the electrical characteristics indicates the presence of a crack in the PLINEs 120, 122, 124. The detection and monitoring circuit 126 may also be configured to monitor the progression of the detected crack in the non-operating region 108 of the IC 102 and warn the end user of the status and / or threat level of the detected crack (e.g., the crack is about to enter the operating region 106 of the IC 102). For example, if a crack 130 (e.g., a crack formed during the dicing of the silicon wafer including the IC 102) propagates to the PLINE 124 and forms a break in / through the PLINE 124, the detection and monitoring circuit 126 may detect an increase in the resistance of the PLINE 124 (e.g., due to an open circuit in the PLINE 124) (e.g., an increase by an order of magnitude). To this extent, the detection and monitoring circuit 126 may notify the end user that the crack has entered / penetrated the PLINE 124 and is in a warning state. If the crack 130 continues to propagate through the non-operating region 108 of the IC 102 past the crack stop structure 114 and forms a break in / through the PLINE 122, the detection and monitoring circuit 126 may detect an increase in the resistance of the PLINE 122 and may notify the end user that the growth of the crack 130 is continuing. Additionally, the detection and monitoring circuit 126 may notify the end user how many days (e.g., 12 months) the IC 102 should be replaced within to avoid a failure of the IC 102. If the crack 130 propagates through and past the crack stop structure 112 and enters / passes through the PLINE 120, the detection and monitoring circuit 126 may detect an increase in the resistance of the PLINE 120 and may notify the end user that the IC 102 is about to fail and the IC 102 should be replaced immediately.

[0034] As described above, and in Figure 1As shown, the crack detection and monitoring system 100 can be configured to provide early, intermediate, and final warnings regarding a crack about to enter the working area 106 of the IC 102. In other embodiments, the crack detection and monitoring system can be configured to provide aging information. For example, the crack detection and monitoring system 100 can be calibrated so that the approximate time of failure of the IC 102 can be determined. For example, in a stable operating environment, the growth rate of a crack in a test IC 102 (e.g., X microns per year) can be determined / estimated. Based on the growth rate, the PLINEs 120, 122, 124 can be spaced a specific distance from the working area 106 of the IC 102, where the distance corresponds to different remaining working lifetimes of the IC 102. When a crack propagates to / passes a given PLINE, the detection and monitoring circuit 126 can warn the end user that the crack has reached the PLINE, and if conditions remain stable, the crack can reach another location on the IC 102 (e.g., the working area 106 of the IC 102) after a certain time. Such an alert can include, for example, "The crack has reached PLINE A, B microns from the working area of the chip. If conditions remain stable, the crack may reach the working area of the IC in approximately 16 months. Replace the IC within 12 months to avoid failure."

[0035] Figure 2 A partial cross-sectional view of the IC 102 taken along line A-A according to an embodiment is shown. As shown, crack stop structures 112, 114 can be formed using multiple metal segments 140 (e.g., vias, via bars, etc.) interconnected with each other and embedded in a dielectric material 144. The metal segments 140 can be formed in the metallization layers M1, M2,......, Mn (e.g., back-end-of-line (BEOL) metallization layers) of the IC 102. The crack stop structures 112, 114 can have a configuration similar to that shown, or can include different configurations of the metal segments 140 and / or the metal interconnects 142 (e.g., the number, shape, spacing, size, etc. of the metal segments 140 and the metal interconnects 142 can vary between the crack stop structures 112, 114). Figure 1 As shown, crack stop structures 112, 114 can be formed using multiple metal segments 140 (e.g., vias, via bars, etc.) interconnected with each other and embedded in a dielectric material 144. The metal segments 140 can be formed in the metallization layers M1, M2,......, Mn (e.g., back-end-of-line (BEOL) metallization layers) of the IC 102. The crack stop structures 112, 114 can have a configuration similar to that shown, or can include different configurations of the metal segments 140 and / or the metal interconnects 142 (e.g., the number, shape, spacing, size, etc. of the metal segments 140 and the metal interconnects 142 can vary between the crack stop structures 112, 114). Figure 2 As shown, crack stop structures 112, 114 can be formed using multiple metal segments 140 (e.g., vias, via bars, etc.) interconnected with each other and embedded in a dielectric material 144. The metal segments 140 can be formed in the metallization layers M1, M2,......, Mn (e.g., back-end-of-line (BEOL) metallization layers) of the IC 102. The crack stop structures 112, 114 can have a configuration similar to that shown, or can include different configurations of the metal segments 140 and / or the metal interconnects 142 (e.g., the number, shape, spacing, size, etc. of the metal segments 140 and the metal interconnects 142 can vary between the crack stop structures 112, 114).

[0036] Each of the PLINEs 120, 122, 124 may include multiple conductive metal segments 150 interconnected by a plurality of conductive metal interconnections 152 (e.g., vias, via bars, etc.) and embedded in a dielectric material 144. The PLINEs 120, 122, 124 (and other PLINEs disclosed herein) may be formed together with the crack stop structures 112, 114 during the same processing steps and may be formed of any suitable metal including, for example, copper, tungsten, aluminum, silver, gold, other metals, or alloys thereof. The metal segments 150 may also be formed in the metallization layers M1, M2, ..., Mn of the IC 102. Similar to the crack stop structures 112, 114, the PLINEs 120, 122, 124 may have similar or different configurations of metal segments 150 and / or metal interconnections 152 (e.g., the number, shape, spacing, size, etc. of the metal segments 150 and metal interconnections 152 may vary between the PLINEs 120, 122, 124).

[0037] According to an embodiment, the PLINE may be coupled to the detection and monitoring circuit 126 via a connection (e.g., a straddling connection) extending above one or more of the guard rings 110, crack stop structures 112, and crack stop structures 114 or a connection (e.g., a tunneling connection) extending below. For example, an IC 102 of a crack detection and monitoring system 200 according to an embodiment including conductive PLINEs 220, 222, 224 and conductive straddling metal connections 230, 232, 234 is shown in Figures 3 - 5 simultaneous reference. Figure 3 A plan view of the IC 102 is shown. Figure 4 Shown is Figure 3 a partially enlarged plan view of the IC. Figure 5 Shown is a partial cross-sectional view along the length of a PLINE (e.g., Figure 3 PLINE 220 in). Although three PLINEs 220, 222, 224 are used in this embodiment, it is apparent that the crack detection and monitoring system 200 may include a greater or lesser number of PLINEs (e.g., one or more). Additionally, the PLINEs may be formed at other locations in the non-operating region 108 of the IC 102, and / or multiple PLINEs may be formed adjacent to each other in the non-operating region 108 of the IC 102.

[0038] With Figure 1Similar to the crack detection and monitoring system 100 shown, the crack detection and monitoring system 200 is configured to detect and monitor the growth of one or more cracks 130 in the non-operating area 108 of the IC 102 before any cracks propagate into the operating area 106 of the IC 102. Generally, the crack detection and monitoring system 200 may include at least one PLINE formed in the non-operating area 108 of the IC 102. For example, as Figure 3 shown, a first PLINE 220, a second PLINE 222, and a third PLINE 224 may be formed in the non-operating area 108 of the IC 102 and may be independently coupled to the detection and monitoring circuit via respective jumper connections.

[0039] The first PLINE 220 may be formed around the outer perimeter of the guard ring 110, located between the guard ring 110 and the crack stop structure 112. The second PLINE 222 may be formed around the outer perimeter of the crack stop structure 112, located between the crack stop structure 112 and the crack stop structure 114. The third PLINE 224 may be formed around the outer perimeter of the crack stop structure 114. Opposite ends 240 of the first PLINE 220 may be coupled to the detection and monitoring circuit 126 via a jumper metal connection 230. The jumper metal connection 230 may extend over the guard ring 110 and be electrically isolated from the guard ring 110. Opposite ends 242 of the second PLINE 222 may be coupled to the detection and monitoring circuit 126 via a jumper metal connection 232. As shown, the jumper metal connection 232 may extend over the crack stop structure 112, the PLINE 220, and the guard ring 110 and be electrically isolated therefrom. Opposite ends 244 of the third PLINE 224 may be coupled to the detection and monitoring circuit 126 via a jumper metal connection 234. The jumper metal connection 234 may extend over the crack stop structure 114, the crack stop structure 112, the PLINE 222, the PLINE 220, and the guard ring 110 and be electrically isolated therefrom. For example, one or more layers of dielectric material 144 and / or the like may be used to provide electrical isolation.

[0040] According to an embodiment, a cross-sectional view along Figure 3 the end of the PLINE 220 in Figure 5Shown in. PLINE 222 and 224 can each have a configuration similar to or different from that of PLINE 220. As shown, PLINE 220 can include a plurality of conductive metal portions 250, which can be daisy-chained (e.g., stitched) together by an alternating sequence of lower conductive metal connectors and upper conductive metal connectors 252, 254. The metal connectors 252, 254 can have similar or different lengths. The lengths of the metal connectors 252, 254 can affect the crack detection accuracy of PLINE 220. For example, when using shorter metal connectors 252, 254, a larger number (e.g., higher density) of metal portions 250 can be daisy-chained together. Generally, the minimum length of the metal connectors 252, 254 can be controlled by the processing rules for forming IC 102. For example, the lithography tool used to fabricate the metal connectors 252, 254 in the corresponding metallization layer of IC 102 may only be able to produce metal lines of a certain minimum length in a specific dielectric layer.

[0041] According to an embodiment, the lower metal connector 252 can be formed in, for example, the lower BEOL metallization layer (e.g., the M1 metallization layer shown) of IC 102. The upper metal connector 254 can be formed in the upper metallization layer of IC 102. According to an embodiment, the lengths of the metal connectors 252, 254 can be, for example, in the range of tens of nanometers to several micrometers (e.g., depending on manufacturing limitations and / or other factors). As Figure 5 shown, a crack 130 propagating to / through PLINE 220 can form a break in / through one or more of the metal portions 250, which can be sensed by the detection and monitoring circuit 126 (e.g., when the resistance of PLINE 220 increases).

[0042] The metal portion 250 can include multiple layers of conductive metal segments 260 interconnected by a plurality of conductive metal interconnections 262 (e.g., vias, via bars, etc.) and embedded in a dielectric material 144. The metal segments 262 can be formed in the metallization layer (e.g., the metallization layers M2 to M5 shown) of IC 102. One or more metal interconnections 262 can also be used to couple the metal portion 250 to the corresponding lower and upper metal connectors 252, 254. The upper metal connector 254 located at the end 240 of PLINE 220 can be coupled to the jumper metal connection 230 through the metal interconnection 262.

[0043] As described above, according to an embodiment, the PLINE can be coupled to the detection and monitoring circuit 126 via a connection (e.g., a jumper connection) extending above one or more of the guard ring 110, the crack stop structure 112, and the crack stop structure 114 or a connection (a tunneling connection) extending below. The IC 102 including the crack detection and monitoring system 300 having a tunneling connection according to an embodiment is shown in Figures 6 - 9 which is simultaneously referenced. For example, Figure 6 shows a plan view of the IC 102 including a plurality of independent conductive PLINEs 320, 322, 324 and conductive tunneling connections 330, 332, 334. Figure 7 shows Figure 6 a partially enlarged plan view of the IC 102 of Figure 8 shows a partial cross-sectional view along the length of the PLINE (e.g., PLINE 320) in Figure 6 . Figure 9 shows a partial cross-sectional view along the line B-B of the crack detection and monitoring system 300 taken in Figure 6 . Although three PLINEs 320, 322, 324 are used in this embodiment, it is obvious that the crack detection and monitoring system 300 can include a greater or lesser number of PLINEs (e.g., one or more). Additionally, the PLINEs can be formed at other locations in the non-active region 108 of the IC 102, and / or a plurality of PLINEs can be formed adjacent to each other in the non-active region 108 of the IC 102.

[0044] Similar to the crack detection and monitoring systems 100, 200 shown in Figure 1 and 3 , the crack detection and monitoring system 300 is configured to detect and monitor the growth of cracks in the non-active region 108 of the IC 102 before any cracks propagate into the active region 106 of the IC 102. Generally, the crack detection and monitoring system 300 can include at least one PLINE formed in the non-active region 108 of the IC 102. For example, as shown in Figure 6 , a first PLINE 320, a second PLINE 322, and a third PLINE 324 can be formed in the non-active region 108 of the IC 102.

[0045] The first PLINE 320 can be formed around the outer perimeter of the guard ring 110, located between the guard ring 110 and the crack stop structure 112. The second PLINE 322 can be formed around the outer perimeter of the crack stop structure 112, located between the crack stop structure 112 and the crack stop structure 114. The third PLINE 324 can be formed around the outer perimeter of the crack stop structure 114.

[0046] Opposite ends 340 of the first PLINE 320 may be coupled to the detection and monitoring circuit 126 via a conductive semiconductor tunneling connection 330. The tunneling connection 330 may extend under the guard ring 110 and be electrically isolated therefrom. Opposite ends 342 of the second PLINE 322 may be coupled to the detection and monitoring circuit 126 via a semiconductor tunneling connection 332. As shown, the tunneling connection 332 may extend under the crack stop structure 112 and the guard ring 110 and be electrically isolated therefrom. Opposite ends 344 of the third PLINE 324 may be coupled to the detection and monitoring circuit 126 via a semiconductor tunneling connection 334. The tunneling connection 334 may extend under the crack stop structure 114, the crack stop structure 112, and the guard ring 110 and be electrically isolated therefrom. According to an embodiment, the tunneling connection 344 may also be electrically isolated from the PLINEs 320, 322, and the tunneling connection 342 may also be electrically isolated from the PLINE 320. As described below, the tunneling connections 340, 342, 344 may be formed using doped regions of the substrate 104 of the IC 102.

[0047] A cross-sectional view along the Figure 6 ends of the PLINE 320 according to an embodiment is shown in Figure 8 . The PLINEs 322 and 324 may each have a configuration similar to or different from that of the PLINE 320. As shown, the PLINE 320 may include a plurality of conductive metal portions 350 that may be daisy-chained together by an alternating sequence of lower conductive metal connectors 352 (only one is shown) and upper conductive metal connectors 354. The metal connectors 352, 354 may have similar or different lengths. The lengths of the metal connectors 352, 354 may affect the crack detection accuracy of the PLINE 320. For example, when shorter metal connectors 352, 354 are used, a larger number (e.g., higher density) of metal portions 350 may be daisy-chained together. Generally, the minimum length of the metal connectors 352, 354 may be controlled by the processing rules used to form the IC 102. For example, the lithography tool used to fabricate the metal connectors 352, 354 in the corresponding metallization layers of the IC 102 may only be able to produce metal lines of a certain minimum length in a particular dielectric layer. According to an embodiment, the lower metal connector 352 may be formed in, for example, the lower BEOL metallization layer (e.g., the M1 metallization layer as shown) of the IC 102. The upper metal connector 354 may be formed in the upper metallization layer of the IC 102. According to an embodiment, the lengths of the metal connectors 352, 354 may be, for example, in the range of tens of nanometers to several micrometers (e.g., depending on manufacturing limitations and / or other factors).

[0048] The metal portions 350 may include multiple layers of conductive metal segments 360 interconnected by a plurality of conductive metal interconnects 362 (e.g., vias, via bars, etc.) and embedded in the dielectric material 144. The metal segments 362 may be formed in a metallization layer (e.g., BEOL metallization layers M1-M5 as shown) of the IC 102. One or more metal interconnects 262 may also be used to couple adjacent metal portions 350 to corresponding upper metal connectors 352. The lowermost metal segment 360 (e.g., M1 metallization layer) of at least one of the metal portions 350 may be coupled to the doped region 356 of the semiconductor substrate 104 via at least one metal interconnect 362 and a doped semiconductor interconnect 364.

[0049] like Figure 8 As shown, a doped semiconductor region 356 may be formed in a doped portion 358 of a semiconductor substrate 104 of an IC 102. At least one doped semiconductor interconnect 364 may be formed over the doped semiconductor region 356 to couple a metal portion 350 located at an end 340 of a PLINE 320 to a tunneling connection 330, which in this embodiment is formed by a doped semiconductor well formed in the doped portion 358 of the semiconductor substrate 104. The metal portion 350 may be coupled to the doped semiconductor interconnect 364 using one or more metal interconnects 362. The doping of the semiconductor region 356, the semiconductor interconnect 364, and the tunneling connection 330 allows an electrical signal to pass when an electrical characteristic (e.g., resistance) of the PLINE 320 is measured. The semiconductor region 356 and the semiconductor interconnect 364 may be coupled to the doped semiconductor well 364 as shown in FIG. Figure 8 Shown is n + doped, or in other embodiments p + Doped. For example, doping may be provided using ion implantation or any other suitable process.

[0050] When Figure 8 As shown, use n + Doped semiconductor region 356 (having n + When doping the semiconductor interconnect 364), an n-doped region 358 may be formed in the semiconductor substrate 104 of the IC 102. + Doped semiconductor region 356. Figure 8 As further shown, in this doping scheme, n near the end 340 of PLINE 320 + The doped semiconductor region 356 may be coupled to the detection and monitoring circuit 126 via a tunnel connection 330 formed using an n-doped semiconductor well (n-doped well) formed in a p-doped region 358 of the semiconductor substrate 104 of the IC 102 .

[0051] According to other embodiments, p +doped semiconductor regions and p + Doped semiconductor interconnects to replace n + The doped semiconductor region 356 and n + Doped semiconductor interconnect 364. p + The doped semiconductor region may be formed on the semiconductor substrate 104 of the IC 102. + In addition, the p-type doped region near the end 340 of the PLINE 320 + The doped semiconductor region may be coupled to the detection and monitoring circuit 126 via a p-doped semiconductor well tunneling connection 330 formed in an n-doped region of the substrate 104 of the IC 102 .

[0052] Figure 9 According to an embodiment, Figure 6 As shown in the figure, an n-doped semiconductor well tunnel connection 332 (hereinafter referred to as n-doped tunnel connection 332) can be formed in the p-doped region 358 of the substrate 104 of the IC 102 to connect the n-doped semiconductor well tunnel connection 332 located near the end 342 of the PLINE 322 via the I / O connection 370. + Doped semiconductor region 356 is coupled to detection and monitoring circuit 126. PLINE 322 may be coupled to a semiconductor region 356 via at least one n + doped semiconductor interconnect 364 and coupled to n + doped semiconductor region 356. At least one n + Doped semiconductor interconnect 364 may also be used to couple n-doped tunnel connection 332 to I / O connection 370 .

[0053] The crack stop structure 114 may be positioned above the p-doped region 358 of the semiconductor substrate 104. The crack stop structure 114 may use at least one n-doped region 358. + The doped semiconductor interconnect 364 is coupled to the p-doped region 358. The bias applied to the p-doped region 358 can be used to reverse bias the p-doped region 358 and at least one n-doped region 358. + The pn junction between the semiconductor interconnects 364 is doped to electrically isolate the crack stop structure 114 from the p-doped region 358 .

[0054] The n-doped tunneling connection 332 extends beneath and is electrically isolated from the crack stop structure 112 and the guard ring 110. At least one p-doped tunneling connection 332 may be used. + Doped semiconductor interconnect 366 couples crack stop structure 112 to n-doped tunnel connection 332. Similarly, guard ring 110 may use at least one p-doped semiconductor interconnect 366. + doped semiconductor interconnect 366 is coupled to n-doped tunnel connection 332. +The reverse-biased pn junction between the doped semiconductor interconnect 366 and the n-doped tunneling junction 332 electrically isolates the crack stop structure 112 and the guard ring 110 from the n-doped tunneling junction 332.

[0055] According to other embodiments, any crack detection and monitoring system described herein can utilize both types of connection structures to electrically connect the PLINE to the detection and monitoring circuit 126. For example, a first PLINE in a crack detection and monitoring system can be electrically connected to the detection and monitoring circuit 126 using a metal jumper connector, a second PLINE in the same crack detection and monitoring system can be electrically connected to the detection and monitoring circuit 126 using a doped semiconductor tunneling connector, and a third PLINE in the same crack detection and monitoring system can be connected using both a jumper connector and a tunneling connector simultaneously.

[0056] Any and / or all PLINEs described herein can be configured to direct and capture cracks propagating through the non-active region 108 of the IC 102. For example, a cross-sectional view of a PLINE 400 for directing and capturing cracks according to an embodiment is shown in Figure 10 FIG. As shown, the PLINE 400 includes first and second conductive interconnect metal portions 402, 404. The metal portion 404 can include multiple conductive metal segments 406 interconnected using a high-density arrangement of conductive metal interconnects 408 (e.g., vias, via bars, etc.) and embedded in a dielectric material 144. The metal portion 402 can also include multiple conductive metal segments 406 interconnected using a high-density arrangement of metal interconnects 408 and embedded in the dielectric material 144. Additionally, a low-density arrangement of conductive metal interconnects 410 (e.g., vias, via bars, etc.) can be used to interconnect multiple (two in this example) metal segments 406 in the metal portion 402. The metal interconnects 410 form a weakened region 412 in the metal portion 402, which effectively attracts cracks propagating towards the PLINE 400. The elongated metal segments 406' in the metal portion 402 can also be coupled to the elongated metal segments 406' in the metal portion 404 via the metal interconnects 410. The metal portion 404 can further include a capture region 414 that has been strengthened to capture / slow down a crack after the crack has propagated through the weakened region 412 in the metal portion 402. The capture region 414 can be strengthened, for example, by providing a set of larger / stronger metal interconnects 416 (e.g., wider / thicker than the metal interconnects 408) and / or by embedding the set of metal interconnects 416 (or even the entire metal portion 404) in a stronger dielectric material 418 that is less prone to cracking (e.g., compared to the dielectric material 144).

[0057] According to embodiments, the high-density arranged metal interconnects 408 and the low-density arranged metal interconnects 410 may be provided in several different ways. For example, the metal interconnects 408, 410 may be arranged in the same pattern, but the metal interconnect 408 may be thicker than the metal interconnect 410. As another example, the metal interconnects 408, 410 may have the same thickness, but the metal interconnect 408 may be arranged more densely than the metal interconnect 410.

[0058] Figure 11A , 11B and 11C show the Figure 10 An example of the crack guidance and capture capabilities of the PLINE 400. Figure 11A In FIG. 4 , a crack 130 propagating through the inactive region 108 of the IC is attracted toward the weakened region 412 provided by the metal interconnect 410 in the metal portion 402. Figure 11B In FIG. 4 , crack 130 passes through the low-density arranged metal interconnects 410 in metal portion 402 toward capture region 414. Figure 11C In the embodiment of the present invention, the crack is captured / slowed down by the metal interconnect 416 in the capture region 414 and its energy is dispersed. The fracture in the metal portion 402 causes an increase in the resistance of the PLINE 400, which is sensed and determined by the detection and monitoring circuit 126. If the capture region 414 is not used, the crack 130 can be captured / slowed down by the high density arrangement of the metal interconnect 408 in the metal portion 404.

[0059] A flowchart of a process for detecting and monitoring cracks in an IC according to an embodiment is shown in FIG. Figure 12 In process A1, the electrical characteristics (e.g., resistance) of multiple PLINEs located in the non-operating area of ​​the IC are monitored (continuously or periodically) by the detection and monitoring circuit. If the detection and monitoring circuit senses a change in the electrical characteristics of a PLINE, indicating that a crack has propagated to / through the PLINE ("Yes" at process A2), the process goes to process A3. Otherwise ("No" at process A2), the process returns to process A1.

[0060] In process A3, the detection and monitoring circuitry provides an alert (e.g., email, text message, system message, etc.) to the end user indicating that a crack failure has occurred at the PLINE. The nature of the alert may depend, for example, on the location of the PLINE in the non-operating area of ​​the IC (e.g., the closer the PLINE is to the operating area of ​​the IC, the stronger the alert). The flow then returns to process A1.

[0061] Figure 13Shows a plan view of the IC 102 including a crack detection and monitoring system 500 according to other embodiments. Similar to the crack detection and monitoring systems 100, 200, 300, the crack detection and monitoring system 500 may include a conductive PLINE 502 formed around the outer periphery of the crack stop structure 114, and a conductive PLINE 504 formed around the outer periphery of the crack stop structure 112 and located between the crack stop structure 112 and the crack stop structure 114. However, different from the crack detection and monitoring systems 100, 200, 300, the crack detection and monitoring system 500 may include multiple (e.g., > 2) adjacent conductive PLINEs formed around the outer periphery of the crack stop structure 110 and located between the crack stop structure 110 and the crack stop structure 112. For example, as Figure 13 shown, five PLINEs 506, 508, 510, 512, 514 may be provided between the crack stop structure 110 and the crack stop structure 112. Each of the PLINEs 502, 504, 506, 508, 510, 512, 514 may be discontinuous (or may be continuous) as described above, and may be coupled to the detection and monitoring circuit 126 via corresponding jumper connections or tunneling connections.

[0062] In operation, the detection and monitoring circuit 126 may be configured to provide a first type of alert when a crack propagates to / through the PLINEs 502, 504, and a second type of alert when a crack propagates to / through the PLINEs 506, 508, 510, 512, 514. For example, the detection and monitoring circuit 126 may be configured to provide an initial alert to the end user when a crack propagates to / through the PLINEs 502, 504. Such alerts may include, for example, "Crack damage has occurred in the IC" and "The crack continues to propagate towards the interior of the IC".

[0063] The crack detection and monitoring system 500 can also be configured to provide aging information regarding the expected remaining life of the IC 102 (e.g., approximate time to failure) when a crack propagates to / through the PLINEs 506, 508, 510, 512, 514. To achieve this function, the growth rate of the crack can be determined in the test IC 102. Based on this growth rate, the PLINEs 506, 508, 510, 512, 514 can be spaced a specific distance from the working area 106 of the IC 102, where each distance represents a different remaining working life of the IC 102. When a crack propagates to / through a given PLINE, the detection and monitoring circuit 126 can warn the end user that the crack has reached that PLINE and that, if the conditions remain the same, the crack may reach the working area of the IC 102 after a certain number of days / months / years (e.g., 18 months). The alert can include, for example, "The crack is approaching the working area of the IC. The IC is expected to fail in approximately 18 months." When the crack propagates to / through another PLINE that is closer to the working area 106 of the IC 102, the detection and monitoring circuit 126 can warn the end user that the crack has reached that PLINE and that, if the conditions remain the same, the crack may reach the working area 106 of the IC 102 after a certain number of days / months / years (e.g., 12 months).

[0064] According to an embodiment, the detection and monitoring circuit can include at least one sensing circuit for detecting and monitoring the resistance of at least one PLINE. For example, the detection and monitoring circuit can include a series (cascaded) arrangement of multi-stage sensing circuits, where each sensing circuit is configured to sense the resistance of a corresponding PLINE. When a crack propagates through the IC, the enable signal generated by the sensing circuit is used to activate the next sensing circuit in the multi-stage sensing circuit.

[0065] Figure 14 Shown is a detection and monitoring circuit 602 according to an embodiment, which can be used in a crack detection and monitoring system 600 including multiple PLINEs (e.g., PLINE 604, PLINE 606, PLINE 608), where PLINE 608 is closer to the working area 106 of the IC 102 than PLINE 606, and where PLINE 606 is closer to the working area 106 than PLINE 604. As Figure 14 shown, the crack detection and monitoring circuit 602 can include N (in this example, N = 3) stages of cascaded sensing circuits. For example, the detection and monitoring circuit 602 can include a first-stage sensing circuit 610 for sensing the resistance R PL0 of PLINE 604, a second-stage sensing circuit 612 for sensing the resistance R PL1 of PLINE 606, and a third-stage sensing circuit 614 for sensing the resistance R of PLINE 608PL2 The third - stage sensing circuit 614. The sensing circuits 610, 612, 614 can be arranged in series (e.g., cascaded) such that the sensing circuit 612 is enabled only after the sensing circuit 610 has detected a crack at PLINE 604. Similarly, the sensing circuit 614 is enabled only after the sensing circuit 612 has detected a crack at PLINE 606. As referenced Figure 14 simultaneously with Figure 15 FIG. 700 shows a circuit diagram of a detection and monitoring circuit 602 including a cascaded arrangement of sensing circuits 610, 612, 614 according to an embodiment.

[0066] In operation, the circuit 700 is configured to output a plurality of different flags indicating the presence and growth of the crack 130 to the operating area 106 of the IC 102. That is, each of the cascaded sensing circuits 610, 612, 614 is configured to set a corresponding flag when the crack 130 propagates closer to the operating area 106 of the IC 102. Corresponding alerts can be provided to the end - user of the IC102 in response to the flags.

[0067] The first - stage sensing circuit 610 receives an input voltage VIN0 generated by a first - stage voltage divider 702. Similarly, the second - stage sensing circuit 612 receives an input voltage VIN1 generated by a second - stage voltage divider 704, and the third - stage sensing circuit 614 receives an input voltage VIN2 generated by a third - stage voltage divider 706.

[0068] The first - stage voltage divider 702 is formed by a reference resistor R0 and a resistor R representing the resistance of PLINE 604 PL0 According to an embodiment, PLINE 604 can have a resistance R of about 10 kΩ when intact PL0 and can have a resistance R greater than 1 MΩ when damaged by a crack PL0 . The resistance of the resistor R0 is much larger than the resistance R of PLINE 604 when intact PL0 . For example, the resistor R0 can have a resistance of about 100 kΩ. VIN0 is the voltage at node 708 of the voltage divider 702 between the resistor R0 and the resistor R PL0 .

[0069] The drain of the n - type field - effect transistor (NFET) N0 is coupled to node 708. The source of the NFET N0 is coupled to the ground voltage VSS (e.g., 0 V). The drain of the p - type field - effect transistor (PFET) P0 is coupled to R0, and the source of the PFET P0 is coupled to the supply voltage VDD (e.g., 1 V).

[0070] The first-stage sensing circuit 610 can be selectively enabled by the enable signal ENN. Additionally, the enable signal ENN is applied to the gates of NFET N0 and PFET P0 of the first-stage voltage divider 702. When the enable signal ENN = 1V (e.g., VDD), the first-stage sensing circuit 610 is disabled, and the first-stage sensing circuit 610 consumes no current (only nA leakage current). Further, when the enable signal ENN = 1V, PFET P0 is turned off and NFET N0 is turned on, pulling the voltage VIN0 at node 708 to ground (e.g., VIN0 = 0V). Thus, when ENN = 1V, the first-stage sensing circuit 610 consumes no power, and no DC current flows through the first-stage voltage divider 702.

[0071] Each sensing circuit 610, 612, 614 receives the reference voltage VREF. VREF can be provided by a voltage divider 720 (formed by the two resistors RR0 and RR1 shown in Figure 15 ), using a bandgap voltage reference circuit, or by any other suitable means. Assuming RR0 = RR1, the voltage divider 720 is configured to output the reference voltage VREF = VDD / 2 (e.g., VREF = ~0.5V).

[0072] When ENN = 0, the first-stage sensing circuit 602 is enabled, NFET N0 is turned off, and PFET P0 is turned on. When enabled (e.g., ENN = 0V), the first-stage sensing circuit 610 is configured to compare the voltage VIN0 and VREF and generate the enable signal CRACKN_S0 provided to the second-stage voltage divider 704 and the second-stage sensing circuit 612. The first-stage sensing circuit 610 can also generate a flag F0 indicating the state of the PLINE 604.

[0073] When intact, the PLINE 604 can have an equivalent resistance R of 10k ohms PL0 . Thus, when ENN = 0V (enabling the first-stage sensing circuit 610), the voltage VIN0 output by the first-stage voltage divider 702 at node 708 is:

[0074] VDD*(R PL0 / (R PL0 +R0)) = VDD*(10k / (10k + 100k)) = ~0.009*VDD = ~0V.

[0075] In response, since VIN0 is less than the reference voltage VREF, the first-stage sensing circuit 610 sets CRACKN_S0 = 1V, which disables the second-stage sensing circuit 612, and sets F0 = 0V, indicating that the PLINE 604 is intact.

[0076] If the PLINE 604 is damaged by a crack, its resistance R PL0 may increase by several orders of magnitude (e.g., from 10 kOhms to >1 MOhms). In this case, the voltage VIN0 output by the first-stage voltage divider 702 at node 708 is:

[0077] VDD*(R PL0 / (R PL0 +R0)) = VDD*(1M / (1M + 100k)) = ~0.9*VDD = ~VDD.

[0078] In response, since VIN0 is now greater than the reference voltage VREF, the first-stage sensing circuit 610 sets CRACKN_S0 = 0V, which enables the second-stage sensing circuit 612 and sets F0 = 1V, indicating that the PLINE 604 is damaged. According to an embodiment, the flag F0 is the inverse of the enable signal CRACKN_S0.

[0079] The second-stage voltage divider 704 is formed by a reference resistor R1 and a resistor R PL1 representing the resistance of the PLINE 606. The third-stage voltage divider 706 similarly includes a reference resistor R2 and a resistor R PL2 representing the resistance of the PLINE 608. The resistances R PL1 、R PL2 of the PLINEs 606, 608 when intact can be approximately 10 kOhms, and the resistances when damaged by a crack can be greater than 1 MOhms. The resistances of the resistors R1, R2 can be approximately 100 kOhms. VIN1 is the voltage at node 710 of the second-stage voltage divider 704. VIN2 is the voltage at node 712 of the third-stage voltage divider 706.

[0080] In the second-stage voltage divider 704, the drain and source of the NFET N1 are coupled to node 710 and ground respectively. The drain and source of the PFET P1 are coupled to the resistor R1 and VDD respectively.

[0081] The second-stage sensing circuit 612 can be selectively enabled by the enable signal CRACKN_S0 generated by the first-stage sensing circuit 610. In addition, the enable signal CRACKN_S0 is applied to the gates of the NFET N1 and PFET P1 of the second-stage voltage divider 704. When the enable signal CRACKN_S0 = 1V (indicating that the PLINE 604 is intact), the second-stage sensing circuit 612 is disabled and does not consume any current. Additionally, when the enable signal CRACKN_S0 = 1V, the PFET P1 is turned off and the NFET N1 is turned on, pulling the voltage VIN1 at node 710 to ground (e.g., VIN1 = 0V).

[0082] When the enable signal CRACKN_S0 = 0V (indicating that PLINE 604 is damaged), the second-stage sensing circuit 612 is enabled, NFET N1 is turned off, and PFET P1 is turned on. When enabled (e.g., CRACKN_0 = 0V), the second-stage sensing circuit 612 is configured to compare the voltage VIN1 and VREF, and generate an enable signal CRACKN_S1 for the third-stage sensing circuit 614. The second-stage sensing circuit 612 can also generate a flag F1 (e.g., the inversion of CRACKN_S1) indicating the state of PLINE 606.

[0083] When intact, PLINE 606 can have an equivalent resistance R of 10 kΩ PL1 . In this case, when CRACKN_S0 = 0V, the voltage VIN1 output by the second-stage voltage divider 704 at node 710 is:

[0084] VDD*(R PL1 / (R PL1 +R1)) = VDD*(10k / (10k + 100k)) = ~0.009*VDD = ~0V.

[0085] In response, since VIN1 is less than the reference voltage VREF, the second-stage sensing circuit 612 sets CRACKN_S1 = 1V, which disables the third-stage sensing circuit 614, and sets F1 = 0V, indicating that PLINE 606 is intact.

[0086] If PLINE 606 has been damaged by a crack, its resistance RPL1 increases by several orders of magnitude (e.g., from 10 kΩ to >1 MΩ). Therefore, the voltage VIN1 output by the second-stage voltage divider 704 at node 710 is:

[0087] VDD*(R PL1 / (R PL1 +R1)) = VDD*(1M / (1M + 100k)) = ~0.9*VDD = ~VDD.

[0088] In response, since VIN1 is now greater than the reference voltage VREF, the second-stage sensing circuit 612 sets CRACKN_S1 = 0V, which enables the third-stage sensing circuit 614, and sets F1 = 1V, indicating that PLINE 606 is damaged.

[0089] In the third-stage voltage divider 706, the drain and source of NFET N2 are coupled to node 712 and ground, respectively. The drain and source of PFET P2 are coupled to resistor R2 and VDD, respectively.

[0090] The third-stage sensing circuit 614 can be selectively enabled by an enable signal CRACKN_S1 generated by the second-stage sensing circuit 612. The enable signal CRACKN_S1 can also be applied to the gates of NFET N2 and PFET P2 of the third-stage voltage divider 706. When the enable signal CRACKN_S1 = 1V (indicating that the PLINE 606 is intact), the third-stage sensing circuit 614 is disabled and does not consume any current, the PFET P2 is turned off, and the NFET N2 is turned on, thereby pulling the voltage VIN2 at the node 712 to ground (e.g., VIN2 = 0V).

[0091] When the enable signal CRACKN_S1 = 0V (indicating that the PLINE 606 is damaged), the third-stage sensing circuit 613 is enabled, the NFET N2 is turned off, and the PFET P2 is turned on. The third-stage sensing circuit 614 compares the voltage VIN2 and VREF, and generates an enable signal CRACKN_S2 and a flag F2 indicating the state of the PLINE 608 (e.g., the inversion of CRACKN_S2). Since in the described embodiment, the third-stage sensing circuit 614 is the last sensing circuit in the cascaded sensing circuit, the enable signal CRACKN_S2 is not used to enable the subsequent sensing circuit.

[0092] When intact, the PLINE 608 can have an equivalent resistance R of 10 kΩ PL2 . In this case, when CRACKN_S1 = 0V, the voltage VIN2 output by the third-stage voltage divider 706 at the node 712 is:

[0093] VDD*(R PL2 / (R PL2 +R2)) = VDD*(10k / (10k + 100k)) = ~0.009*VDD = ~0V.

[0094] Since VIN2 is less than the reference voltage VREF, the third-stage sensing circuit 614 sets CRACKN_S2 = 1V, and sets F2 = 0V, indicating that the PLINE 608 is intact.

[0095] If the PLINE 608 has been damaged by a crack, its resistance R PL2 increases by several orders of magnitude (e.g., from 10 kΩ to >1 MΩ). Therefore, the voltage VIN2 output by the third-stage voltage divider 706 at the node 712 is:

[0096] VDD(R PL2 / (R PL2+R2)) = VDD * (1M / (1M + 100k)) = ~0.9 * VDD = ~VDD.

[0097] In response, since VIN2 is now greater than the reference voltage VREF, the third-stage sensing circuit 614 sets CRACKN_S2 = 0V and sets F2 = 1V, indicating that the PLINE 608 is damaged.

[0098] Figure 16 A more detailed circuit diagram 800 of the detection and monitoring circuit 602 including a cascaded arrangement of sensing circuits 610, 612, 614 according to an embodiment is shown. As Figure 16 shown, in the first-stage sensing circuit 6, the enable signal ENN is coupled to the gate of the PFET T1. The source of the PFET T1 is coupled to VDD, and the drain of the PFET T1 is coupled to the sources of the PFET T2 and PFET T3.

[0099] The input voltage VIN0 at the node 708 of the first-stage voltage divider 702 is coupled to the gate of the NFET T4. The source of the NFET T4 is grounded, and the drain of the NFET T4 is coupled to the drain of the PFET T2 and the gates of the PFETS T2 and T3. The drains of the PFET T3 and the NFET T5 are connected at the node 802. The gate of the NFET T5 is coupled to the reference voltage VREF.

[0100] When ENN = 0V, the enable signal ENN enables the sensing circuit 610, thereby turning on the PFET T1. When ENN = 1V (e.g., VDD), the PFET T1 is turned off and the sensing circuit 610 is disabled. In addition, when ENN = 1V, the reference voltage VREF with a value of ~VDD / 2 turns on the NFET T5 and pulls the voltage OUT0 at the node 802 to ground (0V).

[0101] The voltage OUT0 at the node 802 is passed through the first inverter 804 to generate the enable signal CRACKN_S0, which is transmitted to the second-stage voltage divider 704 and the second-stage sensing circuit 612. The enable signal CRACKN_S0 is also passed through the second inverter 806 to provide the flag F0. When ENN = 1V, OUT0 = 0V, CRACKN_S0 = 1V, and F0 = 0V.

[0102] The enable signal ENN = 0V enables both the first - stage sensing circuit 610 and the first - stage voltage divider 702 simultaneously. The first - stage voltage divider 702 outputs the input voltage VIN0 at node 708. The NFET T4 is gated by the input voltage VIN0, and based on the integrity (intact or damaged) of the PLINE 604, the input voltage VIN0 is either ~0V or VDD. The sensing circuit 610 is configured to compare the current through the NFET T5 caused by the reference voltage VREF with the current through the NFET T4 caused by the input voltage VIN0. When ENN = 0V and the PLINE 604 is intact (without any damage), then VIN0 = 0V, OUT0 = 0V, CRACKN_S0 = 1V, and F0 = 0V. When ENN = 0V and the PLINE 604 is damaged, then VIN0 = ~VDD (1V), CRACKN_S0 = 0V, and F0 = 1V. In this case, the enable signal CRACKN_S0 = 0V will enable the next (second) - stage sensing circuit 612. The second and third - stage sensing circuits 612, 614 operate in a manner similar to the first - stage sensing circuit 610 based on the values of their respective enable signals CRACKN_S0, CRACKN_S1.

[0103] When the PLINE 604 is intact (without any damage), the sensing circuit 610 does not consume any current. In this case, VIN0 = ~0V, which turns off the NFET T4 and floats the MID0 voltage. Since the reference voltage VREF = VDD / 2 (or some other reference voltage, depending on the implementation), the voltage OUT0 is safely pulled to 0V and a known output is provided to the subsequent circuit. The sensing circuit 604 consumes current only when the PLINE 604 is damaged (e.g., when ENN = 0V and VIN0 = 1V).

[0104] Embodiments of the present disclosure may provide several technical and commercial advantages, some of which are discussed by way of example herein. The crack detection and monitoring system disclosed herein is configured to detect the presence of cracks in the non - operating regions of an IC and to warn the end - user of the presence of the cracks and the progress of the cracks towards the operating region of the IC. Additionally, the crack detection and monitoring system disclosed herein is designed to warn the end - user of an impending catastrophic failure before it becomes an actual catastrophic failure (where the crack propagates into the operating region of the IC). This allows the end - user to replace the IC before it fails due to crack propagation. The crack detection and monitoring system can be set up and calibrated in such a way as to provide a rough time frame regarding the impending IC failure.

[0105] The crack detection and monitoring systems disclosed herein may include jumper or tunneling connections to the detection and monitoring circuitry that are surrounded by and span crack stop structures and / or guard rails through vias in the top metal layer (BEOL) or semiconductor substrate of the IC and buried semiconductor wells. The crack detection and monitoring systems disclosed herein may also include deliberately designed weak points that will direct crack growth to desired locations where the cracks will be trapped and their energy dissipated.

[0106] The crack detection and monitoring systems disclosed herein may include an arrangement of multi-stage series connections (e.g., cascading) of sensing circuits for monitoring structures (e.g., PLINE) on the IC. Advantageously, the sensing circuits of the N+1 stage are not enabled and do not consume any power until the sensing circuits of the upstream Nth stage detect damage to their respective structures.

[0107] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequent described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

[0108] Approximating language, as used throughout the specification and claims, may be applied to modify any quantitative representation that could permit variation without resulting in a change in the basic function to which it is related. Accordingly, a value modified by one or more terms, such as "about", "approximately" and "substantially", is not limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of the instrument used to measure the value. Throughout this specification and the claims, range limitations may be combined and / or interchanged, such ranges are identified and include all the sub-ranges contained therein unless the context or language indicates otherwise. "Approximate" applied to a particular value of a range applies to both values of that range and may indicate, unless otherwise determined by the precision of the instrument measuring the value, + / - 10% of said value.

[0109] All corresponding structures, materials, acts, and equivalents of apparatus or steps plus function elements in the following claims are intended to include any structure, material, or act that performs the function in conjunction with other claimed elements that are specifically claimed. The description of the present disclosure has been given for purposes of illustration and description, but the description is not intended to be exhaustive or to limit the present disclosure to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. The embodiments were chosen and described in order to best explain the principles of the present disclosure and its practical application, and to enable others of ordinary skill in the art to understand the present disclosure with various modifications that are suitable for the particular use contemplated.

Claims

1. A crack detection and monitoring system, comprising: a plurality of structures extending around a barrier formed in a non-operating region of an integrated circuit (IC), wherein an operating region of the IC is enclosed within the barrier; and a multi-stage sensing circuit for sensing a change in a characteristic of each of the plurality of structures and receiving an enable signal, wherein each sensing circuit is coupled to a corresponding one of the plurality of structures, and the change in the characteristic indicates damage to the corresponding structure, wherein each sensing circuit selectively generates the enable signal for a next sensing circuit in the multi-stage sensing circuit.

2. The system according to claim 1, wherein, The plurality of structures includes a plurality of conductive peripheral lines (PLINE), and wherein the change in the characteristic indicates the presence of a crack in the structure.

3. The system according to claim 1, wherein The characteristic includes the resistance of the structure.

4. The system according to claim 3, wherein, The sensing circuit in each stage of the multi-stage sensing circuit further includes: a voltage divider circuit coupled to the enable signal received by the sensing circuit for outputting a voltage input signal VIN to the sensing circuit based on a damage state of the structure coupled to the sensing circuit.

5. The system according to claim 4, wherein, The voltage divider circuit further includes: a first resistor representing the resistance of the structure; and a reference resistor coupled to the first resistor at an output node, the resistance of the reference resistor being greater than the resistance of the structure when the structure is undamaged and less than the resistance of the structure when the structure is damaged.

6. The system according to claim 5, wherein The voltage divider circuit further includes: a first field effect transistor (FET); and a second FET; wherein a first terminal of the first FET is coupled to the output node, a second terminal of the first FET is grounded, a first terminal of the second FET is coupled to the reference resistor, a second terminal of the second FET is coupled to a supply voltage, and wherein a gate of the first FET and a gate of the second FET are coupled to the enable signal.

7. The system according to claim 4, wherein The sensing circuit for selectively generating the enable signal for the next sensing circuit further includes: an input for receiving a reference voltage VREF; an input for receiving the voltage input signal VIN from the voltage divider circuit; a circuit for generating an output signal OUT based on the reference voltage VREF and the voltage input signal VIN; and a circuit for generating the enable signal for the next sensing circuit based on the OUT signal.

8. The system according to claim 7, further comprising a circuit for outputting a flag indicating a damage state of the structure coupled to the sensing circuit.

9. The system according to claim 1, wherein The multi-stage sensing circuit is connected in series.

10. A method for detecting and monitoring cracks in an integrated circuit (IC), comprising: providing a plurality of structures in a non-operating region of the IC, the plurality of structures extending around a barrier formed in the non-operating region of the IC, wherein an operating region of the IC is enclosed within the barrier; coupling a multi-stage sensing circuit to the plurality of structures, wherein each sensing circuit is coupled to a corresponding one of the plurality of structures; enabling a sensing circuit in an Nth stage of the multi-stage sensing circuit; Monitoring the characteristics of the corresponding structure coupled to the enabled sensing circuit through the enabled sensing circuit; And In response to detecting a change in the characteristics of the corresponding structure coupled to the enabled sensing circuit, an enable signal is output by the enabled sensing circuit, and the enable signal is used to enable the sensing circuit in the downstream (N + 1)-th stage of the multi-stage sensing circuit.

11. The method according to claim 10, further comprising outputting a mark indicating the change in the characteristics of the corresponding structure coupled to the enabled sensing circuit.

12. The method according to claim 11, further comprising providing an alarm in response to the mark, the alarm indicating that the corresponding structure coupled to the enabled sensing circuit is damaged.

13. The method according to claim 12, wherein, The change in the characteristics of the corresponding structure coupled to the enabled sensing circuit is caused by a crack propagating through the non-operating area of the IC, and the method further comprises providing the alarm before the crack propagates from the non-operating area of the IC to the operating area of the IC.

14. The method according to claim 10, further comprising positioning the structure coupled to the N-th stage of the multi-stage sensing circuit closer to the operating area of the IC than the structure coupled to the (N + 1)-th stage of the multi-stage sensing circuit.

15. The method according to claim 10, wherein, The multi-stage sensing circuits are connected in series.

16. A method, comprising: Coupling a multi-stage sensing circuit to a plurality of structures on an integrated circuit (IC), wherein each sensing circuit is coupled to a corresponding one of the plurality of structures; Enabling the sensing circuit in the N-th stage of the multi-stage sensing circuit; Monitoring the characteristics of the corresponding structure coupled to the enabled sensing circuit through the enabled sensing circuit; And In response to detecting a change in the characteristics of the corresponding structure coupled to the enabled sensing circuit, an enable signal is output by the enabled sensing circuit, and the enable signal is used to enable the sensing circuit in the downstream (N + 1)-th stage of the multi-stage sensing circuit.

17. The method according to claim 16, further comprising generating an alarm indicating damage to the corresponding structure coupled to the enabled sensing circuit.

18. The method according to claim 17, further comprising: Monitoring the propagation of a crack through the IC based on the alarm.

19. The method according to claim 16, wherein, The electrical characteristics include the resistance of the corresponding structure coupled to the enabled sensing circuit.

20. The method according to claim 16, wherein The plurality of structures include conductive peripheral lines (PLINE) located in the non-operating area of the IC, and wherein the change in the characteristics indicates the presence of a crack in the PLINE.

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