Auxiliary voltage-sharing circuit of asymmetric cascade inverter and modulation method of auxiliary voltage-sharing circuit

Abstract

The invention discloses an auxiliary voltage-sharing circuit of an asymmetric cascade inverter and a modulation method thereof, and relates to the technical field of electronic power, the auxiliary voltage-sharing circuit comprises a first module and a second module which are cascaded, the first module comprises a first H-bridge conversion circuit, a direct-current power source # imgabs0 # and a first capacitor, the direct-current power source is connected with the first H-bridge conversion circuit in parallel, and the first capacitor is connected with the second H-bridge conversion circuit in parallel. The first module comprises a first H-bridge conversion circuit, a first capacitor connected in parallel to the DC side of the first H-bridge conversion circuit, the second module comprises a second H-bridge conversion circuit, an auxiliary voltage-sharing circuit and a second capacitor, the second capacitor is connected in parallel to the DC side of the second H-bridge conversion circuit, and the auxiliary voltage-sharing circuit is connected with the second H-bridge conversion circuit and the DC power supply; the first H-bridge conversion circuit and the second H-bridge conversion circuit are cascaded, and the cascaded output port is connected with an AC filter inductor and a load. Direct electric energy conversion from low direct-current voltage to high alternating-current voltage is achieved, and the limitation that each module of a traditional topology must be provided with a direct-current power source is broken through.

Description

Technical Field

[0001] The present invention relates to the field of electronic power technology, and in particular, to an auxiliary voltage balancing circuit and a modulation method for an asymmetric cascaded inverter. Background Art

[0002] Due to its advantages such as modular structure, low harmonic content of the output voltage, and low device voltage stress, the cascaded multilevel inverter has been widely used in fields such as high-voltage DC power transmission, new energy power generation grid connection, and industrial motor drive. However, the traditional cascaded inverter topology has significant technical bottlenecks under the condition that some modules have no power supply: due to the physical circuit topology limitation of power transmission between modules, it is difficult to autonomously balance the DC bus voltages of each module, resulting in limited modulation degree of the system and inability to achieve stable inverter output within the full operating range.

[0003] In the prior art, in order to solve the problem of voltage instability of the no-load module, methods such as dynamic switching of redundant modules and active power distribution control between modules are usually adopted. However, the redundant module scheme increases the system cost and volume; the power distribution based on the control algorithm is limited by the physical circuit transmission capacity and cannot break through the inherent constraints of power transmission under extreme no-load conditions. In response to the above challenges, an innovative solution that can expand the voltage balancing boundary of the cascaded system without sacrificing system efficiency and compactness is needed. Summary of the Invention

[0004] In order to solve the power transmission limitation problem of the traditional cascaded system, the present invention proposes an auxiliary voltage balancing circuit and a modulation method for an asymmetric cascaded inverter to solve the above problems. By reconstructing the auxiliary power transmission path, while maintaining the DC-AC inverter function of the main circuit, the auxiliary DC-DC power transfer channel is used to dynamically balance the energy of the no-load module, thereby breaking through the power transmission limitation of the traditional cascaded system and realizing efficient direct inversion from high-voltage DC to AC.

[0005] The present application discloses an auxiliary voltage balancing circuit for an asymmetric cascaded inverter, including a cascaded first module and second module. The first module includes a first H-bridge conversion circuit, a DC power supply and a first capacitor , the DC power supply is connected in parallel with the first H-bridge conversion circuit, and the first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. The second module includes a second H-bridge conversion circuit, an auxiliary voltage balancing circuit and a second capacitor , the second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit, and the auxiliary voltage balancing circuit is connected to the second H-bridge conversion circuit and the DC power supply ; The first H-bridge conversion circuit and the second H-bridge conversion circuit are cascaded, and an AC filter inductor is connected to the output port after cascading and a load .

[0006] Preferably, the auxiliary voltage equalizing circuit includes a series-connected DC filter inductor and a controllable switch . The DC filter inductor is connected to the positive terminal of the DC power supply , and the controllable switch is connected to the positive terminal of the second capacitor .

[0007] Preferably, both the first H-bridge conversion circuit and the second H-bridge conversion circuit include a first bridge arm and a second bridge arm connected in parallel. The midpoint a1 of the first bridge arm of the first H-bridge conversion circuit is connected to the midpoint b2 of the second bridge arm of the second H-bridge conversion circuit. The midpoint b1 of the second bridge arm of the first H-bridge conversion circuit is connected to an AC output port, and the midpoint a2 of the first bridge arm of the second H-bridge conversion circuit is connected to another AC output port through an AC filter inductor .

[0008] Preferably, the second module includes a plurality of cascaded second H-bridge conversion circuits. Capacitors are connected in parallel on the DC side of each second H-bridge conversion circuit, and each second H-bridge conversion circuit is connected to an auxiliary voltage equalizing circuit. All the auxiliary voltage equalizing circuits are connected in series and then connected to the DC power supply .

[0009] The present application also discloses a modulation method for the auxiliary voltage equalizing circuit of an asymmetric cascaded inverter, which is applied to the auxiliary voltage equalizing circuit of the above-mentioned asymmetric cascaded inverter, and includes the following steps: S1. Define the inverter switching function, construct a three-dimensional vector space, and obtain the modulation vector points ; S2. Initialize the modulation vector points , and obtain the AC sinusoidal modulation wave reference signal ; S3. Pre-charge the capacitors of the second module through the power supply to stabilize the DC voltage of the second module and calculate the voltage difference between the second module and the target voltage ; S4. Select the synthesized basic level vectors and through the AC sinusoidal modulation wave reference signal , and perform vector synthesis; S5. Determine whether to start the auxiliary voltage equalizing circuit through the modulation degree, and obtain the complete modulation vector sequence ; S6. The modulation vector sequence Converted into a first H-bridge conversion circuit, a second H-bridge conversion circuit, and a controllable switch of the PWM pulse sequence and output to the corresponding switching device.

[0010] Preferably, the S1 includes the following steps: Let the switching device be 1 when it is on and 0 when it is off, and define the inverter switching function :

[0011] Among them, represents the th H-bridge conversion circuit, is complementary to the switching device to conduct, is complementary to the switching device to conduct, and represent two different switching paths when the AC ports are both at 0 level, and the overall modulation switching function is ; Establish the X, Y, and Z axes with , , respectively, and form 32 space vector points with the values of , , to construct a three-dimensional vector space.

[0012] Preferably, the initialization method in the S2 is: Assign to .

[0013] Preferably, the formula for vector synthesis in the S4 is:

[0014] Among them, is the switching period of the reference signal , is the operating time, is the operating time; The action time of the vector is:

[0015]

[0016] Define as the total port voltage level number, and it can be obtained that , and enter at the rising edge of ​ The working time of the vector, at this time , at the falling edge moment of .

[0017] Preferably, if the auxiliary voltage equalization circuit is not started in S5, at this time , based on the obtained in S4, judge the power distribution under each current level state. The principle of power distribution is: select the working modes where AC and DC do not interfere with each other from the limited current paths, and select the vector with the strongest power output ability to stabilize the voltage of the passive module; Use to represent the port voltage of the th H-bridge conversion circuit, and the unified formula under different port levels is:

[0018] Among them, is the DC voltage value of the th H-bridge conversion circuit, is the AC current value, is the DC load value of the th H-bridge conversion circuit. The first capacitor of the first H-bridge conversion circuit and the second capacitor of the second H-bridge conversion circuit have the same capacitance value of ; The level ranges of the first module and the second module are both -1 to 1, that is, there is , then needs to meet the following conditions:

[0019] Among them, is the voltage deviation value of the first capacitor, is the voltage deviation value of the second capacitor; Convert the level corresponding to to .

[0020] Preferably, if the auxiliary voltage equalization circuit is started in S5, at this time , based on the obtained in S4, judge the power distribution under the current level state and remove the unavailable paths under each level state; If , let the duty cycle D>0.5 select the path for Lx to release energy, and let the duty cycle D<0.5 select the path for energy storage; If , determine whether to extend the direct current (DC) switching period from to . If the period extension is not performed, let the duty cycle D>0.5 be selected as the energy storage path, and let the duty cycle D<0.5 be selected as the energy release path; if the period extension is performed, then in the first , all are selected as the energy storage path, and in the second , D>0.5 is the energy storage path, and the remaining duty cycle D<0.5 is selected as the energy release path.

[0021] Advantages of the present invention: 1. The present invention provides an auxiliary voltage equalization circuit for an asymmetric cascaded inverter, which can realize direct electric energy conversion from low DC voltage to high AC voltage.

[0022] 2. The proposed auxiliary circuit and corresponding modulation method of the present invention can, while taking into account the power quality of the traditional cascaded inverter topology, break through the limitation that each module of the traditional topology must be equipped with a DC power supply, and effectively expand the application scenarios and scope of the converter. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to an embodiment of the present invention; Figure 2 is an example diagram of an unavailable mode according to an embodiment of the present invention; Figure 3 is a working analysis diagram of the Boost circuit of the AC-DC asymmetric cascaded converter according to an embodiment of the present invention; Figure 4 is a diagram of the current working path and the space vector on the AC side according to an embodiment of the present invention; Figure 5 is a schematic flow diagram of the modulation method of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to an embodiment of the present invention; Figure 6 is a schematic structural diagram of the expansion of the N module according to an embodiment of the present invention; Figure 7 is a waveform diagram for verifying the feasibility of transferring energy using the auxiliary circuit according to an embodiment of the present invention. Detailed Embodiments

[0024] To make the objectives, technical solutions and advantages of the present application clearer, the following examples are given with reference to the accompanying drawings to further elaborate on the present application in detail.

[0025] An embodiment of the present application discloses an auxiliary voltage equalization circuit for an asymmetric cascaded inverter, and its structure is asFigure 1 As shown, it includes a cascaded first module and second module. The first module includes a first H-bridge conversion circuit, a DC power supply and a first capacitor . The DC power supply is connected in parallel with the first H-bridge conversion circuit and is responsible for providing energy input. The first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. The second H-bridge conversion circuit is not connected to any DC power supply but is connected to an auxiliary voltage equalization circuit. It should be noted that only one independent DC power supply is provided in the entire system, and this power supply is only connected to the DC side of the first H-bridge conversion circuit. The second H-bridge conversion circuit operates completely relying on the auxiliary voltage equalization circuit and the energy transfer between modules. The second module includes a second H-bridge conversion circuit, an auxiliary voltage equalization circuit and a second capacitor , and the second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit. The auxiliary voltage equalization circuit is connected to the second H-bridge conversion circuit and the DC power supply ; The first H-bridge conversion circuit and the second H-bridge conversion circuit are cascaded, and an AC filter inductor and a load are connected to the output port after cascading. Each H-bridge conversion circuit adopts a classic bridge structure and is composed of four controllable switch devices with anti-parallel diodes, forming two bridge arms to ensure bidirectional conduction of current and efficient control of the switches. Specifically, both the first H-bridge conversion circuit and the second H-bridge conversion circuit include a first bridge arm and a second bridge arm connected in parallel. The first bridge arm of the first H-bridge conversion circuit is composed of a first switch device and a second switch device connected in series. The second bridge arm of the first H-bridge conversion circuit is composed of a third switch device and a fourth switch device connected in series. The first bridge arm of the second H-bridge conversion circuit is composed of a fifth switch device and a sixth switch device connected in series. The second bridge arm of the second H-bridge conversion circuit is composed of a seventh switch device and an eighth switch device connected in series. The midpoint a1 of the first bridge arm of the first H-bridge conversion circuit is connected to the midpoint b2 of the second bridge arm of the second H-bridge conversion circuit. The midpoint b1 of the second bridge arm of the first H-bridge conversion circuit is connected to an AC output port. The midpoint a2 of the first bridge arm of the second H-bridge conversion circuit is connected to another AC output port through an AC filter inductor , and the load is arranged at the AC output port.

[0026] A capacitor is equipped on the DC side of each H-bridge conversion circuit to smooth voltage fluctuations and provide short-term energy support. A first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. A second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit. The auxiliary voltage equalization circuit includes a series-connected DC filter inductor and a controllable switch . The DC filter inductor is connected to the positive terminal of the DC power supply . The controllable switch is connected to the positive terminal of the second capacitor . This series structure forms an efficient energy transmission channel to ensure that the power supply energy can be transferred to the second H-bridge conversion circuit when necessary. The core function of the auxiliary voltage equalization circuit is voltage equalization, that is, by controlling the on and off of the switch and some switches of the two H-bridge conversion circuits, the energy in the power supply and the inductor is transmitted to the capacitor , so as to maintain the voltage stability of the second capacitor . The set values of the DC voltages of the two modules can be kept consistent, and the voltage stresses of all the switching devices in the H-bridge conversion circuit are evenly distributed. In the asymmetric working mode, photovoltaic power generation systems and DC input sources such as energy storage and batteries can all be used as the power supply of the proposed topology for direct power conversion.

[0027] In this embodiment, in the case of no auxiliary voltage equalization circuit, let the DC voltage of the first H-bridge conversion circuit be , the DC voltage of the second H-bridge conversion circuit be , the capacitance values of the first capacitor and the second capacitor are both , the switching devices output waveforms according to unipolar SVPWM modulation, and the switching frequency is . The modulation degree of the AC-DC conversion is , and the frequency is 50Hz. The value of the AC filter inductor is , and the load resistance value is . In the case of conventional modulation, the output voltage of the cascaded H-bridge inverter after passing through the low-pass filter can be approximated as the fundamental component, then the AC current is:

[0028] Under unipolar SVPWM modulation, the output voltage of the second H-bridge conversion circuit is or 0 (depending on the switch state). Its modulation wave is synchronized with the first H-bridge conversion circuit, so the instantaneous power of the second H-bridge conversion circuit is:

[0029] Since is a PWM wave, and its fundamental wave component is , so the average discharge power of the second H-bridge conversion circuit is:

[0030] Wherein, is one power frequency period.

[0031] When the second capacitor functions as a load, at this time, the electric energy stored in the second capacitor can maintain the time as follows:

[0032] It can be seen from Equation (4) that the discharge time is proportional to the capacitance value of the capacitor and the load (the larger the capacitor or the smaller the load, the slower the discharge). It is inversely proportional to the square of the modulation depth (the deeper the modulation, the faster the discharge). This is the main reason why the power supply module will quickly lose electric energy when the modulation depth of the asymmetric cascade topology without the auxiliary voltage equalization circuit is greater than 0.5. Since the capacitor cannot provide long-term active power support, most of the redundant vector points in the vector plane will not be available. In the asymmetric working mode, even if most of the vector points are discarded, there is still a serious power imbalance problem. This will cause the electric energy of the capacitor to quickly drain during the long-term operation of the 2E level and cannot be replenished at the 0E level, resulting in the abnormal operation of the converter.

[0033] Another embodiment of the present application also discloses a modulation method for the auxiliary voltage equalization circuit of an asymmetric cascade inverter, which is applied to the auxiliary voltage equalization circuit of the above-mentioned asymmetric cascade inverter, as Figure 6 shown, and includes the following steps: S1. Define the inverter switching function, construct a three-dimensional vector space, and obtain the modulation vector point .

[0034] Let it be represented that the device is turned on when the switching device is 1 and the device is turned off when it is 0, and define the inverter switching function :

[0035] Wherein, represents the th H-bridge conversion circuit, and the switching devices are complementarily turned on, and the switching devices are complementarily turned on. And Represent two different switching paths when the representative AC ports are all at the 0 level. Then, the overall modulation switching function of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter proposed in the embodiments of this application will generate 32 possible switching combinations, and the switching combinations involve physically unacceptable switching combinations and some unavailable operating modes.

[0036] In the cascaded inverter structure, when a module loses power support, it cannot operate normally according to the working mode of the traditional H-bridge circuit. Limited by the topological structure, the traditional method cannot achieve voltage equalization of the proposed H-bridge structure, and the auxiliary circuit will bring problems of non-isolation between AC and DC powers, and introduce additional problems in some modes. For example Figure 2 as shown, after the auxiliary circuit is connected, the circuit will have a situation where the inductor is instantaneously short-circuited at several levels. After the inductor voltage instantaneously becomes 0, the current will instantaneously rise and discharge energy through the switch, causing some switching devices to be damaged due to a significant increase in current stress. At the same time, after the circuit is modified, in addition to the risk of damaged devices, in some modes, the load is completely powered by the passive module, which instead causes the voltage of the second module to drop faster.

[0037] It should be noted that the auxiliary voltage equalization circuit can switch to the working mode of the Boost circuit / Buck circuit during some working periods, and use the DC power supply of the first module to supply energy to the second capacitor of the second module to provide energy supplement. The realization of this Boost / Buck mode depends on specific switching state combinations between modules. By controlling the switches and the switching devices of the H-bridge circuit, the energy flow direction is dynamically adjusted, so as to keep the capacitor voltage of module 2 stable under a high modulation degree. For example Figure 3 as shown, when the AC output is at the 0E level, the Boost circuit operates by closing the control switch At this time, some switching tubes of the H-bridge act as equivalent switches to control the inductor to charge and supply functional energy to the capacitor. Through the carefully designed switching combination, the DC-DC conversion circuit can work at different duty cycles, neither interfering with the output characteristics of the AC side nor causing an incorrect current path.

[0038] Based on the above analysis, a three-dimensional vector space as shown Figure 4 can be obtained. The space vector modulation proposed in this embodiment respectively uses , , to establish the X, Y, and Z axes, and uses , , The values ​​of form 32 space vector points. The traditional two-module cascade H bridge has only 9 space vector points (because the redundant vectors are not restricted in the short time scale, some paths are considered equivalent and are summarized together). The vector space of this embodiment produces a completely different effect due to the addition of auxiliary circuits, so it has a fundamental change. The following is an example of an unavailable working path and an example of an available working path: It can be seen from the three-dimensional vector space of this embodiment that the 32 vector points all represent an independent current path. If divided by the AC side port level, there are 2 vector points at the -2E level, 8 vector points at the -E level, 12 vector points at the 0E level, 8 vector points at the E level, and 2 vector points at the 2E level. According to the basic principle of space vector modulation, different vectors can be selected for synthesis in the four intervals of -2E level and -E level, -E level and 0E level, 0E level and E level, and E level and 2E level within a power frequency cycle. If all the options are traversed, there are: 2*8*12*8*2=3072 kinds. In other words, if the vector space path of the circuit in this embodiment is not screened and planned, there will be 3072 combination paths, which is far more than the conventional traditional 2-module cascade converter (the traditional two-module cascade converter has a total of 1*4*6*4*1=96 kinds).

[0039] Depend on Figure 2 It can be seen that not all vector points (working paths) are beneficial to the circuit operation, and some working paths may damage the switching devices. Therefore, when designing the space vector modulation algorithm, it is necessary to screen the vector paths. This is not only a simplification of the modulation algorithm, but also an important step to ensure the normal operation of the circuit. Figure 4 As shown. In the synthesis interval of -2E level and -E level, The synthesis path can be selected from [-1, -1, 0] to [-1, 0–, 0] but not [-1, -1, 0] to [0+, -1, 0]. The reason is that the power consumption of the load borne by the module 2 that has lost power will cause the module 2 to lose power quickly. When the auxiliary circuit is needed to supplement the power of module 2, even if the AC side ports are all at -E level, jumping from [-1, 0–, 0] to [0+, -1, 1] is not allowed, because the path corresponding to the point [0+, -1, 1] is Figure 2 Unavailable working path.

[0040] When jumping to the -E level and 0E level synthesis interval, there are 24 possible path combinations. Figure 4(a) lists two unavailable paths (Path ① and ②), and one selectable path (Path ③). The vector point [1, -1, 1] passed by Path ① will have a path where the inductor is directly short-circuited, and there may be risks beyond expectations during the operation of the circuit. The vector point [0+, 0+, 1] passed by Path ② will not only have a path where the inductor is directly short-circuited, but also put the power supply in a bypass state, wasting the opportunity to supplement electrical energy for Module 2. The vector point [0–, 0–, 1] passed by Path ③ is completely different. It can not only construct the Boost circuit mode while ensuring AC output, but also make the inductor of the auxiliary circuit work in a safe state. It can be seen from this that based on the structure proposed in this embodiment, each vector will make independent contributions to the AC side and DC side within the switching period. The traditional two-module cascaded converter only focuses on the impact on the AC side within the switching period. Therefore, [0+, 0+, 0] and [0-, 0-, 0] are called "redundant vectors" and can play equivalent roles. Based on the structure proposed in this embodiment, [0+, 0+, 1] and [0-, 0-, 1] are no longer equivalent.

[0041] The vector synthesis of 0E level and E level, and E level and 2E level is similar to the above process, and there will be paths that are hoped to be avoided at some vector points. For example, there are unavailable vector points from the vector point [0–, 0–, 1] to the vector point [1, 0+, 1] and then to the vector point [0+, 1, 0]. If the unavailable vector synthesis working path frequently appears during the vector selection process, not only will the converter not work properly, but it will also threaten the safety of the equipment.

[0042] To make the converter work properly, an available working path must be selected. As Figure 4 (b) shows, in the synthesis interval of -2E level and -E level, the synthesis path can be selected from [-1, -1, 0] to [-1, 0–, 0], and then in the synthesis interval of -E level and 0E level, the synthesis path can be selected from [-1, 0–, 0] to [-1, 0+, 1]. This vector point is defined as Point A1, corresponding to the inductor energy storage working mode of the Boost circuit, which is Figure 3 (b) the -E level current path shown. Point A0 is the inductor energy storage working mode of the Boost circuit at 0E level. Point B1 corresponds to the Boost circuit boost working mode at -E level, and Point B0 corresponds to the Boost circuit boost working mode at 0E level. The path diagram of Point B0 is as Figure 3 (a) shown.

[0043] Obviously, in the synthesis interval of -E level and 0E level, The synthesis path can not only be selected from [-1, 0–, 0] to [-1, 0+, 1] (point A1), but also from [-1, 0–, 0] to [-1, 0–, 1] (point B1). Figure 4 (b) only shows one of the multiple paths. In terms of path arrangement, simply selecting a certain point for -E level and a certain point for 0E level cannot ensure the normal operation of the entire converter. According to the control requirements of the DC voltage, the Boost circuit requires a "suitable duty cycle". However, the working time of the upper and lower synthesis vectors in space vector modulation is also fixed. This introduces a conflict between the AC and DC control objectives. In this embodiment, according to path alternation, part of the DC voltage control accuracy is sacrificed to achieve the optimal overall performance.

[0044] Specifically, both the -E level and the 0E level can select the inductor energy storage working mode, and both can also select the Boost circuit boost working mode. This means that when the -E level and the 0E level alternate on the AC side, the DC side can achieve independent control through decoupling. Figure 4 (b) The path ① represents The synthesis path of is from point A1 to point B0 and then to point A1. This is a conventional path selection method, and one up and down vector synthesis and one Boost circuit operation can be completed within one Ts period. Figure 4 (b) The path ② + path ③ represents The synthesis path of is from point A1 to point A0 and then to point B1. One period can only complete one up and down vector synthesis and one inductor energy storage operation of the Boost circuit, and it takes another period to complete the complete Boost circuit operation.

[0045] Correspondingly, within the synthesis interval of the 0E level and the E level, path ④ can be selected, that is, the synthesis path of [S1, S2, Tx] can be selected from [0–, 0+, 1] to [1, 0–, 1]. Within the synthesis interval of the E level and the 2E level, [1, 0–, 1] to [1, 0–, 0] and then to [1, 1, 0] can be selected.

[0046] S2. Initialize the modulation vector point and assign to , obtain the AC sine modulation wave reference signal input by the controller (a fixed-amplitude sine wave can be input by yourself as the control signal when verifying the modulation algorithm), and determine the DC control signal according to the DC voltage.

[0047] S3. Pre-charge the second module capacitor through the power supply to stabilize the DC voltage of the second module. FromFigure 4 As can be seen from the working path shown in (b), at the moment of 0E level, the AC output is 0, but the two vector points A0 and B0 can form a Boost working circuit. After stabilizing the voltage of the second module through the Boost circuit, the voltage difference between the second module and the target voltage can be calculated as the basis for subsequent control.

[0048] S4. Through the AC sine modulation wave reference signal select the synthesized basic level vector and , and according to the volt-second balance principle, the formula for vector synthesis is:

[0049] where is the switching period of the reference signal , is 's working time, is 's working time. is determined by , is determined by , is 's rounding function.

[0050] The acting time of the vector is:

[0051]

[0052] Define as the total number of port voltage levels, and we can get . At the rising edge of , it enters the working time of vector. At this time . At the falling edge of , .

[0053] S5. When S3 and S4 are completed, the inverter is ready for inverter load. According to the modulation degree requirement of the system, it can be selected whether to turn on the auxiliary voltage equalization circuit. Based on the above analysis, when the modulation degree is less than a certain modulation degree, self-balancing can be achieved. In this embodiment, it can be clear that when the modulation degree < 0.635, there is no need to equalize the voltage through an auxiliary hardware circuit. When the modulation degree > 0.635, it is necessary to use the auxiliary circuit and the modulation algorithm proposed in this embodiment to ensure that the DC voltage of the second module is in a stable state (maintaining the same level as the power supply voltage).

[0054] If the auxiliary equalizing circuit is not activated, then , based on what is obtained from S4 judge the power distribution under each current level state. The principle followed by the power distribution is: screen out the working modes in which AC and DC do not interfere with each other from the finite set of current paths, and select the vector with the strongest power output ability to achieve the voltage stability of the passive module.

[0055] Use to represent the port voltage of the th H-bridge conversion circuit, to represent the DC voltage value of the th H-bridge conversion circuit, to represent the AC current value, to represent the DC load value of the th H-bridge conversion circuit. The first capacitor of the first H-bridge conversion circuit and the second capacitor of the second H-bridge conversion circuit both have a capacitance value of

[0056] It can be seen that the selection of the port action vector determines the discharge speed of the capacitor voltage. From the inverter cascaded topology structure of this application, it can be known that the level ranges of the first module and the second module are both from -1 to 1, that is, there is , then needs to meet the following conditions:

[0057] Among them, is the voltage deviation value of the first capacitor, is the voltage deviation value of the second capacitor.

[0058] Convert the level corresponding to to . When or -1, and can be directly converted. When = 0, needs to select 0 + or 0 – according to the principle of avoiding unavailable states. Theoretically speaking, choosing 0 or 0 + or 0 – is equivalent in the case of , which is consistent with the traditional two-module cascade rectification. But for the convenience of switching from 0 to 1, select the combination that can operate normally in both states. The conversion principle is the same as that of the same.

[0059] If the auxiliary voltage equalization circuit is started, at this time , based on the obtained from S4, judge the power distribution under the current level state and remove the unavailable paths under each level state. It is necessary to judge whether the voltage difference between the current moment (moment k) and the previous moment (moment k-1) is in the correct direction of shortening the DC voltage gap.

[0060] If is satisfied, it means that the currently selected voltage equalization path is effective, then there is no need to store too much energy for the inductor (the electrical energy of the second module capacitor is mainly obtained through the inductor ). Determine the size of the space vector modulation duty cycle through the value compared with the triangular wave, and let the duty cycle D>0.5 be selected as the path of energy release, and let the duty cycle D<0.5 be selected as the path of energy storage.

[0061] If is not satisfied, it means that the currently selected voltage equalization path needs to be improved, and the energy stored in the inductor Lx needs to be increased (the electrical energy of the capacitor of module 2 is mainly obtained through the inductor ). Here, it is necessary to judge whether the DC switching period is extended from to . Under normal working conditions, it is preferably not to perform cycle extension. The implementation complexity of the cycle extension algorithm is higher and is only used for extremely urgent situations. If the cycle extension is not performed, then determine the size of the space vector modulation duty cycle through the value compared with the triangular wave, and let the duty cycle D>0.5 be selected as the path of energy storage, and let the duty cycle D<0.5 be selected as the path of energy release; if the cycle extension is performed, then within the first , all are selected as the path of energy storage, within the second , D>0.5 is the path of energy storage, and the remaining duty cycle D<0.5 is selected as the path of energy release.

[0062] Based on the analysis of Figure 4 , when the working path is determined, the value of can be determined. It should be noted that selecting each different value of 1, -1, 0+, 0– will produce different modulation effects.

[0063] S6. The modulation vector sequence Converted into a first H-bridge conversion circuit, a second H-bridge conversion circuit, and a controllable switch of the PWM pulse sequence, and output to the corresponding switching device.

[0064] Based on S5, a complete vector sequence can be output, and is composed of each switch in a bridge arm. According to the switching function definition in Equation (5), it is converted into the on / off output rules of each switching device. After determining the device signals of each switch and combining the action time calculated by S4, a PWM pulse sequence that can be allocated to each switch can be formed.

[0065] Based on the above embodiments, an embodiment of the present application also proposes an auxiliary circuit connection method extended to N modules, and its structure is as Figure 6 shown. Compared with Figure 1 in Figure 6 the second module includes multiple cascaded second H-bridge conversion circuits. A capacitor is connected in parallel to the DC side of each second H-bridge conversion circuit, and each second H-bridge conversion circuit is connected with an auxiliary voltage equalization circuit. After all the auxiliary voltage equalization circuits are connected in series, they are connected to the DC power supply connection. Figure 1 The circuit shown is the basic circuit of two modules. When the user needs to increase the cascading number, the first module remains unchanged as the basic module, and the number of second H-bridge conversion circuits and auxiliary voltage equalization circuits in the second module is increased.

[0066] In a specific embodiment, the feasibility of the proposed auxiliary voltage equalization under high modulation conditions is verified on the Matlab / Simulink platform. The simulation settings are as follows: 1. Use the maximum power output vector selection method to simulate in a traditional two-module cascaded inverter, and remove the power supply of the second module at time t1.

[0067] 2. At time t2, input the auxiliary voltage equalization circuit and input the proposed auxiliary voltage equalization modulation method.

[0068] Figure 7 is the result under this simulation setting condition. The following is a specific analysis: From 0 to t1: The inverter operates normally and the system works stably.

[0069] At time t1 - t2: The second module loses power supply. If traditional SPWM or SVPWM is adopted, it will cause a rapid drop in the power supply voltage. In traditional cascaded inverters, the two modules alternately provide power support for the load, and the reasons for the voltage drop have been analyzed in Formulas (1)-(4). Using the method of maximum power output vector can delay the trend of voltage drop, but it cannot prevent the continuous voltage drop. While the voltage of the second module drops, the inverter port voltage appears asymmetric distortion, and a large amount of harmonics will be injected into the power grid instantaneously by the grid-connected current. Under extreme conditions, the strongest vector modulation can make a certain module share most of the power. However, when the second module loses the support of the DC power supply, the modulation degree of the inverter cannot be higher than 0.635, otherwise the inverter will face collapse.

[0070] After time t2, the auxiliary voltage equalization method proposed in this embodiment is put into use, and the breakthrough of single DC power supply inverter with high AC voltage is achieved by adding an auxiliary circuit and voltage equalization modulation. As Figure 7 shown, when the method proposed in the present invention is adopted, the voltage of the power supply will gradually recover to the set value, and the AC port voltage and AC current will return to normal. After applying the present invention, the limitation of the modulation degree of the traditional inverter is broken through, and stable operation can be maintained under the condition of only one DC power supply with a high modulation degree (≥0.8).

[0071] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. An auxiliary voltage equalization circuit for an asymmetric cascaded inverter, characterized in that Comprising a cascaded first module and second module, the first module includes a first H-bridge conversion circuit, a DC power supply and a first capacitor , the DC power supply is connected in parallel with the first H-bridge conversion circuit, and the first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. The second module includes a second H-bridge conversion circuit, an auxiliary voltage equalization circuit and a second capacitor , the second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit, and the auxiliary voltage equalization circuit is connected to the second H-bridge conversion circuit and the DC power supply ; The first H-bridge conversion circuit and the second H-bridge conversion circuit are cascaded, and an AC filter inductor is connected to the output port after cascading and a load .

2. The auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 1, wherein The auxiliary voltage equalizing circuit includes a DC filtering inductor connected in series and a controllable switch . The DC filtering inductor is connected to the positive terminal of the DC power supply , and the controllable switch is connected to the positive terminal of the second capacitor .

3. The auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 2, characterized in that, The first H-bridge conversion circuit and the second H-bridge conversion circuit both include a first bridge arm and a second bridge arm connected in parallel. The midpoint a1 of the first bridge arm of the first H-bridge conversion circuit is connected to the midpoint b2 of the second bridge arm of the second H-bridge conversion circuit. The midpoint b1 of the second bridge arm of the first H-bridge conversion circuit is connected to an AC output port. The midpoint a2 of the first bridge arm of the second H-bridge conversion circuit is connected to another AC output port through an AC filter inductor ​ 4. The auxiliary voltage sharing circuit of the asymmetric cascaded inverter according to claim 1, wherein The second module includes a plurality of cascaded second H-bridge conversion circuits. A capacitor is connected in parallel to the DC side of each second H-bridge conversion circuit, and each second H-bridge conversion circuit is connected with an auxiliary voltage equalization circuit. After all the auxiliary voltage equalization circuits are connected in series, they are connected to a DC power supply connected.

5. A modulation method for an auxiliary voltage equalization circuit of an asymmetric cascaded inverter, characterized in that, The auxiliary voltage balancing circuit applied to the asymmetric cascaded inverter according to any one of claims 2-3 comprises the following steps: S1. Define the inverter switching function and construct a three-dimensional vector space to obtain the modulation vector point ; S2. Initialize the modulation vector points , and assign to be . Obtain the AC sinusoidal modulation wave reference signal input by the controller, and determine the DC control signal according to the DC voltage; S3. Pre-charge the second module capacitor through the power supply to stabilize the DC voltage of the second module and calculate the voltage difference between the second module and the target voltage ; S4. Select the reference signal of the AC sine modulation wave to select the synthesized basic level vector and perform vector synthesis; S5. Determine whether to activate the auxiliary voltage equalization circuit based on the modulation degree and obtain a complete modulation vector sequence ; S6. Convert the modulation vector sequence into the PWM pulse sequences of the first H-bridge conversion circuit, the second H-bridge conversion circuit, and the controllable switch and output them to the corresponding switching devices.

6. The modulation method of the auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 5, characterized in that, The said S1 comprises the following steps: When the switching device is 1, it indicates that the device is conducting, and when it is 0, it indicates that the device is off. Define the inverter switching function : Among them, represents the th H-bridge conversion circuit, complementary-conducting with the switching device, complementary-conducting with the switching device, and represent two different switching paths when the AC ports are all at 0 level, and the overall modulation switching function is ; Respectively with , , to establish the X, Y, and Z axes, and with , , the values form 32 space vector points to construct a three-dimensional vector space.

7. The modulation method of the auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 6, wherein The initialization method in S2 is as follows: Set to be equal to .

8. The modulation method of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to claim 7, characterized in that, The formula for vector synthesis in the said S4 is: Among them, is the switching period of the reference signal , is 's working time is 's working time; The acting time of the vector is: Definition For the total level number of the port voltage, it can be obtained that , at enters at the rising edge time of the working time of the vector. At this time , at the falling edge time of .

9. The modulation method of the auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 8, characterized in that, If the auxiliary voltage equalization circuit is not started in S5, then at this time , based on what is obtained in S4 judge the power distribution under each current level state. The principle followed by the power distribution is: screen out the working modes in which AC and DC do not interfere with each other from the finite set of current paths, and select the vector with the strongest power output ability to achieve the voltage stability of the passive module; Use to represent the port voltage of the th H-bridge conversion circuit and the corresponding port level value. The unified formula under different port levels is as follows: Among them, is the DC voltage value of the th H-bridge conversion circuit, is the AC current value, is the DC load value of the th H-bridge conversion circuit. The first capacitor of the first H-bridge conversion circuit and the second capacitor of the second H-bridge conversion circuit both have a capacitance value of ; The level ranges of both the first module and the second module are from -1 to 1, that is, there exists , then The following conditions need to be met: Among them, is the voltage deviation value of the first capacitor, is the voltage deviation value of the second capacitor; Convert the corresponding level to .

10. The modulation method of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to claim 9, characterized in that, If the auxiliary voltage equalization circuit is started in S5, then , based on what is obtained in S4 judge the power distribution under the current level state and remove the unavailable paths under each level state; If , when the duty cycle D > 0.5, select the path for Lx to release energy, and when the duty cycle D < 0.5, select the path for energy storage; If , determine whether to extend the DC switching period from to . If the period is not extended, let the duty cycle D > 0.5 be selected as the energy storage path, and let the duty cycle D < 0.5 be selected as the energy release path; if the period is extended, then in the first , all are selected as the energy storage path, in the second , D > 0.5 is the energy storage path, and the remaining duty cycle D < 0.5 is selected as the energy release path.

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