Auxiliary voltage balancing circuit and modulation method for an asymmetric cascaded inverter

Abstract

The present invention discloses an auxiliary voltage balancing circuit and a modulation method thereof for an asymmetric cascaded inverter, which relates to the technical field of electronic power. It includes a cascaded first module and second module. The first module includes a first H-bridge conversion circuit, a DC power supply #imgabs0#, and a first capacitor. The DC power supply is connected in parallel with the first H-bridge conversion circuit, and the first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. The second module includes a second H-bridge conversion circuit, an auxiliary voltage balancing circuit, and a second capacitor. The second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit, and the auxiliary voltage balancing circuit is connected to the second H-bridge conversion circuit and the DC power supply. The first H-bridge conversion circuit is cascaded with the second H-bridge conversion circuit, and an AC filter inductor and a load are connected to the output port after cascading. The present invention realizes the direct power conversion from low DC voltage to high AC voltage and breaks through the limitation that each module of the traditional topology must be equipped with a DC power supply.

Description

Technical Field

[0001] The present invention relates to the field of electronic power technology, and particularly to an auxiliary voltage equalization circuit and a modulation method for an asymmetric cascaded inverter. Background Art

[0002] Cascaded multilevel inverters have been widely used in high-voltage DC power transmission, new energy power generation grid connection, industrial motor drive and other fields due to their modular structure, low harmonic content of the output voltage, and small device voltage stress. However, traditional cascaded inverter topologies have significant technical bottlenecks under the condition that some modules have no power supply: due to the physical circuit topology limitation of power transmission between modules, it is difficult to autonomously balance the DC bus voltages of each module, resulting in limited modulation degree of the system and inability to achieve stable inverter output within the full operating range.

[0003] In the prior art, to solve the problem of voltage instability of no-load modules, methods such as dynamic switching of redundant modules and active power distribution control between modules are usually adopted. However, the redundant module scheme increases the system cost and volume; the power distribution based on the control algorithm is limited by the physical circuit transmission capacity and cannot break through the inherent constraints of power transmission under extreme no-load conditions. In response to the above challenges, an innovative solution that can expand the voltage equalization boundary of the cascaded system without sacrificing system efficiency and compactness is needed. Summary of the Invention

[0004] In order to solve the power transmission limitation problem of the traditional cascaded system, the present invention proposes an auxiliary voltage equalization circuit and a modulation method for an asymmetric cascaded inverter to solve the above problems. By reconstructing the auxiliary power transmission path, while maintaining the DC-AC inverter function of the main circuit, the auxiliary DC-DC power transfer channel is used to dynamically balance the energy of no-load modules, thereby breaking through the power transmission limitation of the traditional cascaded system and achieving efficient direct inversion from high-voltage DC to AC.

[0005] The present application discloses an auxiliary voltage equalization circuit for an asymmetric cascaded inverter, including a cascaded first module and second module. The first module includes a first H-bridge conversion circuit, a DC power supply and a first capacitor , the DC power supply is connected in parallel with the first H-bridge conversion circuit, the first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. The second module includes a second H-bridge conversion circuit, an auxiliary voltage equalization circuit and a second capacitor , the second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit, and the auxiliary voltage equalization circuit is connected to the second H-bridge conversion circuit and the DC power supply ;

[0006] The first H-bridge conversion circuit is cascaded with the second H-bridge conversion circuit, and an AC filter inductor is connected to the output port after cascading. and a load .

[0007] Preferably, the auxiliary voltage equalization circuit includes a series-connected DC filter inductor and a controllable switch . The DC filter inductor is connected to the positive terminal of the DC power supply , and the controllable switch is connected to the positive terminal of the second capacitor .

[0008] Preferably, both the first H-bridge conversion circuit and the second H-bridge conversion circuit include a first bridge arm and a second bridge arm connected in parallel. The midpoint a1 of the first bridge arm of the first H-bridge conversion circuit is connected to the midpoint b2 of the second bridge arm of the second H-bridge conversion circuit. The midpoint b1 of the second bridge arm of the first H-bridge conversion circuit is connected to an AC output port, and the midpoint a2 of the first bridge arm of the second H-bridge conversion circuit is connected to another AC output port through an AC filter inductor .

[0009] Preferably, the second module includes a plurality of cascaded second H-bridge conversion circuits. Capacitors are connected in parallel on the DC side of each second H-bridge conversion circuit, and each second H-bridge conversion circuit is connected to an auxiliary voltage equalization circuit. All the auxiliary voltage equalization circuits are connected in series and then connected to the DC power supply .

[0010] The present application also discloses a modulation method for the auxiliary voltage equalization circuit of an asymmetric cascaded inverter, which is applied to the auxiliary voltage equalization circuit of the above-mentioned asymmetric cascaded inverter, and includes the following steps:

[0011] S1. Define the inverter switching function, construct a three-dimensional vector space, and obtain the modulation vector point ;

[0012] S2. Initialize the modulation vector point , and obtain the AC sine modulation wave reference signal ;

[0013] S3. Pre-charge the capacitors of the second module through the power supply to stabilize the DC voltage of the second module and calculate the voltage difference between the second module and the target voltage ;

[0014] S4. Select the synthesized basic level vectors and through the AC sine modulation wave reference signal , and perform vector synthesis;

[0015] S5. Determine whether to activate the auxiliary voltage equalization circuit based on the modulation degree and obtain a complete modulation vector sequence ;

[0016] S6. Convert the modulation vector sequence into the PWM pulse sequences of the first H-bridge conversion circuit, the second H-bridge conversion circuit, and the controllable switch and output them to the corresponding switching devices.

[0017] Preferably, the S1 includes the following steps:

[0018] Let the switching device be 1 to indicate that the device is on and 0 to indicate that the device is off. Define the inverter switching function :

[0019]

[0020] Among them, represents the th H-bridge conversion circuit, and the switching device conduct complementarily, and the switching device conduct complementarily, and represent two different switching paths when the AC ports are both at 0 level. The overall modulation switching function is ;

[0021] Respectively, establish the X, Y, and Z axes with , , . With the values of , , form 32 space vector points and construct a three-dimensional vector space.

[0022] Preferably, the initialization method in the S2 is: Assign to .

[0023] Preferably, the formula for vector synthesis in the S4 is:

[0024]

[0025] Among them, is the switching period of the reference signal , is the working time of , is the working time of ;

[0026] The action time of the vector is:

[0027]

[0028]

[0029] Define as the total number of port voltage levels, and we can get , at the rising edge of entering the working time of the vector, at this time , at the falling edge of , . .

[0030] Preferably, if the auxiliary equalizing circuit is not started in S5, at this time , based on the obtained in S4, judge the power distribution under each current level state, and the power distribution principle is: screen out the working modes in which AC and DC do not interfere with each other in the finite set of current paths, and select the vector with the strongest power output ability to achieve the voltage stability of the passive module;

[0031] Use to represent the port voltage corresponding to the of the nth H-bridge conversion circuit, and the unified formula under different port levels is:

[0032]

[0033] where, is the DC voltage value of the nth H-bridge conversion circuit, , is the AC current value, is the DC load value of the nth H-bridge conversion circuit, and the first capacitor of the first H-bridge conversion circuit and the second capacitor of the second H-bridge conversion circuit both have a capacitance value of ;

[0034] The level ranges of the first module and the second module are both -1 to 1, that is, there is , then needs to meet the following conditions:

[0035]

[0036] [[ID=7Q]]where, is the voltage deviation value of the first capacitor, is the voltage deviation value of the second capacitor;

[0037] Convert the level corresponding to to .

[0038] Preferably, if the auxiliary voltage equalization circuit is started in S5, then , based on what is obtained in S4 judge the power distribution under the current level state and remove the unavailable paths under each level state;

[0039] If , let the duty cycle D>0.5 be selected as the path for Lx to release energy, and let the duty cycle D<0.5 be selected as the path for energy storage;

[0040] If , judge whether to extend the DC switching period from to . If the cycle extension is not performed, then let the duty cycle D>0.5 be selected as the path for energy storage, and let the duty cycle D<0.5 be selected as the path for releasing energy; if the cycle extension is performed, then in the first all are selected as the path for energy storage, in the second when D>0.5 is the path for energy storage, and the remaining duty cycle D<0.5 is selected as the path for releasing energy.

[0041] Advantages of the present invention:

[0042] 1. The present invention provides an auxiliary voltage equalization circuit for an asymmetric cascaded inverter, which can realize direct electric energy conversion from low DC voltage to high AC voltage.

[0043] 2. The proposed auxiliary circuit and corresponding modulation method of the present invention can, while taking into account the power quality of the traditional cascaded inverter topology, break through the limitation that each module of the traditional topology must be configured with a DC power supply, and effectively expand the application scenarios and scope of application of the converter. Description of the Drawings

[0044] Figure 1 is a schematic structural diagram of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to an embodiment of the present invention;

[0045] Figure 2 is an example diagram of an unavailable mode according to an embodiment of the present invention;

[0046] Figure 3 is a working analysis diagram of the Boost circuit of the AC-DC asymmetric cascaded converter according to an embodiment of the present invention;

[0047] Figure 4 is a diagram of the current working path and the space vector on the AC side according to an embodiment of the present invention;

[0048] Figure 5 Schematic diagram of the modulation method for the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to an embodiment of the present invention;

[0049] Figure 6 Schematic diagram of the structure of the N-module expansion according to an embodiment of the present invention;

[0050] Figure 7 Waveform diagram for verifying the feasibility of transferring energy using an auxiliary circuit according to an embodiment of the present invention. Detailed implementation manners

[0051] To make the objectives, technical solutions and advantages of the present application more clear and understandable, the following examples are given with reference to the accompanying drawings to further elaborate on the present application in detail.

[0052] An embodiment of the present application discloses an auxiliary voltage equalization circuit for an asymmetric cascaded inverter, the structure of which is as Figure 1 shown, including a cascaded first module and second module. The first module includes a first H-bridge conversion circuit, a DC power supply and a first capacitor . The DC power supply is connected in parallel with the first H-bridge conversion circuit and is responsible for providing energy input. The first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. The second H-bridge conversion circuit is not connected to any DC power supply but is connected to the auxiliary voltage equalization circuit. It should be noted that only one independent DC power supply is provided in the entire system, and this power supply is only connected to the DC side of the first H-bridge conversion circuit. The second H-bridge conversion circuit operates completely relying on the auxiliary voltage equalization circuit and the energy transfer between modules. The second module includes a second H-bridge conversion circuit, an auxiliary voltage equalization circuit and a second capacitor . The second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit. The auxiliary voltage equalization circuit is connected to the second H-bridge conversion circuit and the DC power supply ;

[0053] The first H-bridge conversion circuit and the second H-bridge conversion circuit are cascaded, and an AC filter inductor and a load are connected to the output port after cascading. Each H-bridge conversion circuit adopts a classic bridge structure and is composed of four controllable switch devices with anti-parallel diodes, forming two bridge arms to ensure bidirectional current conduction and efficient control of the switches. Specifically, both the first H-bridge conversion circuit and the second H-bridge conversion circuit include a first bridge arm and a second bridge arm connected in parallel. The first bridge arm of the first H-bridge conversion circuit is composed of a first switch device and a second switch device connected in series. The second bridge arm of the first H-bridge conversion circuit is composed of a third switch device and the fourth switching device in series. The first arm of the second H-bridge conversion circuit consists of a fifth switching device and a sixth switching device in series. The second arm of the second H-bridge conversion circuit consists of a seventh switching device and an eighth switching device in series. The midpoint a1 of the first arm of the first H-bridge conversion circuit is connected to the midpoint b2 of the second arm of the second H-bridge conversion circuit. The midpoint b1 of the second arm of the first H-bridge conversion circuit is connected to an AC output port. The midpoint a2 of the first arm of the second H-bridge conversion circuit is connected to another AC output port through an AC filter inductor . The load is set at the AC output port.

[0054] A capacitor is equipped on the DC side of each H-bridge conversion circuit to smooth voltage fluctuations and provide short-term energy support. A first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit, and a second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit. The auxiliary voltage equalization circuit includes a series-connected DC filter inductor and a controllable switch . The DC filter inductor is connected to the positive terminal of the DC power supply , and the controllable switch is connected to the positive terminal of the second capacitor . This series structure forms an efficient energy transmission channel to ensure that the power energy can be transferred to the second H-bridge conversion circuit when necessary. The core function of the auxiliary voltage equalization circuit is voltage equalization, that is, by controlling the on and off of the switch and some switches of the two H-bridge conversion circuits, the energy in the power supply and the inductor is transmitted to the capacitor , so as to maintain the voltage stability of the second capacitor . The set values of the DC voltages of the two modules can be kept consistent, and the voltage stresses of all the switching devices in the H-bridge conversion circuit are also evenly distributed. In the asymmetric working mode, photovoltaic power generation systems and DC input sources such as energy storage and batteries can all be used as the power supply of the proposed topology for direct power conversion.

[0055] In this embodiment, in the case of no auxiliary voltage equalization circuit, let the DC voltage of the first H-bridge conversion circuit be , the DC voltage of the second H-bridge conversion circuit be , the capacitance values of the first capacitor and the second capacitor are both , the switching devices output waveforms according to single-polarity SVPWM modulation, and the switching frequency is . The modulation degree of AC-DC conversion is , and the frequency is 50 Hz. The value of the AC filter inductor is , and the load resistance value is . Under normal modulation conditions, the output voltage of the cascaded H-bridge inverter after passing through the low-pass filter can be approximated as the fundamental component, so the AC current is:

[0056]

[0057] Under unipolar SVPWM modulation, the output voltage of the second H-bridge conversion circuit is or 0 (depending on the switching state). Its modulation wave is synchronized with the first H-bridge conversion circuit, so the instantaneous power of the second H-bridge conversion circuit is:

[0058]

[0059] Since is a PWM wave and its fundamental component is , the average discharge power of the second H-bridge conversion circuit is:

[0060]

[0061] Among them, is a power frequency cycle.

[0062] When the second capacitor functions as a load, at this time, the electric energy <� stored in the second capacitor can be maintained for the following time:

[0063]

[0064] It can be seen from Equation (4) that the discharge time is proportional to the capacitance value of the capacitor and the load (the larger the capacitor or the smaller the load, the slower the discharge). It is inversely proportional to the square of the modulation degree (the deeper the modulation, the faster the discharge). This is the main reason why the power supply module will quickly lose electric energy when the modulation degree of the asymmetric cascaded topology without the auxiliary voltage equalization circuit is greater than 0.5. Since the capacitor cannot provide long-term active power support, most of the redundant vector points in the vector plane cannot be used. In the asymmetric working mode, even if most of the vector points are discarded, there is still a serious power imbalance problem. This will cause the electric energy of the capacitor to quickly drain when the 2E level works for a long time and cannot be replenished at the 0E level, resulting in the converter being unable to work properly.

[0065] Another embodiment of the present application also discloses a modulation method for the auxiliary voltage equalization circuit of an asymmetric cascaded inverter, which is applied to the auxiliary voltage equalization circuit of the above-mentioned asymmetric cascaded inverter, as Figure 6 shown, and includes the following steps:

[0066] S1. Define the inverter switching function, construct a three-dimensional vector space, and obtain the modulation vector points .

[0067] When the switching device is 1, it means the device is conducting, and when it is 0, it means the device is off. Define the inverter switching function :

[0068]

[0069] Among them, represents the th H-bridge conversion circuit, and the switching devices are complementary conducting, and the switching devices are complementary conducting. And represent two different switching paths when the AC ports are both at 0 level. Then, the overall modulation switching function of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter proposed in the embodiment of the present application will generate 32 possible switching combinations, and the switching combinations involve physically unacceptable switching combinations and some unavailable operating modes.

[0070] In the cascaded inverter structure, if a module loses power support, it cannot operate normally according to the traditional H-bridge circuit working mode. Limited by the topological structure, the traditional method cannot achieve the voltage balance of the proposed H-bridge structure, and the auxiliary circuit will bring the problem of non-isolation of AC and DC powers, introducing additional problems in some modes. As Figure 2 shown, after the auxiliary circuit is connected, the circuit will have the situation of instantaneous short circuit of the inductor at several levels. After the inductor voltage instantaneously becomes 0, the current will instantaneously rise to discharge energy through the switch, causing some switching devices to be damaged due to a significant increase in current stress. At the same time, after the circuit is modified, in addition to the risk of damaged devices, in some modes, the load is completely powered by the passive module, which instead causes the voltage of the second module to drop faster.

[0071] It should be noted that the auxiliary voltage equalization circuit can switch to the working mode of the Boost circuit / Buck circuit during some working periods, and use the DC power supply of the first module to provide energy supplement for the second capacitor The switching devices of the H-bridge circuit dynamically adjust the energy flow direction, thereby maintaining the stability of the capacitor voltage of Module 2 under a high modulation degree. As Figure 3 shown, when the AC output is at the 0E level, the Boost circuit operates by closing the control switch . At this time, some switching tubes of the H-bridge act as equivalent switches to control the inductor charging and supplement the capacitor with active energy. Through a carefully designed switching combination, the DC-DC conversion circuit can operate at different duty cycles without disturbing the output characteristics of the AC side or causing an incorrect current path.

[0072] Based on the above analysis, a three-dimensional vector space as Figure 4 shown can be obtained. The space vector modulation proposed in this embodiment respectively establishes the X, Y, and Z axes with , , , and forms 32 space vector points with the values of , , . The traditional two-module cascaded H-bridge has only 9 space vector points (because there are no restrictions on the selection of redundant vectors on a short time scale, and some paths are regarded as equivalent and grouped together). The vector space of this embodiment has a completely different effect due to the addition of the auxiliary circuit, thus resulting in a fundamental change. The following is illustrated by examples of unavailable working paths and available working paths:

[0073] It can be seen from the three-dimensional vector space of this embodiment that the 32 vector points all represent an independent current path. Divided by the port level of the AC side, there are 2 vector points at the -2E level, 8 vector points at the -E level, 12 vector points at the 0E level, 8 vector points at the E level, and 2 vector points at the 2E level. According to the basic principle of space vector modulation, different vectors can be selected for synthesis in the 4 intervals of -2E level and -E level, -E level and 0E level, 0E level and E level, and E level and 2E level within one power frequency cycle. Traversing all the selections, there are: 2 * 8 * 12 * 8 * 2 = 3072 kinds. That is to say, if the vector space paths of the circuit in this embodiment are not screened and planned, there will be 3072 combined paths, far exceeding the conventional two-module cascaded converter (the traditional two-module cascaded converter has a total of 1 * 4 * 6 * 4 * 1 = 96 kinds).

[0074] As Figure 2 known, not all vector points (working paths) are beneficial to the operation of the circuit, and some working paths may damage the switching devices. Therefore, when designing the space vector modulation algorithm, it is necessary to screen the vector paths, which is not only a simplification of the modulation algorithm but also an important step to ensure the normal operation of the circuit. As Figure 4As shown. In the synthesis interval of -2E level and -E level, the synthesis path of can select from [-1, -1, 0] to [-1, 0–, 0] instead of from [-1, -1, 0] to [0+, -1, 0]. The reason is that the power consumption of the load independently borne by the module 2 without power supply will cause the module 2 to quickly lose power. When the auxiliary circuit needs to supplement power for the module 2, even if the AC side ports are all at -E level, it is not allowed to jump from [-1, 0–, 0] to [0+, -1, 1] because the path corresponding to the point [0+, -1, 1] is Figure 2 the unavailable working path of Figure 2 .

[0075] When jumping to the synthesis interval of -E level and 0E level, there are 24 selectable path combination methods in total. Figure 4 (a) lists two unavailable paths (path ① and ②), and a selectable path (path ③). The vector point [1, -1, 1] passed by path ① will have a path where the inductor is directly short-circuited, and there may be risks beyond expectations during the operation of the circuit. The vector point [0+, 0+, 1] passed by path ② will not only have a path where the inductor is directly short-circuited, but also put the power supply in a bypass state, wasting the opportunity to supplement power for the module 2. The vector point [0–, 0–, 1] passed by path ③ is completely different. It can not only construct the Boost circuit mode while ensuring the AC output, but also make the inductor of the auxiliary circuit work in a safe state. It can be seen from this that based on the structure proposed in this embodiment, each vector will have an independent contribution to the AC side and the DC side within the switching period. The traditional two-module cascaded converter only focuses on the impact on the AC side within the switching period, so [0+, 0+, 0] and [0-, 0-, 0] are called "redundant vectors" and can play an equivalent role. Based on the structure proposed in this embodiment, [0+, 0+, 1] and [0-, 0-, 1] are no longer equivalent.

[0076] The vector synthesis of 0E level and E level, and E level and 2E level is similar to the above process, and there will be paths that are hoped to be avoided at some vector points. For example, there are unavailable vector points from the vector point [0–, 0–, 1] to the vector point [1, 0+, 1] and then to the vector point [0+, 1, 0]. If the unavailable vector synthesis working path frequently appears during the vector selection process, not only the converter cannot work properly, but also the safety of the equipment will be threatened.

[0077] To make the converter work properly, an available working path must be selected. As Figure 4 (b) shown, in the synthesis interval of -2E level and -E level, The synthesis path can be selected from [-1, -1, 0] to [-1, 0–, 0], and then in the synthesis interval of -E level and 0E level, The synthesis path can be selected from [-1, 0–, 0] to [-1, 0+, 1]. This vector point is defined as point A1, corresponding to the inductor energy storage working mode of the Boost circuit, which is Figure 3 the -E level current path shown in (b). Point A0 is the inductor energy storage working mode of the Boost circuit at 0E level. Point B1 corresponds to the boost working mode of the Boost circuit at -E level, and point B0 corresponds to the boost working mode of the Boost circuit at 0E level. The path diagram of point B0 is as Figure 3 shown in (a).

[0078] Obviously, in the synthesis interval of -E level and 0E level, the synthesis path can not only be selected from [-1,0–, 0] to [-1, 0+, 1] (point A1), but also from [-1, 0–, 0] to [-1, 0–, 1] (point B1), Figure 4 (b) only shows one of the multiple paths. In terms of path arrangement, simply selecting a certain point at -E level and a certain point at 0E level cannot ensure the normal operation of the entire converter. According to the control requirements of the DC voltage, the Boost circuit needs a "suitable duty cycle". However, the working time of the upper and lower synthesis vectors in space vector modulation is also fixed. This introduces a conflict between the AC and DC control objectives. In this embodiment, according to the path alternation, part of the DC voltage control accuracy is sacrificed to achieve the optimal overall performance.

[0079] Specifically, at both -E level and 0E level, the inductor energy storage working mode can be selected, and the boost working mode of the Boost circuit can also be selected. This means that when the -E level and 0E level alternate on the AC side, the DC side can be independently controlled through decoupling. Figure 4 Path ① in (b) represents the synthesis path of from point A1 to point B0 and then to point A1. This is a conventional path selection method, and one synthesis of the upper and lower vectors and one operation of the boost circuit can be completed within one Ts period. Figure 4 Path ② + Path ③ in (b) represents the synthesis path of from point A1 to point A0 and then to point B1. Only one synthesis of the upper and lower vectors and one inductor energy storage operation of the boost circuit can be completed within one period, and a complete operation of the boost circuit can only be completed after adding another period.

[0080] Accordingly, within the synthesis range of the 0E level and the E level, path ④ can be selected, that is, the synthesis path of [S1, S2, Tx] can be selected from [0–, 0+, 1] to [1, 0–, 1]. Within the synthesis range of the E level and the 2E level, [1, 0–, 1] to [1, 0–, 0] and then to [1, 1, 0] can be selected.

[0081] S2. Initialize the modulation vector points and assign to be , and obtain the AC sinusoidal modulation wave reference signal input by the controller (when verifying the modulation algorithm, a sine wave with a fixed amplitude can be input by oneself as the control signal), and determine the DC control signal according to the DC voltage.

[0082] S3. Pre-charge the second module capacitor through the power supply to stabilize the DC voltage of the second module. From the working path shown in Figure 4 (b), it can be seen that at the moment of 0E level, the AC output is 0, but two vector points A0 and B0 can construct a Boost working circuit. The voltage of the second module can be controlled and stabilized through the Boost circuit, and then calculate the voltage difference between the second module and the target voltage as the basis for subsequent control.

[0083] S4. Select the synthesized basic level vectors through the AC sinusoidal modulation wave reference signal and , and according to the volt-second balance principle, the formula for vector synthesis is:

[0084]

[0085] where is the switching period of the reference signal , is the working time of , is the working time of . is determined by , is determined by , is 's rounding function.

[0086] The action time of the vector is:

[0087]

[0088]

[0089] Define For the total number of port voltage levels, it can be obtained that , at enter at the rising edge of the working time of the vector. At this time , at the falling edge of .

[0090] S5. When S3 and S4 are completed, the inverter is ready for inversion and loading. According to the modulation index requirement of the system, it can be selected whether to turn on the auxiliary voltage balancing circuit. Based on the above analysis, when the modulation index is less than a certain value, self-balancing can be achieved. In this embodiment, it can be clearly seen that when the modulation index < 0.635, there is no need to balance the voltage through an auxiliary hardware circuit. When the modulation index > 0.635, it is necessary to use the auxiliary circuit and the modulation algorithm proposed in this embodiment to ensure that the DC voltage of the second module is in a stable state (maintaining the same level as the power supply voltage).

[0091] If the auxiliary voltage balancing circuit is not started, at this time , based on the obtained by S4, judge the power distribution under each level state. The principle of power distribution is: screen out the working modes in which AC and DC do not interfere with each other from the finite set of current paths, and select the vector with the strongest power output ability to achieve the voltage stability of the passive module.

[0092] Use to represent the port voltage corresponding port level value of the th H-bridge conversion circuit, represents the DC voltage value of the th H-bridge conversion circuit, represents the AC current value, represents the th DC load value of the H-bridge conversion circuit. The first capacitor of the first H-bridge conversion circuit and the second capacitor of the second H-bridge conversion circuit have the same capacitance value of . Through the charge balance formula of the two capacitors, the unified formula under different port levels is obtained as:

[0093]

[0094] It can be seen that the selection of the port active vector determines the discharge speed of the capacitor voltage. From the inverter cascaded topology structure of this application, the level ranges of the first module and the second module are both -1 to 1, that is, there is , then needs to meet the following conditions:

[0095]

[0096] in, is the voltage deviation value of the first capacitor, is the voltage deviation value of the second capacitor.

[0097] Will The corresponding level is converted into .when Or -1, and Can be directly converted when =0, To avoid unavailable state, select 0 + or 0 – In theory, In the case of select 0 + or 0 – is equivalent, which is consistent with the traditional two-module cascade rectifier. Switch from 0 to 1 and select a combination that can operate normally in both states. The conversion principle and same.

[0098] If the auxiliary voltage equalizing circuit is started, , obtained based on S4 Determine the power allocation for the current power level and remove unavailable paths for each power level. This requires determining whether the voltage difference between the current moment (time k) and the previous moment (time k-1) is moving in the correct direction to reduce the DC voltage gap.

[0099] like , indicating that the current voltage equalization path selection is effective, so there is no need to select the inductor Store too much energy (the energy of the second module capacitor is mainly transferred through the inductor Obtain). Determine the space vector modulation duty cycle by comparing the value of the triangle wave, and let the duty cycle D>0.5 be selected as The energy release path is selected so that the duty cycle D<0.5 The path to energy storage.

[0100] like This indicates that the current voltage equalization path selection needs to be improved. It is necessary to increase the energy stored in the inductor Lx (the energy of the capacitor in module 2 is mainly transferred through the inductor Here we need to determine whether the DC switching cycle is Extension for , under normal operating conditions, it is preferably not to perform cycle extension. The implementation complexity of the cycle extension algorithm is higher and it is only used in extremely urgent situations. If cycle extension is not performed, the duty ratio of space vector modulation is determined by comparing with a triangular wave. Let the duty ratio D>0.5 be selected as the path of energy storage, and let the duty ratio D<0.5 be selected as the path of energy release; if cycle extension is performed, then in the first it is all selected as the path of energy storage, and in the second when D>0.5, it is the path of energy storage, and the remaining duty ratio D<0.5 is selected as the path of energy release.

[0101] Based on the analysis of Figure 4 , when the working path is determined, the value of can be determined. It should be noted that selecting each different value of 1, -1, 0+, 0– will produce different modulation effects.

[0102] S6. Convert the modulation vector sequence into the PWM pulse sequences of the first H-bridge conversion circuit, the second H-bridge conversion circuit, and the controllable switch , and output them to the corresponding switching devices.

[0103] Based on S5, a complete vector sequence can be output. and are composed of each switch in one bridge arm. According to the switch function definition in Equation (5), it is converted into the on / off output rules of each switching device. After determining the device signals of each switch and combining with the action time calculated by S4, the PWM pulse sequence that can be allocated to each switch can be formed.

[0104] Based on the above embodiments, an embodiment of the present application also proposes an auxiliary circuit connection method extended to N modules, and its structure is as Figure 6 shown. Compared with Figure 1 , Figure 6 the second module in includes multiple cascaded second H-bridge conversion circuits. A capacitor is connected in parallel to the DC side of each second H-bridge conversion circuit, and each second H-bridge conversion circuit is connected with an auxiliary voltage equalization circuit. After all the auxiliary voltage equalization circuits are connected in series, they are connected to the DC power supply Figure 1 shown in the circuit is the basic circuit of two modules. When the user needs to increase the number of cascades, the first module remains unchanged as the basic module, and the number of second H-bridge conversion circuits and auxiliary voltage equalization circuits in the second module is increased.

[0105] In a specific embodiment, the feasibility of the proposed scheme for assisting voltage balancing under high modulation index conditions was verified on the Matlab / Simulink platform. The simulation settings are as follows:

[0106] 1. The maximum power output vector selection method was used to simulate a traditional two-module cascaded inverter, and the power supply of the second module was removed at time t1.

[0107] 2. The auxiliary voltage balancing circuit was inserted at time t2, and the proposed auxiliary voltage balancing modulation method was applied.

[0108] Figure 7 The following is the result under these simulation settings. The specific analysis is as follows:

[0109] From 0 to t1: The inverter operates normally and the system works stably.

[0110] From t1 to t2: The second module loses power. If traditional SPWM or SVPWM is used, it will cause the power supply voltage to drop rapidly. In a traditional cascaded inverter, the two modules alternately provide power support for the load. The reasons for the drop have been analyzed in formulas (1)-(4). Using the maximum power output vector method can delay the dropping trend, but it cannot prevent the continuous voltage drop. While the voltage of the second module drops, the inverter port voltage shows asymmetric distortion, and a large amount of harmonics will be injected into the grid instantaneously by the grid-connected current. Under extreme conditions, the strongest vector modulation can make a certain module share most of the power. However, when the second module loses the support of the DC power supply, the modulation index of the inverter cannot be higher than 0.635, otherwise the inverter will face collapse.

[0111] After t2, the auxiliary voltage balancing method proposed in this embodiment was applied, and the breakthrough of single DC power supply inverting high AC voltage was achieved by adding an auxiliary circuit and voltage balancing modulation. As Figure 7 shown, when the method proposed in the present invention is adopted, the power supply voltage will gradually recover to the set value, and the AC port voltage and AC current will return to normal. After applying the present invention, the modulation index limit of the traditional inverter is broken through, and stable operation is maintained under high modulation index (≥0.8) conditions with only one DC power supply.

[0112] The above has shown and described the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. An auxiliary voltage balancing circuit for an asymmetric cascaded inverter, characterized in that Comprising a cascaded first module and second module, the first module includes a first H-bridge conversion circuit, a DC power supply and a first capacitor , the DC power supply is connected in parallel with the first H-bridge conversion circuit, and the first capacitor is connected in parallel on the DC side of the first H-bridge conversion circuit. The second module includes a second H-bridge conversion circuit, an auxiliary voltage equalization circuit, and a second capacitor , the second capacitor is connected in parallel on the DC side of the second H-bridge conversion circuit, and the auxiliary voltage equalization circuit is connected to the second H-bridge conversion circuit and the DC power supply ; The first H-bridge conversion circuit and the second H-bridge conversion circuit are cascaded, and an AC filtering inductor is connected to the output port after cascading and a load ; The auxiliary voltage equalizing circuit includes a series-connected DC filter inductor and a controllable switch . One end of the DC filter inductor is connected to the positive terminal of the DC power supply . The other end of the DC filter inductor is connected to one end of the controllable switch . The other end of the controllable switch is connected to the positive terminal of the second capacitor .

2. The auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 1, characterized in that, Both the first H-bridge conversion circuit and the second H-bridge conversion circuit include a first bridge arm and a second bridge arm connected in parallel. The midpoint a1 of the first bridge arm of the first H-bridge conversion circuit is connected to the midpoint b2 of the second bridge arm of the second H-bridge conversion circuit. The midpoint b1 of the second bridge arm of the first H-bridge conversion circuit is connected to an AC output port. The midpoint a2 of the first bridge arm of the second H-bridge conversion circuit is connected to another AC output port through an AC filter inductor ​ 3. The auxiliary voltage equalizing circuit of the asymmetric cascaded inverter according to claim 1, characterized in that The second module includes a plurality of cascaded second H-bridge conversion circuits. A capacitor is connected in parallel to the DC side of each second H-bridge conversion circuit, and each second H-bridge conversion circuit is connected with an auxiliary voltage equalization circuit. After all the auxiliary voltage equalization circuits are connected in series, they are connected to the DC power supply connected.

4. A modulation method for an auxiliary voltage balancing circuit of an asymmetric cascaded inverter, characterized in that, The auxiliary voltage balancing circuit applied to the asymmetric cascaded inverter according to any one of claims 1-2 includes the following steps: S1. Define the inverter switching function, construct a three-dimensional vector space, and obtain the modulation vector points ; S2. Initialize the modulation vector points , and assign to be . Obtain the AC sinusoidal modulation wave reference signal input by the controller, and determine the DC control signal according to the DC voltage; S3. Precharge the second module capacitor through the power supply to stabilize the DC voltage of the second module and calculate the voltage difference between the second module and the target voltage ; S4. Select the synthesized basic level vector through the AC sine modulation wave reference signal and perform vector synthesis; S5. Determine whether to activate the auxiliary voltage equalization circuit based on the modulation index and obtain a complete modulation vector sequence ; S6. Convert the modulation vector sequence into the PWM pulse sequences of the first H-bridge conversion circuit, the second H-bridge conversion circuit, and the controllable switch and output them to the corresponding switching devices.

5. The modulation method of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to claim 4, characterized in that, The said S1 includes the following steps: When the switching device is 1, it indicates that the device is conducting, and when it is 0, it indicates that the device is off. Define the inverter switching function : Among them, represents the th H-bridge conversion circuit, is complementary conductive with the switching device, is complementary conductive with the switching device, and represent two different switching paths when the AC ports are all at 0 level, and the overall modulation switching function is ; Respectively with 、 、 to establish the X, Y, and Z axes, and with 、 、 the values of to form 32 spatial vector points to construct a three-dimensional vector space.

6. The modulation method of the auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 5, characterized in that The initialization method in S2 is: Assign to be .

7. The modulation method of the auxiliary voltage balancing circuit of the asymmetric cascaded inverter according to claim 6, characterized in that, The formula for vector synthesis in the said S4 is: Among them, is the switching period of the reference signal , is the working time of , is the working time of; The action time of the vector is: Definition For the total number of port voltage levels, it can be obtained that , at enters at the rising edge time of the working time of the vector. At this time , at at the falling edge time of .

8. The modulation method of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to claim 7, characterized in that, If the auxiliary equalizing circuit is not started in S5, then at this time , based on what is obtained in S4 judge the power distribution under each current level state. The principle followed by the power distribution is: screen out the working modes in which AC and DC do not interfere with each other from the finite set of current paths, and select the vector with the strongest power output ability to achieve the voltage stability of the passive module; Use to represent the port voltage of the th H-bridge conversion circuit, and the unified formula for different port levels is as follows: ​ Among them, is the DC voltage value of the th H-bridge conversion circuit, is the AC current value, is the DC load value of the th H-bridge conversion circuit. The first capacitor of the first H-bridge conversion circuit and the second capacitor of the second H-bridge conversion circuit both have a capacitance value of ; The level ranges of both the first module and the second module are from -1 to 1, that is, there exists , then the following conditions need to be satisfied: Among them, is the voltage deviation value of the first capacitor, is the voltage deviation value of the second capacitor; Convert the corresponding level into .

9. The modulation method of the auxiliary voltage equalization circuit of the asymmetric cascaded inverter according to claim 8, characterized in that, If the auxiliary voltage equalization circuit is started in S5, then , based on what is obtained in S4 judge the power distribution in the current level state and remove the unavailable paths in each level state; If , let the duty cycle D > 0.5 be selected as the path for Lx to release energy, and let the duty cycle D < 0.5 be selected as the path for energy storage; If , determine whether to extend the DC switching period from to . If the period is not extended, let the duty cycle D > 0.5 be selected as the energy storage path, and let the duty cycle D < 0.5 be selected as the energy release path; if the period is extended, then in the first , all are selected as the energy storage path, in the second , D > 0.5 is the energy storage path, and the remaining duty cycle D < 0.5 is selected as the energy release path.

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