Method for operating a power converter

Abstract

A method for operating a power converter is provided. The method includes operating the power converter in a reduced switching mode. The power converter includes: three input nodes, each configured to receive a respective one of three input voltages; two DC link nodes configured to provide a DC link voltage; a midpoint coupled to each of the two DC link nodes; three inductors, each inductor connected to a respective one of the three input nodes; and a rectifier bridge comprising three legs, each leg coupled to a respective one of the three input nodes through a respective one of the three inductors and connected to a respective one of the three inductors at a respective switch node, where each of the three legs is further connected to two DC link nodes and a midpoint, where the midpoint is connected to a respective one of the three inductors. And comprising at least one electronic switch. Operating the power converter in the reduced switching mode includes deactivating at least one of the three legs for a predefined period of time.

Description

[0001] This application is a divisional application of a Chinese invention patent application with an application date of March 13, 2020, an application number of 202010173723.7, and an application title of "Method for Operating a Power Converter". Technical Field

[0002] The present disclosure generally relates to methods for operating a power converter. Background Art

[0003] Efficient power conversion using an electronic power converter is an important issue in many electronic applications. For example, charging the battery of an electric vehicle requires efficient power conversion, and this is becoming increasingly important as the number of various electric vehicles (cars, bicycles, scooters, etc.) is expected to increase in the coming years. In this type of application, as well as in any other type of power conversion application, it is desirable to keep the losses associated with power conversion as low as possible, that is, to keep the losses occurring in the power converter and associated with operating the power converter as low as possible. Summary of the Invention

[0004] One example relates to a method. The method includes operating a power converter in a reduced switching mode. The power converter includes three input nodes, each configured to receive a respective one of three input voltages; two DC link nodes configured to provide a DC link voltage; and a midpoint coupled to each of the two DC link nodes. Additionally, the power converter includes three inductors, each inductor connected to a respective one of the three input nodes; and a rectifier bridge including three bridge arms. Each bridge arm is coupled to a respective one of the three input nodes through a respective one of the three inductors and is connected to a respective one of the three inductors at a respective switching node. Each of the three bridge arms is also connected to the two DC link nodes and the midpoint and includes at least one electronic switch. Operating the power converter in a reduced switching mode includes deactivating at least one of the three bridge arms during a predefined time period. Description of the Drawings

[0005] Examples are explained below with reference to the drawings. These figures are used to illustrate certain principles and thus only show aspects necessary for understanding these principles. These drawings are not drawn to scale. In the figures, the same reference numerals denote similar features.

[0006] Figure 1 A circuit diagram of a power converter having a Vienna rectifier topology is shown;

[0007] Figure 2 A signal diagram of the input voltage of a power converter according to one example is shown;

[0008] Figure 3 Shows in more detail Figure 1 An example of a power converter of the type shown;

[0009] Figure 4 Shows a signal diagram that shows operating the power converter in a conventional manner;

[0010] Figure 5 Shows that can be used in Figure 3 An example of a bidirectional blocking switch in the power converter shown;

[0011] Figure 6 Shows a control circuit configured to operate the power converter according to Figure 4 The method shown to operate the power converter;

[0012] Figures 7A-7F Shows Figure 1 Different examples of the bridge arms of a bridge rectifier in a power converter of the type shown;

[0013] Figure 8 Shows a signal diagram that shows operating the power converter in a reduced switching mode (1 / 3 mode) according to an example;

[0014] Figure 9 Shows a power converter device having a first power converter and a second power converter, wherein according to Figure 8 And Figure 9 The method shown to operate the second power converter;

[0015] Figure 10 Shows an example of a control circuit configured to operate the power converter device such that according to Figure 8 And Figure 9 The method shown to operate the first power converter;

[0016] Figure 11 Shows an example of a second power converter including two converter stages;

[0017] Figure 12 Shows a control circuit configured to operate a second power converter according to Figure 11 ;

[0018] Figure 13 Shows a signal diagram that shows in more detail operating the power converter in Figure 9 The reduced switching mode shown;

[0019] Figure 14 Shows Figure 13 A modification of the control circuit shown;

[0020] Figure 15shows a signal diagram that shows operation in full 1 / 3 mode, partial boost mode, and full 3 / 3 mode Figure 10 of the power converter device shown;

[0021] Figure 16 shows Figure 15 the different operating modes shown in, which depend on the DC link voltage required during one of six operating phases;

[0022] Figure 17 shows another example of a control circuit configured to operate a second power converter according to Figure 11 ;

[0023] Figure 18 shows an example of a power converter device including a balancing circuit;

[0024] Figure 19 shows an example of a balancing circuit;

[0025] Figure 20 shows a signal diagram that shows operation of the power converter in 2 / 3 mode or 3 / 3 mode;

[0026] Figure 21 shows Figure 20 the different operating modes shown in, which depend on the DC link voltage during one of six operating phases;

[0027] Figure 22 shows a signal diagram of the power converter operating in 2 / 3 mode or 3 / 3 mode at different DC link voltages;

[0028] Figure 23 shows an example of a control circuit configured to operate the power converter in 2 / 3 mode or 3 / 3 mode;

[0029] Figure 24 shows operation of the power converter in one of 1 / 3 mode, 2 / 3 mode, or 3 / 3 mode depending on the DC link voltage during one of six operating phases; and

[0030] Figure 25 shows a signal diagram of the power converter operating in 1 / 3 mode, 2 / 3 mode, or 3 / 3 mode at different DC link voltages. Detailed Description

[0031] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the specification and, for purposes of illustration, show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically stated.

[0032] Figure 1 shows a circuit diagram of a power converter 10 known as a Vienna rectifier, which is a switched-mode three-phase (3Ф) AC-DC power converter. The power converter includes: an input having three input nodes A, B, C, each input node being configured to receive a respective one of three input voltages V1, V2, V3; two DC link nodes X, Z configured to provide a DC link voltage V4 therebetween; and a midpoint Y coupled to each of the two DC link nodes X, Z. Each of the three input voltages V1, V2, V3 is a voltage between a respective input node A, B, C and a common ground node N. The power converter also includes three inductors L1, L2, L3, each inductor being coupled to a respective one of the three input nodes A, B, C. In Figure 1 the example shown, the inductors L1, L2, L3 are directly coupled to the inputs A, B, C. However, this is merely an example. According to another example (not shown), an input filter is connected between the inputs A, B, C and the inductors L1, L2, L3.

[0033] Reference Figure 1 , the power converter also includes a rectifier bridge 1 having three bridge arms 11, 12, 13. Each of the three bridge arms 11, 12, 13, only schematically shown in Figure 1 , includes at least one electronic switch Q1, Q2, Q3 and is connected to a respective one of the three inductors L1, L2, L3 such that each of the bridge arms 11, 12, 13 is coupled to a respective one of the three input nodes A, B, C through a respective one of the three inductors L1, L2, L3. Additionally, each of the three bridge arms 11, 12, 13 is connected to the two DC link nodes X, Z and the midpoint Y.

[0034] As shown, the midpoint Y can be coupled to the first DC link node X of the two DC link nodes X, Z via a first capacitor C1 and to the second DC link node Z of the two DC link nodes X, Z via a second capacitor C2. Hereinafter, the voltage VC1 across the first capacitor C1 is referred to as the first capacitor voltage, and the voltage VC2 across the second capacitor C2 is referred to as the second capacitor voltage.

[0035] According to one example, the input voltages V1, V2, V3 received by the power converter are AC input voltages such as sinusoidal input voltages. The phase shift between each pair of these input voltages V1, V2, V3 can be 120°. Figure 2Shows the signal diagrams of the sinusoidal input voltages V1, V2, V3 during one period of each of these input voltages V1, V2, V3. In this example, the phase shift between each pair of these input voltages V1 - V3 is 120° (2π / 3). Each of the three sinusoidal input voltages V1 - V3 periodically varies between a minimum voltage level and a maximum voltage level, where in this example the maximum voltage level is a positive voltage level and the minimum voltage level is a negative voltage level. According to one example, the magnitude of the minimum level is substantially equal to the magnitude of the maximum level, and the three input voltages V1 - V3 have substantially the same minimum voltage level and the same maximum voltage level. Additionally, the three input voltages V1 - V3 can have substantially the same frequency, where the frequency is, for example, between 50 Hz and 60 Hz.

[0036] Figure 2 Shows the input voltages V1, V2, V3 depending on the phase angle. Hereinafter, the multiple input voltages V1, V2, V3 are also referred to as the input voltage system. Additionally, for illustrative purposes, it is assumed that a specific phase angle α of the input voltage system corresponds to the phase angle α of the first input voltage V1, where α = 0 is the phase angle at the start of the positive half - wave of the first input voltage V1.

[0037] The magnitudes A1, A2, A3 of the maximum voltage level and the minimum voltage level of each input voltage V1, V2, V3 can also be referred to as the amplitudes of the respective input voltages V1, V2, V3. The root - mean - square (RMS) value A1 of the input voltage RMS 、A2 RMS 、A3 RMS is obtained by dividing the amplitude by the square root of 2, i.e., where A represents the amplitude of any one of the three input voltages V1, V2, V3, and where A RMS represents the respective RMS value. According to one example, each of the three input voltages V1, V2, V3 is a 230V RMS grid voltage, i.e., A RMS = A1 RMS = A2 RMS = A3 RMS = 230V RMS . In this example, the amplitude is given by A = A1 = A2 = A3 = 325V.

[0038] At each stage of a cycle of the three input voltages V1, V2, and V3, one of the three input voltages has the highest (positive) voltage level among the three input voltages V1, V2, and V3, and one of the three input voltages has the lowest (negative) voltage level among the three input voltages V1, V2, and V3. Among them, in each cycle, during a specific time period, each of the three input voltages V1, V2, and V3 has the highest level, and each of the three input voltages V1, V2, and V3 has the lowest level. The difference between the highest voltage level and the lowest voltage level is called the line-to-line voltage V LL 。 Associated with Figure 2 the input voltages V1, V2, and V3 shown in LL is also shown in Figure 2 。 It can be seen that the line-to-line voltage is periodic, where the duration of one cycle of the line-to-line voltage V LL is 1 / 6 of the duration of one cycle of the input voltages V1, V2, and V3. In other words, one cycle of the input voltages V1, V2, and V3 includes a phase angle from 0° to 360° (0 to 2π), while one cycle of the line-to-line voltage V LL ranges within 60° of one cycle of the input voltages V1, V2, and V3. The maximum value of the line-to-line voltage V LL_MAX , also referred to as the maximum line-to-line voltage hereinafter, is given by the square root of 3 multiplied by the amplitude A of the three input voltages, that is For example, in an input voltage system with three 230V RMS input voltages V1, V2, and V3, the maximum line-to-line voltage V LL_MAX is 563V.

[0039] Operation Figure 1A power converter of the type shown may include (a) regulating the DC link voltage V4 to have a predefined voltage level, and (b) regulating each of the three input currents I1, I2, I3 to have a current waveform that is substantially the same as the waveform of the respective input voltages V1, V2, V3. Thus, when the input voltages V1, V2, V3 are sinusoidal voltages, these input currents I1, I2, I3 are substantially sinusoidal in waveform. Regulating each input current I1, I2, I3 may include regulating the inductor voltages VL1, VL2, VL3 across the respective inductors L1, L2, L3, where regulating the inductor voltages VL1, VL2, VL3 may include regulating the voltages VA', VB', VC' at circuit nodes A', B', C' disposed between the inductors L1, L2, L3 and the bridge arms 11, 12, 13. Hereinafter, these circuit nodes A', B', C' are referred to as the switching nodes of the bridge arms 11, 12, 13, and the voltages VA', VB', VC' at these switching nodes are referred to as the switching node voltages, where these voltages VA', VB', VC' are referenced to a common ground node N. Hereinafter, reference is made to Figure 3 and Figure 4 explain an example of a method for regulating the inductor voltages VL1, VL2, VL3 to regulate the input currents I1, I2, I3.

[0040] Figure 3 shows Figure 1 a power converter of the type shown, where the bridge arms 11, 12, 13 are implemented according to a specific example. (Further examples for implementing the inductor voltages VL1, VL2, VL3 are explained hereinbelow). Figure 4 shows a signal diagram of the signals that occur in the power converter during one cycle of the input voltages V1, V2, V3. In Figure 3 the example shown, each bridge arm 11, 12, 13 includes electronic switches Q1, Q2, Q3 connected between the respective switching nodes A', B', C' and the midpoint Y, first rectifier elements D11, D21, D31 connected between the respective switching nodes A', B', C' and the first DC link node X, and second rectifier elements D12, D22, D32. The electronic switches Q1, Q2, Q3 may be implemented as bidirectional blocking switches. A "bidirectional blocking switch" is a switch that is capable of blocking current regardless of the polarity of the voltage applied to the electronic switch.

[0041] Figure 5An example of a bidirectional blocking switch is shown. In this example, the electronic switch Q (where Q represents any one of the switches Q1, Q2, Q3) includes two MOSFETs (metal oxide semiconductor field effect transistors) connected in series such that the integrated body diodes are connected in a back-to-back configuration. That is, these MOSFETs are connected in series such that the body diodes integrated in these MOSFETs either connect their anodes or connect their cathodes. The two MOSFETs can be driven by the same drive signal S (where S represents any one of the drive signals S1, S2, S3 received by the switches Q1, Q2, Q3). However, implementing the bidirectional switches Q1, Q2, Q3 in the Figure 5 way shown is only an example. Any other type of bidirectional electronic switch, such as a HEMT (high electron mobility transistor), can also be used.

[0042] Referring Figure 3 to, the first and second rectifier elements D11 - D32 can be implemented as passive rectifier elements such as diodes. However, this is only an example. Active rectifier elements, such as MOSFETs operating as synchronous rectifiers, can also be used.

[0043] In Figure 3 the example shown, the first rectifier elements D11, D21, D31 are configured to implement (positive) current flow from the respective switch nodes A', B', C' to the first DC link node X, and the second rectifier elements D12, D22, D32 are configured to implement (positive) current flow from the second DC link node Z to the respective switch nodes A', B', C'. That is, in Figure 3 the example shown, the cathodes of the diodes forming the first rectifier elements D11, D21, D31 are connected to the first DC link node X, and their anodes are connected to the respective switch nodes A', B', C', and the anodes of the diodes forming the second rectifier elements D12, D22, D32 are connected to the second DC link node Z, and their cathodes are connected to the respective switch nodes A', B', C'.

[0044] Referring to the above, controlling the currents I1, I2, I3 through each inductor L1, L2, L3 includes controlling the voltages VL1, VL2, VL3 across the respective inductors L1, L2, L3. Each inductor voltage VL1, VL2, VL3 is given by subtracting the respective switch node voltages VA', VB', VC' from the respective input voltages V1, V2, V3. The input voltages V1, V2, V3 are predefined by a voltage source (such as the power grid) and can be measured, so that the inductor voltages VL1, VL2, VL3 and thus the inductor currents I1, I2, I3 can be adjusted by adjusting the switch node voltages VA', VB', VC'. This will be explained below with reference to Figure 4 This will be explained.

[0045] Figure 4 Shown are the drive signals S1, S2, S3 of the electronic switches Q1, Q2, Q3, the sinusoidal input voltages V1, V2, V3 and the corresponding input currents I1, I2, I3, which are substantially sinusoidal. Figure 4 Further shown are the currents ID11, ID12 through the first rectifier element D11 and the second rectifier element D12 in the first leg 11 of the leg 11, 12, 13, the current IQ1 through the electronic switch Q1 in the first leg 11 and the voltage VQ1 across the electronic switch Q1 in the first leg 11.

[0046] For the purpose of explanation, it is assumed that the power converter is in a steady state, in which the DC link voltage V4 has reached the desired voltage level and the power consumption of the load Z (as shown by the dashed line in Figure 3 ) connected to the DC link nodes X, Z is constant. The load can be any load, including a load containing another power converter. Referring to Figure 4 , the power converter can operate in continuous conduction mode (CCM), i.e., during each of the positive and negative half-cycles of the respective input voltages V1, V2, V3, the inductor currents I1, I2, I3 do not decrease to zero. (When the respective input voltages V1, V2, V3 cross zero, the input currents I1, I2, I3 only become zero for a short period of time).

[0047] The current directions of the inductor currents I1, I2, and I3 depend on the instantaneous voltage levels of the input voltages V1, V2, and V3 and the midpoint voltage VY. The "midpoint voltage" VY is the voltage at the midpoint Y, which is not directly connected to the ground node N, and the "midpoint voltage" VY is referenced to the ground node N. The midpoint voltage VY or the negative value of the midpoint voltage -VY may also be referred to as the common-mode voltage VCM hereinafter. For illustrative purposes only, hereinafter, the negative value of the midpoint voltage VY will be referred to as the common-mode voltage VCM = -VY. The common-mode voltage VCM can be adjusted to be zero so that the potential of the midpoint is equal to the potential of the ground node. Alternatively, the common-mode voltage VCM can be adjusted to be different from zero and vary within one cycle of the input voltages V1, V2, and V3. In each of these cases, the inductor currents can be adjusted so that each inductor current I1, I2, and I3 is positive during the positive half-cycle of the corresponding input voltage V1, V2, and V3 and negative during the negative half-cycle of the corresponding input voltage V1, V2, and V3. Examples for adjusting the common-mode voltage VCM will be further explained in detail below.

[0048] The control of the input currents I1, I2, and I3 will be explained below with reference to controlling the current I1 through the first inductor L1 of the inductors L1, L2, and L3, which is the inductor connected to the first bridge arm 11. The adjustment of the other two input currents I2 and I3 among the input currents I1, I2, and I3 is implemented in the same way. Hereinafter, the input A coupled to the first bridge arm 11 will be referred to as the first input, the voltage V1 received at this input will be referred to as the first input voltage, the switching node A' of the first bridge arm 11 will be referred to as the first switching node, the inductor L1 connected to the first switching node A' will be referred to as the first inductor, and the voltage VL1 across the first inductor L1 will be referred to as the first inductor voltage VL1.

[0049] During the positive half-cycle of the first input voltage V1, the first inductor current I1 is positive, i.e., the inductor current flows in the direction indicated by the arrow in Figure 3 . In this case, the inductor current I1 flows through the first rectifier element D11 during the off-period of the first switch Q1 (i.e., after the first switch Q1 has been turned off). During the off-period of the electronic switch Q1, the voltage VA' at the first switching node A' is given by the voltage VX at the first DC link node X minus the voltage drop across the first rectifier element D11. However, this voltage drop across the first rectifier element is negligible, such that during the off-period of the first electronic switch Q1, the potential at the first switching node A' is substantially clamped at the voltage VX at the first DC link node X. This voltage VX is referenced to the ground node and will be referred to as the first DC link node voltage hereinafter.

[0050] During the negative half - wave of the first input voltage V1, the first inductor current I1 is negative, i.e., the inductor current flows in the direction opposite to the direction indicated by the arrow in Figure 3 As shown. In this case, the inductor current I1 flows through the second rectifier element D12 during the off - period of the first switch Q1. During the off - period of the electronic switch Q1, the potential at the first switch node A' is given by the voltage VZ at the second DC - link node Z minus the voltage drop across the second rectifier element D12. However, this voltage drop across the second rectifier element is negligible, such that during the off - period of the first electronic switch Q1, the potential at the first switch input node A' is essentially clamped at the voltage VZ at the second DC - link node Z. This voltage VZ is referenced to the ground node and is hereinafter referred to as the second DC - link node voltage.

[0051] In Figure 3 the power converter shown, depending on the polarity of the first input voltage V1 and the switching state of the first electronic switch Q1, the voltage VA' at the first switch node A' (and the other two switch nodes B', C') can have three different levels: (1) VA' = VY during the on - period of the electronic switch Q1; (2) VA' = VX during the off - period of the electronic switch Q1 and when the first input voltage V1 is positive, i.e., during the positive half - wave of the first input voltage V1; and (3) VA' = VZ during the off - period of the electronic switch Q1 and when the first input voltage V1 is negative, i.e., during the negative half - wave of the first input voltage V1.

[0052] The first DC - link node voltage VX is given by the first capacitor voltage VC1 minus the common - mode voltage VCM,

[0053] VX = VC1 - VCM (1a),

[0054] and the second DC - link node voltage VZ is given by minus one times the common - mode voltage VCM minus the second capacitor voltage VC2,

[0055] VZ = - VC2 - VCM=-(VC2 + VCM) (1b),

[0056] where, for illustrative purposes only, it is assumed that the common - mode voltage VCM is VN - VY, where VN is the potential at the ground node N and VY is the potential at the mid - point.

[0057] The common - mode voltage VCM can be positive or negative. In each case, the magnitude of the common - mode voltage VCM is lower than the magnitude of each of the first and second capacitor voltages, such that the first DC - link node voltage VX is positive and the second DC - link node voltage VZ is negative.

[0058] The voltage VL1 across the first inductor L1 is given by , where L1 represents the inductance of the first inductor L1. Therefore, when the inductor voltage VL1 is positive, the inductor current I1 increases; when the inductor voltage VL1 is negative, the inductor current I1 decreases; and when the inductor voltage VL1 is zero, the inductor current I1 remains constant. By appropriately switching the voltage VA' at the first switching node A' between two of the three voltage levels VX, VY, VZ, a first input current I1 can be generated such that it follows a sinusoidal waveform. During the positive half-cycle of the first input voltage V1, (a) the inductor current I1 increases during the conduction period of the first switch Q1, and (b) the inductor current I1 decreases during the off period of the first switch Q1. During the negative half-cycle of the first input voltage V1, (c) the inductor current I1 increases during the conduction period of the first switch Q1, and (d) the inductor current I1 decreases during the off period of the first switch Q1. In each case, when the average value of the inductor voltage VL1 over one conduction period and one off period of the first switch Q1 is positive, the inductor current I1 increases; and when the average value of the inductor voltage VL1 over one conduction period and one off period of the first switch Q1 is negative, the inductor current I1 decreases.

[0059] The electronic switch Q1 (and other switches Q2, Q3) can operate in a pulse-width modulation (PWM) mode at a fixed switching frequency f SW , where the fixed switching frequency f SW is significantly higher than the frequency of the first input voltage V1. For example, the switching frequency f SW is between a few kHz and several tens of kHz, and its range can reach several hundred kHz. To adjust the first switching node voltage VA', the duty cycle d1 of the operation of the first switch Q1 is varied, where, in each driving cycle, the duty cycle d1 is given by the relationship between the duration T ON of the conduction period of the electronic switch Q1 or the duration T OFF of the off period of the electronic switch Q1 and the duration T of one driving cycle, where the duration T of the driving cycle is given by the reciprocal of the switching frequency (T = 1 / f SW ). The duration T OFF of the off period of the electronic switch Q1 is given by subtracting the duration T ON of the conduction period from the duration T of the driving cycle, i.e., T OFF = T - T ON . For illustrative purposes only, it is assumed that the magnitude |d1| of the duty cycle d1 is given by the ratio of the duration T OFF of the off period to the duration T of the driving cycle, i.e.,

[0060] In addition, it is assumed that the duty ratio d1 can be positive or negative, where the duty ratio d1 is positive during the positive half-cycle of the first input voltage V1 and negative during the negative half-cycle of the first input voltage V1. For example, a duty ratio d1 = 0 indicates that the first switch Q1 is turned on during the corresponding drive cycle; a duty ratio d1 = 1 indicates that the first switch Q1 is turned off during the corresponding drive cycle in the positive half-cycle of the first input voltage V1; and a duty ratio d1 = -1 indicates that the first switch Q1 is turned off during the corresponding drive cycle in the negative half-cycle of the first input voltage V1. A positive duty ratio d1 different from one (1) or zero (0) represents the ratio of the duration of the on-time period to the off-time period in the drive cycle in the positive half-cycle of the first input voltage V1. Similarly, a negative duty ratio d1 different from 1 or 0 represents the ratio of the duration of the on-time period to the off-time period in the drive cycle in the negative half-cycle of the first input voltage V1.

[0061] Referring to the above, the first switch node voltage VA' is obtained by switching between the first DC link node voltage VX and the midpoint voltage VY or between the second DC link node voltage VZ and the midpoint voltage VY. Therefore, the first switch node voltage VA' is given by the average voltage at the first switch node A' during one drive cycle. For example, during the positive half-cycle of the input voltage V1, the first switch node voltage VA' is given by

[0062]

[0063] And for example, during the negative half-cycle of the input voltage V1, the first switch node voltage VA' is given by

[0064]

[0065] Therefore, by appropriately adjusting the duty ratio d1 of the first electronic switch Q1, the first switch node voltage VA' can be adjusted, and thus the first inductor voltage VL1 can be adjusted. On the other hand, based on the desired first switch node voltage VA' and the common-mode voltage VCM, the duty ratio d1 can be calculated. Referring to the above, the duty ratio d1 is given by the duration T OFF of the off-time period divided by the duration T of one drive cycle, and the duty ratio d1 is positive in the positive half-cycle of the first input voltage V1 and negative in the negative half-cycle of the first input voltage V1. Therefore, in Equation (2a) and in Equation (2b) Therefore, during the positive half-cycle, based on Equation (2a), the duty ratio d1 is given by

[0066]

[0067] Also, during the negative half-wave period, based on Equation (2b), the duty ratio d1 is given by

[0068]

[0069] The capacitor voltages VC1 and VC2 can be adjusted such that each of these voltages is 50% of the DC link voltage V4, i.e., VC1 = VC2 = V4 / 2. In this case, the duty ratio d1 can be calculated according to Equations (3a) and (3b) as follows

[0070]

[0071] Reference Figure 1 and Figure 3 , the power converter includes a control circuit 2, which is configured to operate at least one electronic switch Q1, Q2, Q3 in each of the bridge arms 11, 12, 13. More specifically, the control circuit 2 can be configured to generate drive signals S1, S2, S3 received by the electronic switches Q1, Q2, Q3 such that the DC link voltage V4 has a predefined voltage level and such that the inductor currents (input currents) I1, I2, I3 substantially have the same waveform as the input voltages V1, V2, V3. To this end, the control circuit 2 receives the DC link voltage signal S V4 , where the DC link voltage signal S V4 represents the DC link voltage V4. The DC link voltage V4 can be measured in a conventional manner by any kind of voltage measurement circuit (not shown) to obtain the DC link voltage signal S V4 . In addition, the control circuit 2 receives the input voltage signals S V1 , S V2 , S V3 , each representing a corresponding one of the input voltages V1, V2, V3, and receives the input current signals S I1 , S I2 , S I3 , each representing a corresponding one of the input currents I1, I2, I3. The input voltages V1, V2, V3 can be measured in a conventional manner to obtain the input voltage signals S V1 , S V2 , S V3 . In addition, the input currents I1, I2, I3 can be measured in a conventional manner to obtain the input current signals S I1 , S I2 , S I3 . Figure 6 An example of the control circuit 2 configured to generate the drive signals S1 - S3 is shown.

[0072] Figure 6 The control circuit 2 shown inV4 and a first filter 21 for the DC link voltage reference signal S V4_REF wherein the DC link voltage reference signal S V4_REF represents the desired voltage level of the DC link voltage V4. The filter 21 subtracts the DC link voltage reference signal S V4 from the DC link voltage signal S V4_REF and filters the difference to generate a DC link voltage error signal S V4_ERR . The filter (or controller) may have one of proportional (P) characteristics, proportional-integral (PI) characteristics, proportional-integral-derivative (PID) characteristics, etc. The multiplier 22 receives the DC link voltage error signal S V4_ERR and the DC link voltage reference signal S V4_REF where the output signal S22 of the multiplier 22 represents the desired output power of the power converter. The divider 23 divides the multiplier output signal S22 by a signal representing 1.5 times the square of the amplitudes of the input voltages V1, V2, V3 The output signal S23 of the divider 23 represents the total desired input current of the power converter, where the total desired input current is the input current required for the power converter to achieve the desired voltage level of the DC link voltage V4 defined by the DC link voltage reference signal S V4_REF .

[0073] Reference Figure 6 , the control circuit 2 further includes three branches, where each of these branches receives the divider output signal S23 and generates a corresponding one of the three drive signals S1, S2, S3. Each of these branches includes multipliers 241, 242, 243 which multiply the divider output signal S23 by the corresponding input voltage signals S V1 , S V2 , S V3 where the output signal of each of these multipliers 241, 242, 243 is an input current reference signal S I1_REF , S I2_REF , S I3_REF , that is, each of these signals S I1_REF , S I2_REF , S I3_REF represents the desired current level of a corresponding one of the input currents I1, I2, I3. Each of these reference signals S I1_REF , S I2_REF , S I3_REF is subtracted from the corresponding input current signal S I1 , S I2 , S I3。The output signals of each of these subtractors 251, 252, 253 are filtered by corresponding filters 261, 262, 263 connected downstream of the respective subtractors 251, 252, 253, where the output signals S VL1_REF 、S VL2_REF 、S VL3_REF represent the desired voltage levels of the corresponding ones of the three inductor voltages VL1, VL2, VL3. Another subtractor 271, 27 2、 273 subtracts the input voltage signals S VL1_REF 、S VL2_REF 、S VL3_REF from the corresponding inductor voltage reference signals S V1 、S V2 、S V3 to obtain the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF ,where each of these switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF represents the desired voltage level of the corresponding one of the three leg input voltages VA', VB', VC'.

[0074] Reference Figure 6 Each of the three branches that generate the drive signals S1, S2, S3 includes a PWM modulator 281, 282, 283 that receives a corresponding one of the leg input voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF ,where each of these modulators 281, 282, 283 is configured to generate a corresponding one of the drive signals S1, S2, S3 based on the respective reference signals S VA'_REF 、S VB'_REF 、S VC'_REF such that, in each drive cycle of at least one of the electronic switches Q1, Q2, Q3, the average value of the corresponding leg input voltage VA', VB', VC' is equal to the voltage level defined by the corresponding leg input voltage reference signal S VA'_REF 、S VB'_REF 、S VC'_REF . The specific implementation of the PWM modulators 281, 282, 283 depends on the type of legs 11, 12, 13 used in the power converter.

[0075] In a three-level power converter, i.e., using Figure 3 and Figures 7A-7CThe power converter implemented by the bridge arms shown, for example, each of the PWM modulators 281, 282, 283 can be configured to calculate the duty cycles d1, d2, d3 of the drive signals S1, S2, S3 based on one of the equations (3a), (3b), or (3c), and generate the drive signals S1, S2, S3 according to the calculated duty cycles.

[0076] Referring to these equations, by appropriately adjusting the duty cycles d1, d2, d3, not only can the switch node voltages VA', VB', VC' be adjusted, but also the common-mode voltage VCM can be adjusted. Basically, in order to obtain a sinusoidal current waveform, the first DC link node voltage VX must be equal to or higher than the highest voltage level of the three input voltages V1, V2, V3, and the second DC link node voltage VZ must be equal to or lower than the lowest voltage level of the three input voltages V1, V2, V3. For example, if it is desired that the common-mode voltage VCM is zero, then each capacitor voltage VC1, VC2 must be higher than the amplitudes of the three input voltages. Therefore, when the input voltages V1, V2, V3 are 230V RMS voltages, each capacitor voltage must be higher than 325V, so that the DC link voltage must be higher than 650V (= 2 × 325V). For example, if the DC link voltage is twice the amplitude of the input voltage and the common-mode voltage VCM is zero, then in the steady state, the duty cycles d1, d2, d3 defined by the equations (3a), (3b), and (3c) basically follow the corresponding input voltages V1, V2, V3.

[0077] However, in some cases, it may be desired to adjust the DC link voltage V4 to a voltage level lower than twice the amplitude of the input voltages V1, V2, V3. This can be achieved by appropriately adjusting the common-mode voltage VCM. In Figure 4 the example shown, the common-mode voltage VCM (not shown) has been selected to be equal to -(Vmax'+Vmin') / 2, where Vmax' represents the voltage level of the highest one of the three switch node voltages VA', VB', VC' at a specific moment, that is, Vmax' = max{VA'; VB'; VC'}, and Vmin' represents the lowest one of the three switch node voltages at a specific moment, that is, Vmin' = min{VA'; VB'; VC'}. In the steady state, the switch node voltages VA', VB', VC' follow the input voltages V1, V2, V3, and can be considered to be basically equal to the input voltages V1, V2, V3 (the inductor voltages VL1, VL2, VL3 are lower compared to the input voltages V1, V2, V3). To adjust the duty cycle, the PWM modulators 281, 282, 283 can each receive a common-mode voltage signal S representing the desired common-mode voltage VCM . This common-mode signal S VCMIt can be provided by a central controller (not shown). The central controller can be a microcontroller or the like.

[0078] In Figure 4 the method shown, the electronic switches Q1, Q2, Q3 in each of the bridge arms 11, 12, 13 are operated in PWM mode during the entire cycle of the input voltages V1, V2, V3. This type of operating mode is also referred to as the 3 / 3 mode below.

[0079] Referring to the above, the bridge arms 11, 12, 13 can be implemented in various ways. Some examples for implementing the respective bridge arms 11 - 13 are explained below with reference to the first bridge arm 11. The second and third bridge arms 12, 13 can be implemented in the same way as the first bridge arm 11. Figure 7A A first example of the first bridge arm 11 is shown. In this example, the first bridge arm 11 is implemented in the manner Figure 3 described. That is, the bridge arm 11 includes a bidirectional blocking switch Q1 connected between the first switch node A' and the midpoint Y, a first rectifier element D11 connected between the first switch node A' and the first DC link node X, and a second rectifier element D12 connected between the second DC link node Z and the first switch node A'.

[0080] Figure 7B A second example for implementing the first bridge arm 11 is shown. In this example, the bridge arm 11 includes a first rectifier element D211 connected to the first DC link node X, a second rectifier element D212 connected to the second DC link node Z, a third rectifier element D213 connected between the switch node A' and the first rectifier element D211, a fourth rectifier element D214 connected between the switch node A' and the second rectifier element D212, a fifth rectifier element D215 connected between the midpoint Y and the first rectifier element D211, and a sixth rectifier element D216 connected between the midpoint Y and the second rectifier element D212. In addition, the electronic switch Q1 is connected between the first rectifier element D211 and the second rectifier element D212. The electronic switch Q1 can be a unidirectional electronic switch, such as a MOSFET. Referring to Figure 7B, the rectifier elements D211 - D216 can be implemented as diodes. These rectifier elements D211 - D216 are connected such that during the positive half - wave of the first input voltage V1, when the electronic switch Q1 is turned on, the inductor current I1 can flow from the first switch node A' through the third rectifier element D213, the electronic switch Q1, and the sixth rectifier element D216 to the mid - point Y. When the electronic switch Q1 is turned off, the inductor current I1 flows through the third rectifier element D213 and the first rectifier element D211. During the negative half - wave of the input voltage V1, when the electronic switch Q1 is turned on, the current flows from the mid - point Y through the fifth rectifier element D215 and the fourth rectifier element D214 to the first switch node A'. When the electronic switch Q1 is turned off, the current flows from the second DC - link node Z through the second rectifier element D212 and the fourth rectifier element D214 to the first switch node A'.

[0081] Figure 7C A third example of the first bridge arm 11 is shown. In this example, the first bridge arm 11 includes a first rectifier element D311 connected to the first DC - link node X, a second rectifier element D312 connected to the second DC - link node Z, a first switch Q311 connected between the first switch node A' and the first rectifier element D311, a second switch Q312 connected between the first switch node A' and the second rectifier element D312, a third rectifier element D313 connected between the mid - point Y and the first rectifier element D311, and a fourth rectifier element D314 connected between the mid - point Y and the second rectifier element D312.

[0082] For example, the electronic switches Q311, Q312 can be unidirectional blocking switches, such as MOSFETs. The electronic switches Q311, Q312 and the rectifier elements D311 - D314 can be connected such that during the positive half - wave of the input voltage V1, when the second electronic switch Q312 is turned on, the inductor current I1 flows through the switch node A' through the second electronic switch Q312 and the fourth rectifier element D314 to the mid - point Y. When the second electronic switch Q312 is turned off, the inductor current I1 flows through the first electronic switch Q311 and the first rectifier element D311 to the first DC - link node X. The first electronic switches Q311, Q312 can be turned on and off simultaneously. In this case, during the off - period, the inductor current I1 flows through the body diode of the MOSFET forming the first electronic switch Q311 and the first rectifier element D311. According to another example, the first electronic switch Q311 and the second electronic switch Q312 are operated in a complementary manner such that only one switch is on at the same time. In this case, when the second switch Q312 is turned off, the first switch Q311 is turned on, so that the inductor current I1 flows through the conducting first electronic switch Q311 and the first rectifier element D311.

[0083] During the negative half - wave of the input voltage V1, when the first electronic switch Q311 is turned on, the inductor current I1 flows from the mid - point Y through the third rectifier element D313 and the first electronic switch Q311 to the first switching node A'. When the first electronic switch Q311 is turned off, the inductor current I1 flows from the second DC - link node Z through the second rectifier element D312 and the second electronic switch Q312 to the first switching node A'.

[0084] Figure 7D Shows the modification of Figure 7C the leg 11 shown. In Figure 7D the example shown, the first switch Q311 is connected between the mid - point Y and the first rectifier element D311, the second switch Q312 is connected between the mid - point Y and the second rectifier element D312, the third rectifier element D313 is connected between the switching node A' and the first rectifier element D311, and the fourth rectifier element D314 is connected between the switching node A' and the second rectifier element D312.

[0085] Figure 7A 、 7B 、each of the legs 11 shown in 7C and 7D is configured to provide three different voltage levels at the first switching node A'. Using Figures 7A to 7D one of the legs 11 shown in, the average potential at the first switching node A' during one driving cycle is generated by two voltage levels, i.e., the potential VX at the first DC - link node X and the potential VY at the mid - point Y during the positive half - wave of the input voltage V1, and the potential VZ at the second DC - link node Z and the potential VY at the mid - point Y during the negative half - wave of the input voltage V1.

[0086] Figure 7E and Figure 7F show additional examples of the first leg 11. In these examples, the leg 11 also includes capacitors in addition to the DC - link capacitors C1, C2. In these examples, in each of the positive and negative half - waves of the input voltage V1, there are more than two different voltage levels available to generate the switching - node voltage VA' such that it presents an expected value. Figure 7E and Figure 7F the legs 11 shown in are so - called multilevel legs, where Figure 7E the leg 11 shown in is a hybrid active neutral - point - clamped converter leg, while Figure 7FThe leg 11 shown in the figure is a stacked multi-cell converter leg. These legs are known (for example, see G. Gateau, T. A. Meynard, H. Foch: "Stacked Multicell Converter (SMC): Properties and design", 2001 IEEE 32 nd nd Annual Power Electronics Specialists Conference, Volume 3, pages 1583 - 1588), so no further explanation is needed for this. Basically, each of these legs can provide more than three different voltage levels, namely three voltage levels VX, VY, VZ and an additional voltage level for generating the switch node voltage VA'.

[0087] In Figures 7A-7F the example shown, the rectifier elements can be implemented as diodes (as shown in the figure). However, this is only an example. According to another example (not shown), these rectifier elements can be implemented as synchronous rectifier elements.

[0088] Referring to the above, operating Figure 1 and Figure 3 a power converter of the type shown can include PWM (pulse width modulation) operation of at least one electronic switch in each of the legs 11, 12, 13 at each time of operation. However, operating the switches Q1, Q2, Q3 in PWM mode is associated with switching losses. "Switching losses" refer to the losses that occur when turning on and off the corresponding switches Q1, Q2, Q3. To improve the efficiency of the power converter, it is desirable to reduce these switching losses.

[0089] According to one example, reducing the switching losses includes operating the power converter in a reduced switching mode, where operating the power converter in a reduced switching mode includes deactivating at least one of the switches Q1, Q2, Q3 in one or two of the legs 11, 12, 13 for a period significantly longer than the duration T of one drive cycle. According to one example, deactivating at least one switch includes deactivating at least one switch for more than 10, more than 100, or even more than 1000 drive cycles. Hereinafter, the leg in which at least one switch is deactivated is referred to as a deactivated leg. Referring to the above, the "at least one electronic switch" of the legs 11, 12, 13 can include one electronic switch or several electronic switches. Figure 7A Figure shows a leg 11 with one electronic switch, where, as Figure 5 shown, one switch can include two transistors. Figures 7B-7FArm 11 with several (unidirectional blocking) switches is shown. In an arm with several switches, "deactivating at least one switch" includes deactivating each of the several switches. Further, as used herein, "at least one electronic switch" is a switch in the corresponding arm for connecting a switching node to the midpoint Y or to a circuit node having a voltage between the voltage at the midpoint Y and one of the first DC link node voltage VX and the second DC link node voltage VZ. For example, Figure 7E and Figure 7F a voltage between the voltage at the midpoint Y and one of the first DC link node voltage VX and the second DC link node voltage VZ is provided in the arm shown. Referring to the above, the rectifier elements coupling the switching nodes A', B', C' to the first DC link node X and the second DC link node Z may include electronic switches. Thus, "deactivating at least one switch" does not include deactivating an electronic switch that functions as a (synchronous) rectifier.

[0090] Figure 8 An example of operating a power converter in a reduced switching mode is shown, where Figure 8 signal diagrams of drive signals S1, S2, S3, input voltages V1, V2, V3, DC link voltage V4, input currents I1, I2, I3, currents ID11, ID12, IQ11 in the first arm 11, and voltage VQ1 across the first switch Q1 in the first arm 11 are shown. In the following Figure 8 the shown operating mode is referred to as the 1 / 3 mode. In this operating mode, there are periods during which only one of the three arms 11, 12, 13 is operated in PWM mode while the other two of the arms 11, 12, 13 are deactivated, i.e., at least one electronic switch Q1, Q2, Q3 in the other two of the arms 11, 12, 13 is turned off. Hereinafter, an arm in which at least one electronic switch is operated in PWM mode is referred to as an "enabled arm", and an arm in which at least one electronic switch is deactivated is referred to as a "deactivated arm", although current can of course flow in a deactivated arm between the corresponding switching node and one of the first DC link node X and the second DC link node Z.

[0091] In Figure 8 the shown example, the power converter is operated in the 1 / 3 mode throughout the entire cycle of the input voltages V1, V2, V3. That is, at each time in the cycle of the input voltages V1, V2, V3, only one of the arms 11, 12, 13 is enabled while the other two arms are deactivated. This type of operating mode is hereinafter referred to as the full 1 / 3 mode. However, this is only an example. According to another example further explained below, the power converter can also be operated such that the power converter is operated in the 1 / 3 mode only during some periods (at some phase angles in a cycle of the input voltages V1, V2, V3).

[0092] Referring to the above, the switch node voltages of the disabled leg are clamped to the DC link voltage VX at the first DC link node X or the DC link voltage VZ at the second DC link node Z. Thus, in the 1 / 3 mode, the switch node voltage of one leg is clamped to the first DC link node voltage VX, while the switch node voltage of the other leg is clamped to the second DC link node voltage VZ. The disabled leg changes within one period of the input voltage system. This will be further explained below with reference to Figure 13 the signal diagrams shown.

[0093] According to an example, the current through the two inductors connected to the disabled leg is regulated by appropriately regulating the DC link voltage V4 by another power converter 5 connected to the DC link nodes X, Z of the power converter. Figure 9 A power converter device is shown in which has a power converter of the type previously explained and another power converter 5 connected to the DC link nodes X, Z of the power converter. Hereinafter, the power converter 10 will also be referred to as the first power converter, and the other power converter 5 will also be referred to as the second power converter. The second power converter 5 can be configured to provide a constant output voltage V OUT or a constant output current I OUT . When the second power converter 5 helps regulate the inductor currents I1, I2, I3 in the first power converter 10 by appropriately regulating the DC link voltage V4, the losses occurring in the second power converter 5 do not increase. However, the switching losses in the first power converter are significantly reduced. Thus, there is a synergy between the control of the first power converter and the control of the second power converter 5.

[0094] Figure 10 An example of a control circuit 4 of a power converter device configured to operate Figure 9 a power converter device having a first power converter and a second power converter of the type shown is shown. Figure 10 The control circuit 4 shown in includes two main branches (or sub - circuits), namely a first branch 40 configured to operate the first power converter and a second branch 6 configured to operate the second power converter 5. It should be noted that Figure 10 the block diagrams shown illustrate the functional blocks of the control circuit 4, rather than a specific implementation. These functional blocks can be implemented in various ways. According to an example, dedicated circuits are used to implement these functional blocks. According to another example, hardware and software are used to implement the control circuit 4. For example, the first control circuit includes a microcontroller and software executed by the microcontroller.

[0095] For purposes of explanation, it is assumed that in Figure 9In the power converter device shown, the output current I of the second power converter 5 is regulated OUT , and the output voltage V is defined by a load (not shown) that receives the output current OUT . The load can be a battery that receives the output current I OUT and defines the output voltage V OUT .

[0096] Figure 10 The first branch 40 of the control circuit 4 shown is based on Figure 6 the control circuit shown, where the same elements have the same reference numerals. Referring Figure 10 , the control circuit 4 receives an output current signal S IOUT , where the output current signal S IOUT represents the output current I OU T. To obtain the output current signal S IOUT , the output current I can be measured in a conventional manner by any kind of current measurement circuit (not shown) OUT . The control circuit 4 includes a first filter 41 that receives the output current signal S IOUT and an output current reference signal S IOUT_REF , where the output current reference signal S IOUT_REF represents the desired current level of the output current I OUT . For example, the first filter 41 subtracts the output current reference signal S IOUT from the output current signal S IOUT_REF , and filters the difference to generate an output signal S V51_REF . According to one example, this output signal S V51_REF represents the desired voltage V51 across the inductor 51 in the second power converter 5, where the inductor 51 carries the output current I OUT . Figure 9 An example of such an inductor 51 is shown

[0097] The filter can have one of a proportional (P) characteristic, a proportional-integral (PI) characteristic, a proportional-integral-derivative (PID) characteristic, etc. An adder 42 receives the filter output signal S V51_REF and an output voltage signal S OUT that represents the output voltage V VOUT , where a multiplier 43 receives the output signal S42 of the adder 42 and the output current reference signal S IOUT_REF . The output signal S43 of the multiplier 43 represents the desired output power of the power converter device. By means of Figure 6 the divider 23 already explained, the multiplier output signal S43 is divided by a signal that represents 1.5 times the square of the amplitude of the input voltages V1, V2, V3 The output signal S23 of the divider 23 represents the total desired input current of the first power converter. To generate three switching node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF , three branches explained in reference Figure 6 process the divider output signal S23. It should be noted that the current control loop is the slowest one among the control loops explained in the context of Figure 10 .

[0098] Controlling the output current I OUT by the control circuit 4 is just an example. According to another example, the output voltage V OUT is controlled. In this example (not shown), the filter 41 receives the output voltage signal S VOUT and the output voltage reference signal S OUT representing the desired voltage level of the output voltage V VOUT_REF . In addition, the adder 42 is omitted, and the multiplier 43 receives the output signal from the filter 41 and the output voltage reference signal S VOUT_REF .

[0099] Referring to Figure 10 , the PWM modulator 44 receives the switching node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF . From these switching node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF , the PWM modulator 44 (a) selects the largest one and deactivates the leg associated with the largest voltage reference signal; (b) selects the smallest one and deactivates the leg associated with the smallest voltage reference signal; and (c) operates the remaining legs in PWM mode. The "remaining legs" are the legs associated with the switching node reference signals between the largest and smallest switching node voltage reference signals. The switching node voltage reference signal will be referred to as the intermediate switching node voltage reference signal hereinafter.

[0100] The second branch 6 of the control circuit also receives the three switching node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF , and is configured to control the operation of the second power converter 5 based on these signals S VA'_REF 、S VB'_REF 、S VC'_REF . An example of the second branch 6 of the control circuit will be further explained in detail below.

[0101] Figure 11An example of the second power converter 5 is shown. In this example, the second power converter 5 includes a first converter stage 51 and a second converter stage 52, where each of the first converter stage 51 and the second converter stage 52 includes a first input node 511, 521, a second input node 512, 522, a first output node 513, 523, and a second output node 514, 524. The first input node 511 of the first converter stage 51 may be connected to the first DC link node X, the second input node 522 of the second converter stage 52 may be connected to the second DC link node Z, and the second input node 512 of the first converter stage 51 and the first input node 521 of the second converter stage 52 may be connected to each other and to the midpoint Y. In addition, the second output node 514 of the first converter stage 51 and the first output node 523 of the second converter stage 52 may be connected to each other. The output voltage VOUT is the voltage between the first output node 513 of the first converter stage 51 and the second output node 524 of the second converter stage 52.

[0102] The converter stages 51, 52 may each be implemented using one of a variety of different converter topologies. According to one example, each of the converter stages 51, 52 is implemented as an isolated DC-DC converter, i.e., the DC-DC converter includes a transformer between the corresponding inputs 511, 512 or 521, 522 and the corresponding outputs 513, 514 or 523, 534. According to another example, each of the converter stages 51, 52 is implemented as a non-isolated DC-DC converter, i.e., the DC-DC converter does not include a transformer between the corresponding inputs 511, 512 or 521, 522 and the corresponding outputs 513, 514 or 523, 534. Examples of different types of DC-DC converters suitable for use as the first converter stage 51 and the second converter stage 52 include, but are not limited to: flyback converters (isolated), LLC converters (isolated), dual active bridge (DAB) converters (isolated), phase-shifted full-bridge converters (isolated), buck-boost converters, boost-buck converters, etc. These types of converters are known and thus do not require further explanation here.

[0103] Figure 12 is shown configured to control Figure 11 An example of a second control circuit branch 6 configured to control the operation of the second power converter 5 of the type shown is shown. The control circuit 6 includes a maximum and minimum selector 61 that receives three switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF . The maximum and minimum selector 61 is configured to select the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REFThe maximum value in and the switching node voltage reference signal S VA'_REF , S VB'_REF , S VC'_REF The minimum value in, and output a first signal S equal to the maximum value in the switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF The maximum value in, and a second signal S equal to the minimum value in the switching node voltage reference signals S MAX ', such that S VA'_REF , S VB'_REF , S VC'_REF The minimum value in, such that S MIN ' = max{S MAX , S VA'_REF , S VB'_REF , S VC'_REF} and S MIN ' = min{S VA'_REF , S VB'_REF , S VC'_REF}. The first signal S MAX ' is also referred to as the maximum switching node voltage reference signal S MAX ', and the second signal S MIN ' is also referred to as the minimum switching node voltage reference signal. The intermediate switching node voltage reference signal is also referred to as S INT ' hereinafter.

[0104] The second control circuit branch 6 is configured to operate the second power converter 5 in such a way that the DC link voltage V4 is equal to the voltage represented by the difference between the maximum switching node voltage reference signal S MAX ' and the minimum switching node voltage reference signal S MIN '. Referring to the above, the switching nodes of the deactivated arm are clamped to the first DC link node voltage VX and the second DC link node voltage VZ respectively. By adjusting the DC link voltage V4 to be equal to the voltage represented by the difference between the maximum switching node voltage reference signal S MAX ' and the minimum switching node voltage reference signal S MIN ', the switching nodes clamped to the first DC link node X and the second DC link node Z receive the switching node voltages calculated by the first control circuit branch 40. Accordingly, the inductor currents of those inductors connected to the deactivated arm have current levels represented by the corresponding input current reference signals calculated by the first control circuit branch 40.

[0105] Referring to Figure 12 , the second control circuit branch 6 includes a subtractor 62 that subtracts the minimum switching node voltage reference signal S MAX ' from the maximum switching node voltage reference signal S MIN', where the multiplier 63 multiplies the output signal of the subtractor by 0.5. The output signal of the multiplier forms the first capacitor voltage reference signal S VC1_REF and the second capacitor voltage reference signal S VC2_REF , where the first capacitor voltage reference signal S VC1_REF represents the expected value of the first capacitor voltage VC1, and the second capacitor voltage reference signal S VC2_REF represents the expected value of the second capacitor voltage VC2. The second control circuit branch 6 includes a first branch and a second branch. The first branch receives the first capacitor voltage reference signal S VC1_REF , and is configured to provide a first input current reference signal S I51_REF , where the first input current reference signal S I51_REF represents the expected input current I51 of the first converter stage 51. The second branch receives the second capacitor voltage reference signal S VC2_REF , and is configured to provide a second input current reference signal S I52_REF , where the second input current reference signal S I52_REF represents the expected input current I52 of the second converter stage 52.

[0106] The first branch includes a subtractor 641, which subtracts the first capacitor voltage signal S VC1_REF representing the first capacitor voltage VC1 from the first capacitor voltage reference signal S CV1 . The output signal of the subtractor is filtered by a filter 651, where the output signal S IC1_REF of the filter represents the expected current level of the current IX flowing into the first capacitor C1. The first input current reference signal S IX is given by the difference between the current signal S IC1_REF representing the current flowing into the first DC link node X (where this current IX is provided by the first power converter) and the filter output signal S I51_REF .

[0107] The second branch includes a subtractor 642, which subtracts the second capacitor voltage signal S VC2_REF representing the second capacitor voltage VC2 from the second capacitor voltage reference signal S CV2 . The output signal of the subtractor is filtered by a filter 652, where the output signal S IC2_REF of the filter represents the expected current level of the current IZ flowing into the second capacitor C2. The second input current reference signal S IZ is given by the difference between the current signal S IC2_REF representing the current flowing into the second DC link node Z (where this current IZ is provided by the first power converter) and the filter output signal S I52_REF .

[0108] Reference Figure 12 , the first PWM modulator 671 receives a first input current reference signal S I51_REF and a first input current signal S I51 , where the latter represents the first input current I51 and is configured to control the operation of one or more switches (not shown in the figure) included in the first converter stage 51 such that the first input current I51 has a current level represented by the first input current reference signal S I51_REF . Similarly, the second PWM modulator 672 receives a second input current reference signal S I52_REF and a second input current signal S I52 , where the latter represents the second input current I52 and is configured to control the operation of one or more switches (not shown in the figure) included in the second converter stage 52 such that the second input current I52 has a current level represented by the second input current reference signal S I52_REF . The specific implementation of the PWM modulators 671, 672 depends on the specific type of power converter used to implement the first converter stage 51 and the second converter stage 52. However, PWM modulators configured to control the input current in various DC-DC converters are known, and thus no further explanation is required for this.

[0109] Referring to the above, in the 1 / 3 mode, which one of the three bridge arms 11, 12, 13 is enabled and which two of the three bridge arms 11, 12, 13 are disabled by the PWM modulator 44 depends on the switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF . The moments when two of these switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF are equal can be ignored, such that at each time, among these switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF , one forms the maximum switch node voltage reference signal S MAX ', one forms the intermediate switch node voltage reference signal S INT ', and one forms the minimum switch node voltage reference signal S MIN '. This will be explained in more detail with reference to Figure 13 .

[0110] Figure 13 Shows the switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REFSignal diagram, where each of these signals represents the desired voltage value of the corresponding switch node voltages VA', VB', VC'. Figure 13 It is further shown at which time or phase angle which bridge arm is operated in PWM mode. Referring to the above and as Figure 13 shown, in the steady state, each switch node voltage reference signal S VA'_REF 、S VB'_REF 、S VC'_REF follows the corresponding input voltage.

[0111] Referring to Figure 13 , the relationship between the respective switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF changes several times within one period. "Relationship" means the signal level of one of the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF with respect to the signal levels of the other two of the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF . In the example shown in Figure 13 , there are six time periods P1 - P6, also referred to as operating phases hereinafter, in each of which the relationship between the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF does not change. (However, the signal levels of the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF change in each of the operating phases P1 - P6.)

[0112] For example, in the first operating phase P1, the first switch node voltage reference signal S VA'_REF has the highest voltage level. That is, the voltage level of the first switch node voltage reference signal S VA'_REF is higher than the voltage level of the second switch node voltage reference signal S VA'_REF 、S VB'_REF 、S VC'_REF and the signal level of the third switch node voltage reference signal S VB'_REF 、S VA'_REF 、S VB'_REF 、S VC'_REF . In addition, in the first operating phase P1, the second switch node voltage reference signal S VC'_REF has the lowest voltage level. That is, the second switch node voltage reference signal S VB'_REF ​VB'_REF has a voltage level lower than the first switch node voltage reference signal S VA'_REF in terms of signal level and the third switch node voltage reference signal S VC'_REF in terms of signal level. In addition, the third switch node voltage reference signal S VC'_REF has a signal level between the signal level of the first switch node voltage reference signal S VA'_REF and the signal level of the second switch node voltage reference signal S VB'_REF . Therefore, in the first operation phase P1, the first switch node voltage reference signal S VA'_REF is the maximum switch node voltage reference signal S MAX ', the second switch node voltage reference signal S VB'_REF is the minimum switch node voltage reference signal S MIN ', and the third switch node voltage reference signal S VC'_REF is the intermediate switch node voltage reference signal S INT '. For example, in the second operation phase P2, the first switch node voltage reference signal S VA'_REF is the maximum switch node voltage reference signal S MAX ', the second switch node voltage reference signal S VB'_REF is the intermediate switch node voltage reference signal S INT ', and the third switch node voltage reference signal S VC'_REF is the minimum switch node voltage reference signal S MIN '.

[0113] Hereinafter, the input voltage having the highest voltage level is referred to as the maximum input voltage Vmax, the input voltage having the lowest voltage level is referred to as the minimum input voltage Vmin, and the input voltage having a voltage level between the highest voltage level and the lowest voltage level is referred to as the intermediate input voltage V INT . Then, the above line-to-line voltage V LL is given by V LL = Vmax - Vmin. Referring to the above, in the steady state, the switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF basically follow the input voltages V1, V2, V3, and thus Figure 12 the output signal S MAX ' - S MIN ' of the subtractor 62 shown basically represents the line-to-line voltage V LL . Figure 13 The subtractor output signal S MAX ' - S MIN ' is also shown in

[0114] Refer to Figure 13, operating the power converter in a 1 / 3 mode includes enabling the leg associated with the intermediate voltage reference signal S INT ' and disabling the legs associated with the maximum switch node voltage reference signal S MAX ' and the minimum switch node voltage reference signal S MIN '. That is, in the first operation phase P1, for example, the third leg 13 is enabled, and in the second operation phase P2, the second leg 12 is enabled, and so on.

[0115] Referring to the above, the legs 11, 12, 13 are enabled and disabled by the PWM modulator 44 in the control circuit 4. According to one example, the PWM circuit 44 is configured to calculate the duty cycles d1, d2, d3 based on the following equations:

[0116]

[0117] These equations are based on Equation (3c). In addition, in the 1 / 3 mode, the common-mode signal S VCM represented by received by the PWM modulator is selected such that the common-mode voltage VCM satisfies

[0118]

[0119] Figure 13 Also shown within one period of the input voltage is the common-mode voltage signal S VCM representing the common-mode voltage VCM. When the duty cycles d1, d2, d3 are adjusted according to Equations (4A)-(4C) and (5), the duty cycle of the leg associated with the maximum switch node voltage reference signal S MAX ' is always "automatically" set to +1 in the corresponding operation phase, thereby clamping the corresponding switch node to VX. In addition, the duty cycle of the leg associated with the minimum switch node voltage reference signal S MIN ' is always "automatically" set to -1 in the corresponding operation phase, thereby clamping the corresponding switch node to VZ. This will be explained below.

[0120] Hereinafter, dmax represents the duty cycle of the leg associated with the maximum switch node voltage reference signal S MAX ' in the corresponding operation phase, and dmin represents the duty cycle of the leg associated with the minimum switch node voltage reference signal S MIN ' in the corresponding operation phase. In addition, Vmax' represents the desired switch node voltage represented by the maximum switch node voltage reference signal S MAX ', and Vmin' represents the desired switch node voltage represented by the minimum switch node voltage reference signal S MINThe desired switching node voltages represented by '. Based on one of equations (4a)-(4c) and equation (5), and considering that the DC link voltage V4 is adjusted such that V4 = Vmax' - Vmin', the duty cycle dmax and the duty cycle dmin are given by the following

[0121]

[0122] Referring to the above, when the first power converter 10 operates in the 1 / 3 mode, the DC link voltage V4 is adjusted by the second converter 5 such that it is equal to Vmax' - Vmin', where Vmax' is the maximum value of the desired switching node voltage and Vmin' is the minimum value of the desired switching node voltage. In the steady state, these desired switching node voltages Vmax', Vmin' are substantially equal to the maximum input voltage Vmax and the minimum input voltage Vmin respectively, such that the varying DC link voltage V4 is substantially equal to the line-to-line voltage V LL . This is the lowest possible DC link voltage that can achieve sinusoidal input currents I1, I2, I3, where in this case the common-mode voltage VCM is different from zero and is given by equation (5).

[0123] Figure 9 The power converter device shown in is not limited to generating a DC link voltage V4 such that it is defined by S MAX '-S MIN ' and is substantially equal to the line-to-line voltage V LL . Figure 14 Shows an example of the second control circuit branch 6, which is configured to generate a DC link voltage V4 such that in some time periods, it is defined by the subtractor output signal S62 (= S MAX '-S MIN '), and in some time periods is higher than that defined by the subtractor output signal S62. In this example, the maximum selector 68 receives the subtractor output signal S62 and the minimum DC link voltage signal S V4_MIN , where the minimum DC link voltage signal S V4_MIN represents the minimum value of the DC link voltage V4 that should be generated at the output of the first power converter 10. The maximum selector outputs the maximum of the two signals it receives to the multiplier 63. Hereinafter, the voltage represented by the minimum DC link voltage signal S V4_MIN will be referred to as the minimum desired DC link voltage V4 MIN .

[0124] When the minimum desired DC link voltage V4 MINWhen it is the minimum value of the subtractor output signal S62 or lower, the DC link voltage is generated as described above, and the first power converter 10 operates in the full 1 / 3 mode, that is, the power converter always operates in the 1 / 3 mode in each of the six operation phases. Figure 15 Such an operation mode is shown again, where Figure 15 it is shown that the power converter operates in the full 1 / 3 mode between the first moment t1 and the second moment t2.

[0125] When the minimum desired DC link voltage signal S V4_MIN is higher than the minimum value of the subtractor output signal S62, the DC link voltage V4 is generated such that in the period when the subtractor output signal S62 is higher than the minimum desired DC link voltage signal S V4_MIN , the DC link voltage V4 is generated based on the subtractor output signal S62. In the remaining time, the DC link voltage V4 is generated based on the minimum desired DC link voltage signal S V4_MIN . In this type of operation, the power converter no longer always operates in the 1 / 3 mode in each of the six operation phases. Instead, there are not only periods when the first power converter operates in the 1 / 3 mode, but also periods when each of the bridge arms 11, 12, 13 operates in the PWM mode. This is shown between the second moment t2 and the third moment t3 in Figure 15 .

[0126] Between these moments t2, t3, the minimum desired DC link voltage V4 MIN increases in order to illustrate how the operation of the power converter changes according to the desired DC link voltage V4 MIN . The minimum desired DC link voltage V4 MIN is the minimum value of the DC link voltage V4, which is also shown in Figure 15 . Basically, as can be seen from Figure 15 , the duration during which the power converter operates in the 1 / 3 mode in one cycle of the input voltages V1, V2, V3 decreases as the minimum DC link voltage V4 MIN increases. The operation mode in which the power converter operates alternately in the 1 / 3 mode and the 3 / 3 mode (as shown between the moments t2 and t3 in Figure 15 ) is hereinafter referred to as the partial boost mode.

[0127] When calculating the duty cycles d1, d2, d3 according to equations (4a)-(4c), the power converter automatically varies between the 1 / 3 mode and the 3 / 3 mode because these duty cycles depend on the DC link voltage V4 adjusted by the second power converter 5. In the partial boost mode, the common-mode voltage VCM can be the same as in the full 1 / 3 mode. However, during those time periods when the power converter operates in the 3 / 3 mode in the partial boost mode, the common-mode voltage VCM can be different from the common-mode voltage in the 1 / 3 mode. Only in the full 1 / 3 mode is the common-mode voltage VCM restricted to the value given in equation (5). However, in the partial boost mode and the full boost mode, there is some degree of freedom to adjust the common-mode voltage VCM such that it is different from the value given in equation (5). In these operating modes, the degree of freedom available to adjust the common-mode voltage VCM can be used to adjust the common-mode voltage VCM so as to minimize the current IY entering the midpoint. This will be further explained in detail below.

[0128] Figure 16 illustrates different operating modes of the first power converter 10, which depend on the minimum desired DC link voltage signal S V4_MIN and the phase angles of the input voltages V1, V2, V3. More specifically, Figure 16 illustrates different operating modes in any one of six operating phases P1 - P6, where each of these operating phases covers 60° of one cycle of the input voltages V1, V2, V3. In Figure 16 , a phase angle of 0° represents the start of the corresponding operating phase, a phase angle of 60° represents the end of the corresponding operating phase, and a phase angle of 30° represents the middle of the corresponding operating phase, which is the moment when the intermediate input voltage crosses zero in the corresponding operating phase.

[0129] Refer to Figure 16 , when the minimum desired DC link voltage signal S V4 _ MIN is lower than the minimum value of the subtractor output signal

[0130] S62, the power converter operates in the full 1 / 3 mode. Referring to the above, in the steady state, the subtractor output signal S62 basically represents the line-to-line voltage V LL , such that when the minimum desired DC link voltage V4 MIN is lower than the minimum line-to-line voltage V LL_MIN , the power converter operates in the full 1 / 3 mode.

[0131] Furthermore, referring to Figure 16 , when the minimum desired DC link voltage signal S V4_MINWhen it is between the minimum value and the maximum value of the subtractor output signal S62, the power converter operates in a partial boost mode. In steady state, the maximum value of the subtractor output signal S62 is substantially equal to the maximum line-to-line voltage V LL_MAX , such that when the DC link voltage V4 is between the minimum line-to-line voltage V LL_MIN and the maximum line-to-line voltage V LL_MAX , the power converter operates in a partial boost mode. In the partial boost mode, the portion of the power converter that operates in the 3 / 3 mode in the operating phase increases as the minimum desired DC link voltage V4 MIN increases, and the portion of the power converter that operates in the 1 / 3 mode in the operating phase decreases as the minimum desired DC link voltage V4 MIN increases.

[0132] Refer to Figure 16 , when the minimum desired DC link voltage signal S V4_MIN is higher than the maximum value of the subtractor output signal S62, the power converter operates in the full 3 / 3 mode. In this operating mode, the DC link voltage V4 is substantially constant and depends only on the minimum desired DC link voltage signal S V4_MIN .

[0133] In the Figure 12 and Figure 14 shown control circuit, the control input currents I51, I52 are controlled such that each of the first capacitor voltage VC1 and the second capacitor voltage VC2 is equal to 50% of the desired DC link voltage V4. However, this is only an example. According to Figure 17 shown in another example, the control input currents I51, I52 are controlled such that the first capacitor voltage is equal to k1 times the desired DC link voltage V4, and the second capacitor voltage is equal to k2 times the desired DC link voltage V4, where k1 + k2 = 1, k1 > 0, k2 > 0. In this case, the first capacitor voltage VC1 and the second capacitor voltage VC2 are different. In this case, the duty ratios d1, d2, d3 can be calculated by the PWM modulator 44 in the control circuit 4 based on equations (3a) and (3b). Optionally, the second control circuit branch 6 may include a maximum selector of the type explained in Figure 14 .

[0134] In the Figure 12 , Figure 14 and Figure 17 shown examples, the first converter stage 51 and the second converter stage 52 not only regulate the DC link voltage V4, but also regulate the first capacitor voltage VC1 and the second capacitor voltage VC2. According to Figure 18Another example shown is that the balancing circuit 7 regulates the ratio of the first capacitor voltage VC1 and the second capacitor voltage VC2. In this case, the first converter stage 51 and the second converter stage 52 only regulate the DC link voltage V4. Additionally, in this case, the two converter stages 51, 52 can be replaced by one converter stage.

[0135] Reference Figure 19 , the balancing circuit may include a first switch 71 connected between the first DC link node X and an inductor 73 connected to the midpoint Y, and a second switch 72 connected between the second DC link node Z and the inductor 73. The control circuit 74 receives the first capacitor voltage signal S VC1 and the second capacitor voltage signal S VC2 , and is configured to control the operation of the first switch 71 and the second switch 72 such that a predefined ratio exists between these voltages VC1, VC2, such as 1:1 or k1:k2. By appropriately turning on and off the first switch 71 and the second switch 72, energy can be transferred between the first DC link capacitor C1 and the second DC link capacitor C2. For example, when the first switch is turned on (while the second switch 72 is turned off), energy is taken from the first DC link capacitor C1, stored in the inductor 73, and transferred to the second DC link capacitor C2 when the first switch is turned off and the second switch 72 is turned on. The duty cycles of operating the two switches 71, 72 define the ratio of the capacitor voltages VC1, VC2, where when the duty cycles of the two switches 71, 72 are 50%, the capacitor voltages VC1, VC2 are substantially equal.

[0136] Referring to the above, in the Figure 9 shown power converter device, the DC link voltage is adjusted by the second power converter 5, where the output voltage V OUT of the second power converter can be defined by a load such as a battery charged by the power converter device. Additionally, the DC link voltage V4 can be adjusted by the above-mentioned minimum DC link voltage signal S V4_MIN . Adjusting the DC link voltage V4 can contribute to achieving a high converter efficiency of the second power converter. Basically, the smaller the difference between the input voltage and the output voltage of the power converter, the higher the efficiency. Therefore, according to one example, the minimum DC link voltage signal S OUT can be adjusted based on the output voltage V V4_MIN such that the minimum desired DC link voltage V4 MIN increases as the output voltage V OUT increases.

[0137] Another example of reducing the switching pattern is called the 2 / 3+PWM pattern and is explained below. In this type of operating mode, the power converter 10 operates either in the 2 / 3 mode or in the 3 / 3 mode (PWM mode). In the 2 / 3 mode, one of the bridge arms 11, 12, 13 is deactivated and the other two of the bridge arms 11, 12, 13 are activated, while in the 3 / 3 mode (PWM mode), each of the bridge arms 11, 12, 13 is activated. Basically, in Figure 1 and Figure 3 In the power converter 10 of the type shown, the sum of the input currents I1, I2, I3 is zero, i.e., I1 + I2 + I3 = 0. Therefore, by adjusting two of the three input currents I1, I2, I3, the third of the three input currents I1, I2, I3 is automatically adjusted. Thus, the power converter can be operated so that one of the bridge arms 11, 12, 13 is deactivated each time. The bridge arms 11, 12, 13 can be deactivated alternately, each for a predefined period of time. This type of operating mode can be called the full 2 / 3 mode. However, in the full 2 / 3 mode, the midpoint current IY (i.e., the current entering the midpoint Y) may be relatively high. However, the latter has an adverse effect on the power conversion loss.

[0138] In the 3 / 3 mode, the midpoint current IY (also called the common-mode current hereinafter) can be reduced by appropriately selecting the common-mode voltage VCM. If the common-mode voltage that can be inserted is high enough, the midpoint current IY can even be reduced to zero by appropriately selecting the common-mode voltage. Hereinafter, VCMzmc represents the zero midpoint current (ZMC) common-mode voltage, which is the common-mode voltage when the midpoint current IY is zero. The ZMC common-mode voltage VCMzmc is given by:

[0139]

[0140] Among them, min_abs{VA′; VB′; VC′} (also known as Vmin_abs') is the desired switching node voltage with the lowest absolute value among the desired switching node voltages VA', VB', and VC'. For example, if |VA'| < |VB'| and |VA'| < |VC'|, then Vmin_abs' = VA'. Therefore, the absolute value of Vmin_abs' is equal to the absolute value of the switching node voltage with the lowest absolute value, |Vmin_abs'| = min{|VA'|; |VB'|; |VC'|}, and the sign of Vmin_abs' is equal to the sign of the switching node voltage with the lowest absolute value. Therefore, Vmin_abs' can be positive or negative. Similarly, max_abs{VA′; VB′; VC′} (also known as Vmax_abs') is the desired switching node voltage with the highest absolute value among the desired switching node voltages VA', VB', and VC'. For example, if |VA'| > |VB'| and |VA'| > |VC'|, then Vmax_abs' = VA'.

[0141] On the other hand, in order to achieve sinusoidal input currents I1, I2, and I3, there are constraints on the first DC link node voltage VX and the second DC link node voltage VZ such that the first DC link node voltage VX is equal to or higher than the maximum value Vmax' of the desired switching node voltages VA', VB', and VC', and the second DC link node voltage VZ is equal to or lower than the minimum value Vmin' of the desired switching node voltages VA', VB', and VC', that is

[0142] VX ≥ Vmax' (8a)

[0143] VZ ≤ Vmin' (8b).

[0144] Referring to the above content, and Therefore, based on equations (8a) and (8b), it can be shown that the common-mode voltage VCM must satisfy the following inequalities in order to obtain sinusoidal input currents:

[0145]

[0146] Below,

[0147]

[0148] which represents the maximum allowable common-mode voltage, and

[0149]

[0150] which represents the minimum allowable common-mode voltage.

[0151] To achieve zero neutral - point current and sinusoidal input voltage, the common - mode voltage VCM should satisfy the following condition, VCM = VCMzmc (11a)

[0152] VCMmin ≤ VCM ≤ VCMmax (11b).

[0153] However, especially when the DC - link voltage V4 is close to the maximum line - to - line voltage V LL_MAX , the two conditions (11a) and (11b) cannot be satisfied simultaneously.

[0154] According to one example, operating a power converter in 2 / 3 + PWM mode includes:

[0155] (a) As long as the ZMC common - mode voltage VCMzmc is within the range given by the maximum common - mode voltage VCMmax and the minimum common - mode voltage VCMmin, that is, as long as:

[0156] VCMmin ≤ VCMzmc ≤ VCMmax (12a),

[0157] then operate the power converter in 3 / 3 mode; and

[0158] (b) As long as the ZMC common - mode voltage VCMzmc is outside the range given by the maximum common - mode voltage VCMmax and the minimum common - mode voltage VCMmin, that is, as long as:

[0159] VCMzmc > VCMmax (12b),

[0160] or

[0161] VCMzmc < VCMmin (12c),

[0162] then operate the power converter in 2 / 3 mode.

[0163] According to one example, in 3 / 3 mode, adjust the common - mode voltage VCM to be equal to the ZMC common - mode voltage VCMzmc. In 2 / 3 mode, the common - mode voltage VCM can be adjusted in various ways so that it is within the range given by the maximum common - mode voltage VCMmax and the minimum common - mode voltage VCMmin. According to one example, adjust the common - mode voltage VCM such that when the ZMC common - mode voltage VCMzmc is greater than the maximum common - mode voltage VCMmax, it is equal to the maximum common - mode voltage VCMmax, and when the ZMC common - mode voltage VCMzmc is less than the minimum common - mode voltage VCMmin, it is equal to the minimum common - mode voltage VCMmin.

[0164] Figure 20 A signal diagram is shown, which shows operating a power converter in 2 / 3 + PWM mode according to one example. In particular, Figure 20Shows the DC-link voltage V4, the input voltages V1, V2, V3, the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the ZMC common-mode voltage VCMzmc, the common-mode voltage VCM, and the drive signals S1, S2, S3. As can be seen from Figure 20 As seen in, as long as the ZMC common-mode voltage VCMzmc is within the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the power converter operates in the PWM mode (3 / 3 mode), where the common-mode voltage VCM is adjusted to be equal to the ZMC common-mode voltage VCMzmc. When the ZMC common-mode voltage VCMzmc is outside the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the power converter operates in the 2 / 3 mode, where the common-mode voltage VCM is adjusted such that when the ZMC common-mode voltage VCMzmc is greater than the maximum common-mode voltage VCMmax, it is equal to the maximum common-mode voltage VCMmax, and such that when the ZMC common-mode voltage VCMzmc is less than the minimum common-mode voltage VCMmin, it is equal to the minimum common-mode voltage VCMmin. In addition, referring to Figure 20 , the bridge arms 11, 12, 13 are alternately deactivated. That is, when the power converter enters the 2 / 3 mode, one of the bridge arms 11, 12, 13 is deactivated and remains deactivated as long as the 2 / 3 mode prevails. The next time the power converter enters the 2 / 3 mode, another one of the bridge arms 11, 12, 13 is deactivated. In this way, the same bridge arm is deactivated every other time the power converter enters the 2 / 3 mode.

[0165] According to one example, when the duty cycles d1, d2, d3 are calculated according to equations (4a), (4b), (4c) and the common-mode voltage VCM is limited to VCMmax or VCMmin, this deactivation strategy is automatically achieved, i.e., when the ZMC common-mode voltage VCMzmc is greater than the maximum common-mode voltage VCMmax, the common-mode voltage VCM is adjusted to be equal to the maximum common-mode voltage VCMmax, and when the ZMC common-mode voltage VCMzmc is less than the minimum common-mode voltage VCMmin, the common-mode voltage VCM is adjusted to be equal to the minimum common-mode voltage VCMmin. When the common-mode voltage VCM is limited to VCMmax, the duty cycle of the bridge arm with the maximum switch node voltage Vmax' becomes +1, thereby automatically deactivating the corresponding bridge arm. Similarly, when the common-mode voltage VCM is limited to VCMmin, the duty cycle of the bridge arm with the minimum switch node voltage Vmin' becomes -1, thereby automatically deactivating the corresponding bridge arm.

[0166] Figure 20 The midpoint current IY is further shown. As can be seen, the midpoint current IY is zero in the 3 / 3 mode and is non-zero only during those time periods (at those phase angles) when the power converter operates in the 2 / 3 mode.

[0167] Basically, the duration of the period during which the power converter operates in the 2 / 3 mode in one cycle of the input voltage depends on the DC link voltage V4. This is shown in Figure 21 and Figure 22 FIG.

[0168] Figure 21 FIG. shows different operating modes of the first power converter 10 depending on the DC link voltage V4 and the phase angles of the input voltages V1, V2, V3. More specifically, Figure 21 FIG. shows different operating modes in any one of the six operating phases P1 - P6, where each of these operating phases covers 60° of one cycle of the input voltages V1, V2, V3. In Figure 21 FIG., a phase angle of 0° represents the start of the corresponding operating phase, a phase angle of 60° represents the end of the corresponding operating phase, and a phase angle of 30° represents the middle of the corresponding operating phase, which is the moment when the middle input voltage crosses zero in the corresponding operating phase.

[0169] Referring to the above, when the DC link voltage V4 is greater than the maximum line - to - line voltage V LL_MAX , the power converter can operate in the 2 / 3 + PWM mode. In the 2 / 3 + PWM mode, the portion of the power converter in the operating phase that operates in the 3 / 3 mode increases as the DC link voltage V4 increases, and the portion of the power converter in the operating phase that operates in the 2 / 3 mode decreases as the minimum desired DC link voltage V4 MIN increases. Further, when the DC link voltage V4 is such that the ZMC common - mode voltage VCMzmc is always within the range given by the maximum common - mode voltage VCMmax and the minimum common - mode voltage VCMmin during one cycle of the input voltages V1, V2, V3, the power converter operates in the full 3 / 3 mode. The DC link voltage threshold V4 FULL _ 3_3 at which the power converter changes from the 2 / 3 + PWM mode to the full 3 / 3 mode is greater than the maximum line - to - line voltage V LL_MAX , and less than twice the amplitude of the input voltages V1, V2, V3.

[0170] Referring to the above, the power converter can be operated in the 2 / 3 mode at each DC link voltage V4 higher than the maximum line - to - line voltage V LL_MAX . Thus, the power converter can be operated in the 2 / 3 mode or the 2 / 3 + PWM mode at a DC link voltage higher than V4 FULL _ 3_3 . However, this will increase the mid - point current IY, so this is not desirable. However, between the maximum line - to - line voltage V LL_MAX and V4 FULL _3_3 Operating the power converter in 2 / 3+PWM mode at a DC link voltage therebetween helps reduce losses.

[0171] Figure 22 Signal diagrams are shown of drive signals S1, S2, S3, input voltage and input currents I1, I2, I3, and the DC link voltage in 2 / 3+PWM mode and full 3 / 3 mode. As can also be seen from these signal diagrams, the duration of the period during which the power converter operates in 2 / 3 mode decreases as the DC link voltage V4 increases.

[0172] Figure 1 or Figure 3 A power converter of the type shown can be operated in 2 / 3+PWM mode by Figure 23 a control circuit of the type shown. The control circuit is based on Figure 6 the control circuit shown and includes a PWM modulator 44 of the type described previously herein, which generates the duty cycles of drive signals S1, S2, S3 in accordance with equations (4a)-(4c). In addition, a common-mode signal generator 45 is configured to generate a common-mode voltage signal S VCM received by the PWM modulator such that (a) when the ZMC common-mode voltage VCMzmc is within the range given by a maximum common-mode voltage VCMmax and a minimum common-mode voltage VCMmin, the common-mode voltage VCM represented by the common-mode voltage signal S VCM is equal to the ZMC common-mode voltage VCMzmc; and (b) when the ZMC common-mode voltage VCMzmc is outside the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the common-mode voltage VCM is within that range. To calculate the maximum common-mode voltage VCMmax, minimum common-mode voltage VCMmin, and ZMC common-mode voltage VCM zmc in accordance with equations (7), (10a), (10b), the common-mode signal generator 45 receives a DC link voltage signal S V4 representing the DC link voltage V4 and switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF ,.

[0173] In the above explanation, it is assumed that when the DC link voltage V4 is higher than the maximum line-to-line voltage V LL_MAX , the (first) power converter 10 can be operated in 2 / 3+PWM mode. When the DC link voltage V4 is higher than the maximum line-to-line voltage V LL_MAX , the power converter operates in full boost mode. However, when the power converter 10 operates in the above partial boost mode, 2 / 3+PWM mode can also be used. Referring below to Figure 24 andFigure 25 This is described below.

[0174] Figure 24 Shows different operating modes of the first power converter 10 in any one of six operating phases P1 - P6, depending on the DC - link voltage V4 and the phase angles of the input voltages V1, V2, V3. Referring to the above, when the DC - link voltage V4 is substantially between the minimum line - to - line voltage V LL_MIN and the maximum line - to - line voltage V LL_MAX the power converter operates in a partial boost mode. In the Figure 24 example shown, in the partial boost mode, the power converter operates in a 1 / 3 mode, 2 / 3 mode, or 3 / 3 mode, where as the DC - link voltage V4 increases, the phase - angle range (duration of the time period) in which the power converter operates in the 1 / 3 mode decreases, and the phase - angle ranges in which the power converter operates in the 2 / 3 or 3 / 3 modes increase.

[0175] Figure 25 Shows the corresponding signal diagrams for operating the power converter in the partial boost mode and the 2 / 3 + PWM mode.

[0176] When generating a common - mode voltage signal S Figure 22 using a common - mode voltage signal generator 45 of the type explained with reference to VCM it is possible to implement the operation of the first power converter 10 in the partial boost mode of the type shown in Figure 10 by means of a control circuit of the type shown in Figure 24 and Figure 25 In this case, when the second power converter 5 generates a DC - link voltage V4 such that it is equal to the voltage represented by Smax' - Smin', the common - mode voltage signal generator 45 automatically generates a common - mode signal so that the common - mode voltage VCM complies with equation (5), i.e., the common - mode voltage used in the 1 / 3 mode.

Claims

1. A method, comprising: Reducing the switching mode operation of a power converter (10), wherein the power converter comprises: Three input nodes (A, B, C), each input node being configured to receive a respective one of three input voltages (V1, V2, V3); Two DC link nodes (X, Z), configured to provide a DC link voltage (V4); A midpoint (Y), coupled to each of the two DC link nodes (X, Z); Three inductors (L1, L2, L3), each inductor being connected to a respective one of the three input nodes (A, B, C); and A rectifier bridge (1), comprising three bridge arms (11, 12, 13), each bridge arm being coupled to a respective one of the three input nodes (A, B, C) through a respective one of the three inductors (L1, L2, L3) and connected to a respective one of the three inductors (L1, L2, L3) at respective switching nodes (A', B', C'), wherein each of the three bridge arms (11, 12, 13) is further connected to the two DC link nodes (X, Z) and the midpoint (Y), and comprises at least one electronic switch (Q1, Q2, Q3), Wherein reducing the switching mode operation of the power converter comprises operating the power converter in a 2 / 3 mode, and Wherein operating the power converter in the 2 / 3 mode comprises deactivating one of the three bridge arms (11, 12, 13) and activating two of the three bridge arms (11, 12, 13) during a specific portion of a cycle of the input voltages (V1, V2, V3).

2. The method according to claim 1, wherein, Operating the power converter in the 2 / 3 mode comprises: Calculating a zero midpoint current (ZMC) common mode voltage (VCMzmc), a minimum desired common mode voltage (VCMmin), and a maximum desired common mode voltage (VCMmax); and Operating the power converter in the 2 / 3 mode when the zero midpoint current common mode voltage (VCMzmc) is outside a voltage range defined by the minimum desired common mode voltage (VCMmin) and the maximum desired common mode voltage (VCMmax).

3. The method according to claim 2, further comprising adjusting the common mode voltage (VCM) such that: When the zero midpoint current common mode voltage (VCMzmc) is greater than the maximum desired common mode voltage (VCMmax), the common mode voltage is equal to the maximum desired common mode voltage (VCMmax), and When the zero midpoint current common mode voltage (VCMzmc) is less than the minimum desired common mode voltage (VCMmin), the common mode voltage is equal to the minimum desired common mode voltage (VCMmin).

4. The method according to any one of the preceding claims, further comprising: Operate the power converter in a 1 / 3 mode or a 3 / 3 mode during the remaining time of the period of the three input voltages (V1, V2, V3), wherein, in the 1 / 3 mode, one of the three bridge arms is enabled, and in the 3 / 3 mode, none of the three bridge arms is disabled.

5. The method according to claim 4, wherein Operating the power converter in the 3 / 3 mode includes: When the zero midpoint current common mode voltage (VCMzmc) is within the voltage range defined by the minimum desired common mode voltage (VCMmin) and the maximum desired common mode voltage (VCMmax), operate the power converter in the 3 / 3 mode.

6. The method according to claim 4, wherein Operating the power converter in the 1 / 3 mode further includes: Calculating the desired switch node voltages (VA', VB', VC') of each of the three bridge arms (11, 12, 13); Disabling one of the three bridge arms associated with the maximum value (Vmax') of the desired switch node voltages (VA', VB', VC'); and Disabling one of the three bridge arms associated with the minimum value (Vmin') of the desired switch node voltages (VA', VB', VC').

7. The method according to claim 6, further comprising: Adjusting the DC link voltage (V4) by another power converter (5).

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