Fault ride-through method of Si / SiC frequency mixing parallel inverter system capable of active junction temperature management and system thereof

Abstract

The invention discloses a fault ride-through method and system of a Si / SiC frequency mixing parallel inverter system capable of active junction temperature management. The method comprises the following steps: S1, acquiring data points; s2, obtaining a double-sequence current reference value; s3, adjusting an operation mode to perform junction temperature management; the maximum value Imax of the current output current is calculated, and the operation mode is adjusted according to the size relation between the Imax and the Ilim1, the Ilim2 and the Ilim3; s4, performing double-sequence current control; the system comprises a data point acquisition module, a current reference value generation module, a junction temperature management module and a double-sequence current control module.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and particularly relates to a fault ride-through method and system for a Si / SiC hybrid switching frequency parallel inverter system with active junction temperature management. Background Art

[0002] Compared with grid-connected inverters based on Si IGBTs, grid-connected inverters based on SiC MOSFETs have been significantly improved in terms of efficiency, power density, power quality, etc. However, the cost per ampere of SiC MOSFETs is relatively high, the rated current is limited, and the long-term reliability problem has not been solved, which restricts its large-scale engineering promotion in high-power power conversion scenarios.

[0003] To solve this problem, a new concept of a hybrid switching frequency parallel inverter system (HSFPIS) has been recently proposed. As shown in Figure 1, the HSFPIS is composed of a high-power Si IGBT main unit (MU) and a low-power SiC MOSFET auxiliary unit (SU) connected in parallel. Among them, the MU processes most of the load power at a low switching frequency to achieve the advantages of large current and low cost; while the SU processes a small part of the load power at a high switching frequency and compensates for the low-frequency ripple generated by the MU, thereby significantly improving the power quality of the grid-connected current. By reasonably configuring the MU and SU, the HSFPIS can provide almost the same efficiency and power quality as a full SiC MOSFET inverter, while significantly reducing the component cost.

[0004] Previous work has focused on the design and optimization of the HSFPIS itself under rated conditions, including hardware circuit design, power distribution ratio and switching frequency optimization, precise ripple compensation strategy, etc. There has been no report on how the HSFPIS can operate reliably and support the reliable power supply of the grid under grid fault conditions. The addition of control degrees of freedom in the main and auxiliary converter units inside the HSFPIS provides the possibility to improve the overload capacity of the system to cope with various complex fault conditions. However, the thermal characteristics of the MU and SU are significantly different. Without appropriate control strategies, the loss heating will be overly concentrated in the SU, which will further lead to the difficulty in fully exerting the overload capacity of the HSFPIS and even cause damage to the SU. Summary of the Invention

[0005] In view of this, the present invention provides a fault ride-through method and system for a Si / SiC hybrid switching frequency parallel inverter system with active junction temperature management, so as to at least solve the problem of how the HSFPIS can operate reliably and support the reliable power supply of the grid under grid fault conditions.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A fault ride-through method for a Si / SiC hybrid parallel inverter system with active junction temperature management, comprising the following steps: S1. Obtain data points; Denote the moment when the grid fault occurs as t = 0, sample t the grid connection point voltage at the moment of = 0 - and the current , and calculate the grid voltage according to and to obtain the amplitude of the positive sequence component of , the amplitude of the negative sequence component and the phase angle difference between the positive and negative sequence components , and form the data point ; S2. Obtain the double-sequence current reference value; Obtain the optimal current reference value that needs to be injected into the system corresponding to the data point , and achieve fault ride-through based on the current optimal current reference value, and update the current output current , where the optimal current reference value includes: d the positive sequence reference current on the axis q , the positive sequence reference current on the d axis , q the negative sequence reference current on the axis S3. Adjust the operation mode for junction temperature management; Calculate the maximum value of the current output current , and adjust the operation mode according to the magnitude relationship between and , and , where , and are the load current values corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in Mode 1, Mode 2, and Mode 3 respectively. Modes 1 to 4 are respectively: Mode 1: Maintain the rated parameters; When is within the range of , maintain the DC link voltage , the switching frequency and the power distribution ratio K unchanged, and do not modify any parameters; Mode 2: Retain the parameter values in Mode 1 and only reduce the DC link voltage ; When is within the range of , reduce Until the lowest DC voltage required for AC-DC conversion is achieved; Mode 3: Retain the parameter values in Mode 2 and adjust the switching frequency and the power distribution ratio K ; When is within the range, decrease the adjusted switching frequency until the adjusted switching frequency required to meet the minimum output power quality is satisfied, and increase the power distribution ratio K until the maximum current that SU can withstand flows through it; Mode 4: Retain the parameter values in Mode 3 and limit the current; when occurs, take current limiting measures and adjust to or less; S4. Dual-sequence current control; Perform output current control in the dq coordinate system to make the output current track the optimal current reference value and achieve optimal fault ride-through. The specific content of optimal fault ride-through is as follows: With the constraints of grid connection point voltage support, power fluctuation suppression, and current peak limit, the goal is to maximize the transmitted active power.

[0007] Preferably, the specific content of calculating the grid voltage and in S1 includes: ; Among them, is the positive-sequence complex vector of the grid voltage dq in the coordinate system, is the negative-sequence complex vector of the grid voltage in the coordinate system, dq is the positive-sequence complex vector of the grid connection point voltage in the coordinate system, dq is the negative-sequence complex vector of the grid connection point voltage in the coordinate system, dq is the positive-sequence complex vector of the grid connection point current in the coordinate system, dq is the negative-sequence complex vector of the grid connection point current in the coordinate system, dq where, is a complex vector representing or or ; and are respectively the axis and d axis ofq The component on the axis is the imaginary unit is the fundamental angular frequency is the line inductance

[0008] Preferably, the specific content of S2 includes: Based on the optimal current reference value lookup table, obtain the data points through interpolation The corresponding optimal current reference value to be injected into the system Among them, the specific content of obtaining the optimal current reference value lookup table is: Assume that the positive and negative sequence components of the current that the converter needs to inject into the power grid are and ; After injecting the corresponding current, the PCC voltage amplitude, current amplitude, and active power fluctuation values are expressed as: ; ; ; In the formula, , and are respectively on the components on the three phases , and are respectively on the components on the three phases is the active power fluctuation value. Other parameters in the formula are all intermediate variables, and the calculation methods are respectively: ; ; ; In the formula, and are respectively the of the point of common coupling voltage d axis and q axis positive sequence components and are respectively the of the point of common coupling voltage d axis and q axis negative sequence components; and are respectively the of the current reference value d axis and q axis positive sequence components and are respectively the current reference value of d axis and q the negative-sequence component of the axis, where the current reference value is the current value that enables the current to meet the fault ride-through requirements; By substituting the PCC voltage amplitude, current amplitude, and active power fluctuation value into the constraint conditions in the optimal fault ride-through at several data points and solving the objective, an optimal current reference value lookup table is obtained; For data points not covered by the optimal current reference value lookup table, the interpolation method is used to determine the current reference value.

[0009] Preferably, calculate the maximum value of the output current of the system under the optimal current reference value The specific content of which includes: ; In the formula, and are respectively the d axis and q axis components of the current output at present.

[0010] Preferably, the optimal fault ride-through in S4 is expressed as: ; Wherein, is the active power output by the system, is the active power fluctuation value; , are the output voltage and current amplitudes, is the rated voltage, is the power reference value.

[0011] A fault ride-through system for a Si / SiC hybrid parallel inverter system with active junction temperature management, comprising: A data point acquisition module, used to record the moment of grid fault as t = 0, sample t = the grid-connected point voltage at the 0 - moment and current , according to and calculate the grid voltage , and obtain the positive-sequence component amplitude , the negative-sequence component amplitude and the phase angle difference between the positive and negative sequence components, and form the data point ; A current reference value generation module, used to obtain the optimal current reference value that needs to be injected into the system corresponding to the data point , implement fault ride-through based on the current optimal current reference value, and update the current output current , where the optimal current reference value includes: d Positive sequence reference current of the axis , q Positive sequence reference current of the axis , d Negative sequence reference current of the axis and q Positive sequence reference current of the axis ; Junction temperature management module, used to calculate the maximum value of the current output currently , and according to and , and 's magnitude relationship to adjust the operation mode, where , and are respectively the load current values corresponding to when the Si or SiC junction temperature reaches the highest junction temperature in Mode 1, Mode 2, and Mode 3. Modes 1 to 4 are respectively: Mode 1: Keep the rated parameters; when is within the interval, keep the DC link voltage , switching frequency and power distribution ratio K unchanged, without modifying any parameters; Mode 2: Retain the parameter values in Mode 1, only reduce the DC link voltage ; when is within the interval, reduce until the lowest DC voltage required to complete the AC-DC conversion; Mode 3: Retain the parameter values in Mode 2, adjust the switching frequency and power distribution ratio K ; when is within the interval, reduce the adjusted switching frequency until the adjusted switching frequency required to meet the lowest output power quality is satisfied, and increase the power distribution ratio K until the maximum current that can be tolerated flows through SU; Mode 4: Retain the parameter values in Mode 3, limit the current; when , take current limiting measures, and adjust to or less; Dual-sequence current control module, used for dqOutput current control is carried out under the coordinate system to make the output current track the optimal current reference value and achieve optimal fault ride-through. The specific content of the optimal fault ride-through is as follows: Under the constraint conditions of grid connection point voltage support, power fluctuation suppression, and current peak limit, the maximum transmission active power is taken as the goal.

[0012] As can be seen from the above technical solutions, compared with the prior art, the present invention discloses a fault ride-through method and system for a Si / SiC hybrid parallel inverter system with active junction temperature management, having the following beneficial effects: The present invention provides a fault ride-through method with an active junction temperature management function for HSFPIS. This method consists of device-level active junction temperature control and system-level optimal support control. Among them, the device-level control realizes the maximization of the overload capacity of HSFPIS by adjusting parameters such as the switching frequency, power distribution ratio, and DC side voltage; the system-level control rationally distributes positive and negative sequence currents, makes full use of the overload capacity of HSFPIS, and realizes the comprehensive optimization of grid connection point voltage support, output current amplitude limit, power fluctuation suppression, power output maximization and other ride-through goals, effectively improving the fault overcurrent capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 It is the basic topological structure of the Si / SiC HSFPIS provided by the embodiment of the present invention; Figure 2 It is the flowchart of a fault ride-through method for a Si / SiC hybrid parallel inverter system with active junction temperature management provided by the present invention; Figure 3 It is the output current of HSFPIS under the overload condition provided by the embodiment of the present invention and the MU current and the SU current as well as the junction temperature waveforms of MU and SU; Figure 4 It is the principle block diagram of a fault ride-through method for a Si / SiC hybrid parallel inverter system with active junction temperature management provided by the present invention; Figure 5 It is the four operating modes of the active junction temperature management strategy provided by the embodiment of the present invention; Figure 6 It is the optimal current reference value lookup table provided by the embodiment of the present invention; among them, (a) according to , and , search for , (b) according to , and , search for , (c) according to , and , search for ; (d) according to , and , search for ; Figure 7 is the schematic diagram of each fault type provided by the embodiment of the present invention; among them, (a) single-phase grounding fault of phase A; (b) interphase short circuit of phases A and B; (c) two-phase grounding of phases A and B; Figure 8 is the simulation result under each typical fault provided by the embodiment of the present invention. Specific implementation manner

[0015] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0016] The present invention provides a fault ride-through method for a Si / SiC hybrid parallel inverter system with active junction temperature management, as shown in Figure 2 below, including the following steps: S1. Obtain data points; record the moment when the grid fault occurs as t =0, sample the grid-connected point voltage t and current at =0 - moment, and calculate the grid voltage according to and to obtain the positive sequence component amplitude of , negative sequence component amplitude and the phase angle difference between the positive and negative sequence components, and form the data point ; S2. Obtain the double-sequence current reference value; obtain the optimal current reference value that needs to be injected into the system corresponding to the data point , implement fault ride-through based on the current optimal current reference value, and update the current output current , where the optimal current reference values ​​include: d Axis positive sequence reference current , q Axis positive sequence reference current , d Axis negative sequence reference current and q Axis positive sequence reference current ; S3. Adjust the operating mode to manage junction temperature; calculate the maximum value of the current output current , and according to and , and The size relationship is used to adjust the operating mode, where , and They are the load current values ​​corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in mode 1, mode 2 and mode 3, respectively. Modes 1 to 4 are: Mode 1: Maintain rated parameters; when exist When within the range, the DC link voltage is maintained , switching frequency and power distribution ratio K No change, no parameters are modified; Mode 2: Keep the parameter values ​​in Mode 1 and only reduce the DC link voltage ;when exist When within the range, reduce Until the minimum DC voltage required to complete the AC-DC conversion; Mode 3: Keep the parameter values ​​in Mode 2 and adjust the switching frequency and power distribution ratio K ;when exist When the switching frequency is within the range, the switching frequency is reduced until the switching frequency required to meet the minimum output power quality is met, thereby improving the power distribution ratio. K Until the maximum current that SU can withstand flows through it; Mode 4: Keep the parameter values ​​in Mode 3 and limit the current; when When Adjust to the following; S4. Double sequence current control; dq The output current is controlled in the coordinate system so that the output current tracks the optimal current reference value and realizes optimal fault ride-through. The specific content of optimal fault ride-through is: under the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to transmit the maximum active power.

[0017] The HSFPIS is composed of a parallel hybrid of a high-power Si IGBT main unit (MU) and a low-power SiC MOSFET auxiliary unit (SU). As shown in Figure 1, the system specifications are as follows: the output current has a rated value of 80 A, and the DC side voltage U dc has a rated value of 1200 V; the power distribution ratio between the MU and the SU is 4:1, that is, the MU processes 80% of the load current and the SU processes 20% of the rated current; the device models of the power devices used in the MU and the SU are infineon IKQ75N120CH7 (1200 V, 82 A) and wolfspeed C2M0080120D (1200 V, 36 A) respectively, and the switching frequencies are 20 kHz and 100 kHz respectively; in the figure C dc is the DC link capacitor, L 1 is the MU filter inductor, L 2 is the SU filter inductor. In order to illustrate the basic principle of the HSFPIS and the problem of the junction temperature imbalance between the MU / SU, Figure 3 from top to bottom shows the output current of the HSFPIS , the MU current , the SU current and the junction temperature waveforms of the MU and the SU under the overload condition.

[0018] (1) The basic principle of the HSFPIS: As can be seen from the current waveforms in Figure 3 , the MU in the HSFPIS is used to process most of the load power, while the SU is used to compensate for the harmonics generated by the MU to improve the power quality. On the one hand, in order to reduce the switching losses, the high-power MU operates at a low switching frequency. On the other hand, although the SU needs to work at a high switching frequency to ensure the compensation accuracy, it only processes a small part of the power, so the increase in the switching frequency will not significantly reduce the overall efficiency. Therefore, through the combination of the MU and the SU, the HSFPIS combines the high-power and low-cost characteristics of the Si inverter and the excellent switching characteristics of the SiC inverter.

[0019] (2) The problem of the junction temperature imbalance between the MU / SU: In order to cope with various complex grid conditions that may occur during grid-connected operation, the HSFPIS needs to have a certain overload capacity. As can be seen from the junction temperature distribution curve in Figure 3 , under the 1.5 p.u. overload condition, the junction temperature of the SU approaches its threshold of 150 °C; under higher overload conditions, the junction temperature of the SU exceeds the limit, while the junction temperature of the MU is still below the threshold, indicating that the junction temperature imbalance problem restricts the best performance of the HSFPIS overload capacity.

[0020] In order to give full play to the overload capacity of HSFPIS and achieve optimal fault ride-through, the present invention proposes a HSFPIS fault ride-through strategy based on multi-level collaboration of "device + system", such as Figure 4 As shown, U g1 To isolate the grid side voltage of the transformer, V MU is the MU control pulse signal, V SU is the pulse signal for SU control. The proposed strategy consists of two main parts: 1) Active device-level junction temperature management: Dynamically adjust the power device operation mode based on the output current reference, thereby maximizing the system overload capacity while avoiding junction temperature exceeding the limit; 2) System-level optimal support strategy: Make full use of the system overload capacity to achieve comprehensive optimization of grid connection point voltage support, output current amplitude limitation, power fluctuation suppression and other goals under grid faults.

[0021] HSFPIS needs to withstand high overcurrent during fault ride-through, and the junction temperature of internal power devices increases significantly, facing the risk of failure. To this end, the present invention proposes a new junction temperature active management strategy based on load current amplitude to fully utilize the favorable characteristics of each device in the hybrid structure. The main motivation of the proposed strategy is to keep the junction temperature of the main and auxiliary units in HSFPIS below the threshold (set to 150°C in this embodiment) to ensure the safe operation of the device, while maximizing the overall overcurrent capability of the system. The new junction temperature active management strategy consists of four operating modes with different DC link voltages, switching frequencies and power allocation ratios, such as Figure 5 As shown, in this embodiment, each mode is specifically set as follows: (1) Mode 1: Maintain rated parameters. When the load current amplitude is When the temperature is within the range, even if no parameters are modified, HSFPIS can ensure that the junction temperature of the internal MU and SU is lower than 150℃.

[0022] (2) Mode 2: Reduce the DC link voltage. In typical scenarios such as photovoltaic power generation and wind power generation, the converter system usually has a DC voltage control link. The switching loss of the power device is positively correlated with the DC bus voltage. Reducing the DC voltage can significantly reduce the temperature of the power device. In this embodiment, when the load current amplitude is When the DC bus voltage is within the range, it is adjusted from 1200 V to 800 V.

[0023] (3) Mode 3: Adjust the switching frequency and power distribution ratio. Due to the limitation of DC voltage utilization, the inverter DC voltage cannot be too low. When within the interval, only reducing the DC bus voltage can no longer ensure the reliability of power devices. At this time, the switching frequencies of MU and SU are respectively reduced to 10 kHz and 50 kHz to reduce switching losses at the expense of a certain power quality; the power distribution ratio K is increased to 5.66:1 to avoid excessive concentration of loss heating in SU. In particular, when occurs, the junction temperatures of MU and SU reach 150 °C simultaneously, indicating is the maximum overcurrent that HSFPIS can withstand.

[0024] (4) Mode 4: Current limiting. When the load current is greater than , current limiting measures need to be taken.

[0025] The values of , and are determined by simulation to be: 120 A (1.50 p.u.), 145 A (1.81 p.u.) and 185 A (2.31 p.u.) respectively.

[0026] To further implement the above technical solution, the specific content of calculating the grid voltage and in S1 includes: ; ; where is the positive sequence complex vector of the grid voltage dq in the coordinate system, is the negative sequence complex vector of the grid voltage dq in the coordinate system, is the positive sequence complex vector of the grid connection point voltage dq in the coordinate system, is the negative sequence complex vector of the grid connection point voltage dq in the coordinate system, is the positive sequence complex vector of the grid connection point current dq in the coordinate system, is the negative sequence complex vector of the grid connection point current dq in the coordinate system, , where is a complex vector representing or , and are respectively the axis and d axis of qThe component on the axis is the imaginary unit is the fundamental angular frequency is the line inductance

[0027] It should be noted that assuming that the grid fault occurs at t = 0. Before and after enabling the fault ride-through strategy, the grid voltage u g can be considered to remain unchanged. Therefore, the grid voltage can be obtained through the circuit state at t = 0−, and then the fault type can be judged

[0028] To further implement the above technical solution, the specific content of S2 includes Based on the optimal current reference value lookup table, the optimal current reference value to be injected into the system corresponding to the data point is obtained by interpolation The specific content of obtaining the optimal current reference value lookup table is Assuming that the positive and negative sequence components of the current that the converter needs to inject into the grid are and ; after injecting the corresponding current, the PCC voltage amplitude, current amplitude, and active power fluctuation value are expressed as ; ; ; In the formula, , and are respectively the components of on the three phases, and are respectively the components of on the three phases, is the active power fluctuation value, and other parameters in the formula are all intermediate variables, and the calculation methods are respectively ; ; ; In the formula, and are respectively the axis and d axis positive sequence components of the grid connection point voltage q , and are respectively the axis of the grid connection point voltage​d Axis and q negative sequence component of the axis; and are respectively the current reference values of d axis and q positive sequence component of the axis, and are respectively the current reference values of d axis and q negative sequence component of the axis, where the current reference value is the current value that enables the current to meet the fault ride-through requirements; By substituting the PCC voltage amplitude, current amplitude, and active power fluctuation values into the constraint conditions in the optimal fault ride-through at several data points and solving the objective, an optimal current reference value lookup table is obtained; For data points not covered by the optimal current reference value lookup table, interpolation methods are used to determine the current reference value.

[0029] It should be noted that: By performing optimal fault ride-through solution on the above PCC voltage amplitude, current amplitude, and active power fluctuation value expressions at several data points, an optimal current reference value lookup table as shown in Figure 6 can be obtained. Figure 6 It shows that given a set of positive and negative sequence component amplitudes and phase angle difference of the grid voltage, a unique set of current reference values , , and that satisfy Equation (1) can be determined. For data points not covered by the data lookup table, interpolation methods can be used to determine the current reference value.

[0030] Based on the optimal current reference value lookup table shown in Figure 5 , through high-dimensional interpolation methods (such as linear interpolation, nearest neighbor interpolation, etc.), calculate the current reference values corresponding to the data point , , and .

[0031] To further implement the above technical solution, the specific content of calculating the maximum output current of the system under the optimal current reference value includes: ; In the formula, and are respectively the d axis andq Axis component.

[0032] To further implement the above technical solution, the optimal fault ride-through in S4 is expressed as: ; Wherein, is the active power output of the system, is the active power fluctuation value; are the output voltage and current amplitudes, is the rated voltage, is the power reference value.

[0033] It should be noted that: How to reasonably utilize the over-current capacity of HSFPIS to achieve optimal fault ride-through is the problem to be solved by the above optimal ride-through model. To reduce the impact of grid faults on the load, it is usually expected that the grid-connected converter has functions such as grid connection point voltage support, power fluctuation suppression, and current peak limitation under fault conditions, and transmits as much active power as possible. Therefore, the control objective of the fault ride-through strategy proposed in this embodiment can be expressed by the above model.

[0034] A fault ride-through system for a Si / SiC hybrid parallel inverter system with active junction temperature management, comprising: A data point acquisition module, configured to record the occurrence time of the grid fault as t =0, sample the grid connection point voltage t and current at =0 - and calculate the grid voltage , obtain the positive sequence component amplitude of , the negative sequence component amplitude and the phase angle difference between the positive and negative sequence components, and form a data point ; A current reference value generation module, configured to obtain the optimal current reference value to be injected into the system corresponding to the data point , implement fault ride-through based on the current optimal current reference value, and update the current output current , wherein the optimal current reference value includes: d The positive sequence reference current on the axis, q The positive sequence reference current on the axis, d The negative sequence reference current on the axis, and q The positive sequence reference current on the axis; The junction temperature management module is used to calculate the maximum value of the current output at present. , and according to and 、 and to adjust the operation mode, where 、 and are the load current values corresponding to the maximum junction temperature of Si or SiC in Mode 1, Mode 2 and Mode 3 respectively. Modes 1 to 4 are respectively: Mode 1: Keep the rated parameters; when is within interval, keep the DC link voltage , switching frequency and power distribution ratio K unchanged, without modifying any parameters; Mode 2: Retain the parameter values in Mode 1, only reduce the DC link voltage ; when is within interval, reduce until the lowest DC voltage required to complete the AC-DC conversion; Mode 3: Retain the parameter values in Mode 2, adjust the switching frequency and power distribution ratio K ; when is within interval, reduce the regulated switching frequency until the regulated switching frequency required to meet the lowest output power quality is satisfied, and increase the power distribution ratio K until the maximum current that SU can withstand flows through it; Mode 4: Retain the parameter values in Mode 3, limit the current; when , take current limiting measures to adjust to or less; The two-order current control module is used to control the output current in the dq coordinate system, so that the output current tracks the optimal current reference value and realizes the optimal fault crossing. The specific content of the optimal fault crossing is: under the constraint conditions of grid connection point voltage support, power fluctuation suppression and current peak limit, with the maximum transmitted active power as the goal.

[0035] The present invention will be further described through simulation experiments below: As Figure 7 shown, at a certain point in the system, (a) A-phase single-phase ground fault, (b) A, B-phase interphase short circuit and (c) A, B-phase two-phase ground fault occur in sequence, where and are the voltages of the fault point A, B, C phases respectively. and are the phase A, B, and C currents at the fault points respectively, is the grounding impedance. Using the method of the present invention, based on the voltage and current signals measured at the PCC point, the fault type ( ), and the optimal current reference value required for fault ride-through ( and ) are calculated, as shown in Table 1, where is the maximum phase voltage amplitude, is the minimum phase voltage amplitude. In addition, Table 1 also gives the theoretical values of the active power and the PCC voltage range after applying the fault ride-through strategy. The simulation results are as Figure 8 shown.

[0036] Table 1 Optimal current reference values, operating modes, and theoretical ride-through effects under different fault conditions ; (1) Scenario 1: Single-phase grounding fault.

[0037] At t = 0 s, a single-phase grounding fault of phase A occurs at a certain point on the grid side of the isolation transformer in the system, and the fault lasts for 0.5 s. At the on the converter side of the isolation transformer, an asymmetric voltage dip of phases A and B is observed, where the minimum phase voltage, phase A, drops to 0.69 p.u. Through sampling and calculation, the positive-sequence component amplitude, negative-sequence component amplitude, and the phase angle difference between the positive and negative sequence components of are 251.182 V, 61.9919 V, and 0.627128 rad / s respectively.

[0038] By looking up the table and interpolation operation, the optimal current reference value required for fault ride-through is obtained, as shown in Table 1. At the same time, the maximum output current of the system under these current reference values is calculated to be 126.5701 A. Therefore, the system operating mode is adjusted to Mode 2, that is, the DC bus voltage is 800 V, the power distribution ratio between the MU and the SU is 4:1, and the switching frequencies of the MU and the SU are 20 kHz and 100 kHz respectively.

[0039] After applying the fault ride-through strategy, the minimum phase voltage at the PCC is lifted to 0.87 p.u., which is greater than the threshold of 0.85 p.u. specified by the national standard. At the same time, the maximum phase voltage and the maximum phase current are 1.10 p.u. and 1.58 p.u. respectively. The errors between the sampled values and the measured values of the maximum phase voltage, minimum phase voltage, and maximum phase current are 1.9%, 2.1%, and 0.07% respectively.

[0040] (2) Scenario 2: Interphase short-circuit fault.

[0041] Att At \(t = 0.5\ s\), a two-phase short circuit fault occurs at a certain point on the grid side of the isolation transformer in the system, and the fault lasts for \(0.5\ s\). At the point on the converter side of the isolation transformer, an asymmetric voltage dip of phases B and C is observed, and the minimum phase voltage, phase B, drops to \(0.71\ p.u.\). Through sampling and calculation, the positive sequence component amplitude, negative sequence component amplitude, and the phase angle difference between the positive and negative sequence components are \(267\ V\), \(47.5251\ V\), and \(-1.2901\ rad / s\) respectively.

[0042] By looking up the table and interpolation operation, the optimal current reference value required for fault ride-through is obtained, as shown in Table 1. At the same time, it is calculated that the maximum system output current under these current reference values is \(114.3585\ A\). Therefore, the system operation mode is adjusted to Mode 1, that is, the DC bus voltage is \(1200\ V\), the power distribution ratio between MU and SU is \(4:1\), and the switching frequencies of MU and SU are \(20\ kHz\) and \(100\ kHz\) respectively.

[0043] After applying the fault ride-through strategy, the minimum phase voltage at the PCC is raised to \(0.92\ p.u.\), which is greater than the threshold of \(0.85\ p.u.\) specified by the national standard. At the same time, the maximum phase voltage and maximum phase current are \(1.09\ p.u.\) and \(1.43\ p.u.\) respectively. The errors between the sampled values and the measured values of the maximum phase voltage, minimum phase voltage, and maximum phase current are \(0.8\%\), \(2.8\%\), and \(0.3\%\) respectively.

[0044] (3) Scenario 3: Two-phase grounding fault.

[0045] At t \(t = 1.0\ s\), a two-phase grounding fault occurs at a certain point on the grid side of the isolation transformer in the system, and the fault lasts for \(0.5\ s\). At the point on the converter side of the isolation transformer, an asymmetric voltage dip of three phases is observed, and the minimum phase voltage, phase B, drops to \(0.42\ p.u.\). Through sampling and calculation, the positive sequence component amplitude, negative sequence component amplitude, and the phase angle difference between the positive and negative sequence components are \(190.696\ V\), \(62.8239\ V\), and \(-1.60899\ rad / s\) respectively.

[0046] By looking up the table and interpolation operation, the optimal current reference value required for fault ride-through is obtained, as shown in Table 1. At the same time, it is calculated that the maximum system output current under these current reference values is \(180.9725\ A\). Therefore, the system operation mode is adjusted to Mode 3, that is, the DC bus voltage is \(800\ V\), the power distribution ratio between MU and SU is \(5.66:1\), and the switching frequencies of MU and SU are \(10\ kHz\) and \(50\ kHz\) respectively.

[0047] After applying the fault ride-through strategy, the minimum phase voltage at the PCC is raised to 0.87 p.u., which is greater than the threshold of 0.85 p.u. specified by the national standard. At the same time, the maximum phase voltage and the maximum phase current are 1.10 p.u. and 2.28 p.u. respectively. The errors between the sampled values and the measured values of the maximum phase voltage, the minimum phase voltage and the maximum phase current are 1.8%, 2.1% and 0.5% respectively.

[0048] In addition, the output power and the device junction temperature during the whole process of the fault are also observed. Under the three fault scenarios, the average output powers are 37.65 kW, 37.72 kW and 37.85 kW respectively, indicating that the fault ride-through strategy proposed in the present invention can maximize the active power transmission during the fault. During the whole process of the fault, the maximum junction temperature of the Si IGBT in the MU is 127 °C, and the maximum junction temperature of the SiC MOSFET in the SU is 144.363 °C, both of which do not exceed the threshold junction temperature of 150 °C for the safe operation of the power device.

[0049] In a power system with a high proportion of renewable energy, grid-connected converters need to have a certain overload capacity to cope with complex working conditions and provide grid support. To improve the overload capacity, traditional converters rely on selecting power devices with larger ratings, which greatly increases the system cost. Therefore, the present invention provides a fault ride-through strategy with an active junction temperature management function for the newly proposed HSFPIS. The proposed strategy consists of device-level active junction temperature control and system-level optimal support control. Among them, the device-level control is used to give full play to the advantages of the HSFPIS topology structure to maximize the overload capacity; the system-level control makes full use of the overload capacity of the HSFPIS to comprehensively optimize the crossing target. The main conclusions are as follows: (1) Through the reasonable cooperation of the Si-based MU and the SiC-based MU, the overcurrent capacity of the HSFPIS is fully exploited, avoiding excessive dependence on redundant design. During the grid fault, a support current of up to 2.3 p.u. can be injected into the grid, which is a 153% increase compared with the 1.5 p.u. overcurrent capacity of traditional converters.

[0050] (2) Through multi-level collaborative control at the device level and the system level, the maximum active power transmission during the grid fault is achieved. Considering the constraints such as grid connection point voltage support, power fluctuation suppression and current peak limit, a fault ride-through strategy for the grid-connected system oriented to maximum power output is proposed. The proposed strategy can greatly improve the maximum active power output capacity of the grid-connected system during the grid fault by reasonably allocating positive and negative sequence currents, thereby minimizing the active power deficit to the greatest extent and avoiding large-area load shedding.

[0051] In addition, the proposed fault ride-through strategy is verified under typical fault scenarios such as single-phase ground fault, phase-to-phase short-circuit fault, and two-phase ground fault. The results show that during the whole process of the fault, the output power of the system hardly degrades, and the junction temperature of the power device remains within the safe operating range.

[0052] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A fault ride-through method for a Si / SiC hybrid parallel inverter system with active junction temperature management, characterized in that, Including the following steps: S1. Obtain data points; record the moment of power grid fault as t = 0, sample t = the grid connection point voltage at time 0 - and current , according to and calculate the power grid voltage , obtain the amplitude of the positive sequence component of , the amplitude of the negative sequence component and the phase angle difference between the positive and negative sequence components , and form the data point ; S2. Obtain the double - order current reference value; Obtain data points The corresponding optimal current reference value to be injected into the system, implement fault ride-through based on the current optimal current reference value, and update the current output current , where the optimal current reference value includes: d Positive sequence reference current of the axis 、 q Positive sequence reference current of the axis 、 d Negative sequence reference current of the axis and q Positive sequence reference current of the axis ; S3. Adjust the operating mode for junction temperature management; calculate the maximum value of the current output at present , and adjust the operating mode according to the relationship between , and . Among them, , and are the load current values corresponding to the maximum junction temperature of Si or SiC in Mode 1, Mode 2, and Mode 3 respectively. Modes 1 to 4 are respectively: Mode 1: Maintain rated parameters; When Within Interval, maintain the DC link voltage , switching frequency And power distribution ratio K Unchanged, without modifying any parameters; Mode 2: Retain the parameter values in Mode 1 and only decrease the DC link voltage ; When is in interval, decrease until the lowest DC voltage required to complete AC-DC conversion is reached; Mode 3: Retain the parameter values in Mode 2 and adjust the switching frequency and the power distribution ratio K ; When within the interval, reduce the adjusted switching frequency until the adjusted switching frequency required to meet the minimum output power quality is reached, and increase the power distribution ratio K until the maximum current that can be tolerated flows through SU; Mode 4: Retain the parameter values in Mode 3 and limit the current; When occurs, take current limiting measures and adjust to or below; S4. Dual - order current control; Output current control is carried out in the dq coordinate system to make the output current track the optimal current reference value and achieve optimal fault ride - through. The specific content of the optimal fault ride - through is as follows: With the constraints of grid - connected point voltage support, power fluctuation suppression, and current peak limit, the goal is to maximize the transmitted active power.

2. The fault ride-through method of a Si / SiC hybrid parallel inverter system with active junction temperature management according to claim 1, characterized in that, In S1, according to and calculate the grid voltage The specific content includes: ； Among them, is dq the positive sequence complex vector of the grid voltage in the coordinate system, is dq the negative sequence complex vector of the grid voltage in the coordinate system, is dq the positive sequence complex vector of the grid connection point voltage in the coordinate system, is dq the negative sequence complex vector of the grid connection point voltage in the coordinate system, is dq the positive sequence complex vector of the grid connection point current in the coordinate system, is dq the negative sequence complex vector of the grid connection point current in the coordinate system, , where is a complex vector, representing or , and are respectively the d axis and q axis components of is the imaginary unit, is the fundamental angular frequency, is the line inductance.

3. The fault ride-through method of a Si / SiC hybrid parallel inverter system with active junction temperature management according to claim 1, characterized in that, The specific content of S2 includes: Based on the optimal current reference value lookup table, obtain data points through interpolation method The corresponding optimal current reference value that needs to be injected into the system Among them, the specific content of obtaining the optimal current reference value lookup table is: Assume that the positive and negative sequence components of the current that the converter needs to inject into the power grid are and ; after injecting the corresponding current, the PCC voltage amplitude, current amplitude, and active power fluctuation values are expressed as: ； ； ； In the formula, and are respectively the components on the three phases. and are respectively the components on the three phases. is the active power fluctuation value, and other parameters in the formula are all intermediate variables, and the calculation methods are respectively: ； ； ； Wherein, and are the positive-sequence components of the axis and d axis of the grid connection point voltage q respectively; and are the negative-sequence components of the axis and d axis of the grid connection point voltage q respectively; and are the positive-sequence components of the axis and d axis of the current reference value q respectively; and are the negative-sequence components of the axis and d axis of the current reference value q respectively, where the current reference value is the current value that enables the current to meet the fault ride-through requirements. By substituting the PCC voltage amplitude, current amplitude, and active power fluctuation value into the constraint conditions in the optimal fault ride - through at several data points and solving the objective, an optimal current reference value lookup table is obtained; For data points not covered in the optimal current reference value lookup table, the interpolation method is used to determine the current reference value.

4. The fault ride-through method of a Si / SiC hybrid parallel inverter system with active junction temperature management according to claim 1, characterized in that, Calculate the maximum output current of the system at the optimal current reference value The specific content includes: ； In the formula, and are respectively the d axis and q axis components of the current output.

5. The fault ride-through method of a Si / SiC mixed-frequency parallel inverter system with active junction temperature management according to claim 1, characterized in that, The optimal fault ride - through in S4 is expressed as: ； wherein, is the active power output by the system, is the active power fluctuation value; are the output voltage and current amplitudes, is the rated voltage, is the power reference value.

6. A fault ride-through system for a Si / SiC hybrid parallel inverter system with active junction temperature management, based on the fault ride-through method for a Si / SiC hybrid parallel inverter system with active junction temperature management according to any one of claims 1 to 5, characterized in that, Including: A data point acquisition module, which is used to record the occurrence time of a power grid fault as t = 0, and sample t = the grid connection point voltage at the 0 - moment and current , and according to and calculate the power grid voltage , and obtain the amplitude of the positive sequence component , the amplitude of the negative sequence component and the phase angle difference between the positive and negative sequence components , and form a data point ; Current reference value generation module for obtaining data points The corresponding optimal current reference value that needs to be injected into the system, based on the current optimal current reference value to achieve fault ride-through, update the current output current , where the optimal current reference values ​​include: d Axis positive sequence reference current , q Axis positive sequence reference current , d Axis negative sequence reference current and q Axis positive sequence reference current ; The junction temperature management module is used to calculate the maximum value of the current output at present , and based on and , and to adjust the operation mode according to their magnitude relationship. Among them, , and are the load current values corresponding to the maximum junction temperature of Si or SiC in Mode 1, Mode 2, and Mode 3 respectively. Modes 1 to 4 are respectively: Mode 1: Maintain rated parameters; When within the interval, maintain the DC link voltage , switching frequency and power distribution ratio K unchanged without modifying any parameters; Mode 2: Retain the parameter values in Mode 1 and only reduce the DC link voltage ; When within range, reduce until the lowest DC voltage required for AC-DC conversion is achieved; Mode 3: Retain the parameter values in Mode 2 and adjust the switching frequency and the power distribution ratio K ; When within the interval, decrease the adjusted switching frequency until the adjusted switching frequency required to meet the minimum output power quality is satisfied, and increase the power distribution ratio K until the maximum current that can be tolerated flows through SU; Mode 4: Retain the parameter values in Mode 3 and limit the current; when occurs, take current-limiting measures to adjust to or below. Dual-order current control module, used for dq output current control in the coordinate system, so that the output current tracks the optimal current reference value to achieve optimal fault ride-through. The specific content of the optimal fault ride-through is as follows: with the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to maximize the transmitted active power.

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