Independent turn-off thyristor half-bridge converter circuit topology and control method

Abstract

The invention provides an independent turn-off thyristor half-bridge converter circuit topology and a control method. A thyristor converter comprises a supporting capacitor Cdc, four capacitors C1, C2, C3 and C4, six thyristors S1, S2, S3, S4, S5 and S6, two sets of coupling inductors and two diodes D1 and D2. S1 and S2 are in complementary conduction, and a positive level and a zero level are output. When the S1 is switched on, the S3 and the S6 are switched on at the same time, the C3 is charged, and the C4 is discharged; when the S2 is conducted, the S4 and the S5 are also conducted at the same time, the C3 is discharged, and the C4 is charged. And when the system is locked, the S1, the S2, the S3 and the S5 are locked at the same time, and the S4 and the S6 are conducted, so that the thyristor half-bridge converter is locked. Compared with an existing thyristor half-bridge converter, the thyristor half-bridge converter has the advantages that upper and lower bridge arm devices can be turned on and turned off independently, and the converter has locking capacity and is flexible to control.

Description

Technical Field

[0001] The present invention belongs to the field of high-power power electronic converters, and particularly relates to an independent turn-off thyristor half-bridge converter circuit topology and a control method. Background Art

[0002] The thyristor half-bridge converter is an important topology in the development of power electronic technology, mainly used in high-voltage and high-current power conversion applications, and is widely used in industrial heating, motor drive and other fields. A thyristor is a semi-controlled device and requires a forced commutation circuit (such as an additional capacitor) to turn off. The series-inductor type thyristor half-bridge converter has received wide attention and application due to its simple circuit structure and control. In the existing series-inductor type thyristor half-bridge converter, the upper and lower half-bridges are directly connected through a single coupled inductor. When the thyristor in the upper arm conducts, the current flowing through the coupled inductor will generate a reverse voltage in the coupled inductor of the lower arm, thereby turning off the lower arm. Conversely, when turning off the thyristor in the upper arm, the thyristor in the lower arm needs to be turned on. Therefore, the conduction and turn-off of the thyristors in the upper and lower arms are mutually dependent and cannot be independently decoupled. Summary of the Invention

[0003] To overcome the shortcomings of the prior art, the present invention proposes an independent turn-off thyristor half-bridge converter circuit topology and a control method.

[0004] An independent turn-off thyristor half-bridge converter circuit topology consists of a support capacitor Cdc, capacitors C1, C2, C3, C4, thyristors S1, S2, S3, S4, S5, S6, two sets of dual-winding coupled inductors, and diodes D1, D2. Among them,

[0005] Capacitor C1 and capacitor C2 are connected in series. The positive electrode of capacitor C1 is connected to the positive electrode of the support capacitor Cdc, and the negative electrode of capacitor C2 is connected to the negative electrode of the support capacitor Cdc; diode D1 and diode D2 are connected in forward series. The cathode of diode D1 is connected to the positive electrode of the support capacitor Cdc, and the anode of diode D2 is connected to the negative electrode of the support capacitor Cdc; the same-name terminals of the first winding L1 of the first set of dual-winding coupled inductors and the same-name terminals of the second winding L3 of the first set of dual-winding coupled inductors are connected in parallel to form the first set of dual-winding coupled inductors; the same-name terminals of the first winding L2 of the second set of dual-winding coupled inductors and the same-name terminals of the second winding L4 of the second set of dual-winding coupled inductors are connected in parallel to form the second set of dual-winding coupled inductors; the anode of thyristor S1 is connected to the positive electrode of the support capacitor Cdc, and the cathode is connected to the same-name terminal of the first winding L1 of the first set of dual-winding coupled inductors. The non-same-name terminal of the first winding L1 of the first set of dual-winding coupled inductors is connected to the same-name terminal of the first winding L2 of the second set of dual-winding coupled inductors. The non-same-name terminal of the first winding L2 of the second set of dual-winding coupled inductors is connected to the anode of thyristor S2, and the cathode of thyristor S2 is connected to the negative electrode of the support capacitor Cdc; capacitor C1 and diode D1 are connected in parallel across thyristor S1 and the first winding L1 of the first set of dual-winding coupled inductors, and capacitor C2 and diode D2 are connected in parallel across the first winding L2 of the second set of dual-winding coupled inductors and thyristor S2, that is, the negative electrode of capacitor C1 and the anode of diode D1 are connected to the non-same-name terminal of the first winding L1 of the first set of dual-winding coupled inductors, and the positive electrode of capacitor C2 and the cathode of diode D2 are connected to the same-name terminal of the first winding L2 of the second set of dual-winding coupled inductors; thyristor S3 and thyristor S4 are connected in antiparallel. The cathode of thyristor S3 and the anode of thyristor S4 are connected to the positive electrode of C3, and the anode of thyristor S3 and the cathode of thyristor S4 are connected to the same-name terminal of the second winding L3 of the first set of dual-winding coupled inductors. The non-same-name terminal of the second winding L3 of the first set of dual-winding coupled inductors is connected to the negative electrode of capacitor C3; thyristor S5 and thyristor S6 are connected in antiparallel. The cathode of thyristor S5 and the anode of thyristor S6 are connected to the positive electrode of capacitor C4, and the anode of thyristor S5 and the cathode of thyristor S6 are connected to the same-name terminal of the second winding L4 of the second set of dual-winding coupled inductors. The non-same-name terminal of the second winding L4 of the second set of dual-winding coupled inductors is connected to the negative electrode of capacitor C4.

[0006] A control method for an independent type turn-off thyristor half-bridge converter circuit topology, comprising:

[0007] When the circuit is running, the thyristors S1 and S2 adopt the traditional pulse width modulation strategy, and the thyristors S1 and S2 are not conducting simultaneously. When the thyristor S1 is conducting, the thyristors S3 and S6 are conducting simultaneously, and the thyristors S2, S4, and S5 are turned off simultaneously. When the thyristor S2 is conducting, the thyristors S4 and S5 are conducting simultaneously, and the thyristors S1, S3, and S6 are turned off simultaneously. The operating frequency range of the thyristors S1, S2, S3, S4, S5, and S6 is 0 - 2 kHz.

[0008] When receiving the blocking signal given by the system, the thyristors S1, S2, S3, and S5 are blocked simultaneously, and the thyristors S4 and S6 are triggered. The current flowing through the thyristors S1 and S2 decreases due to the reverse voltage. When the current decays to zero, the thyristors S1 and S2 are turned off, and the circuit is blocked.

[0009] A computing device includes: at least one processor and a memory storing program instructions; when the program instructions are read and executed by the processor, the computing device is caused to execute a control method for an independent turn - off thyristor half - bridge converter circuit topology.

[0010] A readable storage medium storing program instructions, when the program instructions are read and executed by a computing device, causes the computing device to execute a control method for an independent turn - off thyristor half - bridge converter circuit topology.

[0011] Compared with the existing solutions, the beneficial effects of the present invention are as follows:

[0012] 1) A dual - winding coupled inductor is integrated on each of the upper and lower bridge arms respectively. When the thyristors conducting on each bridge arm are turned off, they respectively form an LC resonance circuit through their respective coupled inductors and capacitors to achieve turn - off, without mutual dependence, and the control is relatively flexible.

[0013] 2) Compared with the existing series - inductor type thyristor half - bridge converter, since each device can be independently turned off, when the blocking signal is sent, all power semiconductor devices can be directly blocked, avoiding the phenomenon of non - turn - off. Description of the Drawings

[0014] Figure 1 It is a schematic diagram of the independent turn - off thyristor half - bridge converter circuit topology of the present invention. Detailed Embodiments

[0015] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0016] Figure 1 It is a schematic diagram of the circuit topology of the stand-alone turn-off thyristor half-bridge converter of the present invention. As Figure 1 shown, the circuit topology of the stand-alone turn-off thyristor half-bridge converter is composed of a support capacitor Cdc, four capacitors C1, C2, C3, C4, six thyristors S1, S2, S3, S4, S5, S6, two sets of coupled inductors, and two diodes D1, D2. The connection relationships of the components are as follows: Capacitor C1 and capacitor C2 are connected in series, the positive electrode of capacitor C1 is connected to the positive electrode of the support capacitor Cdc, and the negative electrode of capacitor C2 is connected to the negative electrode of the support capacitor Cdc; Diode D1 and diode D2 are connected in series in the forward direction, the cathode of diode D1 is connected to the positive electrode of the support capacitor Cdc, and the anode of D2 is connected to the negative electrode of the support capacitor Cdc; The homonymous ends of the first winding L1 of the first set of dual-winding coupled inductors and the homonymous ends of the second winding L3 of the first set of dual-winding coupled inductors are connected in parallel to form the first set of dual-winding coupled inductors; The homonymous ends of the first winding L2 of the second set of dual-winding coupled inductors and the homonymous ends of the second winding L4 of the second set of dual-winding coupled inductors are connected in parallel to form the second set of dual-winding coupled inductors;

[0017] The anode of the thyristor S1 is connected to the positive electrode of the support capacitor Cdc, the cathode is connected to the same-named terminal of the first winding L1 of the first set of dual-winding coupled inductors, the non-same-named terminal of the first winding L1 of the first set of dual-winding coupled inductors is connected to the same-named terminal of L2, the non-same-named terminal of the first winding L2 of the second set of dual-winding coupled inductors is connected to the anode of the thyristor S2, and the cathode of the thyristor S2 is connected to the negative electrode of Cdc; the capacitor C1 and the diode D1 are connected in parallel across the thyristor S1 and the first winding L1 of the first set of dual-winding coupled inductors, and the capacitor C2 and the diode D2 are connected in parallel across the first winding L2 of the second set of dual-winding coupled inductors and the thyristor S2, that is, the negative electrode of the capacitor C1 and the anode of the diode D1 are connected to the non-same-named terminal of the first winding L1 of the first set of dual-winding coupled inductors, and the positive electrode of the capacitor C2 and the cathode of the diode D2 are connected to the same-named terminal of the first winding L2 of the second set of dual-winding coupled inductors; the thyristors S3 and S4 are connected in antiparallel, the cathode of the thyristor S3 and the anode of the thyristor S4 are connected to the positive electrode of the capacitor C3, the anode of the thyristor S3 and the cathode of the thyristor S4 are connected to the same-named terminal of the second winding L3 of the first set of dual-winding coupled inductors, and the non-same-named terminal of the second winding L3 of the first set of dual-winding coupled inductors is connected to the negative electrode of the capacitor C3; the thyristors S5 and S6 are connected in antiparallel, the cathode of the thyristor S5 and the anode of the thyristor S6 are connected to the positive electrode of the capacitor C4, the anode of the thyristor S5 and the cathode of the thyristor S6 are connected to the same-named terminal of the second winding L4 of the second set of dual-winding coupled inductors, and the non-same-named terminal of the second winding L4 of the second set of dual-winding coupled inductors is connected to the negative electrode of the capacitor C4.

[0018] In an embodiment, the capacitance value range of the support capacitor Cdc is 0 to 100 mF, and the capacitance value ranges of the capacitors C1, C2, C3, and C4 are 0 to 500 μF. The coupling coefficient value range between the first winding L1 of the first set of dual-winding coupled inductors and the second winding L3 of the first set of dual-winding coupled inductors is [0.8, 1], and the coupling coefficient value range between the first winding L2 of the second set of dual-winding coupled inductors and the second winding L4 of the second set of dual-winding coupled inductors is [0.8, 1].

[0019] The present invention also provides a control method for the circuit topology of an independent turn-off thyristor half-bridge converter, wherein the self-turn-off of the thyristor can be realized. The following refers to Figure 1 Describe the control process of this control method, and this control process includes:

[0020] When the circuit is operating, the thyristors S1 and S2 adopt the traditional pulse width modulation strategy, and the thyristors S1 and S2 are not turned on simultaneously. When the thyristor S1 is turned on, the thyristors S3 and S6 are turned on simultaneously, and the thyristors S2, S4, and S5 are turned off simultaneously. When the thyristor S2 is turned on, the thyristors S4 and S5 are turned on simultaneously, and the thyristors S1, S3, and S6 are turned off simultaneously. The operating frequency range of the thyristors S1, S2, S3, S4, S5, and S6 is 0 - 2 kHz.

[0021] When receiving the blocking signal given by the system, the thyristors S1, S2, S3, and S5 are blocked simultaneously, and the thyristors S4 and S6 are triggered. The currents flowing through the thyristors S1 and S2 decrease due to the reverse voltage. When the currents decay to zero, the thyristors S1 and S2 are turned off, and the circuit is blocked.

[0022] According to the present invention, there is also provided a computing device, including: at least one processor and a memory storing program instructions; when the program instructions are read and executed by the processor, the computing device is caused to execute the control method of the above-mentioned independent turn-off thyristor half-bridge converter circuit topology.

[0023] According to the present invention, there is also provided a readable storage medium storing program instructions. When the program instructions are read and executed by a computing device, the computing device is caused to execute the control method of the above-mentioned independent turn-off thyristor half-bridge converter circuit topology.

[0024] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0025] Although the present invention has been described in terms of a limited number of embodiments, those skilled in the art in this technical field will appreciate that other embodiments can be envisioned within the scope of the present invention as thus described. Additionally, it should be noted that the language used in this specification has been principally selected for readability and teaching purposes rather than for the purpose of explaining or limiting the subject matter of the present invention.

Claims

1. An independent turn-off thyristor half-bridge converter circuit topology, characterized in that, It consists of a support capacitor Cdc, capacitors C1, C2, C3, C4, thyristors S1, S2, S3, S4, S5, S6, two sets of double-winding coupled inductors, and diodes D1, D2. Among them, Capacitor C1 and capacitor C2 are connected in series. The positive electrode of capacitor C1 is connected to the positive electrode of support capacitor Cdc, and the negative electrode of capacitor C2 is connected to the negative electrode of support capacitor Cdc; diodes D1 and D2 are connected in series forward. The cathode of diode D1 is connected to the positive electrode of support capacitor Cdc, and the anode of diode D2 is connected to the negative electrode of support capacitor Cdc; the same-name ends of the first winding L1 of the first set of double-winding coupled inductors and the second winding L3 of the first set of double-winding coupled inductors are connected in parallel to form the first set of double-winding coupled inductors; the same-name ends of the first winding L2 of the second set of double-winding coupled inductors and the second winding L4 of the second set of double-winding coupled inductors are connected in parallel to form the second set of double-winding coupled inductors; the anode of thyristor S1 is connected to the positive electrode of support capacitor Cdc, the cathode is connected to the same-name end of the first winding L1 of the first set of double-winding coupled inductors, the non-same-name end of the first winding L1 of the first set of double-winding coupled inductors is connected to the same-name end of the first winding L2 of the second set of double-winding coupled inductors, the non-same-name end of the first winding L2 of the second set of double-winding coupled inductors is connected to the anode of thyristor S2, and the cathode of thyristor S2 is connected to the negative electrode of support capacitor Cdc; capacitor C1 and diode D1 are connected in parallel across thyristor S1 and the first winding L1 of the first set of double-winding coupled inductors, and capacitor C2 and diode D2 are connected in parallel across the first winding L2 of the second set of double-winding coupled inductors and thyristor S2, that is, the negative electrode of capacitor C1 and the anode of diode D1 are connected to the non-same-name end of the first winding L1 of the first set of double-winding coupled inductors, and the positive electrode of capacitor C2 and the cathode of diode D2 are connected to the same-name end of the first winding L2 of the second set of double-winding coupled inductors; thyristors S3 and S4 are connected in antiparallel. The cathode of thyristor S3 and the anode of thyristor S4 are connected to the positive electrode of C3, the anode of thyristor S3 and the cathode of thyristor S4 are connected to the same-name end of the second winding L3 of the first set of double-winding coupled inductors, and the non-same-name end of the second winding L3 of the first set of double-winding coupled inductors is connected to the negative electrode of capacitor C3; thyristors S5 and S6 are connected in antiparallel. The cathode of thyristor S5 and the anode of thyristor S6 are connected to the positive electrode of capacitor C4, the anode of thyristor S5 and the cathode of thyristor S6 are connected to the same-name end of the second winding L4 of the second set of double-winding coupled inductors, and the non-same-name end of the second winding L4 of the second set of double-winding coupled inductors is connected to the negative electrode of capacitor C4.

2. The independent turn-off thyristor half-bridge converter circuit topology according to claim 1, characterized in that, The capacitance value range of the support capacitor Cdc is 0~100mF.

3. The independent turn-off thyristor half-bridge converter circuit topology according to claim 1, characterized in that, The capacitance value ranges of capacitors C1, C2, C3, and C4 are 0~500μF.

4. The independent turn-off thyristor half-bridge converter circuit topology according to claim 1, characterized in that, The coupling coefficient value range between the first winding L1 of the first set of double-winding coupled inductors and the second winding L3 of the first set of double-winding coupled inductors is [0.8,1].

5. The independent turn-off thyristor half-bridge converter circuit topology according to claim 1, characterized in that, The coupling coefficient between the first winding L2 of the second set of dual-winding coupled inductors and the second winding L4 of the second set of dual-winding coupled inductors ranges from 0.8 to 1.

6. A control method for an independent turn-off thyristor half-bridge converter circuit topology, applicable to the independent turn-off thyristor half-bridge converter circuit topology according to any one of claims 1-5, characterized in that, Including: During circuit operation, thyristors S1 and S2 adopt the traditional pulse width modulation strategy, and thyristors S1 and S2 are not turned on simultaneously; when thyristor S1 is turned on, thyristors S3 and S6 are turned on simultaneously, and thyristors S2, S4, and S5 are turned off simultaneously; when thyristor S2 is turned on, thyristors S4 and S5 are turned on simultaneously, and thyristors S1, S3, and S6 are turned off simultaneously.

7. The control method of the independent turn-off thyristor half-bridge converter circuit topology according to claim 6, characterized in that, The operating frequency of thyristors S1, S2, S3, S4, S5, and S6 ranges from 0 to 2 kHz.

8. The control method of the independent turn-off thyristor half-bridge converter circuit topology according to claim 6, characterized in that, Also including: When receiving the blocking signal given by the system, thyristors S1, S2, S3, and S5 are blocked simultaneously, and thyristors S4 and S6 are triggered; the current flowing through thyristors S1 and S2 decreases due to the reverse voltage. When the current decays to zero, thyristors S1 and S2 are turned off, and the circuit is blocked.

9. A computing device, characterized in that, Including: At least one processor and a memory storing program instructions; When the program instructions are read and executed by the processor, the computing device is caused to execute the control method of the independent turn-off thyristor half-bridge converter circuit topology according to any one of claims 6-8.

10. A readable storage medium storing program instructions, characterized in that, When the program instructions are read and executed by the computing device, the computing device is caused to execute the control method of the independent turn-off thyristor half-bridge converter circuit topology according to any one of claims 6-8.

Images