Control circuit

Abstract

An embodiment of the present disclosure provides a control circuit, comprising: a comparison circuit configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparison circuit having a bias power source for providing a current for the comparison circuit; the input end of the monitoring circuit is coupled to a first node in the comparison circuit, the output end of the monitoring circuit is coupled to the acceleration circuit, and the monitoring circuit is configured to control the working state of the acceleration circuit based on the voltage and / or current of the first node, so that the acceleration circuit is opened when the control circuit is in the starting stage and closed when the control circuit is in the stable stage; the input end of the acceleration circuit is coupled to the monitoring circuit, the output end of the acceleration circuit is coupled to the bias power supply, and the acceleration circuit is configured to adjust the bias current output by the bias power supply.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor integrated circuit technologies, and particularly to a control circuit. Background Art

[0002] In the field of integrated circuits, low-power design is an important principle. Most circuit modules are in the off state when not necessary and are enabled by an enable signal from the system when necessary. At the same time, to reduce current consumption, the steady-state operating current of many circuit modules is very small, and the related bias current is pressed down to the uA level or even lower.

[0003] The low bias current makes it a difficult problem to quickly establish when the circuit module is enabled. Especially for circuits with feedback loops such as LDO (Low Dropout Linear Regulator). Because circuits with loops usually require a large capacitor for loop compensation to avoid obvious overshoot or even oscillation to ensure the normal operation of the circuit. To reduce mismatch, the device sizes within the loop are usually larger, bringing larger parasitic capacitances. In low-power design, the too-small bias current significantly prolongs the capacitor charging time, that is, the circuit establishment speed is restricted by the low bias current. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a control circuit.

[0005] To achieve the above object, the technical solution of the present disclosure is implemented as follows:

[0006] Embodiments of the present disclosure provide a control circuit, including: a comparison circuit configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparison circuit having a bias power supply for providing current to the comparison circuit; a monitoring circuit, whose input terminal is coupled to a first node within the comparison circuit and whose output terminal is coupled to an acceleration circuit, configured to control the operating state of the acceleration circuit based on the voltage and / or current of the first node, so that the acceleration circuit is turned on when the control circuit is in the startup stage and is turned off when the control circuit is in the stable stage; an acceleration circuit, whose input terminal is coupled to the monitoring circuit and whose output terminal is coupled to the bias power supply, configured to adjust the bias current output by the bias power supply.

[0007] In some embodiments, the monitoring circuit is specifically configured to output a second control signal based on the voltage and / or current of the first node; the acceleration circuit is specifically configured to respond to the second control signal and adjust the bias current output by the bias power supply, so that the bias current when the control circuit is in the startup stage is greater than the bias current when the control circuit is in the stable stage.

[0008] In some embodiments, the monitoring circuit is configured to turn off the acceleration circuit when the voltage and / or current of the first node reaches a first preset value during the startup phase.

[0009] In some embodiments, the comparison circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; wherein, the control terminals of the first transistor and the second transistor are coupled; the input terminals of the first transistor and the second transistor are coupled to the power supply, the output terminal of the first transistor is coupled to the input terminal of the third transistor and the control terminal of the first transistor, the first node is located at the output terminal of the first transistor, the output terminal of the second transistor is coupled to the input terminal of the fourth transistor and the output terminal of the comparison circuit; the output terminals of the third transistor and the fourth transistor are coupled to the ground terminal, the control terminal of the third transistor is the first input terminal of the comparison circuit for receiving a feedback voltage, and the control terminal of the fourth transistor is the second input terminal of the comparison circuit for receiving a reference voltage.

[0010] In some embodiments, the monitoring circuit includes a detection unit, an initialization unit, and a current limiting unit; the detection unit and the current limiting unit are connected in series, and the initialization unit is connected in parallel with the current limiting unit; the output terminal of the detection unit is coupled to the input terminal of the acceleration circuit, and the detection unit is coupled to the first node; the detection unit is configured to provide an adjustment current based on the voltage of the first node; the current limiting unit is configured to adjust the change speed of the voltage at the output terminal of the detection unit; the initialization unit is configured to provide an initial voltage to the output terminal of the detection unit during the startup phase to turn on the acceleration circuit.

[0011] In some embodiments, the detection unit includes a fifth transistor; and / or the initialization unit includes a sixth transistor; the output terminal of the fifth transistor is coupled to the current limiting unit, the output terminal of the fifth transistor is the output terminal of the monitoring circuit, and the output terminals of the current limiting unit and the sixth transistor are coupled to the ground terminal.

[0012] In some embodiments, the current limiting unit includes a resistor and / or a capacitor.

[0013] In some embodiments, the monitoring circuit further includes: a first resistor for adjusting the change speed of the voltage at the output terminal of the detection unit.

[0014] In some embodiments, the acceleration circuit includes a seventh transistor; the control terminal of the seventh transistor is coupled to the output terminal of the monitoring circuit, and the output terminal of the seventh transistor is the output terminal of the acceleration circuit.

[0015] In some embodiments, the acceleration circuit further includes a second resistor connected in series with the seventh transistor for adjusting the acceleration current output by the acceleration circuit; the input terminal of the seventh transistor is coupled to the power supply through the second resistor.

[0016] In some embodiments, the bias power supply includes a current source and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled, the output terminal of the current source is coupled to the input terminal of the current mirror, the input terminal of the current mirror is coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply; the output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

[0017] In some embodiments, the acceleration circuit is specifically configured to respond to the second control signal, turn on during the startup phase of the control circuit to generate an acceleration current, and output the acceleration current to the bias power supply.

[0018] In some embodiments, the acceleration circuit includes an eighth transistor and a third resistor connected in parallel; the control terminal of the eighth transistor is coupled to the output terminal of the fifth transistor, the input terminal of the eighth transistor is coupled to the power supply, and the output terminal of the eighth transistor is the output terminal of the acceleration circuit.

[0019] In some embodiments, the bias power supply includes a fourth resistor and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled, the fourth resistor is connected in series with the third resistor and is coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply; the output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

[0020] In some embodiments, it further includes: a switch circuit, coupled to the comparison circuit, configured to control the operating state of the comparison circuit based on an enable signal; the switch circuit includes a ninth transistor and a tenth transistor; the control terminals of the ninth transistor and the tenth transistor receive the enable signal, the input terminals of the ninth transistor and the tenth transistor are coupled to the power supply, the output terminal of the ninth transistor is coupled to the control terminals of the first transistor and the second transistor, and the output terminal of the tenth transistor is coupled to the output terminal of the second transistor.

[0021] An embodiment of the present disclosure provides a control circuit, including: a comparison circuit configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparison circuit having a bias power supply for providing current to the comparison circuit; a monitoring circuit, whose input terminal is coupled to a first node inside the comparison circuit and whose output terminal is coupled to an acceleration circuit, configured to control the operating state of the acceleration circuit based on the voltage and / or current of the first node, so that the acceleration circuit is turned on when the control circuit is in the startup phase and turned off when the control circuit is in the stable phase; an acceleration circuit, whose input terminal is coupled to the monitoring circuit and whose output terminal is coupled to the bias power supply, configured to adjust the bias current output by the bias power supply. In the embodiment of the present disclosure, the monitoring circuit is coupled to an internal node (the first node) of the comparison circuit, and the internal node of the comparison circuit can more accurately reflect the establishment state of the loop, whereby the acceleration circuit can be turned on and off in a timely manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. is a schematic diagram of an amplifier circuit provided by an embodiment of the present disclosure;

[0023] Figure 2 FIG. is a schematic diagram of a control circuit provided by an embodiment of the present disclosure;

[0024] Figure 3 FIG. is a schematic diagram of a monitoring circuit provided by an embodiment of the present disclosure;

[0025] Figure 4 FIG. is a schematic diagram of an acceleration circuit provided by an embodiment of the present disclosure Figure 1 ;

[0026] Figure 5 FIG. is a schematic diagram of a bias power supply provided by an embodiment of the present disclosure Figure 1 ;

[0027] Figure 6 FIG. is a schematic diagram of an acceleration circuit and a bias power supply provided by an embodiment of the present disclosure Figure 2 。 DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0030] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Throughout the drawings, the same reference numerals indicate the same elements.

[0031] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply that a first element, component, region, layer, or section exists in the present disclosure.

[0032] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0034] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other embodiments.

[0035] Figure 1 A schematic diagram of an amplification circuit provided for an embodiment of the present disclosure. Among them, the circuit is a typical LDO, and the circuit includes a comparator 11, a voltage regulation loop 12 and a feedback output module 13. The input end of the comparator 11 receives a reference voltage Vref, and the output end of the comparator 11 is coupled to the feedback output module 13. The feedback output module 13 includes an output transistor MP, a first feedback resistor RF1 and a second feedback resistor RF2 connected in series; the node between the first feedback resistor RF1 and the second feedback resistor RF2 is connected to the feedback input end of the comparator 11, and the feedback output module 13 is used to output a feedback voltage VFB to the feedback input end of the comparator 11. The input end of the output transistor MP is connected to a power supply VDD, and its output end serves as the output end of the amplification circuit, and is used to provide current for the output voltage of the amplification circuit.

[0036] The comparator 11 can be connected to an adjustable bias power supply. The larger the bias current, the faster the response of the operational amplifier, and the shorter the settling time of the corresponding amplification circuit. The smaller the bias current, the slower the response of the operational amplifier, and the shorter the settling time of the corresponding amplification circuit. Since a large capacitance node is internally provided in this amplification circuit to ensure loop stability; at the same time, in order to reduce mismatch, the sizes of the devices in the amplification circuit are usually relatively large, which will bring larger parasitic capacitances. These capacitances will all affect the settling time of the circuit, especially the settling time in the case of a small bias current.

[0037] Figure 2 A schematic diagram of a control circuit provided for an embodiment of the present disclosure. As Figure 2As shown, the control circuit includes: a comparison circuit 210 configured to compare a reference voltage and a feedback voltage to generate a first control signal. The comparison circuit 210 has a bias power supply 211 for providing current to the comparison circuit 210; a monitoring circuit 220 whose input terminal is coupled to a first node in the comparison circuit 210 and whose output terminal is coupled to an acceleration circuit 230, configured to control the operating state of the acceleration circuit 230 based on the voltage and / or current of the first node, so that the acceleration circuit 230 is turned on when the control circuit is in the startup phase and turned off when the control circuit is in the stable phase; an acceleration circuit 230 whose input terminal is coupled to the monitoring circuit 220 and whose output terminal is coupled to the bias power supply 211, configured to adjust the bias current output by the bias power supply 211.

[0038] In the embodiments of the present disclosure, the case where the monitoring circuit 220 controls the operating state of the acceleration circuit 230 based on the voltage of the first node is taken as an example for illustration. In the following embodiments, the voltage of the first node is denoted by VB.

[0039] In some embodiments, the capacitor Cp1 in the control circuit is the equivalent parasitic capacitance of the output terminal of the control circuit, the capacitor Cc is the Miller capacitance connected across the two ends of the subsequent circuit, and the capacitor Cload is the load capacitance of the output of the subsequent circuit.

[0040] In some embodiments, Figure 2 The subsequent circuit in the illustrated control circuit may specifically include Figure 1 the feedback output module 13 shown. Here, the output terminal of the comparison circuit 210 is connected to the subsequent circuit. In a specific example, the output terminal of the comparison circuit 210 is connected to the control terminal of the output transistor MP.

[0041] In some embodiments, the pre-stage circuit in the control circuit is the input terminal of the control circuit for receiving an external input signal.

[0042] In the embodiments of the present disclosure, the monitoring circuit is coupled to the internal node (the first node) of the comparison circuit. Compared with monitoring the output terminal of the control circuit, the output establishment process is smoother because the establishment of the output terminal is affected by the load and there is a delay in the feedback link, and directly sampling the output terminal is likely to form an overshoot. Therefore, the monitoring circuit controls the operating state of the acceleration circuit according to the internal node of the comparison circuit, which can avoid the influence of the load and the delay. The internal node of the comparison circuit can more accurately reflect the establishment state of the loop, turn on and off the acceleration circuit in a timely manner, and enable the output voltage to be smoothly established.

[0043] In some embodiments, the monitoring circuit 220 is specifically configured to output a second control signal VC based on the voltage and / or current of the first node; the acceleration circuit 230 is specifically configured to adjust the bias current output by the bias power supply 211 in response to the second control signal VC, so that the bias current when the control circuit is in the startup phase is greater than the bias current when the control circuit is in the stable phase.

[0044] In the embodiments of the present disclosure, the acceleration circuit 230 can make the bias current when the control circuit is in the startup phase greater than the bias current when the control circuit is in the stable phase, so as to accelerate the establishment speed of the control circuit in the startup phase.

[0045] In some embodiments, the comparison circuit 210 includes: a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; wherein, the control terminals of the first transistor M1 and the second transistor M2 are coupled; the input terminals of the first transistor M1 and the second transistor M2 are coupled to the power supply, the output terminal of the first transistor M1 is coupled to the input terminal of the third transistor M3 and the control terminal of the first transistor M1, the first node is located at the output terminal of the first transistor M1, the output terminal of the second transistor M2 is coupled to the input terminal of the fourth transistor M4 and the output terminal of the comparison circuit; the output terminals of the third transistor M3 and the fourth transistor M4 are coupled to the ground terminal, the control terminal of the third transistor M3 is the first input terminal of the comparison circuit for receiving the feedback voltage Vb, and the control terminal of the fourth transistor M4 is the second input terminal of the comparison circuit for receiving the reference voltage Va.

[0046] In some embodiments, the feedback voltage Vb is the feedback voltage of the subsequent stage circuit. Specifically, the feedback voltage Vb can be the output voltage of the subsequent stage circuit or the voltage of the node between the first feedback resistor R1 and the second feedback resistor R2 in the subsequent stage circuit.

[0047] In some embodiments, the output terminals of both the third transistor M3 and the fourth transistor M4 are coupled to the output terminal of the bias power supply.

[0048] In some embodiments, the first transistor M1 and the second transistor M2 are PMOS transistors, and the third transistor M3 and the fourth transistor M4 are NMOS transistors.

[0049] In some embodiments, the control circuit further includes: a switch circuit, coupled to the comparison circuit 210 and configured to control the operating state of the comparison circuit 210 based on an enable signal; the switch circuit includes a ninth transistor M9 and a tenth transistor M10; the control terminals of the ninth transistor M9 and the tenth transistor M10 receive the enable signal EN, the input terminals of the ninth transistor M9 and the tenth transistor M10 are coupled to the power supply VDD, the output terminal of the ninth transistor M9 is coupled to the control terminals of the first transistor M1 and the second transistor M2, and the output terminal of the tenth transistor M10 is coupled to the output terminal of the second transistor M2.

[0050] It should be noted that Figure 2 the dashed box of the comparison circuit 210 in

[0051] When the control circuit is not enabled, the ninth transistor M9 and the tenth transistor M10 are controlled to turn on through the enable signal EN. At this time, the first node is pulled up to VDD, so that the output transistor MP in the subsequent circuit is turned off, and the control circuit is in a non-operating state.

[0052] When the control circuit is enabled, the ninth transistor M9 and the tenth transistor M10 are controlled to turn off through the enable signal EN, and the bias power supply works to provide current for the comparison circuit; the third transistor M3 path and the fourth transistor M4 path are turned on, and the voltage at the output terminal of the comparison circuit 210 is fed back to the front-stage circuit through the subsequent circuit. The front-stage circuit outputs the reference voltage Va and the feedback voltage Vb to the third transistor M3 and the fourth transistor M4 based on the voltage fed back by the subsequent circuit. At the initial stage of loop establishment, the reference voltage Va output by the front-stage circuit > the feedback voltage Vb, and the conduction degree of the fourth transistor M4 is greater than that of the third transistor M3. Almost all of the bias current Ib output by the bias power supply is used for the fourth transistor M4 path, and the output terminal of the comparison circuit is pulled down through the fourth transistor M4 path. At this time, there is almost no pulling-down current at the first node. Until the output voltage of the comparison circuit rises to the turn-on voltage of the output transistor MP, the subsequent circuit turns on the feedback, and the front-stage circuit adjusts the feedback voltage Vb based on the feedback of the subsequent circuit to reduce the difference between the reference voltage Va and the feedback voltage Vb. When the reference voltage Va and the feedback voltage Vb are close, the bias current lb flows into the third transistor M3 path, and the voltage of the first node starts to drop. At this time, it corresponds to that the loop establishment is about to be completed, because at this time the reference voltage Va and the feedback voltage Vb are close, that is, the difference between the reference voltage Va and the feedback voltage Vb is very small or 0, making the output voltage value of the comparison circuit stable, and the loop enters a steady state. Based on this, the first node detected in the embodiments of the present disclosure is an internal node of the comparison circuit that can accurately reflect the establishment state of the loop, and thus the acceleration circuit can be turned on and off in a timely manner.

[0053] Figure 3 A schematic diagram of a monitoring circuit provided by an embodiment of the present disclosure. In combination with Figure 2 and Figure 3 As shown, the monitoring circuit 220 includes a detection unit 221, an initialization unit 222, and a current limiting unit 223. The detection unit 221 and the current limiting unit are connected in series, and the initialization unit 222 is connected in parallel with the current limiting unit; the output end of the detection unit 221 is coupled to the input end of the acceleration circuit, and the detection unit 221 is coupled to the first node; the detection unit is used to provide an adjustment current based on the first node voltage; the current limiting unit 223 is used to adjust the change speed of the voltage at the output end of the detection unit; the initialization unit 222 is used to provide an initial voltage for the output end of the detection unit during the startup phase to turn on the acceleration circuit.

[0054] In some embodiments, the detection unit 221 includes a fifth transistor M5; and / or the initialization unit 222 includes a sixth transistor M6; the output end of the fifth transistor M5 is coupled to the current limiting unit 223, the output end of the fifth transistor M5 is the output end of the monitoring circuit 220, and the output ends of the current limiting unit 223 and the sixth transistor M6 are coupled to the ground terminal. Here, the signal output from the output end of the monitoring circuit 220 is the second control signal VC.

[0055] In some embodiments, the fifth transistor M5 is a PMOS transistor.

[0056] In some embodiments, the control end of the sixth transistor M6 is connected to the reverse enable signal EN_INV. The transistor type of the sixth transistor M6 is different from that of the ninth transistor M9 and the tenth transistor M10. Specifically, the ninth transistor M9 and the tenth transistor M10 are PMOS transistors, and the sixth transistor M6 is an NMOS transistor.

[0057] In some embodiments, the current limiting unit 223 includes a resistor and / or a capacitor. In a specific example, the current limiting voltage 223 is a capacitor C1, wherein the output end of the fifth transistor M5 is coupled to the first electrode plate of the capacitor C1, and the second electrode plate of the capacitor C1 and the output end of the sixth transistor M6 are coupled to the ground terminal.

[0058] In some embodiments, the monitoring circuit 220 further includes: a first resistor R1, which is used to adjust the change speed of the voltage at the output end of the detection unit 221. It should be noted that the capacitor C1 is also used to adjust the change speed of the voltage at the output end of the detection unit 221. In other words, the first resistor R1 and the capacitor C1 can perform delay adjustment on the opening and closing of the acceleration circuit, and the resistance value of the first resistor R1 and the capacitance value of the capacitor C1 can be set according to actual requirements.

[0059] When the control circuit is not enabled, the first node is pulled up to VDD, the fifth transistor M5 is turned off, the monitoring circuit is turned off, and the sixth transistor M6 is controlled to be turned on through the inverted enable signal EN_INV, pulling the output terminal of the fifth transistor to the ground terminal. At this time, the voltage (second control signal VC) at the output terminal of the monitoring circuit is the initial voltage (however, at this time the control circuit is not enabled and the acceleration circuit cannot be turned on).

[0060] When the control circuit is enabled and when the loop starts to be established, the sixth transistor M6 is controlled to be turned off through the inverted enable signal EN_INV. The voltage of the first node approaches VDD, the fifth transistor M5 remains turned off, the voltage (second control signal VC) at the output terminal of the monitoring circuit remains the initial voltage, and the acceleration circuit is turned on. When the loop establishment is about to be completed, the voltage of the first node starts to drop. At this time, the fifth transistor M5 is turned on, the voltage (second control signal VC) at the output terminal of the monitoring circuit rises, giving an acceleration circuit turn-off signal, and the acceleration circuit is turned off. After the loop establishment is completed, the voltage (second control signal VC) at the output terminal of the monitoring circuit is determined and no longer responds to the input, thus avoiding multiple triggers to save circuit power consumption.

[0061] Figure 4 Schematic diagram of an acceleration circuit provided by an embodiment of the present disclosure Figure 1 Combined with Figure 2 、 Figure 3 and Figure 4 As shown, the acceleration circuit 230 includes a seventh transistor M7; the control terminal of the seventh transistor M7 is coupled to the output terminal of the monitoring circuit 220, and the output terminal of the seventh transistor M7 is the output terminal of the acceleration circuit 230.

[0062] In some embodiments, the seventh transistor M7 is a PMOS transistor.

[0063] In some embodiments, the acceleration circuit 230 further includes a second resistor R2 for adjusting the acceleration current output by the acceleration circuit; the input terminal of the seventh transistor M7 is coupled to the power supply VDD through the second resistor R2.

[0064] The seventh transistor M7 is in the off state when the monitoring circuit is off. In some embodiments, a switch can be added between the seventh transistor M7 and the second resistor R2 as needed to further accurately control the turn-on timing of the seventh transistor M7. When the voltage (second control signal VC) at the output terminal of the monitoring circuit is the initial voltage, the seventh transistor M7 conducts, and the acceleration circuit provides an acceleration current Iacc determined by the power supply VDD and the second resistor R2.

[0065] In some embodiments, the acceleration circuit is specifically configured to turn on in response to the second control signal VC to generate an acceleration current Iacc when the control circuit is in the startup phase, and output the acceleration current to the bias power supply.

[0066] Figure 5 Schematic diagram of a bias power supply provided by an embodiment of the present disclosure Figure 1 Combined with Figure 2 、 Figure 3 、 Figure 4 and Figure 5 As shown, the bias power supply 211 includes a current source and a current mirror; the current mirror includes at least two mirror transistors M11, Mb1-Mbn; the control terminals of the mirror transistors M11, Mb1-Mbn are coupled to each other, the output terminal of the current source is coupled to the input terminal of the current mirror, the input terminal of the current mirror is also coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply 211; the output terminals of the third transistor M3 and the fourth transistor M4 are both coupled to the output terminal of the bias power supply 211. Wherein, n is greater than or equal to 0.

[0067] When the acceleration circuit is turned on, the acceleration circuit 230 outputs an acceleration current Iacc to the bias power supply 211, and the output current of the current source is Ib0. Thus, the bias current output by the bias power supply 211 is Ib = Ib0 + Iacc. When the acceleration circuit is turned off, the acceleration current Iacc = 0, and the bias current output by the bias power supply 211 is Ib = Ib0, and this is the fixed bias state at this time.

[0068] Figure 6 Schematic diagram of an acceleration circuit and a bias power supply provided by an embodiment of the present disclosure Figure 2 Combined with Figure 2 、 Figure 3 and Figure 6 As shown, the acceleration circuit includes an eighth transistor M8 and a third resistor R3 connected in parallel; the control terminal of the eighth transistor M8 is coupled to the output terminal of the fifth transistor M5, the input terminal of the eighth transistor M8 is coupled to the power supply VDD, and the output terminal of the eighth transistor M8 is the output terminal of the acceleration circuit. The bias power supply includes a fourth resistor R4 and a current mirror; the current mirror includes at least two mirror transistors M11’, Mb1’-Mbn’; the control terminals of the mirror transistors M11’, Mb1’-Mbn’ are coupled to each other, the fourth resistor R4 is connected in series with the third resistor R3 and is coupled to the output terminal of the acceleration circuit 230, and the output terminal of the current mirror is the output terminal of the bias power supply 211; the output terminals of the third transistor M3 and the fourth transistor M4 are both coupled to the output terminal of the bias power supply. Wherein, n is greater than or equal to 0.

[0069] When the control circuit is enabled and the second control signal VC is at the initial voltage (or lower than the first preset value), the eighth transistor M8 is turned on. At this time, the bias current output by the bias power supply 211 is generated by the power supply VDD and the fourth resistor R4, and the bias current output by the bias power supply 211 is Ib = (Vb - V gsM11’) / R4; When the second control signal VC is greater than the first preset value, the eighth transistor M8 is turned off. At this time, the bias current output by the bias power supply 211 is generated by the power supply VDD, the fourth resistor R4, and the third resistor R3. The bias current output by the bias power supply 211 is Ib = (Vb - V gsM11’ ) / (R3 + R4). The bias current output by the bias power supply 211 when the acceleration circuit 230 is started is greater than the bias current output by the bias power supply 211 when the acceleration circuit 230 is turned off. Among them, by adjusting the resistance values of the fourth resistor R4 and the third resistor R3, the magnitude of the bias current Ib can be adjusted, thereby achieving the acceleration effect. V gsM11’ is the gate-source voltage of the mirror transistor M11'.

[0070] In the embodiments of the present disclosure, by setting the monitoring point of the monitoring circuit inside the comparison circuit, the first node inside the comparison circuit can accurately reflect the establishment state of the loop. Therefore, the on and off of the acceleration circuit can be controlled based on the voltage and / or current of the first node, thereby avoiding premature turn-off of the acceleration circuit.

[0071] In the embodiments of the present disclosure, the monitoring point of the monitoring circuit is not directly related to the output of the control circuit, is not easily affected by the output, and will not be triggered multiple times. After the monitoring circuit finishes working, it does not increase the circuit power consumption.

[0072] In the embodiments of the present disclosure, the acceleration circuit acts on the bias power supply to adjust the bias current output by the bias power supply, so that the acceleration effect can be evenly applied to each node of the loop, without affecting the establishment process of the loop itself, and avoiding jitter or overshoot.

[0073] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures, or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitude of the sequence numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0074] The above are only the preferred embodiments of the present disclosure, and do not limit the patent scope of the present disclosure. Any equivalent structural transformation made under the inventive concept of the present disclosure by using the content of the specification and drawings of the present disclosure, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present disclosure.

Claims

1. A control circuit, characterized in that, Comprising: A comparison circuit configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparison circuit having a bias power supply for supplying current to the comparison circuit; A monitoring circuit, whose input terminal is coupled to a first node within the comparison circuit, and whose output terminal is coupled to an acceleration circuit, configured to control the operating state of the acceleration circuit based on the voltage and / or current of the first node, so that the acceleration circuit is turned on when the control circuit is in a startup phase and turned off when the control circuit is in a stable phase; The acceleration circuit, whose input terminal is coupled to the monitoring circuit and whose output terminal is coupled to the bias power supply, is configured to adjust the bias current output by the bias power supply.

2. The control circuit according to claim 1, wherein: The monitoring circuit is specifically configured to output a second control signal based on the voltage and / or current of the first node; The acceleration circuit is specifically configured to, in response to the second control signal, adjust the bias current output by the bias power supply, so that the bias current when the control circuit is in a startup phase is greater than the bias current when the control circuit is in a stable phase.

3. The control circuit according to claim 1, wherein The monitoring circuit is configured to turn off the acceleration circuit when it detects that the voltage and / or current of the first node reaches a first preset value during the startup phase.

4. The control circuit according to claim 1 or 2, wherein: The comparison circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; wherein, the control terminal of the first transistor and the control terminal of the second transistor are coupled; the input terminals of the first transistor and the second transistor are coupled to a power supply, the output terminal of the first transistor is coupled to the input terminal of the third transistor and the control terminal of the first transistor, the first node is located at the output terminal of the first transistor, the output terminal of the second transistor is coupled to the input terminal of the fourth transistor and the output terminal of the comparison circuit; the output terminals of the third transistor and the fourth transistor are coupled to a ground terminal, the control terminal of the third transistor is the first input terminal of the comparison circuit for receiving the feedback voltage, and the control terminal of the fourth transistor is the second input terminal of the comparison circuit for receiving the reference voltage.

5. The control circuit according to claim 4, wherein: The monitoring circuit includes a detection unit, an initialization unit, and a current limiting unit. The detection unit and the current limiting unit are connected in series, and the initialization unit is connected in parallel with the current limiting unit; the output terminal of the detection unit is coupled to the input terminal of the acceleration circuit, and the detection unit is coupled to the first node; The detection unit is used to provide an adjustment current based on the voltage of the first node; The current limiting unit is used to adjust the change speed of the voltage at the output terminal of the detection unit; The initialization unit is used to provide an initial voltage to the output terminal of the detection unit during the startup phase to turn on the acceleration circuit.

6. The control circuit according to claim 5, wherein The detection unit includes a fifth transistor; and / or the initialization unit includes a sixth transistor; The output terminal of the fifth transistor is coupled to the current limiting unit. The output terminal of the fifth transistor is the output terminal of the monitoring circuit. The output terminals of the current limiting unit and the sixth transistor are coupled to the ground terminal.

7. The control circuit according to claim 5, characterized in that The current limiting unit includes a resistor and / or a capacitor.

8. The control circuit according to claim 5, wherein The monitoring circuit further includes: a first resistor for adjusting the change rate of the voltage at the output terminal of the detection unit.

9. The control circuit according to claim 5, characterized in that The acceleration circuit includes a seventh transistor; the control terminal of the seventh transistor is coupled to the output terminal of the monitoring circuit. The output terminal of the seventh transistor is the output terminal of the acceleration circuit.

10. The control circuit according to claim 9, wherein The acceleration circuit further includes a second resistor connected in series with the seventh transistor for adjusting the acceleration current output by the acceleration circuit; the input terminal of the seventh transistor is coupled to the power supply through the second resistor.

11. The control circuit according to claim 10, wherein The bias power supply includes a current source and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled, the output terminal of the current source is coupled to the input terminal of the current mirror, the input terminal of the current mirror is coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply; The output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

12. The control circuit according to claim 7, wherein The acceleration circuit is specifically configured to respond to the second control signal, turn on during the startup phase of the control circuit to generate an acceleration current, and output the acceleration current to the bias power supply.

13. The control circuit according to claim 6, wherein The acceleration circuit includes an eighth transistor and a third resistor connected in parallel; the control terminal of the eighth transistor is coupled to the output terminal of the fifth transistor, the input terminal of the eighth transistor is coupled to the power supply, and the output terminal of the eighth transistor is the output terminal of the acceleration circuit.

14. The control circuit according to claim 9, wherein The bias power supply includes a fourth resistor and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled, the fourth resistor is connected in series with the third resistor and coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply; The output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

15. The control circuit according to claim 4, wherein, Further included is: A switch circuit coupled to the comparison circuit and configured to control the operating state of the comparison circuit based on an enable signal; The switch circuit includes a ninth transistor and a tenth transistor; The control terminals of the ninth transistor and the tenth transistor receive the enable signal. The input terminals of the ninth transistor and the tenth transistor are coupled to the power supply. The output terminal of the ninth transistor is coupled to the control terminals of the first transistor and the second transistor. The output terminal of the tenth transistor is coupled to the output terminal of the second transistor.

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