LVDS (Low Voltage Differential Signaling) circuit and driving control method and device

Abstract

The invention discloses an LVDS (Low Voltage Differential Signaling) circuit and a driving control method and device, and relates to the field of electronic circuits and semiconductors. Aiming at the overshoot problem of an output signal of a traditional LVDS circuit, the invention provides an LVDS circuit which comprises N groups of differential pair transistors which are connected in parallel. Due to the parallel shunt principle, the current on each group of differential pair transistors is reduced, so that the generated switching noise peak is also reduced when any group of differential pair transistors are opened or closed. Moreover, the N groups of differential pair transistors are conducted in a time-sharing manner through the time delay differential signals, so that switching noise peaks generated when the N groups of differential pair transistors perform switching actions are different in time sequence. On this basis, after the switching noise peaks generated on the N parallel branches are superposed at the output end, the switching noise peaks are certainly smaller than the switching noise peaks generated by only one group of differential pair transistors originally, so that the aim of reducing the overshoot of the output signal of the LVDS circuit is fulfilled.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits and semiconductors, and in particular to an LVDS circuit and a drive control method and device. Background Art

[0002] Low Voltage Differential Signaling (LVDS) is a small amplitude differential signal technology. One of its common application principles is as follows: Figure 1 As shown. The LVDS driver consists of a group of differential pairs of transistors (i.e. switch drive transistors Q1~Q4, Q1, Q2 are one differential pair of transistors, Q3, Q4 are another differential pair of transistors) and current sources (two constant current sources). By controlling the conduction state of the switch drive transistor, a positive or negative voltage is generated at both ends of the resistor (100ohm, i.e. 100Ω) (the voltage direction is positive when DP_OUT points to DN_OUT), corresponding to logic "1" and logic "0" respectively, to achieve drive output.

[0003] However, when the LVDS driver turns on or off the switch differential driver tube, it will generate a large switching noise spike, which will cause the output signal to have a large overshoot, resulting in an increase in the rise and fall time of the output signal. At the same time, it will also cause the common-mode feedback voltage of the LVDS driver circuit to be unstable, causing the high-speed signal transmission quality to deteriorate and the bit error rate to increase.

[0004] Therefore, technicians in this field now urgently need an LVDS circuit to solve the overshoot problem existing in the output signal of the traditional LVDS circuit. Summary of the invention

[0005] The purpose of the present application is to provide an LVDS circuit and a drive control method and device to suppress the signal overshoot phenomenon caused by the switching spike generated when the switch tube performs the switching action.

[0006] To solve the above technical problems, the present application provides an LVDS circuit, comprising a first current source, a second current source, and N groups of differential pairs of tubes connected in parallel in series between the first current source and the second current source, wherein the N groups of differential pairs of tubes are used to be turned on in time-sharing manner according to a received delayed differential signal, so that the LVDS circuit outputs a target signal; wherein N is a natural number not less than 2.

[0007] In a possible embodiment, the circuit further includes a delay control unit, the delay control unit includes a preset number of output terminals, and each output terminal is respectively connected to the controlled terminals of the preset number of groups of differential pair transistors;

[0008] The delay control unit is configured to output the preset number of groups of delay differential signals according to the received signal to be processed and the delay control signal; wherein, the preset number is a natural number not less than 2 and not more than N, and there is a delay between at least two of the preset number of groups of delay differential signals.

[0009] In a possible embodiment, the delay control unit includes a delay unit, and the delay unit includes an input end, N output ends, a selector, and M delay modules; wherein, M is a natural number not less than N-1;

[0010] The input end of the delay unit is configured to access the differential signal or the signal to be processed, and the input end of the delay unit and the N output ends of the delay unit form N output paths respectively; wherein, the differential signal is obtained by converting the signal to be processed.

[0011] The selector is configured to control the number of the delay modules accessed in the N output paths according to the delay control signal; the delay unit is configured to perform delay processing on the received signal according to the selector.

[0012] In a possible embodiment, the delay control unit further includes: a differential conversion unit;

[0013] The differential conversion unit is configured to perform differential conversion on the received signal to be processed or the signal to be processed after delay processing to obtain the differential signal or the delay differential signal.

[0014] In a possible embodiment, the delay duration of the delay module is not greater than a first preset duration; wherein, the first preset duration is positively correlated with the cycle duration of the differential signal.

[0015] In a possible embodiment, it includes: a termination resistor;

[0016] The first input ends of the N groups of differential pair transistors are all connected to the positive extreme of the first current source, and the second input ends of the N groups of differential pair transistors are all connected to the negative extreme of the second current source; the first output ends of the N groups of differential pair transistors are all connected to the first end of the termination resistor, and the second output ends of the N groups of differential pair transistors are all connected to the second end of the termination resistor.

[0017] To solve the above technical problems, the present application further provides an LVDS driving control method, which is applied to the LVDS circuit as described above, and the method includes:

[0018] Obtain the signal to be processed;

[0019] Processing the signal to be processed to obtain a delayed differential signal, and outputting the delayed differential signal to the controlled end of N groups of differential pair tubes in the LVDS circuit;

[0020] Control N groups of the differential pair transistors to be turned on in time-sharing according to the delayed differential signal, and enable the LVDS circuit to output a target signal; wherein N is a natural number not less than 2.

[0021] In a possible embodiment, the time interval between any two groups of the N groups of differential pair tubes receiving the delayed differential signal is no greater than a second preset time length; wherein the second preset time length is positively correlated with the cycle length of the delayed differential signal.

[0022] In a possible embodiment, before processing the signal to be processed to obtain a delayed differential signal and outputting the delayed differential signal to the controlled end of the N groups of differential pair tubes in the LVDS circuit, the method further includes:

[0023] Obtaining the state of the delay control flag; wherein the state of the delay control flag includes on and off;

[0024] If the state of the delay control flag is off, the signal to be processed is differentially converted to obtain a differential signal, and the differential signal is simultaneously output to the controlled ends of the N groups of differential pair transistors.

[0025] In order to solve the above technical problems, the present application also provides an LVDS drive control device, which is applied to the LVDS circuit as described above, comprising:

[0026] A signal acquisition module, used for acquiring a signal to be processed;

[0027] A delayed output module, used for processing the signal to be processed to obtain a delayed differential signal, and outputting the delayed differential signal to the controlled end of the N groups of differential pair tubes in the LVDS circuit;

[0028] The time-sharing conduction module is used to control the N groups of differential pair transistors to be time-sharingly conducted according to the delayed differential signal, and enable the LVDS circuit to output the target signal; wherein N is a natural number not less than 2.

[0029] The present application provides an LVDS circuit, including N groups of differential pairs of tubes in parallel. Due to the principle of parallel current shunting, the current on each group of differential pairs of tubes becomes smaller, so when any group of differential pairs of tubes performs a switch action of opening or closing, the switching noise spike generated also becomes smaller. In addition, by delaying the differential signal to make the N groups of differential pairs of tubes conduct in time, the switching noise spikes generated by the N groups of differential pairs of tubes when performing a switch action are also different in timing. Based on this, the switching noise spikes generated by the N groups of differential pairs of tubes in parallel must be smaller than the switching noise spikes originally generated by only one group of differential pairs of tubes after being superimposed at the output end, thereby achieving the purpose of reducing the overshoot of the output signal of the LVDS circuit. Therefore, the present method can effectively reduce the rise and fall time of the output signal, improve the quality of high-speed signal transmission, and reduce the bit error rate.

[0030] The LVDS drive control method and device provided in the present application correspond to the above-mentioned LVDS circuit and have the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 is a structural diagram of an LVDS circuit;

[0033] Figure 2 A structural diagram of an LVDS circuit provided by the present invention;

[0034] Figure 3 A signal waveform diagram of a delayed differential signal DP<2:0> provided by the present invention;

[0035] Figure 4 A signal waveform diagram of a delayed differential signal DN<2:0> provided by the present invention;

[0036] Figure 5 A structural diagram of a delay unit provided by the present invention;

[0037] Figure 6 A structural diagram of a delay control unit provided by the present invention;

[0038] Figure 7 A flow chart of an LVDS drive control method provided by the present invention;

[0039] Figure 8 This is a structural diagram of an LVDS drive control device provided by the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] The core of this application is to provide an LVDS circuit and a drive control method and device.

[0042] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0043] The Low Voltage Differential Signaling (LVDS) circuit uses a very low amplitude signal (about 350 mV) to transmit data through a pair of differential PCB traces or balanced cables. Specifically, it is achieved by controlling the switching state of a group of differential pairs of transistors in the LVDS circuit (i.e., switch transistors Q1~Q4, Q1 and Q2 are one differential pair of transistors, and Q3 and Q4 are another differential pair of transistors). Figure 1 In the LVDS circuit shown, the direction of the current flowing through the resistor is reversed based on the alternating opening of the switch tubes Q1, Q4 and the switch tubes Q2, Q3, and the direction of the voltage drop across the resistor is also reversed, which is equivalent to reversing the LVDS circuit drive output. When the two reversal states are defined as logic "1" and logic "0", the LVDS circuit can generate valid logic "1" and logic "0" states.

[0044] However, in the actual use of LVDS circuits, it is also found that: during the opening and closing of the switch tube, a large switching peak will appear, which will cause a large overshoot phenomenon on the output signal, making the rise and fall time of the output signal longer. At the same time, it will also cause the common mode feedback voltage of the LVDS circuit to be unstable, resulting in problems such as poor high-speed signal transmission quality and increased bit error rate.

[0045] To solve the above problems, the present application provides a LVDS circuit, such as Figure 2 As shown, it includes a first current source and a second current source, which is equivalent to Figure 1 In particular, the LVDS circuit includes: N groups of differential pairs connected in parallel in series between the first current source and the second current source. The N groups of differential pairs are used to conduct in time according to the received delayed differential signal, so that the LVDS circuit outputs the target signal; wherein N is a natural number not less than 2.

[0046] It should be noted that Figure 2 a specific LVDS circuit is given with N = 3 as an example in Figure 2 , but it is not limited that N in this embodiment can only be equal to 3. Specifically as described above, N is any natural number greater than or equal to 2, including 3 but not limited to 3. When N needs to take a smaller or larger value, only need to reduce or increase the number of parallel differential pair transistor groups in the Figure 2 circuit shown in Figure 2 . Taking Figure 2 as an example, the LVDS circuit includes 3 groups of parallel differential pair transistors, which are respectively:

[0047] 1. MP0, MN0, MP1, MN1.

[0048] 2. MP2, MN2, MP3, MN3.

[0049] 3. MP4, MN4, MP5, MN5.

[0050] It is easy to understand that the switching states of the N groups of parallel differential pair transistors are the same, but the difference lies in the difference in the moment of their switching. Specifically, as can be seen from the description of the working principle of the above LVDS circuit, the output signal of the LVDS circuit is determined by the conduction state of the differential pair transistors. And when this circuit adopts multiple groups of parallel differential pair transistors, the output signal of the LVDS circuit is jointly determined by multiple groups of parallel differential pair transistors. The conduction states of these differential pair transistors are kept consistent to ensure the output of effective logic "1" and logic "0" states. However, it should be noted that the multiple groups of differential pair transistors are turned on in a time-sharing manner, that is, although each group of differential pair transistors performs the same switching action, the moment of performing this switching action is different.

[0051] Furthermore, the switching control of the differential pair transistors is realized by the received delayed differential signal. As the name implies, the delayed differential signal is a differential signal with a delay. The differential signal is originally a signal used to control the conduction state of the differential pair transistors in the LVDS circuit. Since there are multiple groups of differential pair transistors in this circuit, multiple groups of differential signals are required. These differential signals are processed so that the processed differential signals are different in timing (the processed differential signals make the conduction moments of at least two groups of driving differential pair transistors among the N groups of driving differential pair transistors different), and the processed differential signals constitute the above-mentioned delayed differential signal.

[0052] Based on the above circuit structure, a set of original differential pair transistors in the LVDS circuit becomes N sets of parallel differential pair transistors. According to the principle of parallel current shunting, when the parameters of the LVDS circuit remain unchanged, the current flowing through each set of differential pair transistors becomes smaller, reduced to 1 / N of the original. Correspondingly, the switching noise spikes that occur when the switching state of the switching transistors changes on each set of differential pair transistors are also suppressed to 1 / N of the original. Further, a time-division conduction control logic is adopted among the N sets of differential pair transistors, that is, the moments when the N sets of differential pair transistors generate switching noise spikes are different. When the switching noise spikes generated by the N sets of parallel differential pair transistors are superimposed at the output end, according to the waveform superposition principle, due to the difference in timing, the superimposed switching noise spikes are also smaller than the switching noise spikes generated by only one set of differential pair transistors originally. Thus, the purpose of suppressing the switching noise spikes is achieved, that is, the overshoot phenomenon of the output signal of the LVDS circuit can be alleviated.

[0053] It should be particularly noted that when N > 2, the time-division conduction of the N sets of differential pair transistors can specifically include two cases: 1. The conduction moments of each set of differential pair transistors are all different; 2. The conduction moment of at least one set of differential pair transistors is different from that of at least one set of other differential pair transistors; correspondingly, the preset number of sets of delayed differential signals can specifically also include two cases: 1. There is a delay between at least two of the preset number of sets of delayed differential signals, and the preset number is a natural number not less than 2 and not greater than N; 2. The preset number is N, and there is a delay between every two of the N sets of delayed differential signals.

[0054] Specifically, for the above case 1, combined with Figure 2 the example, that is, there are Figure 3 and Figure 4 two signal waveform schematic diagrams. Among them, Figure 3 is the waveform schematic diagram of the positive differential pair transistors in the three sets of differential pair transistors accessing the delayed differential signal. Figure 4 is the waveform schematic diagram of the negative differential pair transistors in the three sets of differential pair transistors accessing the delayed differential signal.

[0055] Specifically, for the above case 2, combined with Figure 2 the example. That is, the conduction moments of the first set of differential pair transistors and the second set of differential pair transistors can be the same, but different from the conduction moment of the third set of differential pair transistors, or the conduction moments of the three sets of differential pair transistors can be all different.

[0056] Based on the above principle of reducing the switching noise spikes and the signal overshoot phenomenon, both of the above two cases can suppress the switching noise spikes, and the only difference lies in the degree of suppression. Generally, when the conduction moments of the N sets of differential pair transistors are mutually different, the suppression effect on the switching noise spikes is the best.

[0057] In addition, for the above-mentioned first current source and second current source, this embodiment further provides a further implementation, as follows Figure 2 shown, the first current source and the second current source are provided by a bias circuit.

[0058] Specifically, as Figure 2 shown, a bias circuit is implemented by MOS transistor MP6. One end of MP6 is connected to the power input, and the other end is used as the output of the current source. When a bias voltage is applied to the gate of MP6, MP6 is equivalent to a current source (the first current source). The current source implemented by MP6 outputs a positive current, which is equivalent to Figure 1 the upper constant current source in

[0059] Similarly, another bias circuit is implemented by MOS transistor MN6. One end of MN6 is grounded, and the other end is used as the output of the current source. When a bias voltage is applied to the gate of MN6, MN6 is equivalent to a current source (the second current source). The current source implemented by MN6 outputs a negative current, which is equivalent to Figure 1 the lower constant current source in . Thus, it can be seen that this embodiment realizes two constant current sources in the LVDS circuit through two simple bias circuits, with a simple circuit and low cost.

[0060] Furthermore, in combination with the working principle of the LVDS circuit described above, this embodiment also explains the working principle of the improved LVDS circuit provided in this application:

[0061] As Figure 2 shown, an LVDS circuit provided in this embodiment, in addition to the above-mentioned first current source, second current source, and N groups of parallel differential pair transistors, also includes: a termination resistor (i.e., Figure 2 the 100 ohm resistor in , ohm is the unit of resistance).

[0062] Among them, the first input terminals of the N groups of differential pair transistors are all connected to the positive terminal of the first current source, and the second input terminals of the N groups of differential pair transistors are all connected to the negative terminal of the second current source; the first output terminals of the N groups of differential pair transistors are all connected to the first end of the termination resistor, and the second output terminals of the N groups of differential pair transistors are all connected to the second end of the termination resistor.

[0063] For the above circuit structure, although the N groups of differential pair transistors are turned on in a time-sharing manner, their switching actions within one switching cycle are always the same. Therefore, their influence on the voltage drop direction across the termination resistor within one switching cycle is also the same, only different in timing. Taking Figure 2 a group of differential pair transistors MP0, MN0, MP1, MN1 in as an example:

[0064] When MP0 and MN1 are turned on while MP1 and MN0 are turned off, the direction of the current flowing through the termination resistor is from top to bottom; when MP1 and MN0 are turned on while MP0 and MN1 are turned off, the direction of the current flowing through the termination resistor is from bottom to top. The conduction logic of the other several pairs of differential transistors is the same. Even when the conduction moments of the N pairs of differential transistors are exactly the same, for the current at the termination resistor and the resulting voltage drop, there is no difference from having only one pair of differential transistors. In this embodiment, the time-division conduction of the N pairs of differential transistors is strictly controlled within one switching period to avoid chaotic driving output of the LVDS circuit.

[0065] In summary, a LVDS circuit provided by the present application is based on the principle of parallel shunt. It replaces the original one pair of differential transistors with N pairs of parallel differential transistors to reduce the switching noise spikes generated when each pair of differential transistors performs a switching action. After that, since parallel shunt only targets the parallel branches, when reaching the output end of the LVDS circuit, the outputs of the parallel branches will be superimposed together. Therefore, this circuit also makes the N pairs of differential transistors conduct in a time-division manner by delaying the differential signals, so that the moments of the switching noise spikes generated by the N pairs of differential transistors are not exactly the same. Based on the waveform superposition principle, the switching noise spikes superimposed at the output end of the LVDS circuit are smaller than before at this time, realizing the suppression of the switching noise spikes, that is, realizing the suppression of the overshoot phenomenon of the output signal of the LVDS circuit. This circuit can effectively reduce the rise and fall time of the output signal, improve the high-speed signal transmission quality, and reduce the bit error rate.

[0066] On the other hand, there is no limitation on how to generate the above-mentioned delayed differential signals in the above embodiment. It can be generated by a hardware circuit or can be implemented based on a software method through a microcontroller, a digital signal processor (Digital Signal Processor, DSP), or other devices or equipment with control functions. Since the generation of the delayed differential signals by a software method needs to be specifically analyzed according to the specific controller device applied, and the implementation scheme is nothing more than obtaining a set of delayed differential signals with different delays by performing different delay processing on the differential signals to form the delayed differential signals, this embodiment will not elaborate on this too much.

[0067] However, for how to generate the above-mentioned delayed differential signals through a hardware circuit, this embodiment provides a possible implementation scheme. The above circuit further includes: a delay control unit.

[0068] The delay control unit includes a preset number of output terminals, and each output terminal is respectively connected to the controlled terminals of a preset number of pairs of differential transistors.

[0069] The delay control unit is used to output a preset number of groups of delayed differential signals according to the received signal to be processed and the delay control signal. Wherein, the preset number is a natural number not less than 2 and not more than N, and there is a delay between at least two groups of the delayed differential signals in the preset number of groups of delayed differential signals.

[0070] It should be noted that in this embodiment, the preset number (assumed to be Y) is not limited, and Y can be less than N. That is to say, the output end of the delay control unit is not connected to the controlled ends of each group of differential pair transistors. For the differential pair transistors not connected to the delay control unit, their controlled ends can be directly connected to the differential signals, that is, they are not controlled by the delay. However, as long as the delay control unit is connected to the controlled ends of at least one group of differential pair transistors, by outputting the differential signals after delay processing (i.e., delayed differential signals), it is still possible to make the conduction time of at least one group of differential pair transistors different from that of at least one group of other differential pair transistors, so as to achieve the purpose of suppressing signal overshoot.

[0071] At the same time, the delayed differential signals output by the delay control unit can also be Y groups of differential signals processed with different delays, or Y groups of differential signals processed with the same delay. However, it should be noted that when the delays of the Y groups of differential signals (relative to the delay of the original differential signals) are the same, in order to meet the above principle requirements for suppressing signal overshoot, Y needs to be less than N. That is to say, at least one group of differential pair transistors is not controlled by the delayed differential signals output by the delay control unit, so as to meet the requirement that the conduction time of at least one group of differential pair transistors is different from that of at least one group of other differential pair transistors.

[0072] In addition, not all the differential signals output by the delay control unit must be processed by delay. There may be some differential signals that are not processed by delay, and their time sequences are the same as those of the original differential signals. The conduction times of the differential pair transistors controlled by these delayed differential signals are the same as those of the differential pair transistors controlled by the original differential signals, which is equivalent to being directly controlled by the original differential signals without connecting to the delay control unit. However, it should be noted that the differential signals output by the delay control unit that are not processed by delay are only allowed to account for a part of all the delayed differential signals, so as to meet the requirement that the conduction time of at least one group of differential pair transistors is different from that of at least one group of other differential pair transistors and ensure the suppression effect on signal overshoot.

[0073] In addition, for the signal to be processed and the delay control signal mentioned in this embodiment, the original differential signal belongs to one type of the signal to be processed. In another possible implementation scenario, the signal to be processed can also be the signal at the previous level of the original differential signal. Exemplarily, in a common application scenario of an LVDS circuit, the LVDS circuit needs to convert a set of data into an analog signal for driving output. Then, the signal to be processed can be the original data at this time, but the delay control unit should also have the ability to convert the original data into a differential signal at this time. The specific implementation will be described in subsequent embodiments.

[0074] As for the delay control signal, it is a signal that freely controls the actual delay setting based on the actual needs of the user. As can be seen from the above, there are various implementation manners of the delay differential signal output by the delay control unit that can meet the purpose of overshoot suppression. The delay control signal can be used to control the delay control unit to generate any of the above delay differential signals that can suppress signal overshoot. Moreover, the delay control signal can also be used to control the specific delay time of each delay differential signal relative to the original differential signal to further optimize the signal overshoot suppression effect. This embodiment does not impose any restrictions on this.

[0075] This embodiment provides an implementation manner of providing a delay differential signal in a hardware manner. Based on the delay control unit performing delay processing on the original differential signal, a delay differential signal can be generated according to actual needs (i.e., received), so as to perform time-division conduction control on N groups of differential pair transistors. This meets the above purpose of suppressing the overshoot of the output signal of the LVDS circuit. The solution implemented based on a hardware circuit is more reliable and efficient than a software manner and well adapts to the needs of the actual application scenario.

[0076] Furthermore, the delay control unit in the above embodiment can be implemented by any module with a delay processing function, such as a delay circuit and other modules with a delay function. In a relatively simple embodiment, the above delay control unit can be implemented only by a delay circuit that can generate a fixed delay. This delay circuit is used to perform fixed-delay processing on the original differential signal and then output it to Y groups of differential pair transistors (Y needs to be less than N), which can also meet the need of suppressing signal overshoot.

[0077] However, this embodiment also provides a specific implementation manner of a more complex delay control unit to meet more diverse delay control needs. Specifically, the above delay control unit includes: a delay unit.

[0078] The delay unit includes: an input end, N output ends, a selector, and M delay modules. Wherein, M is a natural number not less than N - 1.

[0079] The input end of the delay unit is used to access differential signals or signals to be processed, and the input end of the delay unit and N output ends of the delay unit form N output paths respectively. Among them, the differential signal is obtained by converting the signal to be processed.

[0080] The selector is used to control the number of delay modules connected to the N output paths according to the delay control signal; the delay unit is used to perform delay processing on the received signal according to the selector.

[0081] It should be noted that the selector controls the number of delay modules connected to the N output paths according to the delay control signal, and the number of delay modules connected to each output path is different. In this embodiment, the delay unit has N output ends, that is, the corresponding delay control unit has N output ends (i.e., Y = N) to control the delay of N groups of differential pair transistors. However, as described in the above embodiment, the delay control unit does not necessarily output the differential signal after delay processing for each group of differential pair transistors. It can be selected to output the differential signal without delay processing for some differential pair transistors. For these differential pair transistors, it is equivalent to directly connecting their controlled ends to the original differential signal. However, based on the implementation scheme provided in this embodiment, a hardware delay control scheme is provided to arbitrarily control the delay control of all or part of the N groups of differential pair transistors without changing the circuit structure. Moreover, it can be specific to the delay control of each group of differential pair transistors, and the delay time length of each group of differential delay signals can be set according to different needs to realize different degrees of time-division conduction of the N groups of differential pair transistors.

[0082] The control of the delay time length of each group of differential delay signals, that is, the control of the conduction time of different groups of differential pair transistors, can be realized by controlling the number of delay modules connected to the corresponding N output paths. Each delay module is used to realize fixed delay processing. Therefore, whenever a delay module is connected, the differential signal flowing through this output path will undergo longer delay processing. It should be noted that this embodiment does not limit whether the delay time lengths of each delay module are the same, and they can be the same or different. However, considering aspects such as the easy availability of devices and the difficulty of control, it is relatively better to select M delay modules with the same delay time length.

[0083] In addition, for the number M of delay modules connected to the output path, in this embodiment, it is any natural number not less than N - 1. This is because the implementation scheme of the delay unit provided in this embodiment needs to be able to make the delay time lengths of each of the N groups of controlled differential pair transistors different to achieve the relatively better output signal overshoot suppression effect. Specifically, for example Figure 2In the circuit shown, if N = 3, the number of delay modules in the corresponding delay unit should be no less than 2. That is, the number of delay modules in the delay unit is at least 2. For three groups of differential pair transistors, it can be that the first group of differential pair transistors is not subjected to delay processing, the second group of differential pair transistors is connected to one delay module for a delay of T duration (assuming a fixed delay of T duration for one delay module), and the third group of differential pair transistors is connected to two delay modules for a delay of 2T duration. This results in three delay differential signals with different timings from each other, realizing the complete time-division conduction of the three groups of differential pair transistors, that is, the conduction moments of the three groups of differential pair transistors are different, ensuring the suppression effect on signal overshoot.

[0084] However, as also explained in the above embodiments, if there is no control requirement for the delay control unit to make the conduction moments of N groups of differential pair transistors different, the number of control modules in the delay unit only needs to satisfy being greater than 0. That is, as long as it is ensured that at least one group of N groups of differential pair transistors is connected to the differential signal after delay processing (it is also necessary to have at least one group of differential pair transistors connected to the original differential signal without delay processing, but this does not involve delay processing), and there is no requirement for the specific delay duration, then only 1 delay module can meet the delay control requirements.

[0085] In addition, for the further circuit implementation of the delay unit, this embodiment also provides a possible circuit structure, as shown in Figure 5 shown. Figure 5 The delay unit in [[ ]] contains 4 delay modules MUX1 to 4, 3 output terminals Data_drv<0>, Data_drv<1> and Data_drv<2>, and the input terminal is Data_in. It should be noted that Figure 5 Data_in in [[ ]] represents the original data input. At this time, the data signal output by the delay unit is the data signal after delay processing, and it still needs to be further converted to obtain the delay differential signal directly used to control the differential pair transistors. And in the circuit shown in Figure 5 the delay control signals connected to the delay unit correspond to Delay_sel<0> and Delay_sel<1>, that is, Delay_sel<1:0>. And in the delay unit shown in Figure 5 there are also more other circuit devices and structures than the most basic implementation form of the delay unit given in the above embodiments, such as logic gates, etc., for building the control circuit, that is, to better control the number of delay modules connected to each output path.

[0086] Specifically, in the circuit shown in Figure 5 the selectors are all two-way selectors, but the number of delay modules it contains is 4, and the number of output terminals or output paths it contains is 3, corresponding to Data_drv<0>, Data_drv<1> and Data_drv<2> respectively. CombiningFigure 5 For the circuit shown, this embodiment presents all control schemes for specifically controlling the number of delay modules connected to each output path.

[0087] Figure 5 The delay control signal in it consists of two binary signals, Delay_sel<1> and Delay_sel<0>. Its possible forms are Delay_sel<1:0> = "00", "01", "10", and "11". Assuming that the delay duration of all delay modules is T, the following is a separate analysis based on different delay control signals:

[0088] 1. "00" corresponds to a delay of 0:0:0 (relative to the input signal Data_in, the same below);

[0089] At this time, the controlled terminals S of MUX1 and MUX3 are both connected to "0", selecting the input terminal "0". After the logical operation of the NOR gate, MUX2 and MUX4 are connected to "1", selecting the input terminal "1".

[0090] At this time, the number of delay modules connected to the output paths Data_drv<0>, Data_drv<1>, and Data_drv<2> is 0, and the three groups of output signals have no delay. This state is also the initial default state of the delay unit, and delay control has not started yet.

[0091] 2. "01" corresponds to a delay of 3T:T:0;

[0092] At this time, the controlled terminal S of MUX1 is connected to "0", the controlled terminal S of MUX2 is connected to "0", the controlled terminal S of MUX3 is connected to "1", and the controlled terminal S of MUX4 is connected to "0". The number of delay modules connected to the output path Data_drv<0> is 3, and the total delay is 3T; the number of delay modules connected to the output path Data_drv<1> is 1, and the total delay is T; the number of delay modules connected to the output path Data_drv<2> is 0, and the total delay is 0.

[0093] 3. "10" corresponds to a delay of 3T:2T:0;

[0094] At this time, the controlled terminal S of MUX1 is connected to "1", the controlled terminal S of MUX2 is connected to "0", the controlled terminal S of MUX3 is connected to "0", and the controlled terminal S of MUX4 is connected to "0". The number of delay modules connected to the output path Data_drv<0> is 3, and the total delay is 3T; the number of delay modules connected to the output path Data_drv<1> is 2, and the total delay is 2T; the number of delay modules connected to the output path Data_drv<2> is 0, and the total delay is 0.

[0095] 4. "11" corresponds to a delay of 4T:2T:0;

[0096] At this time, the control terminal S of MUX1 is connected to "1", the control terminal S of MUX2 is connected to "0", the control terminal S of MUX3 is connected to "1", and the control terminal S of MUX4 is connected to "0". The number of delay modules accessed by the output path Data_drv<0> is 4, and the total delay is 4T; the number of delay modules accessed by the output path Data_drv<1> is 2, and the total delay is 2T; the number of delay modules accessed by the output path Data_drv<2> is 0, and the total delay is 0.

[0097] It should be noted that the above embodiments and Figure 5 The delay unit circuit given only represents one possible implementation form of the delay unit, which can realize the output of delay differential signals under 4 different delay control modes. Except for the first default initial state, the other 3 can meet the requirements of suppressing the overshoot of the LVDS output signal.

[0098] Figure 5 The NAND gates and other logic gates in are adaptive settings made based on the construction of the actual hardware circuit, aiming to achieve the complex gating control logic for each output path in the above delay unit through a simple two-to-one multiplexer. If other circuit structures are used in the delay unit, or four-to-one or more-bit multiplexers and a larger number of delay modules are used, then logic gates may not be added to build the control loop. Figure 5 And this embodiment does not limit the specific implementation circuit structure of the delay unit.

[0099] In summary, this embodiment provides a method for building and implementing the delay function part in the delay control unit based on a hardware circuit. The delay function implemented based on a hardware circuit is more stable, reliable than the software method, and is also less susceptible to environmental interference in actual applications, and can more effectively ensure the suppression effect on the overshoot of the output signal.

[0100] Furthermore, it has been stated in the above embodiments that the delay unit is only responsible for delay processing. When the signal to be processed accessed by the delay control unit is the original data, the delay control unit also needs to have the function of converting the data into a differential signal. This function can be implemented by software, but this embodiment also adaptively provides a hardware circuit solution. As Figure 6 shown, the delay control unit further includes: a differential conversion unit.

[0101] The differential conversion unit is used to perform differential conversion on the received signal to be processed or the signal to be processed after delay processing to obtain a differential signal or a delay differential signal.

[0102] It should be especially noted that this embodiment does not limit the cascading order between the differential conversion unit and the delay unit. Figure 6This is only one possible implementation. In Figure 6 In the circuit shown, the original data signal is first processed by a delay unit to obtain N groups (3 groups) of delayed data signals with different degrees of delay, and then N (3) differential conversion units convert the N groups of delayed data signals into N groups of delayed differential signals.

[0103] However, it is not difficult to know that the differential conversion unit can also be the pre-stage circuit of the delay unit. That is, the original data signal is first converted into a corresponding group of differential signals by the differential conversion unit, and then the delay unit performs delay processing to obtain N groups of different delayed differential signals.

[0104] This embodiment is not limited to either of the above two cascading schemes for the delay control unit, and can be freely selected according to actual needs. Figure 6 This is only one possible implementation and does not limit the delay control unit provided in this embodiment.

[0105] Furthermore, for the differential conversion unit, it is a circuit used to convert a data signal into a corresponding differential signal. In circuit design, converting only the input signal into the corresponding differential signal is a common differential conversion scheme, which can be simply implemented by a single-to-double circuit or other means, and a relatively complex one can be implemented by a composite structure such as a decoder and a differential drive circuit. Therefore, this embodiment does not limit the specific implementation of the differential conversion unit either, and can be freely selected according to actual needs.

[0106] As can be seen from the above, the delay control unit provided in this embodiment further includes a differential conversion unit. It is used to directly process the original data signal, and after differential conversion and delay processing, obtain the delayed differential signals directly used to control the switching of N groups of differential pairs in the LVDS circuit. The delay control unit provided in this embodiment integrates the functions required to control the LVDS circuit into one, so that the control requirements of the improved LVDS circuit can be met without adding additional circuits, ensuring the normal application of the LVDS circuit.

[0107] Furthermore, although a possible implementation is given in the above embodiment that all delay modules in the delay unit can have the same delay duration. However, no restriction is imposed on the specific delay duration of the delay modules. But in the above embodiment, it is also stated that the time-division conduction of N groups of differential pairs should be controlled within one switching period, otherwise there will be a problem of chaotic output. That is, the maximum delay duration that the delay unit can achieve needs to be less than one switching period of the LVDS circuit. Therefore, based on the setting method of taking the same delay duration for all delay modules in the above embodiment, this embodiment also provides a corresponding implementation for the delay duration of each delay module:

[0108] The delay duration of the delay module is not greater than the first preset duration. Among them, the first preset duration is positively correlated with the cycle duration of the differential signal.

[0109] It is easy to know that from the initial raw data signal to the differential signal, and then to the final delayed differential signal (or from the raw data signal to the delayed data signal and then to the final delayed differential signal). No matter which kind of signal it is, its cycle is always unchanged, and only the starting timing of the signal (delay processing) and the signal form (data conversion to differential) are changed. Therefore, although the above limits the first preset duration to be positively correlated with the cycle duration of the differential signal in this embodiment, in fact, it is positively correlated with the cycle duration of any one of the raw data, differential signal or delayed differential signal. However, because this embodiment limits the delay duration of the delay module in the delay unit, only after the differential signal passes through the delay module for delay processing can the delayed differential signal be obtained, that is, there is no delayed differential signal before passing through the delay unit. So this embodiment is described with the differential signal, but it can also be positively correlated with the cycle duration of the raw data signal.

[0110] In addition, this positive correlation can be a proportional relationship based on positive numbers. As can be seen from the above, the time-division conduction should be controlled within one switching cycle, and one switching cycle is also one cycle of the differential signal, and also one cycle of the raw data signal or the delayed differential signal.

[0111] Furthermore, to ensure the suppression effect on signal overshoot, this embodiment also provides a further implementation scheme:

[0112] The maximum delay duration of the delay unit does not exceed 1 / 8 of the differential signal cycle.

[0113] At this time, based on the setting that the delay durations of each delay module are the same, it is reflected in the M delay modules that the delay duration of the delay module does not exceed the requirement of 1 / 8M of the differential signal cycle. For example Figure 5 the delay module in it needs to meet the requirement that the delay duration does not exceed 1 / 32 of the differential signal cycle.

[0114] Based on the requirements for the delay duration of the delay unit and the delay module in this embodiment, during a time-division conduction control process, the time interval between the first-conducted differential pair transistor and the last-conducted differential pair transistor can be controlled within 1 / 8 of a switching cycle, so as to ensure the stable output of the LVDS circuit and better ensure the suppression effect on the overshoot of the output signal of the LVDS circuit.

[0115] In the above embodiment, a LVDS circuit is described in detail. The present application also provides an embodiment corresponding to a LVDS drive control method. The LVDS drive control method provided in this embodiment is applied to the LVDS circuit provided in any of the above embodiments, such as Figure 7 As shown, the method includes:

[0116] S11: Obtain the signal to be processed.

[0117] S12: Process the signal to be processed to obtain a delayed differential signal, and output the delayed differential signal to the controlled end of the N groups of differential pair tubes in the LVDS circuit.

[0118] S13: Control N groups of differential pair transistors to be turned on in time-sharing manner according to the delayed differential signal, and enable the LVDS circuit to output the target signal.

[0119] Wherein, N is a natural number not less than 2.

[0120] It is not difficult to know from the embodiments of the above circuit part that by connecting N groups of differential pairs in parallel, based on the principle of parallel current sharing, the switch spikes generated when each group of differential pairs performs switching actions can be reduced. Therefore, the method only needs to control the time-sharing conduction between the N groups of differential pairs to make the timing of the switch spikes generated by the N groups of differential pairs different. When the switch spikes generated by the parallel branches converge at the output end of the LVDS, the switch spikes generated by their superposition will also be smaller than the switch spikes originally generated by only one group of differential pairs, thereby achieving the purpose of suppressing the overshoot of the output signal.

[0121] Therefore, the method only needs to delay the differential signal originally used to control a group of differential pair switches (or the original data before differential conversion, both of which belong to the above-mentioned signals to be processed) to obtain N groups of delayed differential signals used to control different groups of differential pair switches. There is a delay between at least one group of signals among the N groups of delayed differential signals and at least another group of other signals, that is, the control purpose of time-sharing conduction is achieved, thereby meeting the above requirements to achieve the purpose of overshoot suppression.

[0122] Since the embodiments of the method part correspond to the embodiments of the circuit part, please refer to the description of the embodiments of the circuit part for the embodiments of the method part, which will not be repeated here.

[0123] Furthermore, the above circuit part provides a specific implementation scheme for the delay time setting of the delay module to avoid the influence of infinite delay time on the output of the LVDS circuit and ensure the effect of overshoot suppression. This embodiment also starts from the same perspective and provides a setting scheme for the delay time during time-sharing conduction control from the method level:

[0124] The time interval between any two of the N groups of differential pair transistors receiving the delayed differential signal is not greater than a second preset duration.

[0125] Among them, the second preset duration is positively correlated with the cycle duration of the delayed differential signal.

[0126] In other words, since the time interval between the first-conducted group of differential pair transistors and the last-conducted group of differential pair transistors is the maximum time interval when the N groups of differential pair transistors are controlled for time-division conduction. Therefore, the time interval between any two groups is not greater than the second preset duration, and only the time interval between the first-conducted group of differential pair transistors and the last-conducted group of differential pair transistors needs to be not greater than the second preset duration. Then the corresponding embodiment at this time is similar to the above circuit part. By restricting the maximum time interval of time-division conduction, the adverse effects that the N groups of differential pair transistors may cause to the output of the LVDS circuit due to non-simultaneous switching actions are avoided, and the suppression effect on the output signal overshoot is ensured.

[0127] Similarly to the above circuit part embodiment, the second preset duration is equivalent to the above first preset duration, and the cycle duration of the delayed differential signal is also the same as the cycle durations of the differential signal and the original data signal. That is, this embodiment is the application of the delay duration implementation scheme provided by the above circuit part at the method level, and the principle and effect correspond to the above circuit part embodiment. For details, please refer to the above circuit part embodiment and will not be elaborated here.

[0128] On the other hand, the LVDS circuit provided by the above embodiment can achieve the suppression of signal overshoot through N groups of parallel differential pair transistors. However, as can be seen from the above embodiment, when these N groups of parallel differential pair transistors perform switching actions simultaneously, their performance at the output end is no different from that of the LVDS circuit implemented by a single group of differential pair transistors. Therefore, this embodiment also gives a corresponding implementation scheme for the situation where the output signal overshoot of the LVDS circuit does not need to be suppressed in some special scenarios. Before step S12 of the above method, it further includes:

[0129] S21: Obtain the status of the delay control flag bit.

[0130] Among them, the status of the delay control flag bit includes on and off.

[0131] S22: If the status of the delay control flag bit is off, perform differential conversion on the signal to be processed to obtain a differential signal, and simultaneously output the differential signal to the controlled ends of the N groups of differential pair transistors.

[0132] That is, in this embodiment, the state of the delay control flag is obtained to determine whether it is necessary to conduct N groups of differential pairs of transistors in time-sharing to suppress signal overshoot. If the state of the delay control flag is on, it means that signal overshoot suppression is required, and the purpose can be achieved by going to step S12. However, if the state of the delay control flag is off, it means that signal overshoot suppression is not required at this time. Then, this method turns on N groups of differential pairs of transistors at the same time through step S22. At this time, the LVDS circuit composed of N groups of differential pairs of transistors is no different from the LVDS circuit originally composed of only one group of differential pairs of transistors, and a completely consistent effect can be achieved in the circuit.

[0133] In summary, this embodiment provides a more flexible LVDS drive control method, which adaptively selects whether to perform time-sharing conduction control on N groups of differential pairs of transistors by setting and obtaining the delay control flag. When overshoot suppression is required, time-sharing conduction is selected, and when overshoot suppression is not required, simultaneous conduction is selected. At this time, the LVDS circuit optimized in the above embodiment is no different from the original LVDS circuit, and plays exactly the same role in the circuit, thereby adapting to different needs in different scenarios.

[0134] Finally, in the above embodiment, a LVDS drive control method is described in detail, and the present application also provides an embodiment corresponding to a LVDS drive control device. Figure 8 As shown, this embodiment provides an LVDS drive control device, including:

[0135] The signal acquisition module 11 is used to acquire the signal to be processed.

[0136] The delayed output module 12 is used to process the signal to be processed to obtain a delayed differential signal, and output the delayed differential signal to the controlled end of the N groups of differential pair tubes in the LVDS circuit.

[0137] The time-sharing conduction module 13 is used to control the N groups of differential pair transistors to be time-sharingly conducted according to the delayed differential signal, and to make the LVDS circuit output the target signal; wherein N is a natural number not less than 2.

[0138] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0139] The above has provided a detailed introduction to an LVDS circuit, a driving control method, and a device thereof. The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the relevant parts, reference can be made to the description in the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of this application.

[0140] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

Claims

1. An LVDS circuit, comprising a first current source and a second current source, characterized in that, It further includes N groups of parallel-connected differential pair transistors connected in series between the first current source and the second current source. The N groups of differential pair transistors are used to conduct in a time-division manner according to the received delay differential signal, so that the LVDS circuit outputs a target signal; where N is a natural number not less than 2.

2. The LVDS circuit according to claim 1, wherein The circuit further includes a delay control unit. The delay control unit includes a preset number of output terminals, and each output terminal is respectively connected to the controlled terminals of the preset number of groups of differential pair transistors; The delay control unit is used to output the preset number of groups of delay differential signals according to the received signal to be processed and the delay control signal; where the preset number is a natural number not less than 2 and not greater than N, and there is a delay between at least two groups of the preset number of groups of delay differential signals.

3. The LVDS circuit according to claim 2, characterized in that, The delay control unit includes a delay unit. The delay unit includes an input terminal, N output terminals, a selector, and M delay modules; where M is a natural number not less than N-1; The input terminal of the delay unit is used to access a differential signal or the signal to be processed, and the input terminal of the delay unit and the N output terminals of the delay unit form N output paths; where the differential signal is obtained by converting the signal to be processed. The selector is used to control the number of the delay modules accessed in the N output paths according to the delay control signal; the delay unit is used to perform delay processing on the received signal according to the selector.

4. The LVDS circuit according to claim 3, wherein The delay control unit further includes: a differential conversion unit; The differential conversion unit is used to perform differential conversion on the received signal to be processed or the signal to be processed after delay processing to obtain the differential signal or the delay differential signal.

5. The LVDS circuit according to claim 3, wherein The delay time of the delay module is not greater than a first preset time; where the first preset time is positively correlated with the cycle time of the differential signal.

6. The LVDS circuit according to any one of claims 1 to 5, characterized in that, It includes: A termination resistor; The first input terminals of the N groups of differential pair transistors are all connected to the positive terminal of the first current source, and the second input terminals of the N groups of differential pair transistors are all connected to the negative terminal of the second current source; the first output terminals of the N groups of differential pair transistors are all connected to the first end of the termination resistor, and the second output terminals of the N groups of differential pair transistors are all connected to the second end of the termination resistor.

7. A LVDS driving control method, characterized in that, Applied to the LVDS circuit according to any one of claims 1 to 6, the method includes: Obtaining a signal to be processed; Processing the signal to be processed to obtain a delay differential signal, and outputting the delay differential signal to the controlled terminals of the N groups of differential pair transistors in the LVDS circuit; Controlling the N groups of differential pair transistors to conduct in a time-division manner according to the delay differential signal, and enabling the LVDS circuit to output a target signal; where N is a natural number not less than 2.

8. The LVDS driving control method according to claim 7, wherein The time interval between any two groups of the N groups of differential pair transistors receiving the delay differential signal is not greater than a second preset time; where the second preset time is positively correlated with the cycle time of the delay differential signal.

9. The LVDS driving control method according to claim 7, wherein Before processing the signal to be processed to obtain a delayed differential signal and outputting the delayed differential signal to the controlled terminals of N differential pairs of transistors in the LVDS circuit, the following steps are further included: Obtain the state of the delay control flag bit; wherein, the state of the delay control flag bit includes on and off; If the state of the delay control flag bit is off, perform differential conversion on the signal to be processed to obtain a differential signal, and output the differential signal to the controlled terminals of N differential pairs of transistors simultaneously.

10. An LVDS driving control device, characterized in that, Applied to the LVDS circuit according to any one of claims 1 to 6, it includes: A signal acquisition module for acquiring a signal to be processed; A delay output module for processing the signal to be processed to obtain a delayed differential signal and outputting the delayed differential signal to the controlled terminals of N differential pairs of transistors in the LVDS circuit; A time-division conduction module for controlling N differential pairs of transistors to conduct in a time-division manner according to the delayed differential signal and enabling the LVDS circuit to output a target signal; where N is a natural number not less than 2.

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