Phase locked loop circuit and display driver including the same

Abstract

The invention relates to a phase-locked loop circuit and a display driver including the same. A phase-locked loop circuit according to one embodiment of the present specification includes: a voltage-controlled oscillator configured to output a variable clock signal having an oscillation frequency based on a control voltage; and a bandwidth selection circuit configured to output the binary code value supplied to the voltage-controlled oscillator. The voltage-controlled oscillator outputs a variable clock signal based on a bandwidth selected according to the binary code value. Therefore, the voltage-controlled oscillator can operate with a lower gain.

Description

Technical Field

[0001] This specification relates to a phase-locked loop circuit and a display driver including the phase-locked loop circuit, and more particularly, to a phase-locked loop circuit configured to output a clock signal based on a selected bandwidth and a display driver including the phase-locked loop circuit. Background Art

[0002] A display panel includes a plurality of pixels and may display a desired image by emitting light based on a current flowing through a light-emitting element included in each pixel. To display a desired image through the display panel, a display device may convert image data input to a data processing device such as a timing controller (T-CON) into data in an appropriate format (e.g., RGB data) and transmit the data to a data driving circuit such as a source driver integrated circuit (SD-IC).

[0003] The data driving circuit may supply a data voltage to corresponding pixels of the display panel based on the image data received from the data processing device to drive each pixel. The data processing device may transmit a signal to a plurality of data driving circuits based on a dedicated protocol (e.g., clock embedded data signal (CEDS)). The data driving circuit may recover a clock signal from the received signal and process the image data using the recovered clock signal.

[0004] The data driving circuit may recover the clock signal through a recovery circuit. A phase-locked loop (PLL) circuit is an example of a circuit used in the recovery circuit. The phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) that outputs a clock signal by changing an oscillation frequency according to a control voltage. To extend the operating frequency range of the phase-locked loop (PLL) circuit, it is necessary to increase the gain Kvco of the voltage-controlled oscillator. However, in this case, the output of the voltage-controlled oscillator becomes vulnerable to instability because even a slight change in the control voltage due to noise transmitted through the power supply supplied to the phase-locked loop (PLL) circuit may cause a significant change in the oscillation frequency. The operating frequency range of the phase-locked loop (PLL) circuit may be extended by dividing the bandwidth into intervals, but this method has the disadvantages of requiring additional external pins to determine the bandwidth and requiring manual selection of a desired bandwidth. Additionally, the voltage-controlled oscillator has a characteristic that Kvco decreases in a high control voltage range, resulting in a problem that the oscillation frequency of the output signal in those ranges cannot properly reflect the control voltage. Summary of the Invention

[0005] This specification provides a phase-locked loop circuit that outputs a clock signal based on a selected bandwidth and enables a voltage-controlled oscillator to operate with a lower gain, and a display driver including the phase-locked loop circuit to improve the related art.

[0006] The problem to be solved by the embodiments of the present specification is to provide a phase-locked loop circuit that selects a bandwidth according to a binary code value output from a bandwidth selection circuit, enabling a voltage-controlled oscillator to operate with a lower gain, and a display driver including the phase-locked loop circuit.

[0007] The problem to be solved by the embodiments of the present specification is to provide a phase-locked loop circuit that generates two clock signals with a phase difference of 1 unit interval (UI) using a reference clock signal as an input signal, and automatically selects a bandwidth by associating the two clock signals with interval-specific delay times for dividing frequency bands, and a display driver including the phase-locked loop circuit.

[0008] The problems of the present specification are not limited to the above problems, and those skilled in the art will clearly understand other problems not explicitly stated based on the description provided below.

[0009] A phase-locked loop circuit according to an embodiment of the present specification includes: a voltage-controlled oscillator configured to output a variable clock signal having an oscillation frequency based on a control voltage; and a bandwidth selection circuit configured to output a binary code value supplied to the voltage-controlled oscillator, wherein the voltage-controlled oscillator outputs the variable clock signal based on a selected bandwidth determined by the binary code value.

[0010] In addition, the input signal of the phase-locked loop circuit may include a reference clock signal, the bandwidth selection circuit may include a delay-locked loop circuit, the delay-locked loop circuit locks an internal clock signal to the same frequency as the reference clock signal using the reference clock signal, the delay-locked loop circuit may output two clock signals having a phase difference of 1 unit interval (UI), and may determine the binary code value based on the two clock signals.

[0011] In addition, the bandwidth selection circuit may further include a multi-band selector, and the two clock signals may include a first clock signal and a second clock signal, wherein the first clock signal leads the second clock signal in phase, the multi-band selector receives the two clock signals, divides a predetermined frequency band into a plurality of intervals, sets interval-specific delay times, and determines the binary code value by comparing the delayed clock signal, which is generated by applying the delay time of each interval to the first clock signal, with the second clock signal.

[0012] In addition, the number of the plurality of intervals may be a power of 2 (n is a natural number), and the interval-specific delay times may be sequentially configured as multiples of the shortest delay time among the interval-specific delay times.

[0013] In addition, the multi-band selector may determine whether the delayed clock signal lags behind the second clock signal for each interval, generate a thermometer code value based on the determination result, and convert the thermometer code value into a binary code value.

[0014] Additionally, if the phase of the delayed clock signal leads the phase of the second clock signal, the multi-band selector may determine that the output signal of the frequency comparator is output as a low-level signal (0) for each interval, and if the phase of the delayed clock signal lags the phase of the second clock signal, the multi-band selector may determine that the output signal of the frequency comparator is output as a high-level signal (1) for each interval.

[0015] A display driver according to an embodiment of the present specification includes: a phase-locked loop circuit configured to recover a clock signal based on a signal received from an external device; and a control logic circuit configured to process image data using the recovered clock signal. The phase-locked loop circuit includes: a voltage-controlled oscillator configured to output a variable clock signal having an oscillation frequency based on a control voltage; and a bandwidth selection circuit configured to output a binary code value supplied to the voltage-controlled oscillator, and the voltage-controlled oscillator generates the recovered clock signal by outputting the variable clock signal based on a selected bandwidth determined by the binary code value.

[0016] Specific details of other embodiments are included in the detailed description and the drawings.

[0017] According to an embodiment of the present specification, two clock signals having a 1 unit interval (UI) phase difference can be generated using a reference clock signal that is an input signal of a phase-locked loop (PLL) circuit. By associating the two clock signals generated based on the reference clock signal with interval-specific delay times divided by frequency bands and calculating a code value for selecting a frequency band, the operating bandwidth of a voltage-controlled oscillator (VCO) can be automatically selected.

[0018] Therefore, while keeping the gain Kvco of the voltage-controlled oscillator (VCO) (i.e., the relationship between the control voltage and the oscillation frequency) at a low level, the operating frequency band of the phase-locked loop (PLL) circuit can be broadened. Additionally, the voltage-controlled oscillator (VCO) can have a robust characteristic against noise transmitted through the power supply supplied to the phase-locked loop (PLL) circuit.

[0019] The effects of the present specification are not limited to the above effects, and other effects not explicitly described will be obviously understood by those skilled in the art from the description provided below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By referring to the accompanying drawings and describing in detail the exemplary embodiments of the present specification, the above and other objects, features, and advantages of the present specification will become more apparent to those of ordinary skill in the art. In the drawings:

[0021] Figure 1 is a block diagram of a display device according to an embodiment of the present specification;

[0022] Figure 2 is a block diagram of a source driver circuit according to an embodiment of the present specification;

[0023] Figure 3 is a block diagram of a phase-locked loop circuit according to an embodiment of the related art;

[0024] Figure 4 is a block diagram of a phase-locked loop circuit according to an embodiment of the present specification;

[0025] Figure 5 is a block diagram of a delay-locked loop circuit included in a bandwidth selection circuit according to an embodiment of the present specification;

[0026] Figure 6 is a circuit diagram of a voltage delay line section in a delay-locked loop circuit according to an embodiment of the present specification;

[0027] Figure 7 is a block diagram of a multi-band selector included in a bandwidth selection circuit according to an embodiment of the present specification;

[0028] Figure 8 is a circuit diagram of a frequency comparator included in a multi-band selector according to an embodiment of the present specification;

[0029] Figure 9 is a table illustrating the delay time applied to each frequency comparator according to an embodiment of the present specification;

[0030] Figure 10 and Figure 11 is a timing diagram illustrating a method for calculating a code value by comparing clock signals according to an embodiment of the present specification;

[0031] Figure 12 is a table illustrating binary code values corresponding to thermometer code values according to an embodiment of the present specification;

[0032] Figure 13 is a flowchart illustrating the operation of a phase-locked loop circuit according to an embodiment of the present specification;

[0033] Figure 14 is a graph illustrating the operating frequency versus the control voltage in a phase-locked loop circuit according to an embodiment of the related art; and

[0034] Figure 15 is a graph illustrating the operating frequency versus the control voltage in a phase-locked loop circuit according to an embodiment of the present specification.

[0035] Description of reference numerals

[0036] 10: Phase comparator 20: Charge pump

[0037] 30: Loop filter 40: Voltage-controlled oscillator

[0038] 50: Bandwidth selection circuit 60: Delay locked loop circuit

[0039] 70: Multiband selector Detailed implementation manners

[0040] Advantages and features of the present disclosure and methods for achieving them will be apparent from the implementation manners described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the following implementation manners, but can be implemented in various different forms; on the contrary, the present implementation manners are provided to make the description of the present disclosure complete and to allow those skilled in the art to fully understand the scope of the present disclosure, and the present disclosure is only defined within the scope of the appended claims.

[0041] The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for illustrating the implementation manners of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals may represent the same components. In addition, when describing the present disclosure, if the detailed description of known related technologies is considered to unnecessarily obscure the key points of the present disclosure, the detailed description thereof may be omitted. Terms such as "including", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless the term is used together with the term "only". Unless otherwise clearly stated, the reference to a component of a singular noun includes the plural of that noun.

[0042] When interpreting components, even if not explicitly stated, they are interpreted as including an error range.

[0043] When describing the positional context relationship, for example, when terms such as "on", "above", "below", or "next to" describe the positional relationship between two components, one or more other components may be located between the two components, unless the terms "immediately" or "directly" are used.

[0044] When describing the temporal context relationship, for example, terms such as "after", "subsequently", "next", "before" may also include non-consecutive cases, unless the terms "immediately" or "directly" are used.

[0045] As used herein, the term "component" may refer to a unit that processes at least one function or operation, such as a software or hardware component. The function provided by a "component" may be performed individually by multiple components, or it may be integrated with other additional components. In this specification, a "component" may be implemented in a single circuit or multiple circuits, or in a single device or multiple devices.

[0046] Each of the features of the various embodiments described herein can be linked or combined with each other in whole or in part, and can be technically interlocked and operated in various ways, and each of the embodiments can be executed independently or in combination with each other.

[0047] Hereinafter, a phase-locked loop circuit and a display driver including the phase-locked loop circuit according to an embodiment of the present specification will be described with reference to the accompanying drawings.

[0048] Figure 1 is a block diagram of a display device according to an embodiment of the present specification.

[0049] As Figure 1 shown, a display device according to an embodiment of the present disclosure includes a host system 110, a timing controller 120, a gate driving circuit 130, a data driving circuit 140, and a display panel 150.

[0050] In one embodiment, the display driver may include a timing controller 120, a gate driving circuit 130, and a data driving circuit 140. The timing controller 120, the gate driving circuit 130, and the data driving circuit 140 may be configured as independent chips or as a single chip including at least one of the timing controller 120, the gate driving circuit 130, and the data driving circuit 140.

[0051] The host system 110 processes image data signals and outputs them together with a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The host system 110 supplies the vertical synchronization signal, the horizontal synchronization signal, the data enable signal, the clock signal, and the data signal to the timing controller 120.

[0052] The timing controller 120 receives the data signal and other signals from the host system 110, and outputs a gate timing control signal GDC for controlling the operation timing of the gate driving circuit 130 and a data timing control signal DDC for controlling the operation timing of the data driving circuit 140. The timing controller 120 supplies the data signal DATA together with the data timing control signal DDC to the data driving circuit 140.

[0053] The timing controller 120 may send signals to the data driving circuit 140 based on a dedicated protocol such as a clock embedded data signal CEDS.

[0054] The gate driving circuit 130 outputs a gate signal by shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driving circuit 130 includes a level shifter and a shift register.

[0055] The gate driving circuit 130 supplies gate signals to the sub-pixels SP included in the display panel 150 through gate lines GL1 to GLm. The gate driving circuit 130 may be formed as an in-panel gate structure or in the form of an integrated circuit (IC) on the display panel 150. The part of the gate driving circuit 130 implemented as an in-panel gate structure corresponds to a shift register.

[0056] The data driving circuit 140 samples and latches the data signal DATA in response to a data timing control signal DDC supplied from the timing controller 120, and converts the digital signal into an analog signal corresponding to a gamma voltage. The data driving circuit 140 supplies the data signal to the sub-pixels SP included in the display panel 150 through data lines DL1 to DLn. The data driving circuit 140 may include a plurality of source driver circuits, and each source driver circuit may be formed as an integrated circuit (IC).

[0057] The data driving circuit 140 may receive a clock embedded data signal CEDS from the timing controller 120, recover a clock signal from the received signal, and use the recovered clock signal to process image data.

[0058] The display panel 150 displays an image in response to the gate signal and the data signal output from the driving circuit including the gate driving circuit 130 and the data driving circuit 140. Depending on the substrate material, the display panel 150 may be implemented in a flat, curved, or flexible form. The display panel 150 includes a display area defined by a plurality of pixels and a non-display area in which various signal wirings or pads are formed. In the display area of the display panel 150, a plurality of pixels defined by a plurality of data lines DL1 to DLn and a plurality of gate lines GL1 to GLm are arranged. Each pixel includes a plurality of sub-pixels SP. The sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels, or red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. The sub-pixels SP may have one or more different light-emitting regions according to their light-emitting characteristics.

[0059] The pixel array of the display panel 150 may include a plurality of horizontal pixel rows, where each horizontal pixel row includes a plurality of pixels that are horizontally adjacent and commonly connected to a gate line. Here, each horizontal pixel row does not refer to a physical signal line, but represents a block of a row of pixels implemented by horizontally adjacent pixels.

[0060] Figure 2 is a block diagram of a source driver circuit according to an embodiment of the present specification.

[0061] The data driving circuit 140 may include a clock and data recovery (CDR) circuit 141, a digital control logic (DCL) circuit 142, an amplifier circuit Amp 143, and internal circuits disposed therein.

[0062] The clock and data recovery circuit 141 may receive clock embedded data (CED) and recover a clock signal based on the received data. In one embodiment, a phase-locked loop (PLL) circuit may be used for clock signal recovery. The clock and data recovery circuit 141 may accurately reconstruct the data by sampling the received data using the recovered clock signal.

[0063] The digital control logic circuit 142 may process the digital image data recovered by the clock and data recovery circuit 141. The signals processed in the digital control logic circuit 142 may be output to, for example, the amplifier circuit 143 and then transmitted to the internal circuits.

[0064] Figure 3 is a block diagram of a phase-locked loop circuit according to an embodiment of the related art.

[0065] As Figure 3 shown, a phase-locked loop (PLL) circuit of the related art may include a phase comparator 10, a charge pump 20, a loop filter 30, and a voltage-controlled oscillator 40.

[0066] The phase comparator 10 compares the phase and / or frequency of an input reference clock signal CLK_REF and an output clock signal CLK. The charge pump 20 outputs a charging current or a discharging current based on a comparison result UP / DN from the phase comparator 10. The loop filter 30 is charged or discharged by the charging current or the discharging current, thereby outputting a correspondingly changed control voltage VCONT. The voltage-controlled oscillator VCO 40 determines an oscillation frequency based on the control voltage VCONT and outputs a clock signal CLK having a corresponding frequency.

[0067] Therefore, the phase-locked loop (PLL) circuit may generate and output a stable clock signal CLK having a locked frequency by comparing the input reference clock signal CLK_REF with the output clock signal CLK.

[0068] Figure 4 is a block diagram of a phase-locked loop circuit according to an embodiment of the present specification.

[0069] Referring to Figure 4 and Figure 3 shown, compared with the related art PLL circuit shown, a phase-locked loop (PLL) circuit according to an embodiment of the present specification may further include a bandwidth selection circuit 50.

[0070] The bandwidth selection circuit 50 may receive a reference clock signal CLK_REF that is an input signal of the PLL circuit, and output a binary code value BWMODE<2:0> to the voltage controlled oscillator 40. The voltage controlled oscillator 40 may receive the binary code value from the bandwidth selection circuit 50 and select a frequency band of the output clock signal CLK. In the selected frequency band based on the binary code value, the voltage controlled oscillator 40 may output the clock signal CLK according to the control voltage VCONT. In Figure 4 , the binary code value is represented as 3 bits <2:0>; however, it is not limited thereto, and different numbers of bits may be set according to the number of intervals for dividing the selectable frequency bands.

[0071] In an embodiment of the present specification, the bandwidth selection circuit 50 may include a delay locked loop (DLL) circuit 60 and a multi-band selector 70.

[0072] The delay locked loop (DLL) circuit 60 may receive a reference clock signal CLK_REF that is an input signal of the phase locked loop (PLL) circuit, and use it to lock the internal clock signal of the delay locked loop (DLL) circuit 60 to the same frequency as the reference clock signal CLK_REF. The DLL circuit 60 may output two clock signals having a phase difference of 1 unit interval (UI) to the multi-band selector 70.

[0073] The multi-band selector 70 may receive two clock signals having a phase difference of 1 UI from the DLL circuit 60 and use them to generate a binary code value BWMODE<2:0>. The generated binary code value is output and sent to the voltage controlled oscillator 40.

[0074] The multi-band selector 70 may divide a predetermined frequency band in which the voltage controlled oscillator 40 operates to generate an output signal into a plurality of intervals, assign a delay time to each interval, and generate a binary code value by associating the two received clock signals having a phase difference of 1 UI with the corresponding delay times and calculating the results.

[0075] Figure 5 is a block diagram of a delay locked loop circuit included in a bandwidth selection circuit according to an embodiment of the present specification.

[0076] The delay locked loop (DLL) circuit 60 according to an embodiment of the present specification may include a phase comparator 11, a charge pump 21, and a voltage delay line unit 80.

[0077] The phase comparator 11 compares the phase of the reference clock signal CLK_REF, which is an input signal of the phase-locked loop (PLL) circuit, with the phase of the feedback signal from the output of the DLL circuit 60. Based on whether the phase of the feedback signal is ahead of or lagging behind (i.e., faster or slower) the reference clock signal CLK_REF, the phase comparator 11 generates an UP_DLL signal or a DN_DLL signal and sends it to the charge pump 21.

[0078] The charge pump 21 can output a charging current or a discharging current based on the comparison result from the phase comparator 10 to charge or discharge the capacitor, thereby adjusting the control voltage VCONT_DLL. In one embodiment, the delay-locked loop (DLL) circuit 60 may include a loop filter (not shown), and the control voltage VCONT_DLL can be adjusted by charging or discharging in the loop filter.

[0079] The voltage delay line section 80 receives the control voltage VCONT_DLL and adjusts the delay of each delay unit to synchronize the phase of the reference clock signal CLK_REF with the feedback signal.

[0080] Figure 6 is a circuit diagram of the voltage delay line section of a delay-locked loop circuit according to an embodiment of the present specification.

[0081] The voltage delay line section 80 receives the main clock signal MCLK derived from the reference clock signal CLK_REF. The reference clock signal CLK_REF, as an input signal of the phase-locked loop (PLL) circuit, has a period of N - UI (where N is a natural number) after passing through the phase comparator 11 and the charge pump 21. In one embodiment, the voltage delay line section 80 may compare the phase of the main clock signal MCLK with the phase of one of the output clock signals (such as the CKN signal) that has a delay of N - UI (N is a natural number) relative to the main clock signal MCLK in the output clock signals. When the phases of the two clock signals are synchronized, the voltage delay line section 80 can generate a multi-phase clock signal, and each delay unit of each clock signal has a delay of 0.5UI (i.e., a phase difference of 0.5UI).

[0082] Therefore, the voltage delay line section 80 in the DLL circuit 60 can extract two clock signals with a 1UI phase difference based on the reference clock signal CLK_REF that is an input signal of the PLL circuit. Then, the frequency band of the reference clock signal CLK_REF that is an input signal of the PLL circuit can be determined based on the delay time between the two clock signals.

[0083] Two clock signals for determining the frequency band of the reference clock signal CLK_REF only need to form a pair of clock signals with a phase difference of 1UI. For ease of explanation, the two clock signals used in some parts of this specification are exemplified as the CK1 clock signal and the CK2 clock signal, as Figure 6 shown, but not limited thereto.

[0084] Figure 7 is a block diagram of a multi-band selector included in a bandwidth selection circuit according to an embodiment of this specification; Figure 8 is a circuit diagram of a frequency comparator included in the multi-band selector; and Figure 9 is a table showing the delay times applied to each frequency comparator.

[0085] The multi-band selector 70 receives two clock signals (e.g., the clock signals CK1 and CK2) with a phase difference of 1UI output from the delay locked loop (DLL) circuit 60, and generates and outputs a binary code value BWMODE<2:0>.

[0086] The multi-band selector 70 can divide a predetermined frequency band in which the voltage controlled oscillator 40 operates to generate an output signal into multiple intervals. The multi-band selector 70 can assign a delay time to each interval, and generate a binary code value by associating the received two clock signals with a phase difference of 1UI with the corresponding delay time and calculating the result.

[0087] More specifically, in one embodiment, if the predetermined frequency band is divided into 8 intervals, different delay times can be assigned to each of the 8 intervals. Additionally, the two clock signals with a phase difference of 1UI can include a first clock signal (e.g., CK1) with a phase lead (or faster) and a second clock signal (e.g., CK2) with a phase lag (or slower). The binary code value can be generated by applying the set delay time to the first clock signal to generate a delayed clock signal, and comparing the phase of the delayed clock signal with the phase of the second clock signal to calculate the code value.

[0088] The multi-band selector 70 according to an embodiment of this specification may include a plurality of frequency comparators 72 and an encoder 74.

[0089] In one embodiment, as Figure 8The frequency comparator 72 configured as shown can generate a delayed clock signal CK_delay by applying a set delay time Tdelay to a first clock signal (e.g., CK1). Then, the frequency comparator 72 can compare the phase of the delayed clock signal CK_delay with the phase of a second clock signal (e.g., CK2) and output an output signal Q based on the comparison result. In one embodiment, a D flip-flop (DFF) can be used to output the output signal obtained by comparing the phases of the clock signals.

[0090] The frequency comparators 72 can be configured in a number corresponding to the number of intervals into which a predetermined frequency band is divided. For example, if the predetermined frequency band is divided into 8 intervals, the multi-band selector 70 can include 8 frequency comparators (#1 to #8), as Figure 7 shown. In one embodiment of this specification, the number of intervals into which the predetermined frequency band is divided can be a power of 2 (n is a natural number). This configuration can be based on a binary code value to determine the number of intervals; however, the technical concept of this specification is not limited to this specific method of determining the number of intervals.

[0091] Referring together to Figure 7 and Figure 9 , the delay times Tdelay set for the 8 frequency comparators (#1 to #8) can be different and are represented as Tdelay1 to Tdelay8. In one embodiment of this specification, the delay time set for each frequency comparator 72 (#1 to #8) can be sequentially configured as a multiple of the delay time T assigned to the frequency comparator with the shortest delay time (which is the eighth frequency comparator (#8)). For example, the seventh frequency comparator (#7) can have a delay time of 2T, the sixth frequency comparator (#6) can have a delay time of 3T, and in this way, the first frequency comparator (#1) can have a delay time of 8T.

[0092] Referring to Figure 8 , each frequency comparator 72 (#1 to #8) receives the first clock signal and the second clock signal (e.g., CK1 and CK2). Each frequency comparator applies a separately set delay time Tdelay to the first clock signal to generate a delayed clock signal CK_delay. Then, each frequency comparator compares the phase of the delayed clock signal with the phase of the second clock signal and outputs an output signal Q based on the comparison result. For example, the first frequency comparator (#1) applies a delay time of 8T to the first clock signal to generate a delayed clock signal and compares its phase with the phase of the second clock signal. Similarly, the eighth frequency comparator (#8) applies a delay time of T to the first clock signal to generate a delayed clock signal and compares its phase with the phase of the second clock signal.

[0093] Figure 10 and Figure 11 is a timing diagram illustrating a method for calculating a code value by comparing clock signals according to an embodiment of the present specification.

[0094] Referring to Figure 10 , in the high-frequency band interval, a relatively short delay time (e.g., delay time T, as Figure 9 shown) is applied to the first clock signal CK1 to generate a delayed clock signal CK_delay. This delayed clock signal CK_delay is used to determine whether the second clock signal CK2 is at a high level. Specifically, it is determined whether the second clock signal CK2 is in a high-level state at the rising edge timing of the delayed clock signal CK_delay. As Figure 10 shown, in this case, the output signal Q of the corresponding frequency comparator 72 can be a low-level signal.

[0095] Referring to Figure 11 , in the low-frequency band interval, a relatively long delay time (e.g., 8T, as Figure 9 shown) is applied to the first clock signal CK1 to generate a delayed clock signal CK_delay. This delayed clock signal CK_delay is used to determine whether the second clock signal CK2 is at a high level. Specifically, it is determined whether the second clock signal CK2 is in a high-level state at the rising edge timing of CK_delay. As Figure 11 shown, the output signal Q of the corresponding frequency comparator 72 can be a high-level signal.

[0096] For example, if the frequency band from 1 Gbps to 8 Gbps is divided into 8 intervals, the delay time Tdelay of the 1 Gbps frequency interval can be set to 1 ns to achieve a 1 UI delay, and the delay time Tdelay of the 8 Gbps frequency interval can be set to 0.125 ns to achieve a 1 UI delay. For the sake of understanding, in the high-frequency interval of 8 Gbps, a relatively short delay time of 0.125 ns can be applied to generate the delayed clock signal CK_delay. Conversely, in the low-frequency interval of 1 Gbps, a relatively long delay time of 1 ns can be applied to generate the delayed clock signal CK_delay.

[0097] Figure 12 is a table showing binary code values corresponding to thermometer code values according to an embodiment of the present specification.

[0098] The encoder 74 receives the outputs of each of the frequency comparators 72 as input signals COMP_OUT<0> to COMP_OUT<7>, and generates a thermometer code value based on these inputs. The encoder 74 may generate a thermometer code value COMP_OUT that corresponds to a value of 0 when a low-level signal is received from the frequency comparator, and corresponds to a value of 1 when a high-level signal is received, as Figure 12 shown.

[0099] The encoder 74 may convert the generated thermometer code value COMP_OUT into a binary code value BWMODE. In one embodiment of the present specification, the binary code value may be generated to correspond to the number of 1s in the thermometer code value minus 1. For example, if the thermometer code value has a value of 1 from COMP_OUT<0> to COMP_OUT<4> and a value of 0 from COMP_OUT<5> to COMP_OUT<7>; then the total number of 1s is 5. Subtracting 1 from this total gives a value of 4 corresponding to the binary code value. In this case, the binary code value will be BWMODE<100>.

[0100] The encoder 74 may output the generated binary code value BWMODE, and the output binary code value may be sent to the voltage-controlled oscillator 40 as option information, such that the voltage-controlled oscillator 40 can operate within a frequency band corresponding to the binary code value.

[0101] In addition, in one embodiment of the present specification, the voltage-controlled oscillator 40 may receive current and use a current-starved ring oscillator whose output frequency increases as the input current increases. A current source that increases the current in response to an increase in the control voltage VCONT and the binary code value BWMODE may be applied to the ring oscillator to adjust the frequency of the output signal.

[0102] Figure 13 is a flowchart illustrating the operation of a phase-locked loop circuit according to one embodiment of the present specification.

[0103] A method 1300 for operating a phase-locked loop (PLL) circuit according to one embodiment of the present specification may be as follows:

[0104] In step S1310, the delay-locked loop (DLL) circuit 60 may lock a clock signal at the same frequency as a reference clock signal CLK_REF that is an input signal of the phase-locked loop (PLL) circuit.

[0105] In step S1320, a delay-locked loop (DLL) circuit 60 may send two clock signals with a 1UI phase difference to a multi-band selector 70. Each frequency comparator 72 in the multi-band selector 70 may apply a separately set delay time Tdelay to a first clock signal (e.g., CK1) to generate a delayed clock signal CK_delay. Then, each frequency comparator 72 may compare the phase of the delayed clock signal with the phase of a second clock signal (e.g., CK2) and output an output signal Q based on the comparison result.

[0106] In step S1330, an encoder 74 of the multi-band selector 70 may receive the output signal Q from the frequency comparator 72, generate a thermometer code value COMP_OUT, and convert the thermometer code value to a binary code value BWMODE.

[0107] In step S1340, the multi-band selector 70 may output the converted binary code value BWMODE, and a voltage-controlled oscillator 40 may receive the output binary code value.

[0108] In step S1350, the voltage-controlled oscillator 40 may output a clock signal having an oscillation frequency determined by a control voltage VCONT within a frequency band corresponding to the received binary code value BWMODE. As a result, the voltage-controlled oscillator 40 may operate with a lower gain.

[0109] In step S1360, a phase-locked loop (PLL) circuit may, through its normal operation, generate and output a recovered clock signal based on a signal received from an external device.

[0110] Figure 14 is a graph showing the operating frequency versus the control voltage in a phase-locked loop circuit according to a related art embodiment. Figure 15 is a graph showing the operating frequency versus the control voltage in a phase-locked loop circuit according to an embodiment of the present specification.

[0111] Referring to Figure 14 , a typical phase-locked loop (PLL) circuit exhibits the characteristic that the operating frequency increases linearly with respect to the control voltage VCONT within a certain range. In the range where the control voltage is high, indicated by the right side of the dashed line in Figure 14 , the gain Kvco of the voltage-controlled oscillator 40 may decrease. This decrease in the gain Kvco may lead to a decrease in the loop bandwidth of the phase-locked loop (PLL) circuit, potentially resulting in incorrect operation of the spread-spectrum clock (SSC).

[0112] Furthermore, in order to expand the operating frequency range of the PLL circuit, the gain Kvco of the voltage-controlled oscillator 40 must be increased such that the slope of the linear graph is in the range indicated by Figure 14increases within the range indicated to the left of the dashed line. In this case, the output of the voltage-controlled oscillator 40 becomes vulnerable to instability because even a slight change in the control voltage due to noise transmitted through the power supply supplied to the PLL circuit may cause a significant change in the oscillation frequency.

[0113] In contrast, a phase-locked loop (PLL) circuit according to an embodiment of the present specification can automatically select the operating frequency band of the voltage-controlled oscillator 40 by controlling the voltage-controlled oscillator 40 using a binary code value generated based on a reference clock signal CLK_REF as an input signal.

[0114] Referring to Figure 15 , the phase-locked loop (PLL) circuit can achieve a wider operating frequency range while dividing the frequency range into multiple intervals. The gain Kvco of the voltage-controlled oscillator 40 operating in the frequency band within each interval can be maintained at a low level. In the range indicated to the left of the dashed line of Figure 15 , the linear graph exhibits a smaller slope compared to Figure 14 .

[0115] Additionally, even without using the range of the control voltage VCONT that is vulnerable to the operation of the spread-spectrum clock (SSC) (which is the range indicated to the right of the dashed line of Figure 15 ), the PLL circuit can sufficiently output a high oscillation frequency by using a lower control voltage. As a result, the operation of the spread-spectrum clock (SSC) of the phase-locked loop (PLL) circuit can be performed without any problems. Furthermore, in one embodiment, a low-dropout (LDO) power supply can be used for the low control voltage, thereby enabling the use of a stable control voltage with minimal noise.

[0116] As described above, according to an embodiment of the present specification, a phase-locked loop circuit and a display driver including the phase-locked loop circuit can generate two clock signals having a 1UI phase difference using a reference clock signal as an input signal of the phase-locked loop (PLL) circuit. By associating the two clock signals generated based on the reference clock signal with interval-specific delay times divided by frequency bands and calculating a code value, the operating bandwidth of the voltage-controlled oscillator (VCO) can be automatically selected by selecting a frequency band based on the calculated code value. Therefore, the phase-locked loop (PLL) circuit can ensure a wide operating frequency band while maintaining a low gain of the voltage-controlled oscillator (VCO).

[0117] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to such embodiments, and various modifications can be made within its scope without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are only for illustrative purposes and are not intended to limit the technical concept of the present disclosure, and the scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0118] Cross - reference to related applications

[0119] This application claims the priority and benefits of Korean Patent Application No. 10 - 2024 - 0002712, filed on January 8, 2024, and Korean Patent Application No. 10 - 2024 - 0179444, filed on December 5, 2024, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A phase-locked loop circuit, the phase-locked loop circuit comprising: A voltage-controlled oscillator configured to output a variable clock signal having an oscillation frequency based on a control voltage; And A bandwidth selection circuit configured to output a binary code value supplied to the voltage-controlled oscillator, Wherein the voltage-controlled oscillator outputs the variable clock signal based on a bandwidth selected according to the binary code value.

2. The phase-locked loop circuit according to claim 1, wherein The input signal of the phase-locked loop circuit includes a reference clock signal, and The bandwidth selection circuit includes: A delay-locked loop circuit configured to lock an internal clock signal to the same frequency as the reference clock signal using the reference clock signal and output two clock signals having a 1 unit interval (UI) phase difference.

3. The phase-locked loop circuit according to claim 2, wherein, Determine the binary code value based on the two clock signals.

4. The phase-locked loop circuit according to claim 3, wherein The two clock signals include a first clock signal and a second clock signal, and The first clock signal leads the second clock signal in phase.

5. The phase-locked loop circuit according to claim 4, wherein The bandwidth selection circuit further includes a multi-band selector, and The multi-band selector is configured to: Receive the two clock signals, Divide a predetermined frequency band into a plurality of intervals and assign a delay time to each interval, and Determine the binary code value by comparing a delayed clock signal, which is generated by applying an interval-specific delay time to the first clock signal, with the second clock signal.

6. The phase-locked loop circuit according to claim 5, wherein The number of the plurality of intervals is a power of 2, where n is a natural number, and The interval-specific delay time is sequentially configured as a multiple of the shortest delay time among the interval-specific delay times.

7. The phase-locked loop circuit according to claim 5, wherein, The multi-band selector is configured to: For each interval, determine whether the delayed clock signal lags behind the second clock signal in phase, Generate a thermometer code value based on the determination result, and Convert the thermometer code value into the binary code value.

8. The phase-locked loop circuit according to claim 7, wherein, If the phase of the delayed clock signal leads the phase of the second clock signal, the multi-band selector determines that the output signal of the frequency comparator is output as a low-level signal 0 for each interval, and if the phase of the delayed clock signal lags behind the phase of the second clock signal, the multi-band selector determines that the output signal of the frequency comparator is output as a high-level signal 1 for each interval.

9. A display driver, the display driver comprising: A phase-locked loop circuit configured to recover a clock signal based on a signal received from an external device; And A control logic circuit configured to process image data using the recovered clock signal, Wherein the phase-locked loop circuit includes: A voltage-controlled oscillator configured to output a variable clock signal having an oscillation frequency based on a control voltage; and A bandwidth selection circuit configured to output a binary code value supplied to the voltage-controlled oscillator, and wherein the voltage-controlled oscillator generates the recovered clock signal by outputting the variable clock signal based on a bandwidth selected according to the binary code value.

10. The display driver according to claim 9, wherein an input signal of the phase-locked loop circuit includes a reference clock signal, and the bandwidth selection circuit includes a delay-locked loop circuit configured to lock an internal clock signal to the same frequency as the reference clock signal using the reference clock signal and output two clock signals having a phase difference of 1 unit interval (UI).

11. The display driver according to claim 10, wherein, The binary code value is determined based on the two clock signals.

12. The display driver according to claim 11, wherein the two clock signals include a first clock signal and a second clock signal, and the first clock signal leads the second clock signal in phase.

13. The display driver according to claim 12, wherein the bandwidth selection circuit further includes a multi-band selector, and the multi-band selector is configured to receive the two clock signals, divide a predetermined band into a plurality of intervals and assign a delay time to each interval, and determine the binary code value by comparing a delayed clock signal, which is generated by applying an interval-specific delay time to the first clock signal, with the second clock signal.

14. The display driver according to claim 13, wherein the number of the plurality of intervals is a power of 2, where n is a natural number, and the interval-specific delay time is sequentially configured as a multiple of the shortest delay time among the interval-specific delay times.

15. The display driver according to claim 13, wherein, The multi-band selector is configured to for each interval, determine whether the delayed clock signal lags the second clock signal in phase, generate a thermometer code value based on the determination result, and convert the thermometer code value into the binary code value.

16. The display driver according to claim 15, wherein, If the phase of the delayed clock signal leads the phase of the second clock signal, the multi-band selector is configured to determine that an output signal of a frequency comparator is output as a low-level signal 0 for each interval, and if the phase of the delayed clock signal lags the phase of the second clock signal, the multi-band selector determines that the output signal of the frequency comparator is output as a high-level signal 1 for each interval.

Images