Multi-board card machine frame switch system, UART interface gating method and application

Abstract

The invention discloses a multi-board card machine frame switch system, a UART interface gating method and application, the multi-board card machine frame switch system comprises a main control board and a plurality of function board cards, each function board card comprises a UART interface, the main control board comprises a programmable logic device and a CPU, and the UART interface is connected with the main control board. The programmable logic device comprises a register, a first I2C interface, a switch unit and a debugging interface; the CPU is in communication connection with the first I2C interface, the first I2C interface is connected with the register, the switch unit is connected between the UART interface and the debugging interface, and the CPU realizes read-write control on the register through the I2C interface so as to trigger the gating of the corresponding switch unit and further control the conduction between the corresponding UART interface and the debugging interface. The IO resources of the programmable logic device are utilized, the switch unit is controlled through the register, and gating control over UART interfaces of all the function board cards under the multi-board-card debugging operation and maintenance scene is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a multi-board frame switch system, a UART interface gating method and an application thereof. Background Art

[0002] Currently, the switching router products launched for wide area networks, 5G bearer networks, and data center DCI interconnection scenarios are basically large-scale frame core switches. Such switches usually have the characteristics of a large variety of boards and a large number of slots, and are usually designed with a physically separated control plane and forwarding plane, and the hardware of the main control engine, switching network board, and line card are independent of each other, which increases the difficulty of commissioning and operation and maintenance of the whole machine.

[0003] For the main control board, switching board, line card, and even the PEM power board, fan board, etc., a debugging management port is required to control and obtain information such as the configuration and status of the board. Therefore, there are many debugging interface positions for the whole machine, and the debugging interfaces of the switching board, PEM board, and fan board cannot even be directly led out of the chassis panel, which brings a lot of inconvenience to the debugging and operation and maintenance of the equipment.

[0004] The existing solutions include: after converging the UART debugging interfaces of each board to the main control board through the backplane, an analog switch chip is used in combination with the CPU IO control signal, and the analog switch chip is gated through the IO control to select a specific output channel and then output the output signal of the analog switch.

[0005] The disadvantages of the existing technology are as follows: 1. The control logic of the software system is relatively complex, and the software needs to match and control multiple IOs and organize the mapping table of each IO and the actual selected channel;

[0006] 2. The CPU GPIO resources are limited and there will be a multiplexing situation. When configured as GPIO, the multiplexed interface function cannot be used anymore, resulting in waste of CPU GPIO resources;

[0007] 3. When there are many boards, the corresponding hardware design is relatively complex, and the number of analog switches needs to be increased, and even there is a situation of analog switch cascading, resulting in an increase in the PCB layout area, which is not very suitable for some high-density board scenarios with limited board layout space.

[0008] Therefore, in view of the above technical problems, it is necessary to provide a multi-board frame switch system, a UART interface gating method and an application thereof. Summary of the Invention

[0009] The purpose of the present invention is to provide a multi-board frame switch system, a UART interface gating method and an application thereof, which can solve the problem of inconvenient gating of the debugging and operation and maintenance interfaces of each board in the multi-board frame switch system.

[0010] To achieve the above object, the technical solution provided by a specific embodiment of the present invention is as follows:

[0011] A multi-board frame switch system includes a main control board and a plurality of function boards. The function board includes a UART interface. The main control board includes a programmable logic device and a CPU. The programmable logic device includes a register, a first I2C interface, a switch unit, and a debugging interface;

[0012] The CPU is communicatively connected to the first I2C interface. The first I2C interface is connected to the register. The switch unit is connected between the UART interface and the debugging interface. The CPU realizes the read and write control of the register through the I2C interface to trigger the corresponding switch unit to be selected, thereby controlling the conduction between the corresponding UART interface and the debugging interface.

[0013] In one or more embodiments of the present invention, the register includes a mapping table representing the corresponding relationship between the register value and the UART interface. The CPU is used to access the mapping table through the first I2C interface and write the register value into the register based on the mapping table. The register is used to trigger the corresponding switch unit to be selected based on the register value.

[0014] In one or more embodiments of the present invention, the multi-board frame switch system further includes a backplane, and the backplane is connected between the switch unit and the UART interface.

[0015] In one or more embodiments of the present invention, the main control board further includes a level conversion unit and a connector located outside the main control board. The level conversion unit is connected between the debugging interface and the connector.

[0016] In one or more embodiments of the present invention, the programmable logic device includes a CPLD or an FPGA.

[0017] In one or more embodiments of the present invention, the CPU includes a second I2C interface, and the second I2C interface is communicatively connected to the first I2C interface through a serial clock line and a serial data line.

[0018] In one or more embodiments of the present invention, the switch unit includes a plurality of groups of receiving switches and sending switches. The debugging interface includes a receiving adjustment interface and a sending debugging interface;

[0019] The receiving switch is connected between the UART interface and the receiving adjustment interface, and the sending switch is connected between the UART interface and the sending adjustment interface.

[0020] The technical solution provided by another specific embodiment of the present invention is as follows:

[0021] A UART interface gating method is applied to a multi-board frame switch system. The multi-board frame switch system includes a main control board and several functional boards. The functional boards include UART interfaces. The main control board includes a programmable logic device and a CPU. The programmable logic device includes registers, a first I2C interface, a switch unit, and a debugging interface;

[0022] The UART interface gating method includes:

[0023] The CPU accesses the registers based on the first I2C interface and realizes the read and write control of the registers. The switch unit gates the corresponding UART interface and debugging interface based on the read and write control of the registers.

[0024] The technical solution provided by another specific embodiment of the present invention is as follows:

[0025] An electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it realizes the UART interface gating method described in one or more embodiments of the present invention.

[0026] The technical solution provided by another specific embodiment of the present invention is as follows:

[0027] A computer-readable medium carries computer-executable instructions. When the computer-executable instructions are executed by a processor, they are used to realize the UART interface gating method described in one or more embodiments of the present invention.

[0028] Compared with the prior art, the multi-board frame switch system, UART interface gating method and application of the present invention utilize the IO resources of the programmable logic device, manage and switch the switch unit through registers, and realize the gating control of the UART interfaces of each functional board in the multi-board debugging and operation and maintenance scenario;

[0029] The present invention controls the registers of the programmable logic device through the I2C interface. The control logic is general and concise, and shares relevant resources with other I2C threads, without occupying the CPU resources alone, saving the GPIO resources of the CPU and avoiding waste of CPU resources;

[0030] The present invention adopts digital switches, and the IO driving ability is adjustable, which can ensure good signal edges. The present invention supports multiple level designs and can be flexibly adapted to different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0032] Figure 1 It is the structural schematic diagram of the multi-board-frame switch system in an embodiment of the present invention;

[0033] Figure 2 It is the structural schematic diagram of the multi-board-frame switch system in another embodiment of the present invention;

[0034] Figure 3 It is the flowchart of the UART interface gating method in an embodiment of the present invention;

[0035] Figure 4 It is the hardware structure diagram of an electronic device in an embodiment of the present invention. Detailed implementation manners

[0036] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] Unless otherwise clearly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "having" etc. will be understood to include the stated elements or components, without excluding other elements or other components.

[0038] "Coupled" or "connected" or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connections through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connections through circuits or components such as switches and follower circuits. Additionally, in the present invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0039] In the detailed description of the specification, reference is made to the accompanying drawings which form a part hereof, in which like reference numerals always refer to like elements, and which are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Accordingly, the following detailed description should not be construed in a limiting sense.

[0040] The various operations in the specification may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0041] For the purposes of the present application, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of the present application, the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0042] Various components and devices may be referred to or shown herein in the singular form (e.g., “MOS transistor”, “transistor”, “switch”, etc.), but this is merely for convenience of discussion, and any element referred to in the singular may include a plurality of such elements in accordance with the teachings herein.

[0043] The specification describes the use of the phrases “in this embodiment” or “in other embodiments” or “in some embodiments”, which may each refer to one or more of the same or different embodiments. In addition, the terms “comprising”, “including”, “having”, etc., used with respect to the embodiments of the present application are synonymous.

[0044] As Figure 1 shown, an embodiment of the present invention provides a multi-board frame switch system, including a main control board 10 (Super controller) and a plurality of function boards 20. The function board 20 includes a UART interface 21. The main control board 10 includes a programmable logic device 11 and a CPU. The programmable logic device 11 includes a register 111, a first I2C interface 112, a switch unit 101, and a debugging interface 13.

[0045] The CPU is communicatively connected to the first I2C interface 112. The first I2C interface 112 is connected to the register 111. The switch unit 101 is connected between the UART interface 21 and the debugging interface. The CPU realizes the read and write control of the register 111 through the first I2C interface 112 to trigger the corresponding switch unit 101 to be selected, thereby controlling the conduction between the corresponding UART interface and the debugging interface, and controlling the conduction between the corresponding UART interface 21 and the debugging interface 13.

[0046] In the multi-board frame switch system, the function board 20 that needs to debug and maintain the UART interface 21 includes a network board and a line card. If there is an MCU-related design for the fan board and power board of individual devices, there may also be similar requirements. This embodiment is exemplified based on these two types of function boards 20, namely the network board (Fabric card) and the line card (Line card). It should be noted that the main control board 10 of the multi-board frame switch system usually has a 1+1 redundancy design. However, during the normal operation of the whole machine, only the main main control is in the active state. Only when the main main control fails or is manually switched, the standby main control will be upgraded to the main main control and be activated. Therefore, unless otherwise specified, the main control board 10 mentioned in the following text refers to the main main control.

[0047] As Figure 1 shown, the multi-board frame switch system in this embodiment includes 14 function boards 20, and 14 function boards 20 are taken as an example and divided into 8 line cards (line card [0] to [7]) and 6 network boards (network board [0] to [5]). Each function board corresponds to a switch. For example, line card [0] corresponds to switch S L0 ... line card [7] corresponds to switch S L7 , network board [0] corresponds to switch S F0 ... network board [5] corresponds to switch S F5 . Each switch is connected to the debugging interface 13.

[0048] It can be understood that in this embodiment, the register 111 is a selection register 111, and the register 111 includes a mapping table representing the corresponding relationship between the register value and the UART interface 21. The CPU includes a second I2C interface 121, and the second I2C interface and the first I2C interface 112 are communicatively connected through the serial clock line I2C_SCL and the serial data line I2C_SDA.

[0049] Specifically, the CPU is used to access the mapping table through the second I2C interface 121 and the first I2C interface 112, and write a register value into the register 111 based on the mapping table. The register 111 is used to trigger the selection of the corresponding switch unit based on the register value. For example, when the register value in the mapping table is 000, it corresponds to selecting line card [0]; when the register value is 001, it corresponds to selecting line card [1]... when the register value is 110, it corresponds to selecting line card [6]; when the register value is 111, it corresponds to selecting line card [7].

[0050] As Figure 1 shown, in one embodiment, the multi-board frame switch system further includes a backplane 40, and the backplane 40 is connected between the switch unit 101 and the UART interface 21.

[0051] As Figure 1 shown, the main control board 10 further includes a level conversion unit 12 and a connector 30 located outside the main control board 10. The level conversion unit 12 is connected between the debugging interface 13 and the connector 30, and is used for performing level conversion on the UART signal. The level conversion unit 12 in one embodiment includes an RS232 level conversion chip. Specifically, the RS232 level conversion chip 12 is connected to the debugging interface 13, and the RS232 level conversion chip 12 is used to convert the digital signal (i.e., the UART signal) of the CPLD into the RS232 standard level (such as ±12V or ±15V) to communicate with an external UART interface debugging device through the connector 30. Optionally, the connector 30 is an RJ45 (Registered Jack 45) connector.

[0052] The programmable logic device 11 in one embodiment includes a CPLD (Complex Programmable Logic Device) or an FPGA (Field-Programmable Gate Array). Taking the CPLD as an example, the CPLD provides a large number of programmable general-purpose IOs (Input Output). Connect the UART interfaces 21 of each functional board 20 to the CPLD, and then the CPU accesses the register 111 of the CPLD through the first I2C interface 112, writes a register value into the register 111 according to the specific application scenario to select the corresponding UART interface 21, and converts the level through the RS232 level conversion chip. This embodiment makes full use of the IO resources and flexibility of the CPLD to realize the debugging interface management and switching for the multi-board debugging and operation and maintenance scenario.

[0053] As Figure 2 shown, in another embodiment, the switch unit 101 includes several groups of transmission switches ST and reception switches SR, for example, several transmission switches STL0 ~ST L7 、ST F0 ~ST F5 and several receiving switches SR L0 ~SR L7 、SR F0 ~SR F5 ,(For the convenience of description, ST refers to the sending switch and SR refers to the receiving switch). The debugging interface 13 includes a receiving adjustment interface 132 and a sending debugging interface 131. The receiving switch SR is connected between the UART interface 21 and the receiving adjustment interface 132, and the sending switch ST is connected between the UART interface 21 and the sending adjustment interface 131. It can be understood that the switch unit 101 (including the sending switch ST L0 ~ST L7 、ST F0 ~ST F5 and several receiving switches SR L0 ~SR L7 、SR F0 ~SR F5 ) is a digital switch, and the register value is used to control the corresponding sending switch ST and receiving switch SR to turn on or off.

[0054] Specifically, the switch unit 101 includes 14 receiving switches SR L0 ~SR L7 、SR F0 ~SR F5 and 14 sending switches ST L0 ~ST L7 、ST F0 ~ST F5 , each receiving switch SR L0 ~SR L7 、SR F0 ~SR F5 corresponds to a UART interface 21 of a function board 20 respectively, and each receiving switch SR L0 ~SR L7 、SR F0 ~SR F5 is connected to the receiving adjustment interface 132, and each sending switch ST L0 ~ST L7 、ST F0 ~ST F5 corresponds to a UART interface 21 of a function board 20, and each sending switch ST L0 ~ST L7 、ST F0 ~ST F5All are connected to the transmission adjustment interface 131, that is, each UART interface 21 corresponds to a group of receiving switches SR and transmission switches ST, that is, each UART interface 21 is simultaneously connected to a receiving switch SR and a transmission switch ST, so as to realize two-way communication between the UART interface 21 and the outside of the multi-board frame switch system during the debugging process.

[0055] When the CPU writes the register value 110 into the register 111, the receiving switch SR corresponding to the line card [7] L7 and the transmission switch ST L7 are turned on under the control of the register 111 (it can be understood that the receiving switches SR corresponding to the other function boards L0 ~SR L6 、SR F0 ~SR F5 as well as the transmission switches ST L0 ~ST L6 、ST F0 ~ST F5 remain off), so that the UART interface 21 corresponding to the line card [7] is conducted with the debugging interface 13, and the corresponding UART signal SC_LC[7]_TXD is transmitted through the transmission debugging interface 131, and the corresponding UART signal SC_LC[7]_RXD is received through the receiving debugging interface 132.

[0056] As Figure 3 shown, another embodiment of the present invention provides a UART interface gating method, which is applied to a multi-board frame switch system. The multi-board frame switch system includes a main control board 10 and several function boards 20. The function board 20 includes a UART interface 21. The main control board 10 includes a programmable logic device 11 and a CPU. The programmable logic device 11 includes a register 111, a first I2C interface 112, a switch unit, and a debugging interface.

[0057] Specifically, the UART interface gating method includes:

[0058] S301, accessing the register 111 through the CPU based on the first I2C interface 112 and realizing the read and write control of the register 111;

[0059] S302, gating the corresponding UART interface 21 and the debugging interface through the switch unit based on the read and write control of the register 111.

[0060] The UART interface gating method in this embodiment further includes: configuring the first I2C interface 112 through the CPLD, and opening the relevant permissions for controlling the register 111 through the first I2C interface 112. The CPU configures the second I2C interface to be communicatively connected to the first I2C interface 112. The CPU accesses the mapping table of the register 111 and writes the register value. The switch unit 101 controls the conduction between the corresponding UART interface 21 and the debug interface based on the register value, realizing the gating of the corresponding UART interface 21 according to the specific application scenario. After level conversion through the RS232 level conversion chip 12, it is connected to an external UART interface debugging device (such as a control panel) through the RJ45 connector 30. This embodiment makes full use of the IO resources and flexibility of the CPLD to realize the management and switching of the debug interfaces in the multi-board debugging and operation and maintenance scenarios, and finally realizes the access to the debugging and operation and maintenance interfaces of each line card and network board through the RJ45 connector 30.

[0061] The present invention utilizes the IO resources of the programmable logic device, manages and switches the switch unit through registers, and realizes the gating control of the UART interfaces of each functional board in the multi-board debugging and operation and maintenance scenarios;

[0062] The present invention controls the registers of the programmable logic device through the I2C interface. The control logic is general and concise, and shares relevant resources with other I2C threads, without occupying the CPU resources alone, saving the GPIO resources of the CPU and avoiding waste of CPU resources.

[0063] The present invention adopts digital switches, which have obvious advantages compared with analog switches. The bandwidth of the CPLD IO is usually above 100MHz, and the IO driving ability is adjustable, which can ensure better signal edges. The UART signal levels corresponding to different UART interfaces may be different, such as 1.8V, 2.5V, 3.3V, etc., and the CPLD supports multiple level designs and can be flexibly adapted to different scenarios.

[0064] Figure 4 The hardware structure diagram of the electronic device according to the embodiment of the present specification is shown. As Figure 4 shown, the electronic device 40 may include at least one processor 41, a memory 42 (such as a non-volatile memory), a memory 43, and a communication interface 44, and at least one processor 41, the memory 42, the memory 43, and the communication interface 44 are connected together via a bus 45. At least one processor 41 executes at least one computer-readable instruction stored or encoded in the memory 42.

[0065] It should be understood that the computer-executable instructions stored in the memory 42, when executed, cause at least one processor 41 to perform the various operations and functions described above in the various embodiments of the present specification in combination with Figures 1 to 3 the description.

[0066] In the embodiments of this specification, the electronic device 40 may include, but is not limited to: personal computers, server computers, workstations, desktop computers, laptop computers, notebook computers, mobile electronic devices, smart phones, tablet computers, cellular phones, personal digital assistants (PDAs), handheld devices, messaging devices, wearable electronic devices, consumer electronic devices, and so on.

[0067] According to one embodiment, a program product such as a machine-readable medium is provided. The machine-readable medium may have instructions (i.e., the elements implemented in software as described above), which when executed by the machine, cause the machine to perform the various operations and functions described above in connection with Figures 1 to 3 the various embodiments of this specification. Specifically, a system or device equipped with a readable storage medium may be provided, on which software program code for implementing the functions of any one of the above-described embodiments is stored, and cause a computer or processor of the system or device to read and execute the instructions stored in the readable storage medium.

[0068] In this case, the program code read from the readable medium itself can implement the functions of any one of the above-described embodiments. Therefore, the machine-readable code and the readable storage medium storing the machine-readable code constitute a part of this specification.

[0069] Examples of the readable storage medium include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program code may be downloaded from a server computer or a cloud via a communication network.

[0070] Those skilled in the art should understand that the various embodiments disclosed above can be variously deformed and modified without departing from the essence of the invention. Therefore, the protection scope of this specification should be defined by the appended claims.

[0071] It should be noted that not all steps and units in the above-mentioned various processes and system structure diagrams are necessary, and some steps or units can be ignored according to actual needs. The execution order of the steps is not fixed and can be determined as needed. The device structures described in the above-mentioned various embodiments can be physical structures or logical structures. That is, some units may be implemented by the same physical entity, or some units may be implemented separately by multiple physical entities, or some components in multiple independent devices may be jointly implemented.

[0072] In the above embodiments, the hardware units or modules can be implemented mechanically or electrically. For example, a hardware unit, module, or processor can include permanent dedicated circuitry or logic (such as a dedicated processor, FPGA, or ASIC) to perform the corresponding operations. The hardware unit or processor can also include programmable logic or circuitry (such as a general-purpose processor or other programmable processor), which can be temporarily configured by software to perform the corresponding operations. The specific implementation method (mechanical, or dedicated permanent circuitry, or temporarily configured circuitry) can be determined based on cost and time considerations.

[0073] The specific embodiments described above in conjunction with the accompanying drawings describe exemplary embodiments, but do not represent all embodiments that can be implemented or fall within the scope of the claims. The term "exemplary" used throughout this specification means "serving as an example, instance, or illustration" and does not mean "preferred" or "advantageous" over other embodiments. For the purpose of providing an understanding of the described technology, the specific embodiments include specific details. However, the technology can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0074] The foregoing description of the content of this application is provided to enable any ordinary person skilled in the art to implement or use the content of this application. Various modifications to the content of this application will be obvious to those of ordinary skill in the art, and the general principles corresponding to this application can also be applied to other variations without departing from the scope of protection of the content of this application. Therefore, the content of this application is not limited to the examples and designs described herein, but is consistent with the broadest scope that conforms to the principles and novel features disclosed herein.

Claims

1. A multi-board chassis switch system, comprising a main control board and a plurality of functional boards, wherein the functional board includes a UART interface, characterized in that, The main control board includes a programmable logic device and a CPU. The programmable logic device includes registers, a first I2C interface, a switching unit, and a debugging interface; The CPU is communicatively connected to the first I2C interface. The first I2C interface is connected to the registers. The switching unit is connected between the UART interface and the debugging interface. The CPU realizes the read and write control of the registers through the I2C interface to trigger the corresponding switching unit to be selected and turned on, so as to control the conduction between the corresponding UART interface and the debugging interface.

2. The multi-board chassis switch system according to claim 1, wherein The registers include a mapping table representing the corresponding relationship between the register values and the UART interface. The CPU is used to access the mapping table through the first I2C interface and write register values into the registers based on the mapping table. The registers are used to trigger the corresponding switching unit to be selected and turned on based on the register values.

3. The multi-board chassis switch system according to claim 1, wherein The multi-board frame switch system further includes a backplane, and the backplane is connected between the switching unit and the UART interface.

4. The multi-board frame switch system according to claim 1, wherein, The main control board further includes a level conversion unit and a connector located outside the main control board. The level conversion unit is connected between the debugging interface and the connector.

5. The multi-board frame switch system according to claim 1, characterized in that, The programmable logic device includes a CPLD or an FPGA.

6. The multi-board chassis switch system according to claim 1, characterized in that The CPU includes a second I2C interface, and the second I2C interface and the first I2C interface are communicatively connected through a serial clock line and a serial data line.

7. The multi-board chassis switch system according to claim 1, wherein The switching unit includes several groups of receiving switches and sending switches. The debugging interface includes a receiving adjustment interface and a sending debugging interface; The receiving switches are connected between the UART interface and the receiving adjustment interface, and the sending switches are connected between the UART interface and the sending adjustment interface.

8. A UART interface gating method is applied to a multi-board frame switch system. The multi-board frame switch system includes a main control board and a plurality of functional boards, and the functional boards include UART interfaces. It is characterized in that, The main control board includes a programmable logic device and a CPU. The programmable logic device includes registers, a first I2C interface, a switching unit, and a debugging interface; The UART interface selection method includes: The CPU accesses the registers based on the first I2C interface and realizes the read and write control of the registers; The corresponding UART interface and debugging interface are selected and turned on by the switching unit based on the read and write control of the registers.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it realizes the UART interface selection method as described in claim 8.

10. A computer-readable medium, characterized in that, The computer-readable medium carries computer-executable instructions, and when the computer-executable instructions are executed by the processor, they are used to realize the UART interface selection method as described in claim 8.

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