Hierarchical TCAM packet parsing and field extraction system based on parsing graph optimization

Abstract

This invention discloses a hierarchical TCAM message parsing and field extraction system based on parse graph optimization, relating to the field of communication technology. It includes: a software calculation and configuration module for performing graph topology optimization on the protocol parsing graph to generate multiple independent parsing subgraphs; generating a hardware resource configuration table corresponding to each parsing subgraph based on the key bit set corresponding to each parsing subgraph, and distributing the hardware resource configuration table to the key bit extraction unit, mapping table matching unit, flow classification module, and field extraction module on the hardware side, thereby configuring the logic structure of the target circuit according to the hardware configuration information and realizing dynamic reconfiguration of the protocol parsing function. This invention decomposes the protocol parsing graph into parsing subgraphs and adopts a multi-level unit fusion architecture at the hardware level to achieve pipelined protocol parsing. Combined with key bit matrix compression technology, it can significantly reduce TCAM storage requirements and effectively solve the timing and storage bottlenecks in large-scale message header parsing.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a hierarchical TCAM message parsing and field extraction system based on analytical graph optimization. Background Technology

[0002] With the rapid development of 5G communication, IoT, and cloud computing technologies, network data traffic is experiencing explosive growth and highly heterogeneous protocol types. Multimodal converged networks are gradually becoming the trend of future network architecture. Multimodal converged networks (such as industrial internet and computing power networks) require underlying devices to have the ability to flexibly parse new protocols, process data at high speed, and be programmable. In this context, programmable switches, as the core component of the network data plane, undertake the important tasks of traffic parsing, forwarding, and processing.

[0003] Traditional network devices typically rely on fixed hardware logic for packet parsing and field extraction. While this approach can provide high throughput, it lacks flexibility and is difficult to adapt to the introduction and changes of new protocols.

[0004] Programmable data plane technology based on the P4 (Programming Protocol-independent Packet Processors) language has become the core direction for solving this challenge. In this technology, the programmable parser, as the primary processing unit of the switch, directly determines the overall processing capacity. However, existing programmable parsers still face the following technical bottlenecks:

[0005] (1) The explosion of parsing path combinations and the contradiction of TCAM (Ternary Content Addressable Memory) resources. Current programmable parsers use TCAM to store protocol path rules, but with the increase of protocol complexity, such as tunnel nesting and custom headers, the number of parsing graph paths grows exponentially. Existing programmable parsers achieve protocol compatibility through full path storage, which will cause a lot of TCAM resources to be wasted, which seriously restricts the large-scale deployment of multimodal networks.

[0006] (2) In the scenario of parsing a 2048-bit ultra-long message header, the existing field extraction method adopts a layer-by-layer parsing approach. The parsing depth increases with the increase of protocol complexity, which leads to pipeline stalls, increased storage resource overhead, and affects the overall parsing performance. In addition, existing programmable parsers mostly adopt a fixed field offset matching method, which is difficult to cope with dynamically changing message formats, such as variable-length fields and optional protocol headers, reducing the system's flexibility and adaptability.

[0007] (3) In high-speed network environments, programmable parsers need to complete field extraction and protocol matching within a limited clock cycle. However, existing programmable parsers often require additional parallel parsing units to ensure high throughput, leading to a surge in hardware resource consumption, increased power consumption, and impacting the scalability of FPGAs or ASICs. Furthermore, updating parsing rules requires additional computing resources, further exacerbating the contradiction between throughput and hardware utilization.

[0008] (4) Existing programmable parsers typically rely on a serial parsing method when processing complex messages with multiple protocols, that is, matching and extracting fields sequentially according to the protocol level. This method is prone to increased parsing latency when facing high concurrent traffic and makes it difficult to fully utilize the parallel computing capabilities of the hardware. Although those skilled in the art have attempted to introduce multi-stage pipelines or multiple parsing units, the parsing path dependency problem still exists, resulting in limited parsing throughput and difficulty in meeting the low latency requirements of ultra-high-speed network environments. Summary of the Invention

[0009] To address the aforementioned problems in the existing technology, this invention provides a hierarchical TCAM message parsing and field extraction system based on analytical graph optimization. The technical problem to be solved by this invention is achieved through the following technical solution:

[0010] This invention provides a hierarchical TCAM message parsing and field extraction system based on analytical graph optimization, comprising:

[0011] The software computing configuration module is used to perform graph topology optimization on the protocol parsing graph to generate multiple independent parsing subgraphs; based on the key bit set corresponding to each parsing subgraph, it generates a hardware resource configuration table corresponding to each parsing subgraph, and distributes the hardware resource configuration table to the multi-level extraction mapping module, the flow classification module, and the field extraction module.

[0012] A multi-level extraction mapping module corresponding to multiple parsing subgraphs; a key bit extraction unit in each extraction mapping module is used to obtain a byte data block containing the key bits of the parsing subgraph according to the hardware resource configuration table, separate the key bits from it, and aggregate the key bits of all parsing subgraphs using a first programmable cross switch, and output the formed key bit set to the mapping table matching unit in that extraction mapping module.

[0013] The mapping table matching unit in each level of the extraction mapping module is used to use the key bit set as an index address and identify the protocol parsing path corresponding to each parsing subgraph based on the index address.

[0014] The flow classification module is used to integrate the protocol parsing paths corresponding to all parsing subgraphs, generate a complete protocol parsing path topology, input the key bit set of all parsing subgraphs as a joint index into the TCAM action table, and combine the complete protocol parsing path topology to determine the specific fields to be extracted from the current data packet from the external physical access port.

[0015] The field extraction module is used to locate the physical offset and length of a specific field from the current data packet according to the field extraction instruction, and to route the specific field to the designated storage area of ​​PHV through the second programmable cross switch.

[0016] In one embodiment of the present invention, the software computing configuration module includes an analytical graph optimization unit and a key bit selection unit;

[0017] The analytical graph optimization unit is used to perform graph topology optimization on the protocol analytical graph constructed based on P4 code using a multi-subgraph partitioning algorithm to generate multiple independent analytical subgraphs.

[0018] The key bit selection unit is used to locate the corresponding key bit set according to the structural features of each parsing subgraph, and generate a hardware resource configuration table corresponding to each parsing subgraph according to the physical location of each key bit in the key bit set and the semantic attributes of the nodes in the parsing subgraph corresponding to each key bit; and distribute the hardware resource configuration table to the key bit extraction unit, the mapping table matching unit, the stream classification module and the field extraction module through the software and hardware interface.

[0019] In one embodiment of the present invention, the parsing graph optimization unit is specifically used to perform graph topology optimization on the protocol parsing graph constructed based on P4 code using a multi-subgraph partitioning algorithm to obtain multiple independent parsing subgraphs, traverse all paths in each parsing subgraph, and generate bit string encoding corresponding to each path according to preset rules.

[0020] The key bit selection unit is specifically used to retain the original values ​​of the core flag bits that identify the protocol hierarchy inheritance relationship in the bit string encoding, replace the remaining non-key bits with wildcards X to generate original bit strings; by filling in wildcards X, the length of each original bit string is made consistent to form a level 1 bit string matrix; sequentially remove identical columns, ambiguous columns and duplicate columns from the level 1 bit string matrix to generate a compressed level 2 bit string matrix; based on the information entropy evaluation algorithm, quantify the information contribution of each bit in the original bit string to path differentiation; based on a greedy iteration strategy, remove low-discrimination bits with information contribution below a first preset threshold from the level 2 bit strings until the remaining bits can uniquely identify all paths or reach the theoretical minimum number of bits, to obtain the key bit set of the parsing subgraph.

[0021] In one embodiment of the present invention, the analytical graph optimization unit generates a plurality of mutually independent analytical subgraphs according to the following steps:

[0022] Calculate the in-degree, out-degree, and total degree of each vertex in the protocol parse graph, and determine the vertex with the highest connection density in the protocol parse graph;

[0023] A topologically equivalent replica node is generated for the maximum degree vertex and edge attributes are assigned. Based on the semantic attributes, an edge separation operation is performed on the maximum degree vertex and the replica node to separate the incoming and outgoing edges of the maximum degree vertex and the replica node, resulting in multiple parse subgraphs.

[0024] Update the vertex degree, vertex set, and edge set in each parse subgraph, and verify the segmentation status of the parse subgraph using a connectivity detection algorithm. If there are no shared edges between the parse subgraphs and the vertex size of each parse subgraph meets the second preset threshold, it is determined to be a valid segmentation. Otherwise, the parse subgraphs that have not been effectively segmented are further segmented using a community detection algorithm.

[0025] In one embodiment of the present invention, the key bit extraction unit in each level of the extraction mapping module is specifically used to obtain byte data blocks containing the key bits at the byte level coarse-grained level according to the physical location of the key bits of the parsed subgraph in the received hardware resource configuration table, further separate the key bits from the byte data blocks at the bit level fine-grained level, and aggregate the key bits of all parsed subgraphs using a first programmable cross switch, and output the formed key bit set to the mapping table matching unit in that level of the extraction mapping module.

[0026] In one embodiment of the present invention, the key bit extraction unit includes: a byte address extraction subunit and a bit address extraction subunit;

[0027] The byte address extraction subunit is used to strip the lower 3 bits of the address of each key bit based on the shift register parameters provided by the hardware resource configuration table, generate a byte-aligned physical address, and extract the byte data block containing the key bit according to the physical address.

[0028] The bit address extraction subunit is used to perform bit plane decomposition operation on the byte data block, extract the key bits specified by the mask from the byte data block through a combination of bit mask and shifter logic; aggregate the key bits of all parsed subgraphs using a first programmable cross switch, and output the resulting key bit set to the mapping table matching unit in the extraction mapping module at this level.

[0029] In one embodiment of the present invention, the key bit extraction unit further includes an arbitrator;

[0030] The arbitrator is used to sort and schedule conflicting key bits based on the TCAM rule priority field when key bits of multiple parse subgraphs are located in the same byte data block.

[0031] In one embodiment of the present invention, the mapping table matching unit in each level of extraction mapping module includes a heterogeneous TCAM storage block, wherein the heterogeneous TCAM storage block stores the path in the parsing subgraph corresponding to the level of extraction mapping module;

[0032] The mapping table matching unit is specifically used to use the key bit set as an index address, input it into the heterogeneous TCAM storage block for matching, and obtain the protocol parsing path corresponding to the parsing subgraph.

[0033] In one embodiment of the present invention, the stream classification module includes a matching unit and a TCAM unit;

[0034] The matching unit is used to aggregate the protocol parsing paths corresponding to each parsing subgraph according to the preset weight of the protocol layer to generate a complete protocol parsing path topology; input the joint index into the heterogeneous TCAM storage block, match it with the complete protocol parsing path topology to obtain the unique path identifier of the protocol parsing graph, and obtain the relevant information of the specific field of the path corresponding to the unique path identifier in the current data packet through the RAM address mapping table.

[0035] The TCAM unit is used to predict the next-hop path based on the relevant information of the specific field and to preload the extraction instruction of the unique path identifier.

[0036] In one embodiment of the present invention, the stream classification module further includes a RAM unit, which stores field extraction instructions corresponding to all paths in each parsing subgraph;

[0037] The field extraction module includes: a field extraction engine and a structured metadata output unit;

[0038] The field extraction engine is used to locate the physical offset and length of a specific field in the current data packet according to the field extraction instruction, and extract the specific field.

[0039] The structured metadata output unit is used to generate a protocol-independent standardized metadata structure based on the specific field, and to route the standardized metadata structure to a designated storage area of ​​PHV in PHV format through the second programmable cross switch.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] This invention provides a hierarchical TCAM message parsing system based on analytical graph optimization. Structurally, it can be divided into a software side, a hardware side, a software / hardware interface, and an external physical access port. The software side includes a software computing and configuration module, which performs graph topology optimization on the protocol parsing graph, generating multiple independent parsing subgraphs. Based on the key bit set corresponding to each parsing subgraph, it generates a hardware resource configuration table for each subgraph and distributes the hardware resource configuration table to the key bit extraction unit, mapping table matching unit, flow classification module, and field extraction module on the hardware side. This achieves protocol independence on the hardware side, ensuring the identification and parsing of heterogeneous messages in data centers or next-generation multimodal networks. Simultaneously, the software computing and configuration module uses the P4 language to abstract the protocol parsing logic of any scenario into a programmable data plane description model, and achieves deep decoupling of software and hardware based on compiler layered mapping and hardware resource virtualization.

[0042] In addition, the key bit extraction unit and the mapping table matching unit achieve crossbar-like cross-connection capabilities through a multi-level hierarchical extraction strategy and a dynamic bit mapping table. The flow classification module reconstructs the traditional tree / chain flow table structure into a flat classification model through multi-dimensional key bit joint retrieval and rule space plane mapping.

[0043] In summary, this invention decomposes the complex protocol parsing graph into parsing subgraphs using a graph partitioning algorithm. At the hardware level, it adopts a multi-level unit fusion architecture to achieve pipelined protocol parsing. Combined with key bit matrix compression technology, it can significantly reduce TCAM storage requirements and effectively solve the timing and storage bottlenecks in large-scale message header parsing.

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of a hierarchical TCAM message parsing and field extraction system based on analytical graph optimization provided in an embodiment of the present invention;

[0046] Figure 2 This is a protocol parsing diagram provided in an embodiment of the present invention;

[0047] Figure 3 Yes Figure 2 The analytic subgraph obtained after graph topology optimization of the protocol analytic graph shown;

[0048] Figure 4 This is an example diagram of a partial level 1 bit string matrix provided in an embodiment of the present invention;

[0049] Figure 5 This is an example diagram of a two-level bit string matrix provided in an embodiment of the present invention;

[0050] Figure 6 This is an example diagram of the key bit set of the parsing subgraph provided in the embodiments of the present invention. Detailed Implementation

[0051] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0052] Figure 1 This is a schematic diagram of a hierarchical TCAM message parsing and field extraction system based on analytical graph optimization provided in an embodiment of the present invention. Figure 1 As shown, this embodiment of the invention provides a hierarchical TCAM message parsing and field extraction system based on analytical graph optimization. Structurally, the system can be divided into a software side, a hardware side, a software and hardware interface, and an external physical access port. The software side is used to generate hardware configuration information. The software and hardware interface transmits the hardware configuration information to the hardware side. The hardware side configures the logic structure of the target circuit according to the hardware configuration information to realize the dynamic reconstruction of the protocol parsing function.

[0053] Optionally, the software side includes a software computing configuration module, and the hardware side includes a multi-level extraction mapping module, a stream classification module, and a field extraction module.

[0054] In this embodiment, the software calculation configuration module is used to perform graph topology optimization on the protocol parsing graph to generate multiple independent parsing subgraphs; based on the key bit set corresponding to each parsing subgraph, it generates a hardware resource configuration table corresponding to each parsing subgraph, and distributes the hardware resource configuration table to the multi-level extraction mapping module, the flow classification module, and the field extraction module.

[0055] Figure 2 This is a protocol parsing diagram provided by an embodiment of the present invention. Please refer to [link / reference]. Figure 2 It should be noted that the protocol parse graph is a directed acyclic graph, where each vertex uniquely maps to a network protocol type, such as... Figure 2The diagram shows Ethernet, VLAN (Virtual Local Area Network), IPv4 (Internet Protocol version 4), TCP (Transmission Control Protocol), UDP (User Datagram Protocol), and ICMP (Internet Control Message Protocol). The inheritance relationship between protocols is represented by connectors. Repeated protocols can be distinguished by numeric suffixes, such as VLAN1 and VLAN2. A directed connection from the source node to the destination node is established if and only if the source node's protocol header contains a specific field that points to the destination node's protocol type, and circular dependencies are not allowed.

[0056] The multi-level extraction mapping module corresponds to multiple parsing subgraphs respectively; the key bit extraction unit in each level extraction mapping module is used to obtain the byte data block containing the key bits of the parsing subgraph according to the hardware resource configuration table, separate the key bits from it, and use the first programmable cross switch to aggregate the key bits of all parsing subgraphs, and output the formed key bit set to the mapping table matching unit in the extraction mapping module of that level.

[0057] The mapping table matching unit in each level of the extraction mapping module is used to use the key bit set as an index address to identify the protocol parsing path corresponding to each parsing subgraph based on the index address.

[0058] The flow classification module is used to integrate the protocol parsing paths corresponding to all parsing subgraphs, generate a complete protocol parsing path topology, input the key bit set of all parsing subgraphs as a joint index into the TCAM action table, and combine the complete protocol parsing path topology to determine the specific fields that need to be extracted from the current data packet from the external physical access port.

[0059] The field extraction module is used to locate the physical offset and length of a specific field from the current data packet according to the field extraction instruction, and to route the specific field to the specified storage area of ​​PHV through the second programmable cross switch.

[0060] PHV (Packet Header Vector) is a core data structure in the network programmable data plane. It is used to uniformly carry the field information extracted from the packet header and the processing metadata in the packet processing pipeline. When the current data packet enters the processing pipeline, the parser parses the packet header layer by layer according to the protocol specification and stores the key fields of each layer in the PHV in a structured way to form a complete context description vector.

[0061] In this embodiment, the software calculation configuration module includes an analytical graph optimization unit and a key bit selection unit;

[0062] The analytic graph optimization unit is used to perform graph topology optimization on the protocol analytic graph built based on P4 code using a multi-subgraph partitioning algorithm, generating multiple independent analytic subgraphs;

[0063] The key bit selection unit is used to locate the corresponding key bit set according to the structural features of each parse subgraph, and generate the hardware resource configuration table corresponding to each parse subgraph according to the physical location of each key bit in the key bit set and the semantic attributes of the nodes in the parse subgraph corresponding to each key bit; the hardware resource configuration table is distributed to the key bit extraction unit, the mapping table matching unit, the stream classification module and the field extraction module through the software and hardware interface.

[0064] Furthermore, the parse graph optimization unit is specifically used to perform graph topology optimization on the protocol parse graph constructed based on P4 code using a multi-subgraph partitioning algorithm, resulting in multiple independent parse subgraphs. It then traverses all paths in each parse subgraph and generates a bit string encoding corresponding to each path according to preset rules. It should be understood that P4 (Programming Protocol-independent Packet Processors) is a high-level programming language used to define the behavior of the network data plane. Its core goal is to implement protocol-independent packet processing logic programming. By abstracting the underlying hardware details, P4 enables devices such as switching chips, FPGAs, or smart network interface cards to implement efficient and reconfigurable packet processing pipelines through software programming.

[0065] For example, the analytic graph optimization unit generates multiple independent analytic subgraphs according to the following steps:

[0066] S1. Calculate the in-degree, out-degree, and total degree of each vertex in the protocol parse graph, and determine the vertex with the highest connection density in the protocol parse graph.

[0067] Here, "degree" refers to the number of edges directly connected to a node, "out-degree" refers to the number of edges that a node connects outwards, and "in-degree" refers to the number of edges that a node connects inwards from the outside.

[0068] S2. Generate topologically equivalent replica nodes for the maximum degree vertex and assign edge attributes. Then, perform edge separation operations on the maximum degree vertex and replica nodes based on semantic attributes to separate the incoming and outgoing edges of the maximum degree vertex and replica nodes, resulting in multiple parse subgraphs.

[0069] S3. Update the vertex degree, vertex set, and edge set in each parse subgraph, and verify the segmentation status of the parse subgraph using a connectivity detection algorithm. If there are no shared edges between the parse subgraphs and the vertex size of each parse subgraph meets the second preset threshold, it is determined to be a valid segmentation. Otherwise, the parse subgraphs that have not been effectively segmented are further segmented using a community detection algorithm.

[0070] Figure 3 Yes Figure 2 The illustrated protocol parsing graph is the parse subgraph obtained after graph topology optimization. Please refer to... Figures 2-3 As you can see, Figure 2 The protocol parsing graph shown contains 3×3=9 paths, and the protocol parsing graph is divided into: Figure 3 The two analytic subgraphs shown reduce the number of paths from 9 to 3 + 3 = 6.

[0071] Figure 4 This is an example diagram of a partial level 1 bit string matrix provided in an embodiment of the present invention. Figure 5 This is an example diagram of a two-level bit string matrix provided in an embodiment of the present invention. Figure 6 This is an example diagram of the key bit set of the parsed subgraph provided in this embodiment of the invention. In this embodiment, the key bit selection unit is specifically used to retain the original values ​​of the core flag bits that identify the protocol hierarchy inheritance relationship in the bit string encoding, and replace the remaining non-key bits with wildcards X, generating a result such as... Figure 4 The original bit string shown; then, as... Figure 5 As shown, by padding with wildcards X, the lengths of all original bit strings are made consistent, forming a level 1 bit string matrix. Further, identical columns, ambiguous columns, and duplicate columns are sequentially removed from the level 1 bit string matrix to generate a compressed level 2 bit string matrix. Based on the information entropy evaluation algorithm, the information contribution of each bit in the original bit strings to path differentiation is quantified. Based on a greedy iterative strategy, low-discrimination bits with information contribution below a first preset threshold are removed from the level 2 bit strings until the remaining bits can uniquely identify all paths or reach the theoretical minimum number of bits, resulting in... Figure 6 The set of key bits in the analytic subgraph shown.

[0072] The key bit extraction unit in each extraction mapping module is specifically used to obtain byte data blocks containing key bits at the byte level coarse-grained level according to the physical location of key bits in the parsed subgraph of the received hardware resource configuration table, further separate key bits from the byte data blocks at the bit level fine-grained level, and aggregate the key bits of all parsed subgraphs using the first programmable cross switch, and output the formed key bit set to the mapping table matching unit in the extraction mapping module of that level.

[0073] Optionally, the key bit extraction unit includes: a byte address extraction subunit and a bit address extraction subunit;

[0074] The byte address extraction subunit is used to strip the lower 3 bits of the address of each key bit based on the shift register parameters provided by the hardware resource configuration table, generate a byte-aligned physical address, and extract the byte data block containing the key bit according to the physical address.

[0075] The bit address extraction subunit is used to perform bit-plane decomposition operations on the byte data block. It extracts the key bits specified by the mask from the byte data block through a combination of bit mask and shifter logic. It aggregates the key bits of all parsed subgraphs using the first programmable cross switch and outputs the resulting key bit set to the mapping table matching unit in the extraction mapping module at this level.

[0076] In other embodiments of this application, the key bit extraction unit further includes an arbitrator;

[0077] The arbiter is used to sort and schedule conflicting critical bits based on the TCAM rule priority field when critical bits of multiple parse subgraphs are located in the same byte data block.

[0078] The mapping table matching unit in each level of the extraction mapping module includes a heterogeneous TCAM storage block, which stores the path in the parse subgraph corresponding to that level of the extraction mapping module;

[0079] The mapping table matching unit is specifically used to use the key bit set as an index address, input it into the heterogeneous TCAM storage block for matching, and obtain the protocol parsing path corresponding to the parsing subgraph.

[0080] Furthermore, the flow classification module includes a matching unit and a TCAM unit;

[0081] The matching unit is used to aggregate the protocol parsing paths corresponding to each parsing subgraph according to the preset weight of the protocol layer to generate a complete protocol parsing path topology; the composite index is input into the heterogeneous TCAM storage block and matched with the complete protocol parsing path topology to obtain the unique path identifier of the protocol parsing graph, and the relevant information of the specific field of the path corresponding to the unique path identifier in the current data packet is obtained through the RAM address mapping table.

[0082] The TCAM unit is used to predict the next-hop path based on information related to specific fields and to preload the extraction instructions for the unique path identifier.

[0083] The stream classification module also includes a RAM unit, which stores field extraction instructions corresponding to all paths in each parse subgraph;

[0084] The field extraction module includes: a field extraction engine and a structured metadata output unit;

[0085] The field extraction engine is used to locate the physical offset and length of a specific field in the current data packet according to the field extraction instructions, and extract the specific field.

[0086] The structured metadata output unit is used to generate a protocol-independent standardized metadata structure based on specific fields, and routes the standardized metadata structure to the designated storage area of ​​PHV in PHV format through a second programmable cross switch.

[0087] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0088] This invention provides a hierarchical TCAM message parsing system based on analytical graph optimization. Structurally, it can be divided into a software side, a hardware side, a software / hardware interface, and an external physical access port. The software side includes a software computing and configuration module, which performs graph topology optimization on the protocol parsing graph, generating multiple independent parsing subgraphs. Based on the key bit set corresponding to each parsing subgraph, it generates a hardware resource configuration table for each subgraph and distributes the hardware resource configuration table to the key bit extraction unit, mapping table matching unit, flow classification module, and field extraction module on the hardware side. This achieves protocol independence on the hardware side, ensuring the identification and parsing of heterogeneous messages in data centers or next-generation multimodal networks. Simultaneously, the software computing and configuration module uses the P4 language to abstract the protocol parsing logic of any scenario into a programmable data plane description model, and achieves deep decoupling of software and hardware based on compiler layered mapping and hardware resource virtualization.

[0089] In addition, the key bit extraction unit and the mapping table matching unit achieve crossbar-like cross-connection capabilities through a multi-level hierarchical extraction strategy and a dynamic bit mapping table. The flow classification module reconstructs the traditional tree / chain flow table structure into a flat classification model through multi-dimensional key bit joint retrieval and rule space plane mapping.

[0090] In summary, this invention decomposes the complex protocol parsing graph into parsing subgraphs using a graph partitioning algorithm. At the hardware level, it adopts a multi-level unit fusion architecture to achieve pipelined protocol parsing. Combined with key bit matrix compression technology, it can significantly reduce TCAM storage requirements and effectively solve the timing and storage bottlenecks in large-scale message header parsing.

[0091] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0092] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0093] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A hierarchical TCAM message parsing and field extraction system based on analytical graph optimization, characterized in that, include: The software computation and configuration module is used to perform graph topology optimization on the protocol parsing graph and generate multiple independent parsing subgraphs. The key bit set corresponding to each parsing subgraph is obtained by using key bit matrix compression technology; based on the key bit set corresponding to each parsing subgraph, a hardware resource configuration table corresponding to each parsing subgraph is generated, and the hardware resource configuration table is distributed to the multi-level extraction mapping module, the stream classification module, and the field extraction module; A multi-level extraction mapping module corresponding to multiple parsing subgraphs; a key bit extraction unit in each extraction mapping module is used to obtain a byte data block containing the key bits of the parsing subgraph according to the hardware resource configuration table, separate the key bits from it, and aggregate the key bits of all parsing subgraphs using a first programmable cross switch, and output the formed key bit set to the mapping table matching unit in that extraction mapping module. The mapping table matching unit in each level of the extraction mapping module is used to use the key bit set as an index address and identify the protocol parsing path corresponding to each parsing subgraph based on the index address. The flow classification module is used to integrate the protocol parsing paths corresponding to all parsing subgraphs, generate a complete protocol parsing path topology, input the key bit set of all parsing subgraphs as a joint index into the TCAM action table, and combine the complete protocol parsing path topology to determine the specific fields to be extracted from the current data packet from the external physical access port. The field extraction module is used to locate the physical offset and length of a specific field from the current data packet according to the field extraction instruction, and to route the specific field to the designated storage area of ​​PHV through the second programmable cross switch.

2. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 1, characterized in that, The software computation configuration module includes an analytical graph optimization unit and a key bit selection unit; The analytical graph optimization unit is used to perform graph topology optimization on the protocol analytical graph constructed based on P4 code using a multi-subgraph partitioning algorithm to generate multiple independent analytical subgraphs. The key bit selection unit is used to locate the corresponding key bit set according to the structural features of each parsing subgraph, and generate a hardware resource configuration table corresponding to each parsing subgraph according to the physical location of each key bit in the key bit set and the semantic attributes of the nodes in the parsing subgraph corresponding to each key bit; and distribute the hardware resource configuration table to the key bit extraction unit, the mapping table matching unit, the stream classification module and the field extraction module through the software and hardware interface.

3. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 2, characterized in that, The analytical graph optimization unit is specifically used to perform graph topology optimization on the protocol analytical graph constructed based on P4 code using a multi-subgraph partitioning algorithm to obtain multiple independent analytical subgraphs, traverse all paths in each analytical subgraph, and generate bit string encoding corresponding to each path according to preset rules. The key bit selection unit is specifically used to retain the original values ​​of the core flag bits that identify the protocol hierarchy inheritance relationship in the bit string encoding, replace the remaining non-key bits with wildcards X to generate original bit strings; by filling in wildcards X, the length of each original bit string is made consistent to form a level 1 bit string matrix; sequentially remove identical columns, ambiguous columns and duplicate columns from the level 1 bit string matrix to generate a compressed level 2 bit string matrix; based on the information entropy evaluation algorithm, quantify the information contribution of each bit in the original bit string to path differentiation; based on a greedy iteration strategy, remove low-discrimination bits with information contribution below a first preset threshold from the level 2 bit strings until the remaining bits can uniquely identify all paths or reach the theoretical minimum number of bits, to obtain the key bit set of the parsing subgraph.

4. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 3, characterized in that, The analytical graph optimization unit generates multiple independent analytical subgraphs according to the following steps: Calculate the in-degree, out-degree, and total degree of each vertex in the protocol parse graph, and determine the vertex with the highest connection density in the protocol parse graph; A topologically equivalent replica node is generated for the maximum degree vertex and edge attributes are assigned. Based on the semantic attributes, an edge separation operation is performed on the maximum degree vertex and the replica node to separate the incoming and outgoing edges of the maximum degree vertex and the replica node, resulting in multiple parse subgraphs. Update the vertex degree, vertex set, and edge set in each parse subgraph, and verify the segmentation state of the parse subgraph using a connectivity detection algorithm; If there are no shared edges between the parse subgraphs and the vertex size of each parse subgraph meets the second preset threshold, it is determined to be a valid segmentation; otherwise, the community detection algorithm is used to further segment the parse subgraphs that have not been effectively segmented.

5. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 1, characterized in that, The key bit extraction unit in each level of the extraction mapping module is specifically used to obtain byte data blocks containing the key bits at the byte level coarse-grained level according to the physical location of the key bits of the parsed subgraph in the received hardware resource configuration table, further separate the key bits from the byte data blocks at the bit level fine-grained level, and aggregate the key bits of all parsed subgraphs using the first programmable cross switch, and output the formed key bit set to the mapping table matching unit in the extraction mapping module at that level.

6. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 5, characterized in that, The key bit extraction unit includes: a byte address extraction subunit and a bit address extraction subunit; The byte address extraction subunit is used to strip the lower 3 bits of the address of each key bit based on the shift register parameters provided by the hardware resource configuration table, generate a byte-aligned physical address, and extract the byte data block containing the key bit according to the physical address. The bit address extraction subunit is used to perform bit plane decomposition operation on the byte data block, extract the key bits specified by the mask from the byte data block through a combination of bit mask and shifter logic; aggregate the key bits of all parsed subgraphs using a first programmable cross switch, and output the resulting key bit set to the mapping table matching unit in the extraction mapping module at this level.

7. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 6, characterized in that, The key bit extraction unit also includes an arbitrator; The arbitrator is used to sort and schedule conflicting key bits based on the TCAM rule priority field when key bits of multiple parse subgraphs are located in the same byte data block.

8. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 1, characterized in that, The mapping table matching unit in each level of the extraction mapping module includes a heterogeneous TCAM storage block, which stores the path in the parsing subgraph corresponding to that level of the extraction mapping module; The mapping table matching unit is specifically used to use the key bit set as an index address, input it into the heterogeneous TCAM storage block for matching, and obtain the protocol parsing path corresponding to the parsing subgraph.

9. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 8, characterized in that, The stream classification module includes a matching unit and a TCAM unit; The matching unit is used to aggregate the protocol parsing paths corresponding to each parsing subgraph according to the preset weight of the protocol layer to generate a complete protocol parsing path topology; input the joint index into the heterogeneous TCAM storage block, match it with the complete protocol parsing path topology to obtain the unique path identifier of the protocol parsing graph, and obtain the relevant information of the specific field of the path corresponding to the unique path identifier in the current data packet through the RAM address mapping table. The TCAM unit is used to predict the next-hop path based on the relevant information of the specific field and to preload the extraction instruction of the unique path identifier.

10. The hierarchical TCAM message parsing and field extraction system based on analytical graph optimization according to claim 1, characterized in that, The stream classification module also includes a RAM unit, which stores field extraction instructions corresponding to all paths in each parsing subgraph. The field extraction module includes: a field extraction engine and a structured metadata output unit; The field extraction engine is used to locate the physical offset and length of a specific field in the current data packet according to the field extraction instruction, and extract the specific field. The structured metadata output unit is used to generate a protocol-independent standardized metadata structure based on the specific field, and to route the standardized metadata structure to a designated storage area of ​​PHV in PHV format through the second programmable cross switch.

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