Quenching circuit of avalanche diode and imaging system

Abstract

The invention provides a quenching circuit of an avalanche diode and an imaging system.The quenching circuit of the avalanche diode comprises a quenching reset circuit, a time delay circuit, a comparison circuit and a detection control circuit, and the detection control circuit outputs a quenching signal in the output time period of a first level signal of a first clock signal; in the second level signal, namely the reset phase of the quenching circuit, if the avalanche diode is triggered by photons, the comparison circuit or the time delay circuit generates a corresponding first change signal or second change signal; when the detection control circuit detects the first change signal or the second change signal of the comparison circuit or the time-delay circuit, the detection control circuit can judge that the avalanche diode is triggered in the reset stage, at the moment, a quenching signal is output, the quenching reset circuit enters the quenching stage in advance, and the power consumption when the quenching circuit is triggered in the reset stage is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of imaging systems, and particularly relates to a quenching circuit for an avalanche diode and an imaging system. Background Art

[0002] An SPAD (Single photon Avalanche diode) imaging system uses an SPAD array as a light receiver, and obtains the input light intensity by sensing information such as the photon counting rate, thereby realizing imaging.

[0003] Among them, when the SPAD is over-reverse biased, due to the triggering of photons, the SPAD will generate a self-sustaining current. If no suppression measures are taken, the avalanche process will continue until the device is permanently damaged. Therefore, a quenching circuit is needed to suppress the avalanche in time, and then quench the avalanche current. In order to achieve high resolution of the imaging system, the scale of the SPAD array is large, so the quenching circuit is required to have low power consumption characteristics.

[0004] Among them, the quenching circuit works in the quenching stage and the reset stage. In the reset stage, the quenching switch in the quenching circuit is in the conducting state, and there may be photon triggering in the avalanche diode, resulting in a current loop formed between the quenching circuit and the avalanche diode. At this time, the avalanche diode can be simplified as a relatively small load resistor in form, and the quenching transistor is fully conducting, causing a large DC power consumption in the circuit.

[0005] As Figure 1 shown, a conventional quenching circuit is composed of a quenching transistor, a capacitor and a comparator. Assuming that the avalanche diode uses a positive bias voltage, the gate voltage of the quenching transistor is controlled by a clock signal, the comparator compares the anode voltage of the avalanche diode, and outputs a pulse signal. The subsequent signal processing circuit determines information such as the photon counting rate according to the pulse signal and the clock signal, and then determines the image information.

[0006] The quenching circuit works in the quenching stage and the reset stage. As Figure 2 shown, when the avalanche diode is at a positive bias voltage, the quenching period is the low-level period of the clock signal, and the reset period is the high-level period of the clock signal. Assuming that photons trigger the avalanche diode when CK = 0, the circuit enters the quenching stage: at this time, the quenching transistor is turned off, and its function is equivalent to an "infinite" quenching resistor. At this time, the avalanche current charges the parasitic capacitor Cpar, and VA0 quickly rises to Vex, so that the voltage across the avalanche diode ≤ VBK, thereby realizing rapid quenching. Among them, VBK is the avalanche voltage of the avalanche diode, and Vex is the over-bias voltage of the avalanche diode. Thereafter, during the period when CK remains 0, VA0 remains at Vex, and even if other photons are incident, the avalanche diode cannot be triggered. Therefore, the maximum photon counting rate that the quenching circuit can achieve is the frequency of the clock signal.

[0007] However, as Figure 3 shown, when a photon triggers during the reset phase, since VA0 drops, the voltage across the avalanche diode is higher than VBK. At this time, if a photon is incident, the avalanche diode is triggered. Since the quenching tube is still in the conducting state and has a small on-resistance, the avalanche current of the avalanche diode is not sufficient to increase VA0 to Vex, so the avalanche diode cannot be quenched. At this time, the avalanche diode can be formally simplified to a smaller load resistor, and the quenching tube is fully conducting, resulting in a large DC power consumption in the circuit.

[0008] The maximum duration of the high power consumption is the high-level pulse width of the clock signal. It is not until the clock signal is set to 0 again that the quenching tube turns off, and the avalanche current charges Cpar, increasing VA0 to Vex. This causes the avalanche diode to enter the quenching phase and wait for the next reset.

[0009] When the incident light is strong, the probability of a photon triggering during the reset phase increases. Especially when the array scale of the avalanche diode is large, the problem of high power consumption will be more serious. Summary of the Invention

[0010] The object of the present invention is to provide a quenching circuit for an avalanche diode, aiming to solve the problem of large power consumption existing in the traditional quenching circuit.

[0011] The first aspect of the embodiment of the present invention proposes a quenching circuit for an avalanche diode, including: A bias voltage circuit, connected to the first end of the avalanche diode, and the bias voltage circuit is used to provide a bias voltage; A quenching and reset circuit, connected to the second end of the avalanche diode, and the quenching and reset circuit is used to quench or reset the avalanche diode according to a quenching signal or a reset signal; A delay circuit, used to delay an input first clock signal by a preset duration and output it as a second clock signal, where the first clock signal is alternately composed of a first level signal and a second level signal with opposite levels; A comparison circuit, connected to the second end of the avalanche diode, and the comparison circuit is used to output a third level signal when the input voltage is greater than or equal to a preset threshold voltage, and output a fourth level signal with a level opposite to that of the third level signal when the input voltage is less than the preset threshold voltage; A detection and control circuit, respectively connected to the comparison circuit, the delay circuit, and the quenching and reset circuit, and the detection and control circuit is used for: Output the reset signal during the output period of each of the second level signals, and output the quenching signal when detecting the first change signal generated by the comparison circuit, or when detecting the second change signal generated by the delay circuit and not detecting the second change signal generated by the comparison circuit; Output the quenching signal during the output period of the first level signal, where the first change signal and the second change signal are a rising edge and a falling edge of each other.

[0012] A second aspect of the embodiments of the present invention provides an imaging system, including a pixel array and an image processing circuit. The pixel array includes pixel units arranged in an array, and each pixel unit includes an avalanche diode connected to the quenching circuit of the avalanche diode as described above; The image processing circuit is respectively connected to the quenching circuits of the avalanche diodes, and the image processing circuit is configured to process the photon count rate output by the quenching circuits of the avalanche diodes and determine image information.

[0013] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned quenching circuit of the avalanche diode includes a quenching reset circuit, a delay circuit, a comparison circuit, and a detection control circuit. The detection control circuit outputs the quenching signal during the output period of the first level signal of the first clock signal, so that the quenching circuit works in the quenching stage. Among them, in the second level signal, that is, the reset stage of the quenching circuit, if the avalanche diode is triggered by photons, the comparison circuit or the delay circuit will generate a corresponding first change signal or a second change signal. When the detection control circuit detects the first change signal or the second change signal of the comparison circuit or the delay circuit, it can determine that the avalanche diode is triggered in the reset stage. At this time, the quenching signal is output, so that the quenching reset circuit enters the quenching stage in advance, reducing the power consumption when the quenching circuit is triggered in the reset stage. Description of the Drawings

[0014] Figure 1 Is a circuit schematic diagram of a traditional quenching circuit; Figure 2 Is a first signal waveform schematic diagram of the quenching stage and the reset stage of a traditional quenching circuit; Figure 3 Is a signal waveform schematic diagram of a traditional quenching circuit with photon triggering in the reset stage; Figure 4 Is a signal waveform schematic diagram of a traditional quenching circuit without photon triggering in the reset stage; Figure 5 Is a first signal waveform schematic diagram of the first case of a traditional quenching circuit in the reset stage; Figure 6 Is a first signal waveform schematic diagram of the second case of a traditional quenching circuit in the reset stage; Figure 7 The first structural schematic diagram of the quenching circuit provided by the embodiment of the present invention; Figure 8 The first signal waveform schematic diagram of the quenching circuit provided by the embodiment of the present invention without photon triggering; Figure 9 The first signal waveform schematic diagram of the first situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 10 The second signal waveform schematic diagram of the first situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 11 The first signal waveform schematic diagram of the second situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 12 The second signal waveform schematic diagram of the second situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 13 The third signal waveform schematic diagram of the second situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 14 The fourth signal waveform schematic diagram of the second situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 15 The second signal waveform schematic diagram of the quenching stage and the reset stage of the traditional quenching circuit; Figure 16 The second signal waveform schematic diagram of the first situation in the reset stage of the traditional quenching circuit; Figure 17 The second signal waveform schematic diagram of the second situation in the reset stage of the traditional quenching circuit; Figure 18 The second structural schematic diagram of the quenching circuit provided by the embodiment of the present invention; Figure 19 The second signal waveform schematic diagram of the quenching circuit provided by the embodiment of the present invention without photon triggering; Figure 20 The third signal waveform schematic diagram of the first situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 21 The fifth signal waveform schematic diagram of the second situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 22 The sixth signal waveform schematic diagram of the second situation in the reset stage of the quenching circuit provided by the embodiment of the present invention; Figure 23 The third structural schematic diagram of the quenching circuit provided by the embodiment of the present invention; Figure 24 The third signal waveform diagram of the quenching circuit provided by the embodiment of the present invention without photon triggering; Figure 25 The fourth signal waveform diagram of the quenching circuit provided by the embodiment of the present invention in case 1 during the reset stage; Figure 26 The seventh signal waveform diagram of the quenching circuit provided by the embodiment of the present invention in case 2 during the reset stage; Figure 27 The eighth signal waveform diagram of the quenching circuit provided by the embodiment of the present invention in case 2 during the reset stage; Figure 28 The fourth signal waveform diagram of the quenching circuit provided by the embodiment of the present invention without photon triggering; Figure 29 The fifth signal waveform diagram of the quenching circuit provided by the embodiment of the present invention in case 1 during the reset stage; Figure 30 The ninth signal waveform diagram of the quenching circuit provided by the embodiment of the present invention in case 2 during the reset stage; Figure 31 The tenth signal waveform diagram of the quenching circuit provided by the embodiment of the present invention in case 2 during the reset stage; Figure 32 The fourth structural diagram of the quenching circuit provided by the embodiment of the present invention; Figure 33 The first circuit diagram of the quenching circuit provided by the embodiment of the present invention; Figure 34 The second circuit diagram of the quenching circuit provided by the embodiment of the present invention; Figure 35 The third circuit diagram of the quenching circuit provided by the embodiment of the present invention; Figure 36 The circuit diagram of the quenching switch provided by the embodiment of the present invention; Figure 37 The fifth structural diagram of the quenching circuit provided by the embodiment of the present invention; Figure 38 The waveform diagram of the output clock of the quenching circuit provided by the embodiment of the present invention; Figure 39 The structural diagram of the imaging system provided by the embodiment of the present invention.

[0015] Among them, the reference numerals in the figure are: 1. Quenching circuit; 2. Image processing circuit; 10. Quenching reset circuit; 20. Delay circuit; 30. Comparison circuit; 40. Detection control circuit; 50. Bias voltage circuit; 60. Clock generation circuit; 11. Quenching switch; 41. First detection circuit; 42. Second detection circuit; 43. Logic control circuit; 100. Pixel array; 101. Pixel unit; 431. First logic gate circuit; 432. Second logic gate circuit; 433. Third logic gate circuit; SPAD, avalanche diode; M1, quenching transistor; Cpar, capacitor; DFF1, first D flip-flop; DFF2, second D flip-flop; DFF3, third D flip-flop; DFF4, fourth D flip-flop; DFF5, fifth D flip-flop; DFF6, sixth D flip-flop; U1, first inverter; U2, second inverter; U3, third inverter; U4, fourth inverter; U5, buffer; AND1, AND gate; OR1, first OR gate; OR2, second OR gate; CK1, first clock signal; CK2, second clock signal; CK0, output clock of the detection control circuit; VA0, anode voltage of the avalanche diode; VC0, cathode voltage of the avalanche diode; VC1, output signal of the comparison circuit; Q1, output signal of the first detection circuit; Q2, output signal of the second detection circuit. Detailed implementation mode

[0016] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] The terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0018] The quenching circuit of a conventional avalanche diode SPAD is composed of a quenching transistor M1, a capacitor Cpar and a comparator U0. The capacitor Cpar is generally a parasitic capacitor. For example, Figure 1 As shown, assuming that the avalanche diode SPAD uses a positive bias voltage, the gate voltage of the quenching transistor M1 is controlled by the clock signal CK. The comparator U0 compares the anode voltage of the avalanche diode SPAD and outputs a pulse signal. The subsequent image processing circuit 2 determines information such as the photon counting rate based on the pulse signal and the clock signal, and then determines the image information.

[0019] The quenching circuit operates in a quenching stage and a reset stage. As Figure 2 shown, when the avalanche diode SPAD is under a positive bias voltage, the quenching period is the low-level period of the clock signal, and the reset period is the high-level period of the clock signal CK. Assume that a photon triggers the avalanche diode SPAD when CK = 0, and the circuit enters the quenching stage: At this time, the quenching transistor M1 is turned off, which acts as an "infinite" quenching resistor. At this time, the avalanche current charges the parasitic capacitance Cpar, and VA0 rapidly rises to Vex, making the voltage across the avalanche diode SPAD ≤ VBK, thereby achieving rapid quenching. Here, Vex is the over-bias voltage of the avalanche diode SPAD, and VBK is the avalanche voltage of the avalanche diode SPAD. Thereafter, during the period when CK remains 0, VA0 remains at Vex. Even if other photons are incident, the avalanche diode SPAD cannot be triggered. Therefore, the maximum photon counting rate that the quenching circuit can achieve is the frequency of the clock signal.

[0020] However, as Figure 3 shown, if a photon triggers during the reset stage, since VA0 drops, the voltage across the avalanche diode SPAD is higher than VBK. At this time, if a photon is incident, the avalanche diode SPAD is triggered. Since the quenching transistor M1 is still in the conducting state and has a small on-resistance, the avalanche current of the avalanche diode SPAD is not sufficient to increase VA0 to Vex. Therefore, the avalanche diode SPAD cannot be quenched. At this time, the avalanche diode SPAD can be simplified as a smaller load resistor in form, and the quenching transistor M1 is fully conducting, resulting in a large DC power consumption in the circuit.

[0021] The maximum duration of the high power consumption is the high-level pulse width of the clock signal CK. Until the clock signal is set to 0 again, the quenching transistor M1 is turned off, and the avalanche current charges Cpar, increasing VA0 to Vex. This makes the avalanche diode SPAD enter the quenching stage and wait for the next reset.

[0022] When the incident light is strong, the probability of a photon triggering during the reset stage increases. Especially when the array scale of the avalanche diode SPAD is large, the problem of high power consumption will be more serious.

[0023] The first aspect of the embodiment of the present invention proposes a quenching circuit 1 for an avalanche diode SPAD to reduce the power consumption of the quenching circuit 1 and the overall power consumption of the imaging system.

[0024] The avalanche diode SPAD can adopt a positive bias voltage or a negative bias voltage, which is specifically designed according to different circuit structures.

[0025] Among them, taking the avalanche diode SPAD with a positive bias voltage as an example, the cathode of the avalanche diode SPAD is connected to the positive bias voltage, and the anode of the avalanche diode SPAD is connected to the quenching and reset circuit 10. As Figure 4As shown, during the reset phase, when the clock signal is a high-level signal and there is no photon trigger, the anode voltage VA0 of the avalanche diode SPAD decreases. When it drops to the preset threshold voltage Vth, the level of the output signal VA1 of the comparison circuit 30 flips, switching from a low level to a high level. That is, the output signal VA1 of the comparison circuit 30 only has a rising edge, where Vth is the preset threshold voltage.

[0026] During the reset phase, if there is a photon trigger, there may be the following two situations.

[0027] First, as Figure 5 shown, in addition to the rising edge, the output signal VA1 of the comparison circuit 30 also has a falling edge. That is, when there is a photon trigger after the voltage at the second end of the avalanche diode SPAD drops to the preset threshold voltage Vth, the anode voltage VA0 of the avalanche diode SPAD rises. When it rises to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 will generate a falling edge.

[0028] Second, as Figure 6 shown, the voltage at the second end of the avalanche diode SPAD remains high, and the output signal VA1 of the comparison circuit 30 has neither a rising edge nor a falling edge. The reason is that there is a photon trigger before the anode voltage VA0 of the avalanche diode SPAD drops to the preset threshold voltage Vth. Subsequently, the voltage at the second end of the avalanche diode SPAD remains in a state greater than the preset threshold voltage Vth. At this time, the output signal VA1 of the comparison circuit 30 remains at a low level state.

[0029] Or assume that the avalanche diode SPAD is biased with a negative bias voltage. The anode of the avalanche diode SPAD is connected to the negative bias voltage, and the cathode of the avalanche diode SPAD is connected to the quenching and reset circuit 10. As Figure 15 shown, the avalanche diode SPAD is in the quenching phase when the clock signal is high and in the reset phase when it is low.

[0030] During the reset phase, if there is a photon trigger, there may be the following two situations.

[0031] First, as Figure 16 shown, in addition to the falling edge, the output signal VA1 of the comparison circuit 30 also has a rising edge. That is, when there is a photon trigger after the voltage at the second end of the avalanche diode SPAD rises to the preset threshold voltage Vth during the reset phase, the anode voltage VA0 of the avalanche diode SPAD decreases. When it drops to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 will generate a rising edge.

[0032] Second, as Figure 17As shown, the cathode voltage VC0 of the avalanche diode SPAD remains low continuously, and there is neither a rising edge nor a falling edge in the output signal VA1 of the comparison circuit 30. The reason is that there is a photon trigger before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth. Subsequently, the voltage at the second end of the avalanche diode SPAD is maintained at a state less than the preset threshold voltage Vth. At this time, the output signal VA1 of the comparison circuit 30 is maintained at a high level state.

[0033] Therefore, in order to avoid additional power consumption caused by the quenching circuit 1 being triggered during the reset phase, in this embodiment, a quenching circuit 1 for the avalanche diode SPAD is proposed, as Figure 7 or Figure 18 shown, the quenching circuit 1 of the avalanche diode SPAD includes: A bias voltage circuit 50, connected to the first end of the avalanche diode SPAD, and the bias voltage circuit 50 is used to provide a bias voltage; A quenching and reset circuit 10, connected to the second end of the avalanche diode SPAD, and the quenching and reset circuit 10 is used to quench or reset the avalanche diode SPAD according to a quenching signal or a reset signal; A delay circuit 20, used to delay the input first clock signal CK1 by a preset duration and output it as a second clock signal CK2. The first clock signal CK1 is composed of an alternating first level signal and a second level signal with opposite levels; A comparison circuit 30, connected to the second end of the avalanche diode SPAD, and the comparison circuit 30 is used to output a third level signal when the input voltage is greater than or equal to the preset threshold voltage Vth, and output a fourth level signal with a level opposite to that of the third level signal when the input voltage is less than the preset threshold voltage Vth; A detection and control circuit 40, respectively connected to the comparison circuit 30, the delay circuit 20, and the quenching and reset circuit 10. The detection and control circuit 40 is used for: Outputting a reset signal during the output period of each second level signal, and outputting a quenching signal when detecting the first change signal generated by the comparison circuit 30, or when detecting the second change signal generated by the delay circuit 20 and not detecting the second change signal generated by the comparison circuit 30; Outputting a quenching signal during the output period of the first level signal. The first change signal and the second change signal are a rising edge and a falling edge respectively.

[0034] In this embodiment, first, the quenching circuit 1 shown in Figure 7 , that is, the positive bias voltage of the avalanche diode SPAD, will be described.

[0035] As Figure 7As shown, a positive bias voltage is input to the cathode of the avalanche diode SPAD. The anode of the avalanche diode SPAD is connected to the quenching and reset circuit 10 and the comparison circuit 30. The detection control circuit 40 is connected to the output end of the comparison circuit 30 and detects the change signal of the output of the comparison circuit 30. The output signal VA1 of the comparison circuit 30 can be used as the output signal of the quenching circuit 1. The subsequent signal processing circuit can determine the photon counting rate and image information based on the output signal of the quenching circuit 1.

[0036] As Figure 8 shown, the quenching signal and the reset signal are high and low level signals respectively and form the output clock CK0 of the detection control circuit 40. At this time, the second level signal is high level and the first level signal is low level. When the quenching circuit 1 works in the quenching stage, the quenching transistor M1 in the quenching and reset circuit 10 receives the low level quenching signal and turns off. The anode voltage VA0 of the avalanche diode SPAD rises through an upward change and then stabilizes at Vex, and then enters the reset stage. The detection control circuit 40 first outputs a high level reset signal. The quenching transistor M1 of the quenching and reset circuit 10 receives the high level signal and is triggered to conduct. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to drop. When it drops to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 flips, switching from low level to high level. If there is no photon trigger during the reset stage, the voltage of the avalanche diode SPAD will rise until it stabilizes at Vex at the next quenching stage, and the output signal VA1 of the comparison circuit 30 will switch to low level when the voltage of the avalanche diode SPAD rises to the preset threshold voltage Vth at the next quenching stage. In this state, the quenching signal and the reset signal are high and low level signals respectively and form the output clock CK0 of the detection control circuit 40. The output clock CK0 of the detection control circuit 40 has the same high and low level phases as the first clock signal CK1. Among them, Vex is the overbias voltage of the avalanche diode SPAD, and VBK is the avalanche voltage of the avalanche diode SPAD.

[0037] When the above situation one occurs, as Figure 9 shown, that is, during the reset stage, when the anode voltage VA0 of the avalanche diode SPAD is triggered by a photon after dropping to the preset threshold voltage Vth, at this time, the voltage of the avalanche diode SPAD will rise after dropping, resulting in a rising edge and a falling edge in the comparison circuit 30. Among them, the first change signal is the falling edge and the second change signal is the rising edge.

[0038] In this case, as Figure 10As shown, during the output period of the second-level signal, i.e., the reset period, after the reset signal is output, the detection control circuit 40 will detect the falling edge generated by the comparison circuit 30. At this time, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a low-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0039] and as Figure 11 shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching reset circuit 10 switches from a low level to a high level. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to decrease, and when it decreases to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches from a low level to a high level. The duration for the anode voltage VA0 of the avalanche diode SPAD to decrease from Vex to the preset threshold voltage Vth is defined as td1. In this embodiment, the preset duration of the delay of the set delay circuit 20 is td2, where td2 > td1.

[0040] As Figure 12 shown, when the above-mentioned situation two occurs during the reset stage, the voltage at the second end of the avalanche diode SPAD remains high, and the output signal VA1 of the comparison circuit 30 has neither a rising edge nor a falling edge. The reason is that there is a photon trigger before the anode voltage VA0 of the avalanche diode SPAD decreases to the preset threshold voltage Vth. Subsequently, the voltage at the second end of the avalanche diode SPAD maintains a state greater than the preset threshold voltage Vth. At this time, the output signal VA1 of the comparison circuit 30 maintains a low-level state.

[0041] As Figure 13 shown, assuming that during the reset stage, i.e., the output period of the second-level signal of the first clock signal CK1, without photon trigger, the anode voltage VA0 of the avalanche diode SPAD will decrease, and when it decreases to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches to a high level. At this time, the detection control circuit 40 first detects the second change signal, the detection control circuit 40 maintains the output of the reset signal, and controls the quenching reset circuit 10 to maintain the reset state.

[0042] And when the above-mentioned situation two occurs during the reset stage, that is, during the reset stage, there is a photon trigger before the anode voltage VA0 of the avalanche diode SPAD decreases to the preset threshold voltage Vth, resulting in the anode voltage VA0 of the avalanche diode SPAD maintaining a state greater than the preset threshold voltage Vth, and the output signal VA1 of the comparison circuit 30 maintains a low level.

[0043] In this case, as Figure 14 shown, after the detection control circuit 40 outputs a reset signal, it does not detect the second change signal generated by the comparison circuit 30. At the same time, since the phase of the second clock signal CK2 is the same as that of the first clock signal CK1, the detection control circuit 40 can detect the rising edge of the second clock signal CK2. When the rising edge of the second clock signal CK2 is detected, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a low-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0044] At the same time, when entering the quenching stage, that is, when the first clock signal CK1 switches to output a first-level signal, the detection control circuit 40 outputs a quenching signal. The quenching transistor M1 in the quenching reset circuit 10 receives a low-level signal and turns off, and the anode voltage VA0 of the avalanche diode SPAD rises and then stabilizes at Vex after passing through.

[0045] In the reset stage, by detecting the falling edge of the comparison circuit 30 and the rising edge generated by the detection delay circuit 20, it can be detected and judged whether the avalanche diode SPAD is triggered in the reset stage. When it is determined that the avalanche diode SPAD is triggered in the reset stage, a quenching signal is output to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, no path is formed with the avalanche diode SPAD, that is, no power consumption is generated, reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0046] And as Figure 18 shown, the negative bias voltage of the avalanche diode SPAD is described.

[0047] As Figure 18 shown, a negative bias voltage is input to the anode of the avalanche diode SPAD. The cathode of the avalanche diode SPAD is connected to the quenching reset circuit 10 and the comparison circuit 30. At this time, the second-level signal is a low level, and the first-level signal is a high level.

[0048] As Figure 19As shown, the quenching signal and the reset signal are high and low level signals respectively and form the output clock CK0 of the detection control circuit 40. When the quenching circuit 1 operates in the quenching stage, that is, during the output period of the first level signal, the detection control circuit 40 outputs a high-level quenching signal. The quenching transistor M1 in the quenching reset circuit 10 receives the high-level quenching signal and turns off. The cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a downward change, and then enters the reset stage, that is, the output period of the second level signal. The detection control circuit 40 outputs a low-level reset signal. The quenching transistor M1 of the quenching reset circuit 10 receives the low-level signal and is triggered to conduct. At this time, the cathode voltage VC0 of the avalanche diode SPAD starts to rise. When it rises to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 flips, switching from high level to low level. If there is no photon trigger during the reset stage, the voltage of the avalanche diode SPAD will start to drop in the next quenching stage until it stabilizes at 0, and the output signal VA1 of the comparison circuit 30 will switch to high level when the voltage of the avalanche diode SPAD drops to the preset threshold voltage Vth in the next quenching stage. In this state, the high and low level phases of the output clock CK0 of the detection control circuit 40 are the same as those of the first clock signal CK1. Among them, Vex is the stable voltage when the avalanche diode SPAD is reset.

[0049] When the above situation one occurs, such as Figure 20 As shown, that is, during the reset stage, when the cathode voltage VC0 of the avalanche diode SPAD is triggered by photons after rising to the preset threshold voltage Vth, at this time, the voltage of the avalanche diode SPAD will drop after rising, resulting in a falling edge and a rising edge in the comparison circuit 30. Among them, the first change signal is the rising edge, and the second change signal is the falling edge.

[0050] In this case, such as Figure 20 As shown, during the output period of the second level signal, that is, the reset period, after the reset signal is output, the second level signal is low level. The detection control circuit 40 will detect the rising edge generated by the comparison circuit 30. At this time, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a high-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD quickly drops to 0, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0051] And such as Figure 21As shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching and reset circuit 10 switches from a high level to a low level. At this time, the cathode voltage VC0 of the avalanche diode SPAD starts to rise, and when it rises to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches from a high level to a low level. The duration for the cathode voltage VC0 of the avalanche diode SPAD to rise from 0 to the preset threshold voltage Vth is defined as td1. In this embodiment, the preset duration of the delay circuit 20 is set as td2, where td2 > td1.

[0052] As Figure 22 shown, when the above-mentioned situation 2 occurs in the reset stage, the cathode voltage VC0 of the avalanche diode SPAD remains high, and the output signal VA1 of the comparison circuit 30 has neither a rising edge nor a falling edge. The reason is that there is a photon trigger before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth. Subsequently, the cathode voltage VC0 of the avalanche diode SPAD maintains a state less than the preset threshold voltage Vth. At this time, the output signal VA1 of the comparison circuit 30 maintains a high level state.

[0053] As Figure 21 shown, assume that in the reset stage, that is, during the output period of the second level signal of the first clock signal CK1, without a photon trigger, the cathode voltage VC0 of the avalanche diode SPAD will rise, and when it rises to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches to a low level. At this time, the detection and control circuit 40 first detects the second change signal, the detection and control circuit 40 maintains the output of the reset signal, and controls the quenching and reset circuit 10 to maintain the reset state.

[0054] And when the above-mentioned situation 2 occurs in the reset stage, that is, in the reset stage, there is a photon trigger before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth, resulting in the cathode voltage VC0 of the avalanche diode SPAD maintaining a state less than the preset threshold voltage Vth, and the output signal VA1 of the comparison circuit 30 maintains a high level.

[0055] In this case, as Figure 22As shown, after the detection control circuit 40 outputs a reset signal, it does not detect the second change signal generated by the comparison circuit 30. At the same time, since the phase of the second clock signal CK2 is the same as that of the first clock signal CK1, the detection control circuit 40 can detect the falling edge of the second clock signal CK2. When the falling edge of the second clock signal CK2 is detected, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a high-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD rapidly decreases to 0, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0056] At the same time, when entering the quenching stage, that is, when the first clock signal CK1 switches to output the first level signal, the detection control circuit 40 outputs a quenching signal. The quenching transistor M1 in the quenching reset circuit 10 receives the high-level signal and turns off, and the cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a downward change.

[0057] In the reset stage, by detecting the rising edge of the comparison circuit 30 and the falling edge generated by the detection delay circuit 20, it can be detected and judged whether the avalanche diode SPAD is triggered in the reset stage. When it is determined that the avalanche diode SPAD is triggered in the reset stage, a quenching signal is output to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, no path will be formed with the avalanche diode SPAD, that is, no power consumption is generated, reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0058] Among them, the detection control circuit 40 can be correspondingly set based on the biasing method of the avalanche diode SPAD and the change direction of the output voltage of the avalanche diode SPAD. In an alternative embodiment, as Figure 23 shown, the detection control circuit 40 includes: The first detection circuit 41 is connected to the output end of the comparison circuit 30. The first detection circuit 41 is used to output a first detection signal when detecting the first change signal or trigger the output of a second detection signal when not detecting the first change signal during the output period of each second level signal; The second detection circuit 42 is respectively connected to the output end of the comparison circuit 30 and the output end of the delay circuit 20. The second detection circuit 42 is used to output a third detection signal when detecting the second change signal generated by the delay circuit 20 and not detecting the second change signal generated by the comparison circuit 30 during the output period of each second level signal, otherwise output a fourth detection signal; The logic control circuit 43 is respectively connected to the first detection circuit 41, the second detection circuit 42 and the quenching reset circuit 10. The logic control circuit 43 is used for: Output a reset signal during the output period of each second-level signal, and output a quenching signal when receiving the first detection signal or the third detection signal, or output a reset signal when receiving the second detection signal or the fourth detection signal; Output a quenching signal during the output period of the first-level signal.

[0059] In this embodiment, first, the quenching circuit 1 shown by Figure 23 is described, that is, the avalanche diode SPAD is forward-biased.

[0060] As Figure 23 shown, the cathode of the avalanche diode SPAD inputs a forward bias voltage, the anode of the avalanche diode SPAD is connected to the quenching reset circuit 10 and the comparison circuit 30, the output terminals of the comparison circuit 30 are respectively connected to the first detection circuit 41 and the second detection circuit 42, the first detection circuit 41 is used to detect whether the output signal VA1 of the comparison circuit 30 has a falling edge, the second detection circuit 42 is used to detect whether the output signal VA1 of the comparison circuit 30 has a rising edge, and the second detection circuit 42 is also used to detect whether the second clock signal CK2 of the delay circuit 20 has a rising edge.

[0061] As Figure 24 shown, when the quenching circuit 1 works in the quenching stage, the quenching transistor M1 in the quenching reset circuit 10 receives a low-level signal and turns off, the anode voltage VA0 of the avalanche diode SPAD rises through an increase and then stabilizes at Vex, and then enters the reset stage. The logic control circuit 43 first outputs a high-level reset signal, and the quenching transistor M1 of the quenching reset circuit 10 receives the high-level signal and is triggered to conduct. At this time, the anode voltage VA0 of the avalanche diode SPAD starts to drop. When it drops to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 flips, switching from low level to high level. If there is no photon trigger during the reset stage, the voltage of the avalanche diode SPAD will rise until it stabilizes at Vex at the beginning of the next quenching stage. Among them, Vex is the over-bias voltage of the avalanche diode SPAD, and VBK is the avalanche voltage of the avalanche diode SPAD.

[0062] When the above situation one occurs, as Figure 25 shown, that is, during the reset stage, when the anode voltage VA0 of the avalanche diode SPAD is triggered by photons after dropping to the preset threshold voltage Vth, at this time, the voltage of the avalanche diode SPAD will rise after dropping, resulting in a rising edge and a falling edge in the comparison circuit 30. Among them, the first change signal is the falling edge, and the second change signal is the rising edge.

[0063] In this case, as Figure 25As shown, during the output period of the second-level signal, i.e., the reset period, when the logic control circuit 43 outputs a high-level reset signal, the first detection circuit 41 will detect a falling edge generated by the comparison circuit 30. At this time, the first detection circuit 41 outputs a first detection signal. At this time, the first detection signal can be a low-level signal. When the logic control circuit 43 receives the low-level signal, it triggers the output of a quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a low-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0064] Similarly, during the reset period, if there is no photon trigger and the first detection circuit 41 does not detect a falling edge, the first detection circuit 41 outputs a second detection signal. The second detection signal can be a signal with a level opposite to that of the first detection signal, such as a high-level signal. Here, Q1 represents the output signal of the first detection circuit 41.

[0065] And as Figure 26 shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching reset circuit 10 switches from a low level to a high level. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to decrease, and when it decreases to a preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches from a low level to a high level. The duration for the anode voltage VA0 of the avalanche diode SPAD to decrease from Vex to the preset threshold voltage Vth is defined as td1. In this embodiment, the preset duration of the delay of the set delay circuit 20 is td2, where td2 > td1.

[0066] As Figure 26 shown, assume that during the reset stage, i.e., the output period of the second-level signal of the first clock signal CK1, if there is no photon trigger, the anode voltage VA0 of the avalanche diode SPAD will decrease, and when it decreases to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches to a high level. At this time, the second change signal is detected first, and the detection control circuit 40 maintains the output of the reset signal and controls the quenching reset circuit 10 to remain in the reset state.

[0067] And when the above-mentioned situation 2 occurs during the reset stage, that is, during the reset stage, before the anode voltage VA0 of the avalanche diode SPAD decreases to the preset threshold voltage Vth, there is a photon trigger, resulting in the anode voltage VA0 of the avalanche diode SPAD maintaining a state greater than the preset threshold voltage Vth, and the output signal VA1 of the comparison circuit 30 remains at a low level.

[0068] In this case, as Figure 27As shown, after the logic control circuit 43 outputs a reset signal, the second detection circuit 42 does not detect the second change signal generated by the comparison circuit 30. At the same time, since the phase of the second clock signal CK2 is the same as that of the first clock signal CK1, the second detection circuit 42 can detect the rising edge of the second clock signal CK2. When the rising edge of the second clock signal CK2 is detected, the second detection circuit 42 outputs a third detection signal and triggers the logic control circuit 43 to output a quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a low-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0069] When the second detection circuit 42 detects the second change signal generated by the comparison circuit 30, the second detection circuit 42 outputs a fourth detection signal. The third detection signal and the fourth detection signal can be high and low level signals with respect to each other. At this time, the logic control circuit 43 can maintain the output of the reset signal, where Q2 represents the output signal of the second detection circuit 42.

[0070] At the same time, when entering the quenching stage, that is, when the first clock signal CK1 switches to output a first-level signal, the detection control circuit 40 outputs a quenching signal. The quenching transistor M1 in the quenching reset circuit 10 receives a low-level signal and turns off. The anode voltage VA0 of the avalanche diode SPAD rises and then stabilizes at Vex after passing through a rising process.

[0071] In the reset stage, by using the first detection circuit 41 and the second detection circuit 42 to respectively detect the falling edge of the comparison circuit 30 and the rising edge generated by the detection delay circuit 20, it is possible to detect and determine whether the avalanche diode SPAD is triggered in the reset stage. When it is determined that the avalanche diode SPAD is triggered in the reset stage, the logic control circuit 43 can output a quenching signal to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, no path is formed with the avalanche diode SPAD, that is, no power consumption is generated, reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0072] And as Figure 18 and Figure 23 shown, it is described with the negative of the avalanche diode SPAD.

[0073] As Figure 18As shown, a negative bias voltage is input to the anode of the avalanche diode SPAD. The cathode of the avalanche diode SPAD is connected to the quenching and reset circuit 10 and the comparison circuit 30. The output terminals of the comparison circuit 30 are respectively connected to the first detection circuit 41 and the second detection circuit 42. The first detection circuit 41 is used to detect whether a rising edge appears in the output signal VA1 of the comparison circuit 30, and the second detection circuit 42 is used to detect whether a falling edge appears in the output signal VA1 of the comparison circuit 30. The second detection circuit 42 is also used to detect whether a rising edge appears in the second clock signal CK2 of the delay circuit 20.

[0074] As Figure 28 shown, when the quenching circuit 1 operates in the quenching stage, the logic control circuit 43 outputs a high-level quenching signal. The quenching transistor M1 in the quenching and reset circuit 10 receives the high-level signal and turns off. The cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a downward change, and then enters the reset stage. The logic control circuit 43 outputs a low-level reset signal. The quenching transistor M1 of the quenching and reset circuit 10 receives the low-level signal and is triggered to conduct. At this time, the cathode voltage VC0 of the avalanche diode SPAD starts to rise. When it rises to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 flips, switching from high level to low level.

[0075] When the above situation one occurs, as Figure 29 shown, that is, in the reset stage, when the cathode voltage VC0 of the avalanche diode SPAD is triggered by photons after rising to the preset threshold voltage Vth, at this time, the voltage of the avalanche diode SPAD will drop after rising, resulting in a falling edge and a rising edge in the comparison circuit 30. Among them, the first change signal is the rising edge, and the second change signal is the falling edge.

[0076] In this case, as Figure 29 shown, after the logic control circuit 43 outputs a low-level reset signal, the first detection circuit 41 will detect the rising edge generated by the comparison circuit 30. At this time, the first detection circuit 41 outputs a first detection signal. At this time, the first detection signal can be a high-level signal. When the logic control circuit 43 receives the high-level signal, it is triggered to output a quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a high-level signal, and controls the quenching transistor M1 in the quenching and reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD quickly drops to 0, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0077] Similarly, during the reset period, when there is no photon trigger and the first detection circuit 41 does not detect a rising edge, the first detection circuit 41 outputs a second detection signal, and the second detection signal can be a signal with a level opposite to that of the first detection signal, such as a low-level signal. Herein, Q1 represents the output signal of the first detection circuit 41.

[0078] And as Figure 30 shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching and reset circuit 10 switches from a high level to a low level. At this time, the cathode voltage VC0 of the avalanche diode SPAD starts to rise, and when it rises to a preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches from a high level to a low level. The duration for the cathode voltage VC0 of the avalanche diode SPAD to rise from 0 to the preset threshold voltage Vth is defined as td1. In this embodiment, the preset duration of the delay of the set delay circuit 20 is td2, where td2 > td1.

[0079] As Figure 30 shown, assume that during the reset stage, that is, during the output period of the second-level signal of the first clock signal CK1, when there is no photon trigger, the cathode voltage VC0 of the avalanche diode SPAD will rise, and when it rises to the preset threshold voltage Vth, the output signal VA1 of the comparison circuit 30 switches to a low level. At this time, a second change signal is detected first, and the detection control circuit 40 maintains the output of the reset signal and controls the quenching and reset circuit 10 to remain in the reset state.

[0080] And when the above-mentioned situation 2 occurs during the reset stage, that is, during the reset stage, before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth, there is a photon trigger, resulting in the cathode voltage VC0 of the avalanche diode SPAD maintaining a state less than the preset threshold voltage Vth, and the output signal VA1 of the comparison circuit 30 remains at a high level.

[0081] In this case, as Figure 31 shown, after the logic control circuit 43 outputs the reset signal, the second detection circuit 42 does not detect the second change signal generated by the comparison circuit 30. At the same time, since the second clock signal CK2 has the same phase as the first clock signal CK1, the second detection circuit 42 can detect the falling edge of the second clock signal CK2. When the falling edge of the second clock signal CK2 is detected, the second detection circuit 42 outputs a third detection signal and triggers the logic control circuit 43 to output a quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a high-level signal, and controls the quenching transistor M1 in the quenching and reset circuit 10 to turn off, and the cathode voltage VC0 of the avalanche diode SPAD quickly drops to 0, so that the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0082] When the second detection circuit 42 detects the second change signal generated by the comparison circuit 30, the second detection circuit 42 outputs a fourth detection signal. The third detection signal and the fourth detection signal can be high and low level signals with respect to each other. At this time, the logic control circuit 43 can maintain the output of the reset signal. Herein, Q2 represents the output signal of the second detection circuit 42.

[0083] Meanwhile, when entering the quenching stage, that is, when the first clock signal CK1 switches to output a first level signal, the detection control circuit 40 outputs a quenching signal. The quenching transistor M1 in the quenching reset circuit 10 receives a high level signal and turns off. The cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a downward change.

[0084] In the reset stage, by using the first detection circuit 41 and the second detection circuit 42 to respectively detect the rising edge of the comparison circuit 30 and the falling edge generated by the detection delay circuit 20, it is possible to detect and determine whether the avalanche diode SPAD is triggered in the reset stage. When it is determined that the avalanche diode SPAD is triggered in the reset stage, the logic control circuit 43 can output a quenching signal to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, no path is formed with the avalanche diode SPAD, that is, no power consumption is generated, reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0085] Furthermore, in order to improve the trigger detection efficiency in the reset stage, different preset threshold voltages Vth can also be set, so as to quickly detect trigger events when the avalanche diode SPAD is triggered in the reset stage, such as Figure 32 As shown, in an alternative embodiment, there are multiple delay circuits 20. Each delay circuit 20 is configured to delay the input first clock signal CK1 by a preset duration and then output a second clock signal CK2. The delay durations corresponding to the respective delay circuits 20 are not equal; There are multiple comparison circuits 30. Each comparison circuit 30 is configured to compare the input voltage with a preset threshold voltage Vth respectively, and output a third level signal when the input voltage is greater than or equal to the preset threshold voltage Vth, or output a fourth level signal when the input voltage is less than or equal to the preset threshold voltage Vth. The preset threshold voltages Vth corresponding to the respective comparison circuits 30 are not equal; There are multiple first detection circuits 41. The first detection circuits 41 are connected to the comparison circuits 30 in a one-to-one correspondence; There are multiple second detection circuits 42. Each second detection circuit 42 is respectively connected to the output terminal of a comparison circuit 30 and the output terminal of a delay circuit 20; The logic control circuit 43 is connected to multiple first detection circuits 41 and multiple second detection circuits 42 respectively. The logic control circuit 43 is configured to: Output a reset signal during the output period of each second-level signal, and output a quenching signal when receiving one of the first detection signals or the third detection signal earlier, or output a reset signal when receiving one of the second detection signals or the fourth detection signal earlier; Output a quenching signal during the output period of the first-level signal.

[0086] In this embodiment, a multi-threshold detection strategy is adopted, and the preset threshold voltages Vth corresponding to each comparison circuit 30 are not equal, so that the voltage change of the second end of the avalanche diode SPAD from the reset stage to the quenching circuit 1 in the range of 0 to Vex can be divided into multiple intervals for refined detection. For example, taking the forward bias voltage of the avalanche diode SPAD as an example, in the quenching stage, as Figure 24 shown, the quenching transistor M1 in the quenching reset circuit 10 receives a low-level signal and turns off. The anode voltage VA0 of the avalanche diode SPAD rises and then stabilizes at Vex, and then enters the reset stage. The quenching transistor M1 of the quenching reset circuit 10 receives a high-level signal and is triggered to conduct. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to drop until it drops to 0. Assume that the preset threshold voltages Vth of multiple comparison circuits 30 are 0.4Vex and 0.6Vex respectively.

[0087] When the above situation one occurs, as Figure 25 shown, during the output period of the second-level signal, that is, the reset period, the anode voltage VA0 of the avalanche diode SPAD first drops to 0.6Vex. The comparison circuit 30 corresponding to the preset threshold voltage Vth of 0.6Vex first outputs a falling edge. The first detection circuit 41 connected to the comparison circuit 30 will first detect the falling edge. At this time, the first detection circuit 41 first outputs a first detection signal. The logic control circuit 43 triggers and outputs a quenching signal in advance when receiving the first detection signal earlier, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD quickly increases to Vex, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0088] In addition, multiple delay circuits 20 can delay the first clock signal CK1 for different preset durations respectively. For example, the original preset duration is 0.5 ns. Then, when two delay circuits 20 are set, assuming there are two comparison circuits 30, and the preset threshold voltages Vth corresponding to the two comparison circuits 30 are not equal. The times when the anode voltage VA0 of the avalanche diode SPAD drops to 0.4Vex and 0.6Vex respectively during the reset phase are td1_1 and td1_2. Then, the preset durations of the corresponding delay circuits 20 for delay are td2_1 and td2_2 respectively. Then, it is required that td2_1 > td1_1 and td2_2 > td1_2. For example, if td1_1 and td1_2 are 0.5 ns and 0.3 ns respectively, then td2_1 and td2_2 can be set to 0.6 ns and 0.4 ns respectively.

[0089] And when the above-mentioned situation 2 occurs during the reset phase, as Figure 27 shown, the second detection circuit 42 does not detect the second change signal generated by the comparison circuit 30. At the same time, since the phase of the second clock signal CK2 is the same as that of the first clock signal CK1, the second detection circuit 42 can first detect the rising edge of the second clock signal CK2 with a preset delay duration of 0.4 ns. When detecting the rising edge of the second clock signal CK2, the corresponding second detection circuit 42 first outputs a third detection signal, and triggers the logic control circuit 43 to first output a quenching signal and control the quenching tube M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0090] During the reset phase, by setting multiple delay circuits 20, multiple comparison circuits 30, multiple first detection circuits 41 and multiple second detection circuits 42, different threshold comparisons and preset duration settings can be set, so as to realize earlier control of the quenching tube M1, further reduce the power consumption of the quenching circuit 1 and the overall power consumption of the imaging system.

[0091] The quenching reset circuit 10 can adopt a corresponding quenching tube M1 and capacitor Cpar structure. The comparison circuit 30 can adopt corresponding comparators, inverters, etc. The delay circuit 20 can adopt multiple inverters or non-inverters or delay elements. The first detection circuit 41 and the second detection circuit 42 can adopt corresponding flip-flops, latches, etc. The logic control circuit 43 can adopt corresponding logic gates, controllers, etc.

[0092] In an alternative embodiment, the quenching reset circuit 10 includes a quenching switch 11 and a capacitor Cpar; The first end of the quenching switch 11, the first end of the capacitor Cpar, and the second end of the avalanche diode SPAD are connected, and the second end of the quenching switch 11 is grounded or connected to the first positive voltage terminal Vbias; The first detection circuit 41 includes a first D flip-flop DFF1; The data terminal of the first D flip-flop DFF1 is connected to the second positive voltage terminal VCC, the corresponding clock terminal of the first D flip-flop DFF1 is connected to the output terminal of the comparison circuit 30, the corresponding reset terminal of the first D flip-flop DFF1 is used to input the first clock signal CK1, and the output terminal of the first D flip-flop DFF1 constitutes the output terminal of the first detection circuit 41.

[0093] The second detection circuit 42 includes a second D flip-flop DFF2 and a third D flip-flop DFF3; The data terminal of the second D flip-flop DFF2 is connected to the second positive voltage terminal VCC, the corresponding clock terminal of the second D flip-flop DFF2 is connected to the output terminal of the comparison circuit 30, the corresponding reset terminals of the second D flip-flop DFF2 and the third D flip-flop DFF3 are used to input the first clock signal CK1, the corresponding clock terminal of the third D flip-flop DFF3 is used to input the corresponding second clock signal CK2, the corresponding output terminal of the second D flip-flop DFF2 is connected to the data terminal of the third D flip-flop DFF3, and the corresponding output terminal of the third D flip-flop DFF3 constitutes the output terminal of the second detection circuit 42.

[0094] When one of the first detection circuit 41 and the second detection circuit 42 is included, the logic control circuit 43 includes a first logic gate circuit 431. Two input terminals of the first logic gate circuit 431 are respectively connected to the output terminal of the first detection circuit 41 and the output terminal of the second detection circuit 42. Another input terminal of the first logic gate circuit 431 is also used to input the first clock signal CK1, and the output terminal of the first logic gate circuit 431 constitutes the output terminal of the logic control circuit 43.

[0095] Among them, according to different biasing methods of the avalanche diode SPAD, the connection method between the quenching switch 11 and the avalanche diode SPAD is different. As Figure 33 shown, in an optional embodiment, the avalanche diode SPAD is forward-biased. The cathode of the avalanche diode SPAD is connected to the first positive voltage terminal Vbias. The anode of the avalanche diode SPAD, the first end of the quenching switch 11, and the first end of the capacitor Cpar are connected to form the output terminal of the quenching reset circuit 10. The second end of the quenching switch 11 and the second end of the capacitor Cpar are grounded.

[0096] The quenching switch 11 includes a quenching tube M1.

[0097] Corresponding to the forward bias voltage of the avalanche diode SPAD, the data terminal D of the first D flip-flop DFF1 is connected to the second positive voltage terminal VCC. The inverted clock terminal CN of the first D flip-flop DFF1 is connected to the output terminal of the comparison circuit 30. The inverted reset terminal RN of the first D flip-flop DFF1 is used to input the first clock signal CK1. The output terminal Q of the first D flip-flop DFF1 constitutes the output terminal of the first detection circuit 41.

[0098] The data terminal D of the second D flip-flop DFF2 is connected to the second positive voltage terminal VCC. The clock terminal C of the second D flip-flop DFF2 is connected to the output terminal of the comparison circuit 30. The inverted reset terminals RN of the second D flip-flop DFF2 and the third D flip-flop DFF3 are used to input the first clock signal CK1. The clock terminal C of the third D flip-flop DFF3 is used to input the corresponding second clock signal CK2. The inverted output terminal QN of the second D flip-flop DFF2 is connected to the data terminal D of the third D flip-flop DFF3. The output terminal Q of the third D flip-flop DFF3 constitutes the output terminal of the second detection circuit 42.

[0099] The first logic gate circuit 431 includes a second inverter U2, a third inverter U3, and an AND gate AND1; The input terminal of the second inverter U2 is connected to the output terminal of the first detection circuit 41. The input terminal of the third inverter U3 is connected to the output terminal of the second detection circuit 42. The output terminal of the second inverter U2 is connected to the first input terminal of the AND gate AND1. The output terminal of the third inverter U3 is connected to the second input terminal of the AND gate AND1. The third input terminal of the AND gate AND1 is used to input the first clock signal CK1. The output terminal of the AND gate AND1 constitutes the output terminal of the logic control circuit 43.

[0100] Each delay circuit 20 includes an inverter U5; The input terminal of the inverter U5 is used to input the first clock signal CK1. The output terminal of the inverter U5 is used to output the second clock signal CK2.

[0101] The comparison circuit 30 includes a first inverter U1; The input terminal of the first inverter U1 is connected to the second terminal of the avalanche diode SPAD. The output terminal of the first inverter U1 constitutes the output terminal of the comparison circuit 30.

[0102] In this embodiment, the comparison circuit 30 adopts an inverter structure. The inverter has a corresponding threshold voltage Vth. For example, the threshold voltage Vth of a CMOS inverter is half of the power supply voltage, and the threshold voltage Vth of a TTL inverter can be 0.8V, etc. When the anode voltage VA0 of the avalanche diode SPAD is greater than the threshold voltage Vth corresponding to the first inverter U1, the first inverter U1 outputs a high level. And when the anode voltage VA0 of the avalanche diode SPAD is less than the threshold voltage Vth corresponding to the first inverter U1, the first inverter U1 outputs a low level. By using different models and types of inverters in the comparison circuit 30, a first inverter U1 with different threshold voltages Vth can be obtained to achieve threshold comparison without using a comparator structure and without additionally setting a reference voltage source for outputting the threshold voltage Vth, thus simplifying the circuit structure.

[0103] As Figure 33 shown, a positive bias voltage is input to the cathode of the avalanche diode SPAD. The anode of the avalanche diode SPAD is connected to the quenching transistor M1, the capacitor Cpar, and the first inverter U1 of the comparison circuit 30. The output terminals of the first inverter U1 are respectively connected to the first D flip-flop DFF1 and the second D flip-flop DFF2. The first D flip-flop DFF1 is used to detect whether a falling edge appears in the output signal of the first inverter U1. The second D flip-flop DFF2 is used to detect whether a rising edge appears in the output signal VA1 of the comparison circuit 30. The third D flip-flop DFF3 is used to detect whether a rising edge appears in the second clock signal CK2 of the delay circuit 20. The first D flip-flop DFF1 is triggered by a falling edge, and the second D flip-flop DFF2 and the third D flip-flop DFF3 are triggered by a rising edge.

[0104] As Figure 24 shown, when the quenching circuit 1 works in the quenching stage, the AND gate AND1 first outputs a low-level quenching signal. The quenching transistor M1 receives the low-level signal and turns off. The anode voltage VA0 of the avalanche diode SPAD rises and then stabilizes at Vex after rising, and then enters the reset stage. The quenching transistor M1 receives the high-level signal and is triggered to conduct. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to decrease. When it drops to the preset threshold voltage Vth, the output signal of the first inverter U1 flips, switching from a low level to a high level. If no photons trigger during the reset stage, the voltage of the avalanche diode SPAD will rise until it stabilizes at Vex at the beginning of the next quenching stage.

[0105] When the above situation one occurs, as Figure 25As shown, during the output period of the second-level signal, i.e., the reset period, the AND gate AND1 first outputs a high-level reset signal. The first D flip-flop DFF1 will detect the falling edge generated by the first inverter U1. At this time, the first D flip-flop DFF1 outputs a high-level signal. When the AND gate AND1 receives a low-level signal through the second inverter U2, at this time, the first clock signal CK1 is at a high level, and the AND gate AND1 outputs a low-level quenching signal. That is, the output clock CK0 of the logic control circuit 43 switches to a low-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex. Therefore, the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0106] And when the above-mentioned situation 2 occurs during the reset phase, that is, during the reset phase, there is a photon trigger before the anode voltage VA0 of the avalanche diode SPAD drops to the preset threshold voltage Vth, resulting in the anode voltage VA0 of the avalanche diode SPAD maintaining a state greater than the preset threshold voltage Vth, and the output signal of the first inverter U1 remains at a low level.

[0107] In this case, as Figure 27 shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparison circuit 30. The second D flip-flop DFF2 maintains an output of high level. Since the phase of the second clock signal CK2 is the same as that of the first clock signal CK1, the third D flip-flop DFF3 samples the high level and can detect the rising edge of the second clock signal CK2. When the rising edge of the second clock signal CK2 is detected, the third D flip-flop DFF3 outputs a high-level signal. The third D flip-flop DFF3 outputs a low level through the third inverter U3. At this time, the first clock signal CK1 is at a high level, and the AND gate AND1 outputs a low-level quenching signal. That is, the output clock CK0 of the logic control circuit 43 switches to a low-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex. Therefore, the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0108] In the reset stage, by using the first D flip-flop DFF1 to detect the falling edge of the comparison circuit 30, the second D flip-flop DFF2 to detect the falling edge of the comparison circuit 30, and the third D flip-flop DFF3 to detect the falling edge of the delay circuit 20, it is possible to detect and determine whether the avalanche diode SPAD is triggered in the reset stage. When it is determined that the avalanche diode SPAD is triggered in the reset stage, the AND gate AND1 can output a quenching signal to quickly turn off the quenching tube M1 in the quenching and reset circuit 10 in advance. Since the quenching tube M1 is in the off state, no path is formed with the avalanche diode SPAD, that is, no power consumption is generated, reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0109] In another alternative embodiment, as Figure 34 shown, the avalanche diode SPAD has a negative bias voltage. The anode of the avalanche diode SPAD is connected to the negative voltage terminal -VBK. The cathode of the avalanche diode SPAD, the first end of the quenching switch 11, and the first end of the capacitor Cpar are connected to form the output terminal of the quenching and reset circuit 10. The second end of the quenching switch 11 is connected to the third positive voltage terminal Vex, and the second end of the capacitor Cpar is grounded; The quenching switch 11 includes a quenching tube M1; The data terminal D of the first D flip-flop DFF1 is connected to the second positive voltage terminal VCC. The clock terminal C of the first D flip-flop DFF1 is connected to the output terminal of the comparison circuit 30. The reset terminal R of the first D flip-flop DFF1 is used to input the first clock signal CK1. The output terminal Q of the first D flip-flop DFF1 constitutes the output terminal of the first detection circuit 41.

[0110] The data terminal D of the second D flip-flop DFF2 is connected to the second positive voltage terminal VCC. The inverted clock terminal CN of the second D flip-flop DFF2 is connected to the output terminal of the comparison circuit 30. The reset terminals R of the second D flip-flop DFF2 and the third D flip-flop DFF3 are used to input the first clock signal CK1. The inverted clock terminal CN of the third D flip-flop DFF3 is used to input the corresponding second clock signal CK2. The inverted output terminal QN of the second D flip-flop DFF2 is connected to the data terminal D of the third D flip-flop DFF3. The output terminal Q of the third D flip-flop DFF3 constitutes the output terminal of the fifth detection unit.

[0111] When the first detection circuit 41 and the second detection circuit 42 include one, the first logic gate circuit 431 includes a first OR gate OR1; The first input terminal of the first OR gate OR1 is connected to the output terminal of the first detection circuit 41. The second input terminal of the first OR gate OR1 is connected to the output terminal of the second detection circuit 42. The third input terminal of the first OR gate OR1 is used to input the first clock signal CK1. The output terminal of the first OR gate OR1 constitutes the output terminal of the logic control circuit 43; Each delay circuit 20 includes an inverter U5; The input terminal of the inverter U5 is used to input the first clock signal CK1, and the output terminal of the inverter U5 is used to output the second clock signal CK2.

[0112] The comparison circuit 30 includes a first inverter U1; The input terminal of the first inverter U1 is connected to the second terminal of the avalanche diode SPAD, and the output terminal of the first inverter U1 constitutes the output terminal of the comparison circuit 30.

[0113] In this embodiment, the comparison circuit 30 adopts an inverter structure. The inverter has a corresponding threshold voltage. For example, the threshold voltage of a CMOS inverter is half of the power supply voltage, and the threshold voltage of a TTL inverter can be 0.8V, etc. When the cathode voltage VC0 of the avalanche diode SPAD is greater than the corresponding threshold voltage of the first inverter U1, the first inverter U1 outputs a high level, and when the cathode voltage VC0 of the avalanche diode SPAD is less than the corresponding threshold voltage of the first inverter U1, the first inverter U1 outputs a low level. By adopting different models and types of inverters in the comparison circuit 30, inverters with different threshold voltages can be obtained to achieve threshold comparison. There is no need to adopt a comparator structure, and there is no need to additionally set a reference voltage source for outputting the threshold voltage, which simplifies the circuit structure.

[0114] As Figure 34 shown, a negative bias voltage -VBK is input to the anode of the avalanche diode SPAD. The cathode of the avalanche diode SPAD is connected to the quenching transistor M1, the capacitor Cpar, and the first inverter U1 of the comparison circuit 30. The second terminal of the quenching transistor M1 inputs Vex. The output terminal of the first inverter U1 is respectively connected to the first D flip-flop DFF1 and the second D flip-flop DFF2. The first D flip-flop DFF1 is used to detect whether a rising edge appears in the output signal of the first inverter U1. The second D flip-flop DFF2 is used to detect whether a falling edge appears in the output signal VA1 of the comparison circuit 30. The third D flip-flop DFF3 is used to detect whether a falling edge appears in the second clock signal CK2 of the delay circuit 20. The first D flip-flop DFF1 is triggered by a rising edge, and the second D flip-flop DFF2 and the third D flip-flop DFF3 are triggered by a rising edge.

[0115] As Figure 28As shown, when the quenching circuit 1 operates in the quenching stage, the first OR gate OR1 first outputs a high-level quenching signal. The quenching transistor M1 receives the high-level signal and turns off. The cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a downward change and then enters the reset stage. The quenching transistor M1 receives a low-level signal and is triggered to conduct. At this time, the cathode voltage VC0 of the avalanche diode SPAD begins to rise. When it rises to the preset threshold voltage Vth, the output signal of the first inverter U1 flips, switching from high level to low level.

[0116] When the above situation one occurs, such as Figure 29 As shown, during the output period of the second level signal, that is, the reset period, the first D flip-flop DFF1 will detect the rising edge generated by the first inverter U1. At this time, the first D flip-flop DFF1 outputs a low-level signal. When the first OR gate OR1 receives the low-level signal, at this time, the first clock signal CK1 is at a high level, and the first OR gate OR1 outputs a high-level quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a high-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly drops to 0, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0117] And when the above situation two occurs during the reset stage, that is, during the reset stage, before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth, there is a photon trigger, resulting in the cathode voltage VC0 of the avalanche diode SPAD remaining in a state less than the preset threshold voltage Vth, and the output signal of the first inverter U1 remains at a high level.

[0118] In this case, such as Figure 31 As shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparison circuit 30. The second D flip-flop DFF2 maintains an output of high level. Since the second clock signal CK2 has the same phase as the first clock signal CK1, the third D flip-flop DFF3 can detect the falling edge of the second clock signal CK2. When the falling edge of the second clock signal CK2 is detected, the third D flip-flop DFF3 outputs a high-level signal, the first OR gate OR1 outputs a high-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD rapidly drops to 0, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0119] Similarly, such as Figure 35As shown, when multiple comparison circuits 30, delay circuits 20, first detection circuits 41, and second detection circuits 42 are provided, different logic gate circuits can be adopted by the logic control circuit 43. In an alternative embodiment, the logic control circuit 43 includes a second logic gate circuit 432 and a third logic gate circuit 433; Multiple input terminals of the second logic gate circuit 432 are respectively connected to output terminals of multiple first detection circuits 41. Multiple input terminals of the third logic gate circuit 433 are respectively connected to output terminals of multiple second detection circuits 42 and an output terminal of the second logic gate circuit 432. Another input terminal of the third logic gate circuit 433 is used for inputting a first clock signal CK1. An output terminal of the third logic gate circuit 433 constitutes an output terminal of the logic control circuit.

[0120] Wherein, when the biasing modes of the avalanche diodes SPAD are different, different circuit structures can be adopted by the second logic gate circuit 432 and the third logic gate circuit 433. In an alternative embodiment, when the avalanche diode SPAD is forward biased, as Figure 35 shown, the second logic gate circuit 432 includes a first OR gate OR1, and the third logic gate circuit 433 includes multiple fourth inverters U4 and an AND gate AND1. Multiple input terminals of the first OR gate OR1 are respectively connected to output terminals of multiple first detection circuits 41. Output terminals of multiple second detection circuits 42 and an output terminal of the first OR gate OR1 are respectively connected to multiple input terminals of the AND gate AND1 through a fourth inverter U4. Another input terminal of the AND gate AND1 is further used for inputting the first clock signal CK1. An output terminal of the AND gate AND1 constitutes an output terminal of the logic control circuit 43.

[0121] The first OR gate OR1 performs an OR operation on output signals of multiple first detection circuits 41 and outputs a high level when receiving at least one high level. Multiple fourth inverters U4 invert output signals of the first OR gate OR1 and multiple second detection circuits 42. The inverted signals are subjected to an AND operation through the AND gate AND1. When the above-mentioned situation one occurs, assume that the preset threshold voltages Vth of multiple first inverters are 0.4Vex and 0.6Vex respectively.

[0122] When the above-mentioned situation one occurs, as Figure 25As shown, during the output period of the second-level signal, i.e., the reset period, the anode voltage VA0 of the avalanche diode SPAD first drops to 0.6Vex. The first inverter U1 corresponding to the preset threshold voltage Vth of 0.6Vex first outputs a falling edge. The first D flip-flop DFF1 connected to the first inverter U1 will first detect the falling edge. At this time, the first D flip-flop DFF1 first outputs a high-level signal. The first OR gate OR1 outputs a high level and receives a low-level signal through the fourth inverter U4. At this time, the first clock signal CK1 is at a high level, and the AND gate AND1 outputs a quenching signal at a low level, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0123] And when the above situation 2 occurs during the reset stage, assuming that td1_1 and td1_2 are 0.5ns and 0.3ns respectively, then td2_1 and td2_2 can be set to 0.6ns and 0.4ns respectively.

[0124] As Figure 27 shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparison circuit 30, and the second D flip-flop DFF2 maintains the output of a high level. At the same time, since the phase of the second clock signal CK2 is the same as that of the first clock signal CK1, the third D flip-flop DFF3 can first detect the rising edge of the second clock signal CK2 with a preset delay duration of 0.4ns. When detecting the rising edge of the second clock signal CK2, the corresponding third D flip-flop DFF3 first outputs a high-level signal. The third D flip-flop DFF3 outputs a low level through the fourth inverter U4. At this time, the first clock signal CK1 is at a high level, and the AND gate AND1 outputs a quenching signal at a low level, that is, the output clock CK0 of the logic control circuit 43 switches to a low-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0125] And when the avalanche diode SPAD is negatively biased, the second logic gate circuit 432 includes a second OR gate, and the third logic gate circuit 433 includes a third OR gate.

[0126] Assume that the preset threshold voltages Vth of multiple first inverters U1 are 0.4Vex and 0.6Vex respectively.

[0127] When the above situation 1 occurs, as Figure 25As shown, during the output period of the second-level signal, i.e., the reset period, the anode voltage VA0 of the avalanche diode SPAD first drops to 0.4Vex. The first inverter U1 corresponding to the preset threshold voltage Vth of 0.4Vex first outputs a rising edge. The first D flip-flop DFF1 connected to the first inverter U1 will first detect the rising edge. At this time, the first D flip-flop DFF1 first outputs a low-level signal, and the second OR gate OR2 outputs a low-level signal. At this time, the first clock signal CK1 is at a high level, and the third OR gate OR3 outputs a high-level quenching signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0128] And when the above-mentioned second situation occurs during the reset stage, assuming that td1_1 and td1_2 are 0.5ns and 0.3ns respectively, then td2_1 and td2_2 can be set to 0.6ns and 0.4ns respectively. As Figure 27 As shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparison circuit 30, and the second D flip-flop DFF2 maintains a high-level output. At the same time, since the phase of the second clock signal CK2 is the same as that of the first clock signal CK1, the third D flip-flop DFF3 can first detect the falling edge of the second clock signal CK2 with a preset delay duration of 0.4ns. When detecting the falling edge of the second clock signal CK2, the corresponding third D flip-flop DFF3 first outputs a high-level signal, and the second OR gate outputs a high-level signal. At this time, the first clock signal CK1 is at a high level, and the third OR gate outputs a high-level quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a high-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and thus the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0129] Among them, when there is a photon trigger during the reset stage, there may also be a third situation. Taking the positive bias voltage of the avalanche diode SPAD as an example, the comparison circuit 30 does not show a falling edge until the quenching reset circuit 10 outputs a quenching signal. Or taking the negative bias voltage of the avalanche diode SPAD as an example, the comparison circuit 30 does not show a rising edge until the quenching reset circuit 10 outputs a quenching signal.

[0130] The reason is that there is a photon trigger after the voltage at the second end of the avalanche diode SPAD drops to the preset threshold voltage Vth or rises to the preset threshold voltage Vth during the reset stage. However, due to the too small on-resistance of the quenching transistor M1, although the voltage at the second end of the avalanche diode SPAD rises or drops, it is still lower or higher than the preset threshold voltage Vth, resulting in the inability to produce the falling edge or rising edge of situation one.

[0131] For this reason, it is necessary to ensure that the on-resistance of the quenching tube M1 reaches a preset resistance value. In an alternative embodiment, as Figure 36 shown, the quenching switch 11 includes a plurality of parallel quenching branches. Each quenching branch includes a selection switch S and a quenching tube M1 connected in series. The control end of each quenching tube M1 is used to receive a quenching signal or a reset signal, and each selection switch S is used to receive a switch selection signal and conduct or cut off correspondingly.

[0132] By setting a plurality of parallel quenching branches, different selection switches S can be selected to conduct according to the required on-resistance, so as to generate different on-resistances in parallel, so that the on-resistance of the quenching switch 11 reaches the preset on-resistance, so that when the voltage at the second end of the avalanche diode SPAD drops to the preset threshold voltage Vth or rises to the preset threshold voltage Vth during the reset stage and there is a photon trigger, an upward edge or a downward edge of a certain situation can occur, ensuring the accuracy of signal detection and the reliability of the on-off control of the quenching tube.

[0133] Among them, the width-to-length ratio of each quenching tube M1 is small. The fewer the selection switches S are closed, the smaller the width-to-length ratio of the quenching switch 11 is, and the larger the on-resistance is.

[0134] In addition, the on-resistance of the quenching switch 11 can also be changed by changing the output clock CK0 of the detection control circuit 40. In an alternative embodiment, as Figure 37 shown, the quenching circuit 1 further includes: A signal attenuation circuit 60, connected between the quenching reset circuit 10 and the detection control circuit 40. The signal attenuation circuit 60 is used to attenuate the output signal of the detection control circuit 40 and output it to the quenching reset circuit 10.

[0135] In this embodiment, the signal attenuation circuit 60 increases the on-resistance of the quenching switch 11 by reducing the amplitude of the output clock CK0 of the detection control circuit 40, so that the on-resistance of the quenching switch 11 reaches the preset on-resistance, so that when the voltage at the second end of the avalanche diode SPAD drops to the preset threshold voltage Vth or rises to the preset threshold voltage Vth during the reset stage and there is a photon trigger, an upward edge or a downward edge of a certain situation can occur, ensuring the accuracy of signal detection and the reliability of the on-off control of the quenching tube.

[0136] Among them, the signal attenuation circuit 60 can adopt structures such as an attenuator and a voltage dividing circuit, and the specific structure is not limited.

[0137] The above-mentioned quenching circuit 1 includes an avalanche diode SPAD, a quenching and reset circuit 10, a delay circuit 20, a comparison circuit 30, and a detection and control circuit 40. The detection and control circuit 40 outputs a quenching signal at the first-level signal of the first clock signal CK1, enabling the quenching circuit 1 to operate in the quenching stage. Among them, in the second-level signal, that is, the reset stage of the quenching circuit 1, if the avalanche diode SPAD is triggered by photons, the comparison circuit 30 or the delay circuit 20 will generate a corresponding first change signal or second change signal. When the detection and control circuit 40 detects the first change signal or second change signal of the comparison circuit 30 or the delay circuit 20, it can determine that the avalanche diode SPAD is triggered in the reset stage. At this time, a quenching signal is output to advance the quenching and reset circuit 10 into the quenching stage, reducing the power consumption when the quenching circuit 1 is triggered in the reset stage.

[0138] Moreover, the quenching circuit 1 uses clock control for active quenching and does not change the clock frequency of the first clock signal CK1. Therefore, the quenching circuit 1 can measure a relatively high photon counting rate, enabling the quenching circuit 1 to have a low dead time characteristic. At the same time, to ensure the accuracy of the intensity information sensed by the system, the photon counting rate output by the quenching circuit 1 can show a "non-decreasing" trend with the light intensity, ensuring the accuracy of the light intensity information sensed by the system.

[0139] The present invention also proposes an imaging system, as Figure 39 shown. The imaging system includes a pixel array 100 and an image processing circuit 2. The pixel array 100 includes pixel units 101 arranged in an array. Each pixel unit 101 includes an avalanche diode SPAD connected to the above-mentioned quenching circuit 1. The specific structure of the quenching circuit 1 refers to the above-mentioned embodiments. Since this imaging system adopts all the technical solutions of the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be elaborated here one by one. Among them, the image processing circuit 2 is respectively connected to the quenching circuits 1 of the avalanche diodes SPAD. The image processing circuit 2 is used to process the photon counting rate output by the quenching circuits 1 of the avalanche diodes SPAD and determine the image information.

[0140] In this embodiment, the image processing circuit 2 can adopt corresponding logic gates and signal processing circuits, and obtain the output signal VA1 of the comparison circuit 30 in the quenching circuit and the clock signal received by the quenching and reset circuit 10. The photon counting rate and image information are determined according to the clock signal and the output signal VA1 of the comparison circuit 30.

[0141] The signal processing circuit can include a counter, a memory, a signal processing circuit, etc. By counting, storing, and signal processing the photon counting rate, the corresponding image information can be obtained.

[0142] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A quenching circuit for an avalanche diode, characterized in that, Including: A bias voltage circuit connected to the first end of the avalanche diode, the bias voltage circuit being configured to provide a bias voltage; A quenching and reset circuit connected to the second end of the avalanche diode, the quenching and reset circuit being configured to quench or reset the avalanche diode according to a quenching signal or a reset signal; A delay circuit configured to delay an input first clock signal by a preset duration and output a second clock signal, the first clock signal being composed of alternating first level signals and second level signals of opposite levels; A comparison circuit connected to the second end of the avalanche diode, the comparison circuit being configured to output a third level signal when an input voltage is greater than or equal to a preset threshold voltage, and output a fourth level signal of a level opposite to that of the third level signal when the input voltage is less than the preset threshold voltage; A detection and control circuit connected to the comparison circuit, the delay circuit, and the quenching and reset circuit respectively, the detection and control circuit being configured to: Output the reset signal during the output period of each of the second level signals, and output the quenching signal when detecting a first change signal generated by the comparison circuit, or when detecting a second change signal generated by the delay circuit and not detecting a second change signal generated by the comparison circuit; Output the quenching signal during the output period of the first level signal, the first change signal and the second change signal being a rising edge and a falling edge of each other.

2. The quenching circuit of an avalanche diode according to claim 1, wherein The detection and control circuit includes: A first detection circuit connected to the output end of the comparison circuit, the first detection circuit being configured to output a first detection signal when detecting the first change signal or trigger the output of a second detection signal when not detecting the first change signal during the output period of each of the second level signals; A second detection circuit connected to the output end of the comparison circuit and the output end of the delay circuit respectively, the second detection circuit being configured to output a third detection signal when detecting the second change signal generated by the delay circuit and not detecting the second change signal generated by the comparison circuit during the output period of each of the second level signals, and otherwise output a fourth detection signal; A logic control circuit connected to the first detection circuit, the second detection circuit, and the quenching and reset circuit respectively, the logic control circuit being configured to: Output the reset signal during the output period of each of the second level signals, and output the quenching signal when receiving the first detection signal or the third detection signal, or output the reset signal when receiving the second detection signal or the fourth detection signal; Output the quenching signal during the output period of the first level signal.

3. The quenching circuit of the avalanche diode according to claim 2, characterized in that, There are multiple delay circuits, each delay circuit being configured to delay the input first clock signal by a preset duration and output a second clock signal respectively, and the delay durations corresponding to the delay circuits are not equal; The comparison circuits include a plurality of them, and each comparison circuit is configured to compare an input voltage with a preset threshold voltage respectively, and output the third level signal when the input voltage is greater than or equal to the preset threshold voltage, or output the fourth level signal when the input voltage is less than or equal to the preset threshold voltage, and the preset threshold voltages corresponding to the comparison circuits are not equal; The first detection circuits include a plurality of them, and the first detection circuits are connected to the comparison circuits in a one-to-one correspondence; The second detection circuits include a plurality of them, and each second detection circuit is respectively connected to the output end of a comparison circuit and the output end of a delay circuit; The logic control circuit is respectively connected to a plurality of the first detection circuits and a plurality of the second detection circuits, and the logic control circuit is configured to: Output the reset signal during the output period of each second level signal, and output the quenching signal according to receiving one of the first detection signals or the third detection signals first, or output the reset signal according to receiving one of the second detection signals or the fourth detection signals first; Output the quenching signal during the output period of the first level signal.

4. The quenching circuit of an avalanche diode according to claim 3, characterized in that, The first detection circuit includes a first D flip-flop; The data terminal of the first D flip-flop is connected to the second positive voltage terminal, the corresponding clock terminal of the first D flip-flop is connected to the output end of the comparison circuit, the corresponding reset terminal of the first D flip-flop is used to input the first clock signal, and the corresponding output terminal of the first D flip-flop constitutes the output end of the first detection circuit.

5. The quenching circuit of an avalanche diode according to claim 4, characterized in that, The second detection circuit includes a second D flip-flop and a third D flip-flop; The data terminal of the second D flip-flop is connected to the second positive voltage terminal, the clock terminal of the second D flip-flop is connected to the output end of the comparison circuit, the corresponding reset terminals of the second D flip-flop and the third D flip-flop are used to input the first clock signal, the corresponding clock terminal of the third D flip-flop is used to input the corresponding second clock signal, the corresponding output terminal of the second D flip-flop is connected to the data terminal of the third D flip-flop, and the corresponding output terminal of the third D flip-flop constitutes the output end of the second detection circuit.

6. The quenching circuit of an avalanche diode according to claim 3, characterized in that, When the first detection circuit and the second detection circuit include one, the logic control circuit includes a first logic gate circuit, two input terminals of the first logic gate circuit are respectively connected to the output end of the first detection circuit and the output end of the second detection circuit, another input terminal of the first logic gate circuit is further used to input the first clock signal, and the output terminal of the first logic gate circuit constitutes the output end of the logic control circuit; Or, when the first detection circuit and the second detection circuit include a plurality of them, the logic control circuit includes a second logic gate circuit and a third logic gate circuit; Multiple input ends of the second logic gate circuit are respectively connected to output ends of multiple first detection circuits. Multiple input ends of the third logic gate circuit are respectively connected to output ends of multiple second detection circuits and the output end of the second logic gate circuit. Another input end of the third logic gate circuit is used for inputting the first clock signal. An output end of the third logic gate circuit forms an output end of the logic control circuit.

7. The quenching circuit of an avalanche diode according to claim 1, characterized in that, The comparison circuit includes a first inverter; An input end of the first inverter is connected to a second end of the avalanche diode. An output end of the first inverter forms an output end of the comparison circuit.

8. The quenching circuit of an avalanche diode according to claim 1, characterized in that, The quenching and reset circuit includes a quenching switch and a capacitor; A first end of the quenching switch, a first end of the capacitor and a second end of the avalanche diode are connected. A second end of the quenching switch is grounded or connected to a first positive voltage terminal; The quenching switch includes a quenching tube; Alternatively, the quenching switch includes multiple parallel quenching branches; Each quenching branch includes a selection switch and a quenching tube connected in series. Control ends of the quenching tubes are used for receiving the quenching signal or the reset signal. Each selection switch is used for receiving a switch selection signal and corresponding on / off.

9. The quenching circuit of an avalanche diode according to any one of claims 1 to 8, characterized in that, The quenching circuit of the avalanche diode further includes: A signal attenuation circuit, connected between the quenching and reset circuit and the detection control circuit, for attenuating an output signal of the detection control circuit and outputting the attenuated signal to the quenching and reset circuit.

10. An imaging system, characterized in that, It includes a pixel array and an image processing circuit. The pixel array includes pixel units arranged in an array. Each pixel unit includes an avalanche diode and a quenching circuit of the avalanche diode according to any one of claims 1 to 9 connected to each other; The image processing circuit is respectively connected to the quenching circuits of the avalanche diodes, and is used for processing the photon counting rate output by the quenching circuits of the avalanche diodes and determining image information.

Images