Monolithic digital readout integrated circuit with frame integration function and frame integration method

Abstract

The invention discloses a monolithic digital readout integrated circuit with a frame integration function and a frame integration method, and belongs to the technical field of integrated circuits. The read-out integrated circuit architecture comprises a pixel circuit array, a column-level counting type ADC array with a preset number function, a static random access memory array, a control circuit, a biasing circuit and an interface circuit. The output of the pixel circuit array is used as the input of the column-level counting type ADC array with the preset number function; the output of the column-level counting type ADC array with the preset number function is used as the input of the static random access memory array and the interface circuit; the output of the static random access memory array is used as the input of the column-level counting type ADC array with the preset number function; and the output of the control circuit is used as the input of the column-level counting type ADC array, the static random access memory array and the pixel circuit array with the preset number function. The monolithic frame integral read-out integrated circuit realizes column-level digitization, and is higher in pixel size adaptability, simpler and more convenient in design and lower in power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a monolithic digital readout integrated circuit with a frame integration function and a frame integration method. Background Art

[0002] A readout integrated circuit is a key component of an infrared focal plane image sensor, which directly affects the performance, quality, and efficiency of an imaging system. With the increasing demand for high-performance imaging systems in fields such as medical imaging, aerospace, industrial automation, and security monitoring, readout integrated circuit technology has been continuously developing towards directions such as digitalization, large-area array, small pixel, high sensitivity, low power consumption, high dynamic range, low noise, and high frame rate.

[0003] In response to the development requirements of high dynamic range and high signal-to-noise ratio for infrared focal plane image sensors, the frame integration technology in image processing algorithms is introduced into the readout integrated circuit to implement a monolithic frame integration readout integrated circuit, which can not only improve the dynamic range, signal-to-noise ratio, and sensitivity of the image sensor, but also simplify the design of the imaging system, improve the integration level, and save manufacturing costs. The frame integration technology refers to the signal accumulation of multiple frames of images within a certain period of time. By using the principle that the inter-frame signal-related noise is uncorrelated, the noise is suppressed, and the signal strength is increased, thereby realizing the improvement of the signal-to-noise ratio and dynamic range. It is also called the multi-frame accumulation technology. In some applications with medium to high background intensities, the signals can be accumulated in multiple frames and then averaged to only suppress the noise to improve the signal-to-noise ratio. Applying the frame integration technology to the readout integrated circuit can significantly improve the signal-to-noise ratio and dynamic range of the readout integrated circuit, improve the imaging quality, and enhance the performance of the readout integrated circuit.

[0004] The early application of the frame integration technology in the readout circuit had the disadvantage of low integration level, requiring off-chip storage, A / D conversion, and image processing modules to cooperate to achieve, which also brought greater power consumption overhead to the system and increased the manufacturing cost. With the rapid development of ROIC and the continuous progress of CMOS technology, the frame integration function has been integrated onto the ROIC.

[0005] "384×288 Focal Plane Readout Circuit with Pixel Accumulation Function" (Li Yu et al., Infrared and Laser Engineering, 2011, Vol. 40, No. 11, pp. 2110 - 2113) proposed an infrared focal plane readout circuit with pixel accumulation function. By introducing the pixel accumulation function at the input stage, within one frame period, the same pixel is sampled by integration multiple times and transferred and accumulated to the accumulation capacitor to equivalently extend the integration time and obtain a higher signal-to-noise ratio. "Research on Infrared Focal Plane Readout Circuit for Astronomical Applications" (Liang Qinghua et al., Infrared and Laser Engineering, 2024, Vol. 53, No. 1, pp. 55 - 67) proposed a frame integration infrared focal plane readout circuit for astronomical applications. By studying the digital function of non-destructive readout, the circuit integrates without resetting to achieve an extremely long integration time and multi-frame accumulation of signals.

[0006] However, although the above-mentioned readout integrated circuits with multiple accumulation functions have improved the dynamic range and signal-to-noise ratio of the readout integrated circuits to a certain extent, it is necessary to balance the charge capacity of the accumulation capacitor and the pixel size. Although the function of merging multi-pixel accumulation capacitors has been proposed to increase the accumulated charge capacity and extend the integration time, they are all implemented in the analog domain. And analog readout integrated circuits have disadvantages such as weak anti-interference ability, low integration level, the output being affected by the non-linearity of analog circuits, and being difficult to meet the requirements of high speed and high precision. Moreover, for an imaging system, analog readout integrated circuits need to perform back-end analog-to-digital conversion and quantization into digital signals for imaging, which increases the cost of the system and reduces the integration level of the system. The readout integrated circuit that realizes the frame integration function in the digital domain needs to integrate A / D conversion and accumulation circuits within the pixel, which has extremely high requirements for the pixel size and is difficult to implement in a readout circuit with a small pixel size. And the pixel-level readout integrated circuit itself has problems such as complex design, high power consumption, and large area overhead. Although CN118670537A discloses a pixel-level infrared detector readout circuit, which proposes that a high-signal-to-noise ratio, high-precision, and lower-power digital readout integrated circuit with a smaller pixel size and controllable integration duration can be realized by only integrating circuits such as counters and registers in the pixel, its pixel design is complex and there are many functional circuits in the pixel, still difficult to be implemented in a small-pixel digital readout circuit, difficult to meet the application requirements of small-size and high-resolution readout integrated circuits, and the power consumption of the pixel-level readout circuit increases sharply with the increase of the pixel array specification. Summary of the Invention

[0007] In view of the above-mentioned technical problems, the present invention provides a monolithic digital readout integrated circuit with a frame integration function and a frame integration method, aiming to solve the problems that the design of existing digital readout integrated circuits with a multi-frame accumulation function is limited by the pixel size, complex in design, and large in power consumption and area overhead. The readout circuit adopts the current mainstream column-level digital readout integrated circuit architecture with high resolution, low power consumption, and low cost. Through innovative design of the circuit architecture, a monolithic frame integration readout integrated circuit with column-level digitization, stronger pixel size adaptability, simpler design, and lower power consumption is realized.

[0008] The technical solution of the present invention is as follows:

[0009] A monolithic digital readout integrated circuit with a frame integration function, comprising: a pixel circuit array, a column-level counting type analog-to-digital conversion circuit (ADC) array with a preset function, a static random access memory array, a control circuit, a bias circuit, and an interface circuit.

[0010] Specifically, the pixel circuit array outputs m rows of pixel signals row by row through n column buses to the column-level counting type ADC array with a preset function corresponding to each column of the pixel circuit array, as the input of the column-level counting type ADC array with a preset function, for subsequent processing.

[0011] Specifically, the output of the column-level counting type ADC array with a preset function serves as the input of the static random access memory array and the interface circuit. The column-level counting type ADC array with a preset function receives signals from the pixel circuit array, processes them, and sends the output of each column of the column-level counting type ADC array to the static random access memory array corresponding to the pixel circuit array one by one for storage. At the same time, the output of each column of the column-level counting type ADC array with a preset function is sent to the interface circuit for waiting to be processed.

[0012] Specifically, the output of the static random access memory array serves as the input of the column-level counting type ADC array with a preset function. Under the control of the control circuit, the output data of the column-level counting type ADC array with a preset function can be written into the static random access memory array corresponding to the position of the pixel circuit array one by one, and the data in the static random access memory array can be read out under the control of the control circuit and sent to the column-level counting type ADC array with a preset function.

[0013] Specifically, the output of the control circuit serves as the input of the column-level counting type ADC array with a preset function, the static memory array, the pixel circuit array, and the interface circuit.

[0014] Specifically, the pixel circuit array is connected to a detector for detecting weak electrical signals input by the detector.

[0015] Specifically, the column-level counting ADC array with preset number function is used to quantize the analog electrical signals detected by the pixel circuit into digital signals; specifically, it also includes that the initial value of each count of the counter in the column-level counting ADC array with preset number function can be set to different values, and the analog-to-digital conversion can start from the preset bit each time.

[0016] Specifically, the static random access memory array has data writing and reading functions for storing the data output by the column-level counting ADC array with preset number function; at the same time, the data read from the static random access memory array is sent to the counter in the column-level counting ADC array with preset number function for setting its position.

[0017] Specifically, the control circuit is used to dynamically adjust the frame integration strategy and control the detection, quantization, storage, and reading of signals.

[0018] The present invention also provides a frame integration method based on the monolithic digital readout integrated circuit with frame integration function described above, including:

[0019] 1. After the control circuit receives the frame number signal to be accumulated, it starts to accumulate single-frame data;

[0020] 2. In the single-frame data accumulation stage, the control circuit generates control signals for global reset, global integration, and sequential row readout, and controls the pixel circuit array to sequentially complete global reset, global integration, and sequential row readout of a single frame;

[0021] 3. In the sequential row readout stage, after each row signal is generated, the control circuit generates control signals for memory array reading, counter setting, quantization start, and memory array writing; the memory array reading signal controls the static random access memory array to read the previous frame signal to the counter of the column-level counting ADC array with preset number function, and the counter is set under the control of the counter setting signal, so that the starting state of the counter is the data of the previous frame; after all columns of the current row are quantized, the memory array writing control signal controls the current quantization result to be written into the static random access memory array corresponding to the pixel circuit array; the operations of the sequential row readout stage are repeated for each row until all pixel signals are quantized and stored, the current frame ends, and the previous frame signal is accumulated to the current frame;

[0022] 4. To save frame time, the operations of counter setting and memory array reading signals can be placed before the sequential row readout of the pixel circuit array;

[0023] 5. Repeat steps 2 and 3. When the number of frames accumulates to the set value, the control circuit generates a data output control signal, and the interface circuit outputs the accumulated data of multiple frames row by row to complete the frame integration function.

[0024] The advantages of the monolithic digital readout integrated circuit of the present invention are as follows:

[0025] (1) This architecture breaks the pixel size limitation of the existing digital readout integrated circuit with multiple integration and accumulation functions, can be used for small pixels, can flexibly adjust the injection stage structure, and has better adaptability;

[0026] (2) Based on the current mainstream column-level ADC architecture, the accumulation function can be realized without specially designing an adder, which reduces the circuit complexity; at the same time, compared with the pixel-level design, it saves power consumption, simplifies the pixel design, and can meet the requirements of the readout integrated circuit of low-power small-size chips. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0028] Figure 1 It is a schematic diagram of the architecture of a monolithic digital readout integrated circuit with a frame integration function of the present invention.

[0029] Figure 2 It is a circuit schematic diagram of the DI injection and column-level single-slope ADC used in the embodiments of the present invention.

[0030] Figure 3 It is a flowchart of the frame integration method of the present invention. Detailed Embodiments

[0031] To make the purpose, technical solutions and advantages of the present invention clearer, the following further details the present invention in conjunction with specific embodiments and with reference to the drawings. Obviously, the drawings in the following description are only a part of the embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, those of ordinary skill in the art can obtain other embodiments without creative efforts, which all belong to the protection scope of the present invention.

[0032] See Figure 1As shown in the figure, an embodiment of the monolithic digital readout integrated circuit architecture with frame integration function includes: a direct injection (DI) pixel circuit array, a column-level single-slope ADC array with preset number function, a static random access memory array, and control circuits, bias circuits, and interface circuits.

[0033] Specifically, it is agreed that the number of frames for frame integration is M = 2 N (N is 1, 2, 3...), and this digital readout integrated circuit with frame integration function takes M frame periods as one frame integration period.

[0034] Specifically, in each frame period, global reset, global integration, row-by-row sequential readout of the pixel circuit array, and quantization and cumulative storage of the pixel readout signal are completed.

[0035] Specifically, the implementation process of this embodiment of the digital readout integrated circuit with frame integration function is as Figure 3 shown, and the following will be combined with Figure 2 for specific description.

[0036] Preferably, the pixel circuit array adopts a direct injection (DI) mode with a simple structure. As Figure 2 shown, each pixel in the array is connected to the photodiode array of the detector; as Figure 3 shown, in the current frame period, the control circuit first generates a global reset signal RST, globally resets the pixel circuit array to the VR level, and then waits for the start of integration; then the control circuit generates an integration control signal to control all the injection transistors M1 of the pixels to open simultaneously, and the integration capacitor Cint starts to globally integrate the weak current Iph induced by the photodiode; after the integration ends, the pixel array enters the row sequential readout stage; in the row sequential readout stage, the control circuit sequentially generates row readout signals RD<1>~RD <m>; An RD signal represents a row period. In each row period, the pixel signals of the corresponding row are sent through the column bus to the column-level single-slope ADC with a preset function for quantization and cumulative storage until all data is written into the static random access memory array for storage.

[0037] Specifically, the column-level single-slope ADC with a preset function includes a ramp circuit, a comparator, a latch, and a settable counter; as Figure 2 shown, the output of the ramp circuit and the output of the pixel circuit are respectively connected to the two input terminals of the comparator. The output of the comparator is connected to the inputs of the counter and the latch. The output of the counter is connected to the latch. The output of the latch is connected to the static random access memory array and the interface circuit through the data output bus; as Figure 3 shown, at the same time when the pixel circuit array starts the global integration of the current frame, the control circuit generates a counter set signal SET_COUNT to set the counter. At this time, the control circuit generates a memory array read signal RD_SRAM to read the data of the previous frame stored in the static random access memory into the counter, making the counter in the state of the previous frame data and waiting for the start of the current frame counting; by Figure 2 shown, in the readout stage of the pixel circuit array, after the start of the row period, the control circuit generates a quantization clock signal CLK_ADC and a ramp generation signal ramp. The counter starts counting, the ramp circuit starts to generate a ramp voltage, and the ADC array starts to quantize the analog signal from the pixel; the generation of the ramp voltage and the counting of the counter start simultaneously; when the ramp voltage is equal to the pixel output, the comparator flips and the output state changes. The counter stops counting and triggers the latch to latch the current count value; after the data is latched, the control circuit generates a write control signal WR_SRAM to write the quantized data of the current frame latched by the latch into the corresponding row of the static random access memory array for storage. At the same time, it is sent to the interface circuit for waiting for output; after the quantization and storage of the current row signal are completed, it enters the quantization and storage of the next row signal until all the pixel circuit array signals of the current frame are quantized and stored, the current frame period ends, and it enters the next frame period.

[0038] Specifically, the initial value of the counter is set to 0 in the first frame period, and the initial value of the remaining frame periods is set to the value of the previous frame data. The counter starts counting from the set value, and the data of the previous frame is accumulated to the current frame.

[0039] Specifically, the static random access memory array stores data in binary numbers. Under the control of the write control signal WR_SRAM of the current frame, the data of the current row is stored. When the read control signal RD_SRAM of the next frame arrives, the data stored in the corresponding row is output to the counter of the column-level single-slope ADC array with the function of presetting numbers, and the counter is set, so that the counter starts counting from the preset position; this static random access memory can stably store and read data when powered on.

[0040] Specifically, the control circuit is used to generate all the timing control signals required for global reset, global integration, row sequential readout, ADC quantization, and storage and reading of data in the static random access memory array in each frame period, and at the same time control the interface circuit to output data.

[0041] Specifically, when the data accumulates to M frames, the control circuit generates a data output signal, and outputs the data of the last frame period through the interface circuit to complete the frame integration function.

[0042] Specifically, the output data is shifted N bits from the high bit to the low bit, and the output data is the data after multi-frame accumulation and averaging.

[0043] The above embodiments only express the preferred implementation modes of the present invention, and the description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.< / m>

Claims

1. A monolithic digital readout integrated circuit with frame integration function, characterized in that, It includes a pixel circuit array, a column-level counting ADC array with a preset function, a static random access memory array, a control circuit, a bias circuit, and an interface circuit; The output of the pixel circuit array serves as the input of the column-level counting ADC array with a preset function; The output of the column-level counting ADC array with a preset function serves as the input of the static random access memory array; The output of the column-level counting ADC array with a preset function serves as the input of the interface circuit; The output of the static random access memory array serves as the input of the column-level counting ADC array with a preset function; The output of the control circuit serves as the input of the column-level counting ADC array with a preset function, the static random access memory array, the pixel circuit array, and the interface circuit.

2. The monolithic digital readout integrated circuit with a frame integration function according to claim 1, characterized in that, The pixel circuit array outputs m rows of pixel signals row by row through n column buses to the column-level counting ADC array with a preset function corresponding to each column of the pixel circuit array as the input of the column-level counting ADC array with a preset function for subsequent processing; the n column buses correspond to the n columns of the pixels.

3. The monolithic digital readout integrated circuit with frame integration function according to claim 1, characterized in that The output of the column-level counting ADC array with a preset function serves as the input of the static random access memory array and the interface circuit. The column-level counting ADC array with a preset function receives signals from the pixel circuit array, and after processing, sends the output of each column of the column-level counting ADC array to the static random access memory array corresponding to the pixel circuit array one by one for storage. At the same time, the output of each column of the column-level counting ADC array with a preset function is sent to the interface circuit for waiting for processing.

4. A monolithic digital readout integrated circuit with a frame integration function according to claim 3, characterized in that, The static random access memory has data writing and reading functions, is used to store the data output by the column-level counting ADC array with a preset function, and is also used to set the column-level counting ADC array with a preset function.

5. A monolithic digital readout integrated circuit with a frame integration function according to claim 4, characterized in that, Under the control of the control circuit, the output data of the column-level counting ADC array with a preset function can be written into the static random access memory array corresponding to the position of the pixel circuit array one by one. The static random access memory can read out the data in the static random access memory array under the control of the control circuit and send it to the column-level counting ADC array with a preset function.

6. The monolithic digital readout integrated circuit with a frame integration function according to claim 5, characterized in that The column-level counting ADC array with a preset function is used to quantize the analog electrical signals detected by the pixel circuit into digital signals.

7. A monolithic digital readout integrated circuit with frame integration function according to claim 6, characterized in that, The initial value of each count of the counter in the column-level counting ADC array with a preset function can be set to different values under the control of the control circuit and starts the analog-to-digital conversion from the set initial value each time.

8. A monolithic digital readout integrated circuit with a frame integration function according to claim 7, characterized in that, The column-level single-slope ADC array with preset number function includes a ramp circuit, a comparator, a latch, and a settable counter; the output of the ramp circuit and the output of the pixel circuit array are respectively connected to two input ends of the comparator, the output of the comparator is connected to the inputs of the counter and the latch, the output of the counter is connected to the latch, and the output of the latch is connected to the static random access memory array and the interface circuit through a data output bus.

9. A monolithic digital readout integrated circuit with frame integration function according to any one of claims 1-8, characterized in that The pixel circuit array adopts a direct injection mode, and each pixel in the array is connected to the photodiode array of the detector; The control circuit is used to dynamically adjust the frame integration strategy and control the acquisition, quantization, storage, and reading of signals.

10. A frame integration method for a monolithic digital readout integrated circuit with frame integration function according to any one of claims 1-9, characterized in that, It includes the following steps: (1) After the control circuit receives the number-of-frames signal to be accumulated, it starts to accumulate single-frame data; (2) In the single-frame data accumulation stage, the control circuit generates control signals for global reset, global integration, and sequential row readout, and controls the pixel circuit array to sequentially complete global reset, global integration, and sequential row readout of a single frame; (3) In the sequential row readout stage, after each row signal is generated, the control circuit generates control signals for memory array reading, counter setting, quantization start, and memory array writing; The memory array read signal controls the static random access memory array to read the previous frame signal into the counter of the column-level counting ADC array with preset number function, and sets the counter under the control of the counter setting signal, so that the starting state of the counter is the data of the previous frame; after quantization of all columns in the current row is completed, the memory array write control signal controls the current quantization result to be written into the static random access memory array corresponding to the pixel circuit array; the operation of the sequential row readout stage is repeated for each row until all pixel signals are quantized and stored, the current frame ends, and the previous frame signal is accumulated to the current frame; (4) Repeat steps (2) and (3). When the number of frames accumulates to the set value, the control circuit generates a data output control signal, and the interface circuit outputs the multi-frame accumulated data row by row to complete the frame integration function.

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